Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Generic driver for memory-mapped GPIO controllers. |
| 3 | * |
| 4 | * Copyright 2008 MontaVista Software, Inc. |
| 5 | * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | * |
| 12 | * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... |
| 13 | * ...`` ```````.. |
| 14 | * ..The simplest form of a GPIO controller that the driver supports is`` |
| 15 | * `.just a single "data" register, where GPIO state can be read and/or ` |
| 16 | * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` |
| 17 | * ````````` |
| 18 | ___ |
| 19 | _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... |
| 20 | __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . |
| 21 | o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` |
| 22 | `....trivial..'~`.```.``` |
| 23 | * ``````` |
| 24 | * .```````~~~~`..`.``.``. |
| 25 | * . The driver supports `... ,..```.`~~~```````````````....````.``,, |
| 26 | * . big-endian notation, just`. .. A bit more sophisticated controllers , |
| 27 | * . register the device with -be`. .with a pair of set/clear-bit registers , |
| 28 | * `.. suffix. ```~~`````....`.` . affecting the data register and the .` |
| 29 | * ``.`.``...``` ```.. output pins are also supported.` |
| 30 | * ^^ `````.`````````.,``~``~``~~`````` |
| 31 | * . ^^ |
| 32 | * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. |
| 33 | * .. The expectation is that in at least some cases . ,-~~~-, |
| 34 | * .this will be used with roll-your-own ASIC/FPGA .` \ / |
| 35 | * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / |
| 36 | * ..````````......``````````` \o_ |
| 37 | * | |
| 38 | * ^^ / \ |
| 39 | * |
| 40 | * ...`````~~`.....``.`..........``````.`.``.```........``. |
| 41 | * ` 8, 16, 32 and 64 bits registers are supported, and``. |
| 42 | * . the number of GPIOs is determined by the width of ~ |
| 43 | * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ |
| 44 | * `.......````.``` |
| 45 | */ |
| 46 | |
| 47 | #include <linux/init.h> |
| 48 | #include <linux/err.h> |
| 49 | #include <linux/bug.h> |
| 50 | #include <linux/kernel.h> |
| 51 | #include <linux/module.h> |
| 52 | #include <linux/spinlock.h> |
| 53 | #include <linux/compiler.h> |
| 54 | #include <linux/types.h> |
| 55 | #include <linux/errno.h> |
| 56 | #include <linux/log2.h> |
| 57 | #include <linux/ioport.h> |
| 58 | #include <linux/io.h> |
| 59 | #include <linux/gpio.h> |
| 60 | #include <linux/slab.h> |
| 61 | #include <linux/platform_device.h> |
| 62 | #include <linux/mod_devicetable.h> |
| 63 | #include <linux/basic_mmio_gpio.h> |
| 64 | |
| 65 | static void bgpio_write8(void __iomem *reg, unsigned long data) |
| 66 | { |
| 67 | writeb(data, reg); |
| 68 | } |
| 69 | |
| 70 | static unsigned long bgpio_read8(void __iomem *reg) |
| 71 | { |
| 72 | return readb(reg); |
| 73 | } |
| 74 | |
| 75 | static void bgpio_write16(void __iomem *reg, unsigned long data) |
| 76 | { |
| 77 | writew(data, reg); |
| 78 | } |
| 79 | |
| 80 | static unsigned long bgpio_read16(void __iomem *reg) |
| 81 | { |
| 82 | return readw(reg); |
| 83 | } |
| 84 | |
| 85 | static void bgpio_write32(void __iomem *reg, unsigned long data) |
| 86 | { |
| 87 | writel(data, reg); |
| 88 | } |
| 89 | |
| 90 | static unsigned long bgpio_read32(void __iomem *reg) |
| 91 | { |
| 92 | return readl(reg); |
| 93 | } |
| 94 | |
| 95 | #if BITS_PER_LONG >= 64 |
| 96 | static void bgpio_write64(void __iomem *reg, unsigned long data) |
| 97 | { |
| 98 | writeq(data, reg); |
| 99 | } |
| 100 | |
| 101 | static unsigned long bgpio_read64(void __iomem *reg) |
| 102 | { |
| 103 | return readq(reg); |
| 104 | } |
| 105 | #endif /* BITS_PER_LONG >= 64 */ |
| 106 | |
| 107 | static void bgpio_write16be(void __iomem *reg, unsigned long data) |
| 108 | { |
| 109 | iowrite16be(data, reg); |
| 110 | } |
| 111 | |
| 112 | static unsigned long bgpio_read16be(void __iomem *reg) |
| 113 | { |
| 114 | return ioread16be(reg); |
| 115 | } |
| 116 | |
| 117 | static void bgpio_write32be(void __iomem *reg, unsigned long data) |
| 118 | { |
| 119 | iowrite32be(data, reg); |
| 120 | } |
| 121 | |
| 122 | static unsigned long bgpio_read32be(void __iomem *reg) |
| 123 | { |
| 124 | return ioread32be(reg); |
| 125 | } |
| 126 | |
| 127 | static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin) |
| 128 | { |
| 129 | return 1 << pin; |
| 130 | } |
| 131 | |
| 132 | static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc, |
| 133 | unsigned int pin) |
| 134 | { |
| 135 | return 1 << (bgc->bits - 1 - pin); |
| 136 | } |
| 137 | |
| 138 | static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) |
| 139 | { |
| 140 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 141 | unsigned long pinmask = bgc->pin2mask(bgc, gpio); |
| 142 | |
| 143 | if (bgc->dir & pinmask) |
| 144 | return !!(bgc->read_reg(bgc->reg_set) & pinmask); |
| 145 | else |
| 146 | return !!(bgc->read_reg(bgc->reg_dat) & pinmask); |
| 147 | } |
| 148 | |
| 149 | static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) |
| 150 | { |
| 151 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 152 | |
| 153 | return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio)); |
| 154 | } |
| 155 | |
| 156 | static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) |
| 157 | { |
| 158 | } |
| 159 | |
| 160 | static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
| 161 | { |
| 162 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 163 | unsigned long mask = bgc->pin2mask(bgc, gpio); |
| 164 | unsigned long flags; |
| 165 | |
| 166 | spin_lock_irqsave(&bgc->lock, flags); |
| 167 | |
| 168 | if (val) |
| 169 | bgc->data |= mask; |
| 170 | else |
| 171 | bgc->data &= ~mask; |
| 172 | |
| 173 | bgc->write_reg(bgc->reg_dat, bgc->data); |
| 174 | |
| 175 | spin_unlock_irqrestore(&bgc->lock, flags); |
| 176 | } |
| 177 | |
| 178 | static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, |
| 179 | int val) |
| 180 | { |
| 181 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 182 | unsigned long mask = bgc->pin2mask(bgc, gpio); |
| 183 | |
| 184 | if (val) |
| 185 | bgc->write_reg(bgc->reg_set, mask); |
| 186 | else |
| 187 | bgc->write_reg(bgc->reg_clr, mask); |
| 188 | } |
| 189 | |
| 190 | static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) |
| 191 | { |
| 192 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 193 | unsigned long mask = bgc->pin2mask(bgc, gpio); |
| 194 | unsigned long flags; |
| 195 | |
| 196 | spin_lock_irqsave(&bgc->lock, flags); |
| 197 | |
| 198 | if (val) |
| 199 | bgc->data |= mask; |
| 200 | else |
| 201 | bgc->data &= ~mask; |
| 202 | |
| 203 | bgc->write_reg(bgc->reg_set, bgc->data); |
| 204 | |
| 205 | spin_unlock_irqrestore(&bgc->lock, flags); |
| 206 | } |
| 207 | |
| 208 | static void bgpio_multiple_get_masks(struct bgpio_chip *bgc, |
| 209 | unsigned long *mask, unsigned long *bits, |
| 210 | unsigned long *set_mask, |
| 211 | unsigned long *clear_mask) |
| 212 | { |
| 213 | int i; |
| 214 | |
| 215 | *set_mask = 0; |
| 216 | *clear_mask = 0; |
| 217 | |
| 218 | for (i = 0; i < bgc->bits; i++) { |
| 219 | if (*mask == 0) |
| 220 | break; |
| 221 | if (__test_and_clear_bit(i, mask)) { |
| 222 | if (test_bit(i, bits)) |
| 223 | *set_mask |= bgc->pin2mask(bgc, i); |
| 224 | else |
| 225 | *clear_mask |= bgc->pin2mask(bgc, i); |
| 226 | } |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc, |
| 231 | unsigned long *mask, |
| 232 | unsigned long *bits, |
| 233 | void __iomem *reg) |
| 234 | { |
| 235 | unsigned long flags; |
| 236 | unsigned long set_mask, clear_mask; |
| 237 | |
| 238 | spin_lock_irqsave(&bgc->lock, flags); |
| 239 | |
| 240 | bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask); |
| 241 | |
| 242 | bgc->data |= set_mask; |
| 243 | bgc->data &= ~clear_mask; |
| 244 | |
| 245 | bgc->write_reg(reg, bgc->data); |
| 246 | |
| 247 | spin_unlock_irqrestore(&bgc->lock, flags); |
| 248 | } |
| 249 | |
| 250 | static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, |
| 251 | unsigned long *bits) |
| 252 | { |
| 253 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 254 | |
| 255 | bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat); |
| 256 | } |
| 257 | |
| 258 | static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, |
| 259 | unsigned long *bits) |
| 260 | { |
| 261 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 262 | |
| 263 | bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set); |
| 264 | } |
| 265 | |
| 266 | static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, |
| 267 | unsigned long *mask, |
| 268 | unsigned long *bits) |
| 269 | { |
| 270 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 271 | unsigned long set_mask, clear_mask; |
| 272 | |
| 273 | bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask); |
| 274 | |
| 275 | if (set_mask) |
| 276 | bgc->write_reg(bgc->reg_set, set_mask); |
| 277 | if (clear_mask) |
| 278 | bgc->write_reg(bgc->reg_clr, clear_mask); |
| 279 | } |
| 280 | |
| 281 | static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) |
| 282 | { |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, |
| 287 | int val) |
| 288 | { |
| 289 | return -EINVAL; |
| 290 | } |
| 291 | |
| 292 | static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, |
| 293 | int val) |
| 294 | { |
| 295 | gc->set(gc, gpio, val); |
| 296 | |
| 297 | return 0; |
| 298 | } |
| 299 | |
| 300 | static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
| 301 | { |
| 302 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 303 | unsigned long flags; |
| 304 | |
| 305 | spin_lock_irqsave(&bgc->lock, flags); |
| 306 | |
| 307 | bgc->dir &= ~bgc->pin2mask(bgc, gpio); |
| 308 | bgc->write_reg(bgc->reg_dir, bgc->dir); |
| 309 | |
| 310 | spin_unlock_irqrestore(&bgc->lock, flags); |
| 311 | |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) |
| 316 | { |
| 317 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 318 | |
| 319 | return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ? |
| 320 | GPIOF_DIR_OUT : GPIOF_DIR_IN; |
| 321 | } |
| 322 | |
| 323 | static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
| 324 | { |
| 325 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 326 | unsigned long flags; |
| 327 | |
| 328 | gc->set(gc, gpio, val); |
| 329 | |
| 330 | spin_lock_irqsave(&bgc->lock, flags); |
| 331 | |
| 332 | bgc->dir |= bgc->pin2mask(bgc, gpio); |
| 333 | bgc->write_reg(bgc->reg_dir, bgc->dir); |
| 334 | |
| 335 | spin_unlock_irqrestore(&bgc->lock, flags); |
| 336 | |
| 337 | return 0; |
| 338 | } |
| 339 | |
| 340 | static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio) |
| 341 | { |
| 342 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 343 | unsigned long flags; |
| 344 | |
| 345 | spin_lock_irqsave(&bgc->lock, flags); |
| 346 | |
| 347 | bgc->dir |= bgc->pin2mask(bgc, gpio); |
| 348 | bgc->write_reg(bgc->reg_dir, bgc->dir); |
| 349 | |
| 350 | spin_unlock_irqrestore(&bgc->lock, flags); |
| 351 | |
| 352 | return 0; |
| 353 | } |
| 354 | |
| 355 | static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val) |
| 356 | { |
| 357 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 358 | unsigned long flags; |
| 359 | |
| 360 | gc->set(gc, gpio, val); |
| 361 | |
| 362 | spin_lock_irqsave(&bgc->lock, flags); |
| 363 | |
| 364 | bgc->dir &= ~bgc->pin2mask(bgc, gpio); |
| 365 | bgc->write_reg(bgc->reg_dir, bgc->dir); |
| 366 | |
| 367 | spin_unlock_irqrestore(&bgc->lock, flags); |
| 368 | |
| 369 | return 0; |
| 370 | } |
| 371 | |
| 372 | static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio) |
| 373 | { |
| 374 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
| 375 | |
| 376 | return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ? |
| 377 | GPIOF_DIR_IN : GPIOF_DIR_OUT; |
| 378 | } |
| 379 | |
| 380 | static int bgpio_setup_accessors(struct device *dev, |
| 381 | struct bgpio_chip *bgc, |
| 382 | bool bit_be, |
| 383 | bool byte_be) |
| 384 | { |
| 385 | |
| 386 | switch (bgc->bits) { |
| 387 | case 8: |
| 388 | bgc->read_reg = bgpio_read8; |
| 389 | bgc->write_reg = bgpio_write8; |
| 390 | break; |
| 391 | case 16: |
| 392 | if (byte_be) { |
| 393 | bgc->read_reg = bgpio_read16be; |
| 394 | bgc->write_reg = bgpio_write16be; |
| 395 | } else { |
| 396 | bgc->read_reg = bgpio_read16; |
| 397 | bgc->write_reg = bgpio_write16; |
| 398 | } |
| 399 | break; |
| 400 | case 32: |
| 401 | if (byte_be) { |
| 402 | bgc->read_reg = bgpio_read32be; |
| 403 | bgc->write_reg = bgpio_write32be; |
| 404 | } else { |
| 405 | bgc->read_reg = bgpio_read32; |
| 406 | bgc->write_reg = bgpio_write32; |
| 407 | } |
| 408 | break; |
| 409 | #if BITS_PER_LONG >= 64 |
| 410 | case 64: |
| 411 | if (byte_be) { |
| 412 | dev_err(dev, |
| 413 | "64 bit big endian byte order unsupported\n"); |
| 414 | return -EINVAL; |
| 415 | } else { |
| 416 | bgc->read_reg = bgpio_read64; |
| 417 | bgc->write_reg = bgpio_write64; |
| 418 | } |
| 419 | break; |
| 420 | #endif /* BITS_PER_LONG >= 64 */ |
| 421 | default: |
| 422 | dev_err(dev, "unsupported data width %u bits\n", bgc->bits); |
| 423 | return -EINVAL; |
| 424 | } |
| 425 | |
| 426 | bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask; |
| 427 | |
| 428 | return 0; |
| 429 | } |
| 430 | |
| 431 | /* |
| 432 | * Create the device and allocate the resources. For setting GPIO's there are |
| 433 | * three supported configurations: |
| 434 | * |
| 435 | * - single input/output register resource (named "dat"). |
| 436 | * - set/clear pair (named "set" and "clr"). |
| 437 | * - single output register resource and single input resource ("set" and |
| 438 | * dat"). |
| 439 | * |
| 440 | * For the single output register, this drives a 1 by setting a bit and a zero |
| 441 | * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit |
| 442 | * in the set register and clears it by setting a bit in the clear register. |
| 443 | * The configuration is detected by which resources are present. |
| 444 | * |
| 445 | * For setting the GPIO direction, there are three supported configurations: |
| 446 | * |
| 447 | * - simple bidirection GPIO that requires no configuration. |
| 448 | * - an output direction register (named "dirout") where a 1 bit |
| 449 | * indicates the GPIO is an output. |
| 450 | * - an input direction register (named "dirin") where a 1 bit indicates |
| 451 | * the GPIO is an input. |
| 452 | */ |
| 453 | static int bgpio_setup_io(struct bgpio_chip *bgc, |
| 454 | void __iomem *dat, |
| 455 | void __iomem *set, |
| 456 | void __iomem *clr, |
| 457 | unsigned long flags) |
| 458 | { |
| 459 | |
| 460 | bgc->reg_dat = dat; |
| 461 | if (!bgc->reg_dat) |
| 462 | return -EINVAL; |
| 463 | |
| 464 | if (set && clr) { |
| 465 | bgc->reg_set = set; |
| 466 | bgc->reg_clr = clr; |
| 467 | bgc->gc.set = bgpio_set_with_clear; |
| 468 | bgc->gc.set_multiple = bgpio_set_multiple_with_clear; |
| 469 | } else if (set && !clr) { |
| 470 | bgc->reg_set = set; |
| 471 | bgc->gc.set = bgpio_set_set; |
| 472 | bgc->gc.set_multiple = bgpio_set_multiple_set; |
| 473 | } else if (flags & BGPIOF_NO_OUTPUT) { |
| 474 | bgc->gc.set = bgpio_set_none; |
| 475 | bgc->gc.set_multiple = NULL; |
| 476 | } else { |
| 477 | bgc->gc.set = bgpio_set; |
| 478 | bgc->gc.set_multiple = bgpio_set_multiple; |
| 479 | } |
| 480 | |
| 481 | if (!(flags & BGPIOF_UNREADABLE_REG_SET) && |
| 482 | (flags & BGPIOF_READ_OUTPUT_REG_SET)) |
| 483 | bgc->gc.get = bgpio_get_set; |
| 484 | else |
| 485 | bgc->gc.get = bgpio_get; |
| 486 | |
| 487 | return 0; |
| 488 | } |
| 489 | |
| 490 | static int bgpio_setup_direction(struct bgpio_chip *bgc, |
| 491 | void __iomem *dirout, |
| 492 | void __iomem *dirin, |
| 493 | unsigned long flags) |
| 494 | { |
| 495 | if (dirout && dirin) { |
| 496 | return -EINVAL; |
| 497 | } else if (dirout) { |
| 498 | bgc->reg_dir = dirout; |
| 499 | bgc->gc.direction_output = bgpio_dir_out; |
| 500 | bgc->gc.direction_input = bgpio_dir_in; |
| 501 | bgc->gc.get_direction = bgpio_get_dir; |
| 502 | } else if (dirin) { |
| 503 | bgc->reg_dir = dirin; |
| 504 | bgc->gc.direction_output = bgpio_dir_out_inv; |
| 505 | bgc->gc.direction_input = bgpio_dir_in_inv; |
| 506 | bgc->gc.get_direction = bgpio_get_dir_inv; |
| 507 | } else { |
| 508 | if (flags & BGPIOF_NO_OUTPUT) |
| 509 | bgc->gc.direction_output = bgpio_dir_out_err; |
| 510 | else |
| 511 | bgc->gc.direction_output = bgpio_simple_dir_out; |
| 512 | bgc->gc.direction_input = bgpio_simple_dir_in; |
| 513 | } |
| 514 | |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) |
| 519 | { |
| 520 | if (gpio_pin < chip->ngpio) |
| 521 | return 0; |
| 522 | |
| 523 | return -EINVAL; |
| 524 | } |
| 525 | |
| 526 | int bgpio_remove(struct bgpio_chip *bgc) |
| 527 | { |
| 528 | gpiochip_remove(&bgc->gc); |
| 529 | return 0; |
| 530 | } |
| 531 | EXPORT_SYMBOL_GPL(bgpio_remove); |
| 532 | |
| 533 | int bgpio_init(struct bgpio_chip *bgc, struct device *dev, |
| 534 | unsigned long sz, void __iomem *dat, void __iomem *set, |
| 535 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, |
| 536 | unsigned long flags) |
| 537 | { |
| 538 | int ret; |
| 539 | |
| 540 | if (!is_power_of_2(sz)) |
| 541 | return -EINVAL; |
| 542 | |
| 543 | bgc->bits = sz * 8; |
| 544 | if (bgc->bits > BITS_PER_LONG) |
| 545 | return -EINVAL; |
| 546 | |
| 547 | spin_lock_init(&bgc->lock); |
| 548 | bgc->gc.dev = dev; |
| 549 | bgc->gc.label = dev_name(dev); |
| 550 | bgc->gc.base = -1; |
| 551 | bgc->gc.ngpio = bgc->bits; |
| 552 | bgc->gc.request = bgpio_request; |
| 553 | |
| 554 | ret = bgpio_setup_io(bgc, dat, set, clr, flags); |
| 555 | if (ret) |
| 556 | return ret; |
| 557 | |
| 558 | ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN, |
| 559 | flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); |
| 560 | if (ret) |
| 561 | return ret; |
| 562 | |
| 563 | ret = bgpio_setup_direction(bgc, dirout, dirin, flags); |
| 564 | if (ret) |
| 565 | return ret; |
| 566 | |
| 567 | bgc->data = bgc->read_reg(bgc->reg_dat); |
| 568 | if (bgc->gc.set == bgpio_set_set && |
| 569 | !(flags & BGPIOF_UNREADABLE_REG_SET)) |
| 570 | bgc->data = bgc->read_reg(bgc->reg_set); |
| 571 | if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR)) |
| 572 | bgc->dir = bgc->read_reg(bgc->reg_dir); |
| 573 | |
| 574 | return ret; |
| 575 | } |
| 576 | EXPORT_SYMBOL_GPL(bgpio_init); |
| 577 | |
| 578 | #ifdef CONFIG_GPIO_GENERIC_PLATFORM |
| 579 | |
| 580 | static void __iomem *bgpio_map(struct platform_device *pdev, |
| 581 | const char *name, |
| 582 | resource_size_t sane_sz) |
| 583 | { |
| 584 | struct resource *r; |
| 585 | resource_size_t sz; |
| 586 | |
| 587 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); |
| 588 | if (!r) |
| 589 | return NULL; |
| 590 | |
| 591 | sz = resource_size(r); |
| 592 | if (sz != sane_sz) |
| 593 | return IOMEM_ERR_PTR(-EINVAL); |
| 594 | |
| 595 | return devm_ioremap_resource(&pdev->dev, r); |
| 596 | } |
| 597 | |
| 598 | static int bgpio_pdev_probe(struct platform_device *pdev) |
| 599 | { |
| 600 | struct device *dev = &pdev->dev; |
| 601 | struct resource *r; |
| 602 | void __iomem *dat; |
| 603 | void __iomem *set; |
| 604 | void __iomem *clr; |
| 605 | void __iomem *dirout; |
| 606 | void __iomem *dirin; |
| 607 | unsigned long sz; |
| 608 | unsigned long flags = pdev->id_entry->driver_data; |
| 609 | int err; |
| 610 | struct bgpio_chip *bgc; |
| 611 | struct bgpio_pdata *pdata = dev_get_platdata(dev); |
| 612 | |
| 613 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
| 614 | if (!r) |
| 615 | return -EINVAL; |
| 616 | |
| 617 | sz = resource_size(r); |
| 618 | |
| 619 | dat = bgpio_map(pdev, "dat", sz); |
| 620 | if (IS_ERR(dat)) |
| 621 | return PTR_ERR(dat); |
| 622 | |
| 623 | set = bgpio_map(pdev, "set", sz); |
| 624 | if (IS_ERR(set)) |
| 625 | return PTR_ERR(set); |
| 626 | |
| 627 | clr = bgpio_map(pdev, "clr", sz); |
| 628 | if (IS_ERR(clr)) |
| 629 | return PTR_ERR(clr); |
| 630 | |
| 631 | dirout = bgpio_map(pdev, "dirout", sz); |
| 632 | if (IS_ERR(dirout)) |
| 633 | return PTR_ERR(dirout); |
| 634 | |
| 635 | dirin = bgpio_map(pdev, "dirin", sz); |
| 636 | if (IS_ERR(dirin)) |
| 637 | return PTR_ERR(dirin); |
| 638 | |
| 639 | bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL); |
| 640 | if (!bgc) |
| 641 | return -ENOMEM; |
| 642 | |
| 643 | err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags); |
| 644 | if (err) |
| 645 | return err; |
| 646 | |
| 647 | if (pdata) { |
| 648 | if (pdata->label) |
| 649 | bgc->gc.label = pdata->label; |
| 650 | bgc->gc.base = pdata->base; |
| 651 | if (pdata->ngpio > 0) |
| 652 | bgc->gc.ngpio = pdata->ngpio; |
| 653 | } |
| 654 | |
| 655 | platform_set_drvdata(pdev, bgc); |
| 656 | |
| 657 | return gpiochip_add(&bgc->gc); |
| 658 | } |
| 659 | |
| 660 | static int bgpio_pdev_remove(struct platform_device *pdev) |
| 661 | { |
| 662 | struct bgpio_chip *bgc = platform_get_drvdata(pdev); |
| 663 | |
| 664 | return bgpio_remove(bgc); |
| 665 | } |
| 666 | |
| 667 | static const struct platform_device_id bgpio_id_table[] = { |
| 668 | { |
| 669 | .name = "basic-mmio-gpio", |
| 670 | .driver_data = 0, |
| 671 | }, { |
| 672 | .name = "basic-mmio-gpio-be", |
| 673 | .driver_data = BGPIOF_BIG_ENDIAN, |
| 674 | }, |
| 675 | { } |
| 676 | }; |
| 677 | MODULE_DEVICE_TABLE(platform, bgpio_id_table); |
| 678 | |
| 679 | static struct platform_driver bgpio_driver = { |
| 680 | .driver = { |
| 681 | .name = "basic-mmio-gpio", |
| 682 | }, |
| 683 | .id_table = bgpio_id_table, |
| 684 | .probe = bgpio_pdev_probe, |
| 685 | .remove = bgpio_pdev_remove, |
| 686 | }; |
| 687 | |
| 688 | module_platform_driver(bgpio_driver); |
| 689 | |
| 690 | #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ |
| 691 | |
| 692 | MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); |
| 693 | MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); |
| 694 | MODULE_LICENSE("GPL"); |