| Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | Interface between kernel and boot loaders on Exynos boards |
| 2 | ========================================================== |
| 3 | |
| 4 | Author: Krzysztof Kozlowski |
| 5 | Date : 6 June 2015 |
| 6 | |
| 7 | The document tries to describe currently used interface between Linux kernel |
| 8 | and boot loaders on Samsung Exynos based boards. This is not a definition |
| 9 | of interface but rather a description of existing state, a reference |
| 10 | for information purpose only. |
| 11 | |
| 12 | In the document "boot loader" means any of following: U-boot, proprietary |
| 13 | SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before |
| 14 | executing kernel. |
| 15 | |
| 16 | |
| 17 | 1. Non-Secure mode |
| 18 | |
| 19 | Address: sysram_ns_base_addr |
| 20 | Offset Value Purpose |
| 21 | ============================================================================= |
| 22 | 0x08 exynos_cpu_resume_ns, mcpm_entry_point System suspend |
| 23 | 0x0c 0x00000bad (Magic cookie) System suspend |
| 24 | 0x1c exynos4_secondary_startup Secondary CPU boot |
| 25 | 0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot |
| 26 | 0x20 0xfcba0d10 (Magic cookie) AFTR |
| 27 | 0x24 exynos_cpu_resume_ns AFTR |
| 28 | 0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR |
| 29 | |
| 30 | |
| 31 | 2. Secure mode |
| 32 | |
| 33 | Address: sysram_base_addr |
| 34 | Offset Value Purpose |
| 35 | ============================================================================= |
| 36 | 0x00 exynos4_secondary_startup Secondary CPU boot |
| 37 | 0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot |
| 38 | 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot |
| 39 | 0x20 exynos_cpu_resume (Exynos4210 r1.0) AFTR |
| 40 | 0x24 0xfcba0d10 (Magic cookie, Exynos4210 r1.0) AFTR |
| 41 | |
| 42 | Address: pmu_base_addr |
| 43 | Offset Value Purpose |
| 44 | ============================================================================= |
| 45 | 0x0800 exynos_cpu_resume AFTR, suspend |
| 46 | 0x0800 mcpm_entry_point (Exynos542x with MCPM) AFTR, suspend |
| 47 | 0x0804 0xfcba0d10 (Magic cookie) AFTR |
| 48 | 0x0804 0x00000bad (Magic cookie) System suspend |
| 49 | 0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot |
| 50 | 0x0818 0xfcba0d10 (Magic cookie, Exynos4210 r1.1) AFTR |
| 51 | 0x081C exynos_cpu_resume (Exynos4210 r1.1) AFTR |
| 52 | |
| 53 | |
| 54 | 3. Other (regardless of secure/non-secure mode) |
| 55 | |
| 56 | Address: pmu_base_addr |
| 57 | Offset Value Purpose |
| 58 | ============================================================================= |
| 59 | 0x0908 Non-zero Secondary CPU boot up indicator |
| 60 | on Exynos3250 and Exynos542x |
| 61 | |
| 62 | |
| 63 | 4. Glossary |
| 64 | |
| 65 | AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other |
| 66 | modules are power gated, except the TOP modules |
| 67 | MCPM - Multi-Cluster Power Management |