| Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | MIPS Global Interrupt Controller (GIC) |
| 2 | |
| 3 | The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. |
| 4 | It also supports local (per-processor) interrupts and software-generated |
| 5 | interrupts which can be used as IPIs. The GIC also includes a free-running |
| 6 | global timer, per-CPU count/compare timers, and a watchdog. |
| 7 | |
| 8 | Required properties: |
| 9 | - compatible : Should be "mti,gic". |
| 10 | - interrupt-controller : Identifies the node as an interrupt controller |
| 11 | - #interrupt-cells : Specifies the number of cells needed to encode an |
| 12 | interrupt specifier. Should be 3. |
| 13 | - The first cell is the type of interrupt, local or shared. |
| 14 | See <include/dt-bindings/interrupt-controller/mips-gic.h>. |
| 15 | - The second cell is the GIC interrupt number. |
| 16 | - The third cell encodes the interrupt flags. |
| 17 | See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid |
| 18 | flags. |
| 19 | |
| 20 | Optional properties: |
| 21 | - reg : Base address and length of the GIC registers. If not present, |
| 22 | the base address reported by the hardware GCR_GIC_BASE will be used. |
| 23 | - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors |
| 24 | to which the GIC may not route interrupts. Valid values are 2 - 7. |
| 25 | This property is ignored if the CPU is started in EIC mode. |
| 26 | |
| 27 | Required properties for timer sub-node: |
| 28 | - compatible : Should be "mti,gic-timer". |
| 29 | - interrupts : Interrupt for the GIC local timer. |
| 30 | |
| 31 | Optional properties for timer sub-node: |
| 32 | - clocks : GIC timer operating clock. |
| 33 | - clock-frequency : Clock frequency at which the GIC timers operate. |
| 34 | |
| 35 | Note that one of clocks or clock-frequency must be specified. |
| 36 | |
| 37 | Example: |
| 38 | |
| 39 | gic: interrupt-controller@1bdc0000 { |
| 40 | compatible = "mti,gic"; |
| 41 | reg = <0x1bdc0000 0x20000>; |
| 42 | |
| 43 | interrupt-controller; |
| 44 | #interrupt-cells = <3>; |
| 45 | |
| 46 | mti,reserved-cpu-vectors = <7>; |
| 47 | |
| 48 | timer { |
| 49 | compatible = "mti,gic-timer"; |
| 50 | interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
| 51 | clock-frequency = <50000000>; |
| 52 | }; |
| 53 | }; |
| 54 | |
| 55 | uart@18101400 { |
| 56 | ... |
| 57 | interrupt-parent = <&gic>; |
| 58 | interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; |
| 59 | ... |
| 60 | }; |