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gerrit.nordix.org / codeaurora / cp-linux / 8d8f6542b666daf5e87de156590e635c2c4da0c0 / . / arch / arm / boot / dts / stih410.dtsi
blob: 40318869c733668a15e3d318ff291c3221336125 [file] [log] [blame]
Kyle Swenson8d8f6542021-03-15 11:02:55 -0600[diff] [blame^]1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih410-clock.dtsi"
10#include "stih407-family.dtsi"
11#include "stih410-pinctrl.dtsi"
12/ {
13 aliases {
14 bdisp0 = &bdisp0;
15 };
16
17 soc {
18 usb2_picophy1: phy2 {
19 compatible = "st,stih407-usb2-phy";
20 #phy-cells = <0>;
21 st,syscfg = <&syscfg_core 0xf8 0xf4>;
22 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
23 <&picophyreset STIH407_PICOPHY0_RESET>;
24 reset-names = "global", "port";
25
26 status = "disabled";
27 };
28
29 usb2_picophy2: phy3 {
30 compatible = "st,stih407-usb2-phy";
31 #phy-cells = <0>;
32 st,syscfg = <&syscfg_core 0xfc 0xf4>;
33 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
34 <&picophyreset STIH407_PICOPHY1_RESET>;
35 reset-names = "global", "port";
36
37 status = "disabled";
38 };
39
40 ohci0: usb@9a03c00 {
41 compatible = "st,st-ohci-300x";
42 reg = <0x9a03c00 0x100>;
43 interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
44 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
45 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
46 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
47 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
48 reset-names = "power", "softreset";
49 phys = <&usb2_picophy1>;
50 phy-names = "usb";
51
52 status = "disabled";
53 };
54
55 ehci0: usb@9a03e00 {
56 compatible = "st,st-ehci-300x";
57 reg = <0x9a03e00 0x100>;
58 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_usb0>;
61 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
62 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
63 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
64 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
65 reset-names = "power", "softreset";
66 phys = <&usb2_picophy1>;
67 phy-names = "usb";
68
69 status = "disabled";
70 };
71
72 ohci1: usb@9a83c00 {
73 compatible = "st,st-ohci-300x";
74 reg = <0x9a83c00 0x100>;
75 interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
76 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
77 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
78 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
79 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
80 reset-names = "power", "softreset";
81 phys = <&usb2_picophy2>;
82 phy-names = "usb";
83
84 status = "disabled";
85 };
86
87 ehci1: usb@9a83e00 {
88 compatible = "st,st-ehci-300x";
89 reg = <0x9a83e00 0x100>;
90 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_usb1>;
93 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
94 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
95 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
96 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
97 reset-names = "power", "softreset";
98 phys = <&usb2_picophy2>;
99 phy-names = "usb";
100
101 status = "disabled";
102 };
103
104 sti-display-subsystem {
105 compatible = "st,sti-display-subsystem";
106 #address-cells = <1>;
107 #size-cells = <1>;
108
109 assigned-clocks = <&clk_s_d2_quadfs 0>,
110 <&clk_s_d2_quadfs 0>,
111 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
112 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
113 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
114 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
115 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
116 <&clk_s_d2_flexgen CLK_PIX_GDP4>;
117
118 assigned-clock-parents = <0>,
119 <0>,
120 <&clk_s_d2_quadfs 0>,
121 <&clk_s_d2_quadfs 0>,
122 <&clk_s_d2_quadfs 0>,
123 <&clk_s_d2_quadfs 0>,
124 <&clk_s_d2_quadfs 0>,
125 <&clk_s_d2_quadfs 0>;
126
127 assigned-clock-rates = <297000000>, <297000000>;
128
129 ranges;
130
131 sti-compositor@9d11000 {
132 compatible = "st,stih407-compositor";
133 reg = <0x9d11000 0x1000>;
134
135 clock-names = "compo_main",
136 "compo_aux",
137 "pix_main",
138 "pix_aux",
139 "pix_gdp1",
140 "pix_gdp2",
141 "pix_gdp3",
142 "pix_gdp4",
143 "main_parent",
144 "aux_parent";
145
146 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
147 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
148 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
149 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
150 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
151 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
152 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
153 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
154 <&clk_s_d2_quadfs 0>,
155 <&clk_s_d2_quadfs 1>;
156
157 reset-names = "compo-main", "compo-aux";
158 resets = <&softreset STIH407_COMPO_SOFTRESET>,
159 <&softreset STIH407_COMPO_SOFTRESET>;
160 st,vtg = <&vtg_main>, <&vtg_aux>;
161 };
162
163 sti-tvout@8d08000 {
164 compatible = "st,stih407-tvout";
165 reg = <0x8d08000 0x1000>;
166 reg-names = "tvout-reg";
167 reset-names = "tvout";
168 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
172 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
173 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
174 <&clk_s_d0_flexgen CLK_PCM_0>,
175 <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
176 <&clk_s_d2_flexgen CLK_HDDAC>;
177
178 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
179 <&clk_tmdsout_hdmi>,
180 <&clk_s_d2_quadfs 0>,
181 <&clk_s_d0_quadfs 0>,
182 <&clk_s_d2_quadfs 0>,
183 <&clk_s_d2_quadfs 0>;
184 };
185
186 sti-hdmi@8d04000 {
187 compatible = "st,stih407-hdmi";
188 reg = <0x8d04000 0x1000>;
189 reg-names = "hdmi-reg";
190 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
191 interrupt-names = "irq";
192 clock-names = "pix",
193 "tmds",
194 "phy",
195 "audio",
196 "main_parent",
197 "aux_parent";
198
199 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
200 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
201 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
202 <&clk_s_d0_flexgen CLK_PCM_0>,
203 <&clk_s_d2_quadfs 0>,
204 <&clk_s_d2_quadfs 1>;
205
206 hdmi,hpd-gpio = <&pio5 3>;
207 reset-names = "hdmi";
208 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
209 ddc = <&hdmiddc>;
210 };
211
212 sti-hda@8d02000 {
213 compatible = "st,stih407-hda";
214 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
215 reg-names = "hda-reg", "video-dacs-ctrl";
216 clock-names = "pix",
217 "hddac",
218 "main_parent",
219 "aux_parent";
220 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
221 <&clk_s_d2_flexgen CLK_HDDAC>,
222 <&clk_s_d2_quadfs 0>,
223 <&clk_s_d2_quadfs 1>;
224 };
225 };
226
227 bdisp0:bdisp@9f10000 {
228 compatible = "st,stih407-bdisp";
229 reg = <0x9f10000 0x1000>;
230 interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
231 clock-names = "bdisp";
232 clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
233 };
234 };
235};