| Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * arch/arm/plat-omap/include/mach/irqs.h |
| 3 | * |
| 4 | * Copyright (C) Greg Lonnon 2001 |
| 5 | * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> |
| 6 | * |
| 7 | * Copyright (C) 2009 Texas Instruments |
| 8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 23 | * |
| 24 | * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 |
| 25 | * are different. |
| 26 | */ |
| 27 | |
| 28 | #ifndef __ASM_ARCH_OMAP15XX_IRQS_H |
| 29 | #define __ASM_ARCH_OMAP15XX_IRQS_H |
| 30 | |
| 31 | /* |
| 32 | * IRQ numbers for interrupt handler 1 |
| 33 | * |
| 34 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below |
| 35 | * |
| 36 | */ |
| 37 | #define INT_CAMERA (NR_IRQS_LEGACY + 1) |
| 38 | #define INT_FIQ (NR_IRQS_LEGACY + 3) |
| 39 | #define INT_RTDX (NR_IRQS_LEGACY + 6) |
| 40 | #define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7) |
| 41 | #define INT_HOST (NR_IRQS_LEGACY + 8) |
| 42 | #define INT_ABORT (NR_IRQS_LEGACY + 9) |
| 43 | #define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13) |
| 44 | #define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14) |
| 45 | #define INT_UART3 (NR_IRQS_LEGACY + 15) |
| 46 | #define INT_TIMER3 (NR_IRQS_LEGACY + 16) |
| 47 | #define INT_DMA_CH0_6 (NR_IRQS_LEGACY + 19) |
| 48 | #define INT_DMA_CH1_7 (NR_IRQS_LEGACY + 20) |
| 49 | #define INT_DMA_CH2_8 (NR_IRQS_LEGACY + 21) |
| 50 | #define INT_DMA_CH3 (NR_IRQS_LEGACY + 22) |
| 51 | #define INT_DMA_CH4 (NR_IRQS_LEGACY + 23) |
| 52 | #define INT_DMA_CH5 (NR_IRQS_LEGACY + 24) |
| 53 | #define INT_TIMER1 (NR_IRQS_LEGACY + 26) |
| 54 | #define INT_WD_TIMER (NR_IRQS_LEGACY + 27) |
| 55 | #define INT_BRIDGE_PUB (NR_IRQS_LEGACY + 28) |
| 56 | #define INT_TIMER2 (NR_IRQS_LEGACY + 30) |
| 57 | #define INT_LCD_CTRL (NR_IRQS_LEGACY + 31) |
| 58 | |
| 59 | /* |
| 60 | * OMAP-1510 specific IRQ numbers for interrupt handler 1 |
| 61 | */ |
| 62 | #define INT_1510_IH2_IRQ (NR_IRQS_LEGACY + 0) |
| 63 | #define INT_1510_RES2 (NR_IRQS_LEGACY + 2) |
| 64 | #define INT_1510_SPI_TX (NR_IRQS_LEGACY + 4) |
| 65 | #define INT_1510_SPI_RX (NR_IRQS_LEGACY + 5) |
| 66 | #define INT_1510_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) |
| 67 | #define INT_1510_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) |
| 68 | #define INT_1510_RES12 (NR_IRQS_LEGACY + 12) |
| 69 | #define INT_1510_LB_MMU (NR_IRQS_LEGACY + 17) |
| 70 | #define INT_1510_RES18 (NR_IRQS_LEGACY + 18) |
| 71 | #define INT_1510_LOCAL_BUS (NR_IRQS_LEGACY + 29) |
| 72 | |
| 73 | /* |
| 74 | * OMAP-1610 specific IRQ numbers for interrupt handler 1 |
| 75 | */ |
| 76 | #define INT_1610_IH2_IRQ INT_1510_IH2_IRQ |
| 77 | #define INT_1610_IH2_FIQ (NR_IRQS_LEGACY + 2) |
| 78 | #define INT_1610_McBSP2_TX (NR_IRQS_LEGACY + 4) |
| 79 | #define INT_1610_McBSP2_RX (NR_IRQS_LEGACY + 5) |
| 80 | #define INT_1610_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) |
| 81 | #define INT_1610_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) |
| 82 | #define INT_1610_LCD_LINE (NR_IRQS_LEGACY + 12) |
| 83 | #define INT_1610_GPTIMER1 (NR_IRQS_LEGACY + 17) |
| 84 | #define INT_1610_GPTIMER2 (NR_IRQS_LEGACY + 18) |
| 85 | #define INT_1610_SSR_FIFO_0 (NR_IRQS_LEGACY + 29) |
| 86 | |
| 87 | /* |
| 88 | * OMAP-7xx specific IRQ numbers for interrupt handler 1 |
| 89 | */ |
| 90 | #define INT_7XX_IH2_FIQ (NR_IRQS_LEGACY + 0) |
| 91 | #define INT_7XX_IH2_IRQ (NR_IRQS_LEGACY + 1) |
| 92 | #define INT_7XX_USB_NON_ISO (NR_IRQS_LEGACY + 2) |
| 93 | #define INT_7XX_USB_ISO (NR_IRQS_LEGACY + 3) |
| 94 | #define INT_7XX_ICR (NR_IRQS_LEGACY + 4) |
| 95 | #define INT_7XX_EAC (NR_IRQS_LEGACY + 5) |
| 96 | #define INT_7XX_GPIO_BANK1 (NR_IRQS_LEGACY + 6) |
| 97 | #define INT_7XX_GPIO_BANK2 (NR_IRQS_LEGACY + 7) |
| 98 | #define INT_7XX_GPIO_BANK3 (NR_IRQS_LEGACY + 8) |
| 99 | #define INT_7XX_McBSP2TX (NR_IRQS_LEGACY + 10) |
| 100 | #define INT_7XX_McBSP2RX (NR_IRQS_LEGACY + 11) |
| 101 | #define INT_7XX_McBSP2RX_OVF (NR_IRQS_LEGACY + 12) |
| 102 | #define INT_7XX_LCD_LINE (NR_IRQS_LEGACY + 14) |
| 103 | #define INT_7XX_GSM_PROTECT (NR_IRQS_LEGACY + 15) |
| 104 | #define INT_7XX_TIMER3 (NR_IRQS_LEGACY + 16) |
| 105 | #define INT_7XX_GPIO_BANK5 (NR_IRQS_LEGACY + 17) |
| 106 | #define INT_7XX_GPIO_BANK6 (NR_IRQS_LEGACY + 18) |
| 107 | #define INT_7XX_SPGIO_WR (NR_IRQS_LEGACY + 29) |
| 108 | |
| 109 | /* |
| 110 | * IRQ numbers for interrupt handler 2 |
| 111 | * |
| 112 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below |
| 113 | */ |
| 114 | #define IH2_BASE (NR_IRQS_LEGACY + 32) |
| 115 | |
| 116 | #define INT_KEYBOARD (1 + IH2_BASE) |
| 117 | #define INT_uWireTX (2 + IH2_BASE) |
| 118 | #define INT_uWireRX (3 + IH2_BASE) |
| 119 | #define INT_I2C (4 + IH2_BASE) |
| 120 | #define INT_MPUIO (5 + IH2_BASE) |
| 121 | #define INT_USB_HHC_1 (6 + IH2_BASE) |
| 122 | #define INT_McBSP3TX (10 + IH2_BASE) |
| 123 | #define INT_McBSP3RX (11 + IH2_BASE) |
| 124 | #define INT_McBSP1TX (12 + IH2_BASE) |
| 125 | #define INT_McBSP1RX (13 + IH2_BASE) |
| 126 | #define INT_UART1 (14 + IH2_BASE) |
| 127 | #define INT_UART2 (15 + IH2_BASE) |
| 128 | #define INT_BT_MCSI1TX (16 + IH2_BASE) |
| 129 | #define INT_BT_MCSI1RX (17 + IH2_BASE) |
| 130 | #define INT_SOSSI_MATCH (19 + IH2_BASE) |
| 131 | #define INT_USB_W2FC (20 + IH2_BASE) |
| 132 | #define INT_1WIRE (21 + IH2_BASE) |
| 133 | #define INT_OS_TIMER (22 + IH2_BASE) |
| 134 | #define INT_MMC (23 + IH2_BASE) |
| 135 | #define INT_GAUGE_32K (24 + IH2_BASE) |
| 136 | #define INT_RTC_TIMER (25 + IH2_BASE) |
| 137 | #define INT_RTC_ALARM (26 + IH2_BASE) |
| 138 | #define INT_MEM_STICK (27 + IH2_BASE) |
| 139 | |
| 140 | /* |
| 141 | * OMAP-1510 specific IRQ numbers for interrupt handler 2 |
| 142 | */ |
| 143 | #define INT_1510_DSP_MMU (28 + IH2_BASE) |
| 144 | #define INT_1510_COM_SPI_RO (31 + IH2_BASE) |
| 145 | |
| 146 | /* |
| 147 | * OMAP-1610 specific IRQ numbers for interrupt handler 2 |
| 148 | */ |
| 149 | #define INT_1610_FAC (0 + IH2_BASE) |
| 150 | #define INT_1610_USB_HHC_2 (7 + IH2_BASE) |
| 151 | #define INT_1610_USB_OTG (8 + IH2_BASE) |
| 152 | #define INT_1610_SoSSI (9 + IH2_BASE) |
| 153 | #define INT_1610_SoSSI_MATCH (19 + IH2_BASE) |
| 154 | #define INT_1610_DSP_MMU (28 + IH2_BASE) |
| 155 | #define INT_1610_McBSP2RX_OF (31 + IH2_BASE) |
| 156 | #define INT_1610_STI (32 + IH2_BASE) |
| 157 | #define INT_1610_STI_WAKEUP (33 + IH2_BASE) |
| 158 | #define INT_1610_GPTIMER3 (34 + IH2_BASE) |
| 159 | #define INT_1610_GPTIMER4 (35 + IH2_BASE) |
| 160 | #define INT_1610_GPTIMER5 (36 + IH2_BASE) |
| 161 | #define INT_1610_GPTIMER6 (37 + IH2_BASE) |
| 162 | #define INT_1610_GPTIMER7 (38 + IH2_BASE) |
| 163 | #define INT_1610_GPTIMER8 (39 + IH2_BASE) |
| 164 | #define INT_1610_GPIO_BANK2 (40 + IH2_BASE) |
| 165 | #define INT_1610_GPIO_BANK3 (41 + IH2_BASE) |
| 166 | #define INT_1610_MMC2 (42 + IH2_BASE) |
| 167 | #define INT_1610_CF (43 + IH2_BASE) |
| 168 | #define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) |
| 169 | #define INT_1610_GPIO_BANK4 (48 + IH2_BASE) |
| 170 | #define INT_1610_SPI (49 + IH2_BASE) |
| 171 | #define INT_1610_DMA_CH6 (53 + IH2_BASE) |
| 172 | #define INT_1610_DMA_CH7 (54 + IH2_BASE) |
| 173 | #define INT_1610_DMA_CH8 (55 + IH2_BASE) |
| 174 | #define INT_1610_DMA_CH9 (56 + IH2_BASE) |
| 175 | #define INT_1610_DMA_CH10 (57 + IH2_BASE) |
| 176 | #define INT_1610_DMA_CH11 (58 + IH2_BASE) |
| 177 | #define INT_1610_DMA_CH12 (59 + IH2_BASE) |
| 178 | #define INT_1610_DMA_CH13 (60 + IH2_BASE) |
| 179 | #define INT_1610_DMA_CH14 (61 + IH2_BASE) |
| 180 | #define INT_1610_DMA_CH15 (62 + IH2_BASE) |
| 181 | #define INT_1610_NAND (63 + IH2_BASE) |
| 182 | #define INT_1610_SHA1MD5 (91 + IH2_BASE) |
| 183 | |
| 184 | /* |
| 185 | * OMAP-7xx specific IRQ numbers for interrupt handler 2 |
| 186 | */ |
| 187 | #define INT_7XX_HW_ERRORS (0 + IH2_BASE) |
| 188 | #define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) |
| 189 | #define INT_7XX_CFCD (2 + IH2_BASE) |
| 190 | #define INT_7XX_CFIREQ (3 + IH2_BASE) |
| 191 | #define INT_7XX_I2C (4 + IH2_BASE) |
| 192 | #define INT_7XX_PCC (5 + IH2_BASE) |
| 193 | #define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) |
| 194 | #define INT_7XX_SPI_100K_1 (7 + IH2_BASE) |
| 195 | #define INT_7XX_SYREN_SPI (8 + IH2_BASE) |
| 196 | #define INT_7XX_VLYNQ (9 + IH2_BASE) |
| 197 | #define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) |
| 198 | #define INT_7XX_McBSP1TX (11 + IH2_BASE) |
| 199 | #define INT_7XX_McBSP1RX (12 + IH2_BASE) |
| 200 | #define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) |
| 201 | #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) |
| 202 | #define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) |
| 203 | #define INT_7XX_MCSI (16 + IH2_BASE) |
| 204 | #define INT_7XX_uWireTX (17 + IH2_BASE) |
| 205 | #define INT_7XX_uWireRX (18 + IH2_BASE) |
| 206 | #define INT_7XX_SMC_CD (19 + IH2_BASE) |
| 207 | #define INT_7XX_SMC_IREQ (20 + IH2_BASE) |
| 208 | #define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) |
| 209 | #define INT_7XX_TIMER32K (22 + IH2_BASE) |
| 210 | #define INT_7XX_MMC_SDIO (23 + IH2_BASE) |
| 211 | #define INT_7XX_UPLD (24 + IH2_BASE) |
| 212 | #define INT_7XX_USB_HHC_1 (27 + IH2_BASE) |
| 213 | #define INT_7XX_USB_HHC_2 (28 + IH2_BASE) |
| 214 | #define INT_7XX_USB_GENI (29 + IH2_BASE) |
| 215 | #define INT_7XX_USB_OTG (30 + IH2_BASE) |
| 216 | #define INT_7XX_CAMERA_IF (31 + IH2_BASE) |
| 217 | #define INT_7XX_RNG (32 + IH2_BASE) |
| 218 | #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) |
| 219 | #define INT_7XX_DBB_RF_EN (34 + IH2_BASE) |
| 220 | #define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) |
| 221 | #define INT_7XX_SHA1_MD5 (36 + IH2_BASE) |
| 222 | #define INT_7XX_SPI_100K_2 (37 + IH2_BASE) |
| 223 | #define INT_7XX_RNG_IDLE (38 + IH2_BASE) |
| 224 | #define INT_7XX_MPUIO (39 + IH2_BASE) |
| 225 | #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) |
| 226 | #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) |
| 227 | #define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) |
| 228 | #define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) |
| 229 | #define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) |
| 230 | #define INT_7XX_DMA_CH6 (53 + IH2_BASE) |
| 231 | #define INT_7XX_DMA_CH7 (54 + IH2_BASE) |
| 232 | #define INT_7XX_DMA_CH8 (55 + IH2_BASE) |
| 233 | #define INT_7XX_DMA_CH9 (56 + IH2_BASE) |
| 234 | #define INT_7XX_DMA_CH10 (57 + IH2_BASE) |
| 235 | #define INT_7XX_DMA_CH11 (58 + IH2_BASE) |
| 236 | #define INT_7XX_DMA_CH12 (59 + IH2_BASE) |
| 237 | #define INT_7XX_DMA_CH13 (60 + IH2_BASE) |
| 238 | #define INT_7XX_DMA_CH14 (61 + IH2_BASE) |
| 239 | #define INT_7XX_DMA_CH15 (62 + IH2_BASE) |
| 240 | #define INT_7XX_NAND (63 + IH2_BASE) |
| 241 | |
| 242 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and |
| 243 | * 16 MPUIO lines */ |
| 244 | #define OMAP_MAX_GPIO_LINES 192 |
| 245 | #define IH_GPIO_BASE (128 + IH2_BASE) |
| 246 | #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) |
| 247 | #define OMAP_IRQ_END (IH_MPUIO_BASE + 16) |
| 248 | |
| 249 | /* External FPGA handles interrupts on Innovator boards */ |
| 250 | #define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) |
| 251 | #ifdef CONFIG_MACH_OMAP_INNOVATOR |
| 252 | #define OMAP_FPGA_NR_IRQS 24 |
| 253 | #else |
| 254 | #define OMAP_FPGA_NR_IRQS 0 |
| 255 | #endif |
| 256 | #define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) |
| 257 | |
| 258 | #define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32)) |
| 259 | |
| 260 | #ifdef CONFIG_FIQ |
| 261 | #define FIQ_START 1024 |
| 262 | #endif |
| 263 | |
| 264 | #endif |