| Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2007-2009 Analog Devices Inc. |
| 3 | * Philippe Gerum <rpm@xenomai.org> |
| 4 | * |
| 5 | * Licensed under the GPL-2 or later. |
| 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_BLACKFIN_SMP_H |
| 9 | #define __ASM_BLACKFIN_SMP_H |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/threads.h> |
| 13 | #include <linux/cpumask.h> |
| 14 | #include <linux/cache.h> |
| 15 | #include <asm/blackfin.h> |
| 16 | #include <mach/smp.h> |
| 17 | |
| 18 | #define raw_smp_processor_id() blackfin_core_id() |
| 19 | |
| 20 | extern void bfin_relocate_coreb_l1_mem(void); |
| 21 | extern void arch_send_call_function_single_ipi(int cpu); |
| 22 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); |
| 23 | |
| 24 | #if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1) |
| 25 | asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr); |
| 26 | extern unsigned long blackfin_iflush_l1_entry[NR_CPUS]; |
| 27 | #endif |
| 28 | |
| 29 | struct corelock_slot { |
| 30 | int lock; |
| 31 | }; |
| 32 | extern struct corelock_slot corelock; |
| 33 | |
| 34 | #ifdef __ARCH_SYNC_CORE_ICACHE |
| 35 | extern unsigned long icache_invld_count[NR_CPUS]; |
| 36 | #endif |
| 37 | #ifdef __ARCH_SYNC_CORE_DCACHE |
| 38 | extern unsigned long dcache_invld_count[NR_CPUS]; |
| 39 | #endif |
| 40 | |
| 41 | void smp_icache_flush_range_others(unsigned long start, |
| 42 | unsigned long end); |
| 43 | #ifdef CONFIG_HOTPLUG_CPU |
| 44 | void coreb_die(void); |
| 45 | void cpu_die(void); |
| 46 | void platform_cpu_die(void); |
| 47 | int __cpu_disable(void); |
| 48 | int __cpu_die(unsigned int cpu); |
| 49 | #endif |
| 50 | |
| 51 | void smp_timer_broadcast(const struct cpumask *mask); |
| 52 | |
| 53 | |
| 54 | #endif /* !__ASM_BLACKFIN_SMP_H */ |