Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * OpenRISC time.c |
| 3 | * |
| 4 | * Linux architectural port borrowing liberally from similar works of |
| 5 | * others. All original copyrights apply as per the original source |
| 6 | * declaration. |
| 7 | * |
| 8 | * Modifications for the OpenRISC architecture: |
| 9 | * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License |
| 13 | * as published by the Free Software Foundation; either version |
| 14 | * 2 of the License, or (at your option) any later version. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/time.h> |
| 19 | #include <linux/timex.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/ftrace.h> |
| 22 | |
| 23 | #include <linux/clocksource.h> |
| 24 | #include <linux/clockchips.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/io.h> |
| 27 | |
| 28 | #include <asm/cpuinfo.h> |
| 29 | |
| 30 | static int openrisc_timer_set_next_event(unsigned long delta, |
| 31 | struct clock_event_device *dev) |
| 32 | { |
| 33 | u32 c; |
| 34 | |
| 35 | /* Read 32-bit counter value, add delta, mask off the low 28 bits. |
| 36 | * We're guaranteed delta won't be bigger than 28 bits because the |
| 37 | * generic timekeeping code ensures that for us. |
| 38 | */ |
| 39 | c = mfspr(SPR_TTCR); |
| 40 | c += delta; |
| 41 | c &= SPR_TTMR_TP; |
| 42 | |
| 43 | /* Set counter and enable interrupt. |
| 44 | * Keep timer in continuous mode always. |
| 45 | */ |
| 46 | mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c); |
| 47 | |
| 48 | return 0; |
| 49 | } |
| 50 | |
| 51 | /* This is the clock event device based on the OR1K tick timer. |
| 52 | * As the timer is being used as a continuous clock-source (required for HR |
| 53 | * timers) we cannot enable the PERIODIC feature. The tick timer can run using |
| 54 | * one-shot events, so no problem. |
| 55 | */ |
| 56 | |
| 57 | static struct clock_event_device clockevent_openrisc_timer = { |
| 58 | .name = "openrisc_timer_clockevent", |
| 59 | .features = CLOCK_EVT_FEAT_ONESHOT, |
| 60 | .rating = 300, |
| 61 | .set_next_event = openrisc_timer_set_next_event, |
| 62 | }; |
| 63 | |
| 64 | static inline void timer_ack(void) |
| 65 | { |
| 66 | /* Clear the IP bit and disable further interrupts */ |
| 67 | /* This can be done very simply... we just need to keep the timer |
| 68 | running, so just maintain the CR bits while clearing the rest |
| 69 | of the register |
| 70 | */ |
| 71 | mtspr(SPR_TTMR, SPR_TTMR_CR); |
| 72 | } |
| 73 | |
| 74 | /* |
| 75 | * The timer interrupt is mostly handled in generic code nowadays... this |
| 76 | * function just acknowledges the interrupt and fires the event handler that |
| 77 | * has been set on the clockevent device by the generic time management code. |
| 78 | * |
| 79 | * This function needs to be called by the timer exception handler and that's |
| 80 | * all the exception handler needs to do. |
| 81 | */ |
| 82 | |
| 83 | irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs) |
| 84 | { |
| 85 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 86 | struct clock_event_device *evt = &clockevent_openrisc_timer; |
| 87 | |
| 88 | timer_ack(); |
| 89 | |
| 90 | /* |
| 91 | * update_process_times() expects us to have called irq_enter(). |
| 92 | */ |
| 93 | irq_enter(); |
| 94 | evt->event_handler(evt); |
| 95 | irq_exit(); |
| 96 | |
| 97 | set_irq_regs(old_regs); |
| 98 | |
| 99 | return IRQ_HANDLED; |
| 100 | } |
| 101 | |
| 102 | static __init void openrisc_clockevent_init(void) |
| 103 | { |
| 104 | clockevent_openrisc_timer.cpumask = cpumask_of(0); |
| 105 | |
| 106 | /* We only have 28 bits */ |
| 107 | clockevents_config_and_register(&clockevent_openrisc_timer, |
| 108 | cpuinfo.clock_frequency, |
| 109 | 100, 0x0fffffff); |
| 110 | |
| 111 | } |
| 112 | |
| 113 | /** |
| 114 | * Clocksource: Based on OpenRISC timer/counter |
| 115 | * |
| 116 | * This sets up the OpenRISC Tick Timer as a clock source. The tick timer |
| 117 | * is 32 bits wide and runs at the CPU clock frequency. |
| 118 | */ |
| 119 | |
| 120 | static cycle_t openrisc_timer_read(struct clocksource *cs) |
| 121 | { |
| 122 | return (cycle_t) mfspr(SPR_TTCR); |
| 123 | } |
| 124 | |
| 125 | static struct clocksource openrisc_timer = { |
| 126 | .name = "openrisc_timer", |
| 127 | .rating = 200, |
| 128 | .read = openrisc_timer_read, |
| 129 | .mask = CLOCKSOURCE_MASK(32), |
| 130 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 131 | }; |
| 132 | |
| 133 | static int __init openrisc_timer_init(void) |
| 134 | { |
| 135 | if (clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency)) |
| 136 | panic("failed to register clocksource"); |
| 137 | |
| 138 | /* Enable the incrementer: 'continuous' mode with interrupt disabled */ |
| 139 | mtspr(SPR_TTMR, SPR_TTMR_CR); |
| 140 | |
| 141 | return 0; |
| 142 | } |
| 143 | |
| 144 | void __init time_init(void) |
| 145 | { |
| 146 | u32 upr; |
| 147 | |
| 148 | upr = mfspr(SPR_UPR); |
| 149 | if (!(upr & SPR_UPR_TTP)) |
| 150 | panic("Linux not supported on devices without tick timer"); |
| 151 | |
| 152 | openrisc_timer_init(); |
| 153 | openrisc_clockevent_init(); |
| 154 | } |