blob: d28d6e95020fe3913a0af333ef24680659f6aee4 [file] [log] [blame]
Kyle Swenson8d8f6542021-03-15 11:02:55 -06001/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/slab.h>
19#include <linux/io.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22
23#include <soc/tegra/fuse.h>
24
25#include "clk.h"
26
27static DEFINE_SPINLOCK(periph_ref_lock);
28
29/* Macros to assist peripheral gate clock */
30#define read_enb(gate) \
31 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
32#define write_enb_set(val, gate) \
33 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
34#define write_enb_clr(val, gate) \
35 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
36
37#define read_rst(gate) \
38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
39#define write_rst_clr(val, gate) \
40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
41
42#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
43
44#define LVL2_CLK_GATE_OVRE 0x554
45
46/* Peripheral gate clock ops */
47static int clk_periph_is_enabled(struct clk_hw *hw)
48{
49 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
50 int state = 1;
51
52 if (!(read_enb(gate) & periph_clk_to_bit(gate)))
53 state = 0;
54
55 if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
56 if (read_rst(gate) & periph_clk_to_bit(gate))
57 state = 0;
58
59 return state;
60}
61
62static int clk_periph_enable(struct clk_hw *hw)
63{
64 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
65 unsigned long flags = 0;
66
67 spin_lock_irqsave(&periph_ref_lock, flags);
68
69 gate->enable_refcnt[gate->clk_num]++;
70 if (gate->enable_refcnt[gate->clk_num] > 1) {
71 spin_unlock_irqrestore(&periph_ref_lock, flags);
72 return 0;
73 }
74
75 write_enb_set(periph_clk_to_bit(gate), gate);
76 udelay(2);
77
78 if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
79 !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
80 if (read_rst(gate) & periph_clk_to_bit(gate)) {
81 udelay(5); /* reset propogation delay */
82 write_rst_clr(periph_clk_to_bit(gate), gate);
83 }
84 }
85
86 if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
87 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
88 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
89 udelay(1);
90 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
91 }
92
93 spin_unlock_irqrestore(&periph_ref_lock, flags);
94
95 return 0;
96}
97
98static void clk_periph_disable(struct clk_hw *hw)
99{
100 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
101 unsigned long flags = 0;
102
103 spin_lock_irqsave(&periph_ref_lock, flags);
104
105 gate->enable_refcnt[gate->clk_num]--;
106 if (gate->enable_refcnt[gate->clk_num] > 0) {
107 spin_unlock_irqrestore(&periph_ref_lock, flags);
108 return;
109 }
110
111 /*
112 * If peripheral is in the APB bus then read the APB bus to
113 * flush the write operation in apb bus. This will avoid the
114 * peripheral access after disabling clock
115 */
116 if (gate->flags & TEGRA_PERIPH_ON_APB)
117 tegra_read_chipid();
118
119 write_enb_clr(periph_clk_to_bit(gate), gate);
120
121 spin_unlock_irqrestore(&periph_ref_lock, flags);
122}
123
124const struct clk_ops tegra_clk_periph_gate_ops = {
125 .is_enabled = clk_periph_is_enabled,
126 .enable = clk_periph_enable,
127 .disable = clk_periph_disable,
128};
129
130struct clk *tegra_clk_register_periph_gate(const char *name,
131 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
132 unsigned long flags, int clk_num, int *enable_refcnt)
133{
134 struct tegra_clk_periph_gate *gate;
135 struct clk *clk;
136 struct clk_init_data init;
137 struct tegra_clk_periph_regs *pregs;
138
139 pregs = get_reg_bank(clk_num);
140 if (!pregs)
141 return ERR_PTR(-EINVAL);
142
143 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
144 if (!gate) {
145 pr_err("%s: could not allocate periph gate clk\n", __func__);
146 return ERR_PTR(-ENOMEM);
147 }
148
149 init.name = name;
150 init.flags = flags;
151 init.parent_names = parent_name ? &parent_name : NULL;
152 init.num_parents = parent_name ? 1 : 0;
153 init.ops = &tegra_clk_periph_gate_ops;
154
155 gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
156 gate->clk_base = clk_base;
157 gate->clk_num = clk_num;
158 gate->flags = gate_flags;
159 gate->enable_refcnt = enable_refcnt;
160 gate->regs = pregs;
161
162 /* Data in .init is copied by clk_register(), so stack variable OK */
163 gate->hw.init = &init;
164
165 clk = clk_register(NULL, &gate->hw);
166 if (IS_ERR(clk))
167 kfree(gate);
168
169 return clk;
170}