| Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | /** |
| 2 | * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. |
| 3 | * |
| 4 | * This source file is released under GPL v2 license (no other versions). |
| 5 | * See the COPYING file included in the main directory of this source |
| 6 | * distribution for the license terms and conditions. |
| 7 | */ |
| 8 | |
| 9 | #ifndef _20K2REGISTERS_H_ |
| 10 | #define _20K2REGISTERS_H_ |
| 11 | |
| 12 | |
| 13 | /* Timer Registers */ |
| 14 | #define WC 0x1b7000 |
| 15 | #define TIMR 0x1b7004 |
| 16 | # define TIMR_IE (1<<15) |
| 17 | # define TIMR_IP (1<<14) |
| 18 | #define GIP 0x1b7010 |
| 19 | #define GIE 0x1b7014 |
| 20 | |
| 21 | /* I2C Registers */ |
| 22 | #define I2C_IF_ADDRESS 0x1B9000 |
| 23 | #define I2C_IF_WDATA 0x1B9004 |
| 24 | #define I2C_IF_RDATA 0x1B9008 |
| 25 | #define I2C_IF_STATUS 0x1B900C |
| 26 | #define I2C_IF_WLOCK 0x1B9010 |
| 27 | |
| 28 | /* Global Control Registers */ |
| 29 | #define GLOBAL_CNTL_GCTL 0x1B7090 |
| 30 | |
| 31 | /* PLL Registers */ |
| 32 | #define PLL_CTL 0x1B7080 |
| 33 | #define PLL_STAT 0x1B7084 |
| 34 | #define PLL_ENB 0x1B7088 |
| 35 | |
| 36 | /* SRC Registers */ |
| 37 | #define SRC_CTL 0x1A0000 /* 0x1A0000 + (256 * Chn) */ |
| 38 | #define SRC_CCR 0x1A0004 /* 0x1A0004 + (256 * Chn) */ |
| 39 | #define SRC_IMAP 0x1A0008 /* 0x1A0008 + (256 * Chn) */ |
| 40 | #define SRC_CA 0x1A0010 /* 0x1A0010 + (256 * Chn) */ |
| 41 | #define SRC_CF 0x1A0014 /* 0x1A0014 + (256 * Chn) */ |
| 42 | #define SRC_SA 0x1A0018 /* 0x1A0018 + (256 * Chn) */ |
| 43 | #define SRC_LA 0x1A001C /* 0x1A001C + (256 * Chn) */ |
| 44 | #define SRC_CTLSWR 0x1A0020 /* 0x1A0020 + (256 * Chn) */ |
| 45 | #define SRC_CD 0x1A0080 /* 0x1A0080 + (256 * Chn) + (4 * Regn) */ |
| 46 | #define SRC_MCTL 0x1A012C |
| 47 | #define SRC_IP 0x1A102C /* 0x1A102C + (256 * Regn) */ |
| 48 | #define SRC_ENB 0x1A282C /* 0x1A282C + (256 * Regn) */ |
| 49 | #define SRC_ENBSTAT 0x1A202C |
| 50 | #define SRC_ENBSA 0x1A232C |
| 51 | #define SRC_DN0Z 0x1A0030 |
| 52 | #define SRC_DN1Z 0x1A0040 |
| 53 | #define SRC_UPZ 0x1A0060 |
| 54 | |
| 55 | /* GPIO Registers */ |
| 56 | #define GPIO_DATA 0x1B7020 |
| 57 | #define GPIO_CTRL 0x1B7024 |
| 58 | #define GPIO_EXT_DATA 0x1B70A0 |
| 59 | |
| 60 | /* Virtual memory registers */ |
| 61 | #define VMEM_PTPAL 0x1C6300 /* 0x1C6300 + (16 * Chn) */ |
| 62 | #define VMEM_PTPAH 0x1C6304 /* 0x1C6304 + (16 * Chn) */ |
| 63 | #define VMEM_CTL 0x1C7000 |
| 64 | |
| 65 | /* Transport Registers */ |
| 66 | #define TRANSPORT_ENB 0x1B6000 |
| 67 | #define TRANSPORT_CTL 0x1B6004 |
| 68 | #define TRANSPORT_INT 0x1B6008 |
| 69 | |
| 70 | /* Audio IO */ |
| 71 | #define AUDIO_IO_AIM 0x1B5000 /* 0x1B5000 + (0x04 * Chn) */ |
| 72 | #define AUDIO_IO_TX_CTL 0x1B5400 /* 0x1B5400 + (0x40 * Chn) */ |
| 73 | #define AUDIO_IO_TX_CSTAT_L 0x1B5408 /* 0x1B5408 + (0x40 * Chn) */ |
| 74 | #define AUDIO_IO_TX_CSTAT_H 0x1B540C /* 0x1B540C + (0x40 * Chn) */ |
| 75 | #define AUDIO_IO_RX_CTL 0x1B5410 /* 0x1B5410 + (0x40 * Chn) */ |
| 76 | #define AUDIO_IO_RX_SRT_CTL 0x1B5420 /* 0x1B5420 + (0x40 * Chn) */ |
| 77 | #define AUDIO_IO_MCLK 0x1B5600 |
| 78 | #define AUDIO_IO_TX_BLRCLK 0x1B5604 |
| 79 | #define AUDIO_IO_RX_BLRCLK 0x1B5608 |
| 80 | |
| 81 | /* Mixer */ |
| 82 | #define MIXER_AMOPLO 0x130000 /* 0x130000 + (8 * Chn) [4095 : 0] */ |
| 83 | #define MIXER_AMOPHI 0x130004 /* 0x130004 + (8 * Chn) [4095 : 0] */ |
| 84 | #define MIXER_PRING_LO_HI 0x188000 /* 0x188000 + (4 * Chn) [4095 : 0] */ |
| 85 | #define MIXER_PMOPLO 0x138000 /* 0x138000 + (8 * Chn) [4095 : 0] */ |
| 86 | #define MIXER_PMOPHI 0x138004 /* 0x138004 + (8 * Chn) [4095 : 0] */ |
| 87 | #define MIXER_AR_ENABLE 0x19000C |
| 88 | |
| 89 | #endif |