diff --git a/board/davinci/dv-evm/dv_board.c b/board/davinci/dv-evm/dv_board.c
index 88b1e57..834eb68 100644
--- a/board/davinci/dv-evm/dv_board.c
+++ b/board/davinci/dv-evm/dv_board.c
@@ -29,14 +29,10 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/emac_defs.h>
 
-#define MACH_TYPE_DAVINCI_EVM		901
-
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void	i2c_init(int speed, int slaveaddr);
 extern void	timer_init(void);
 extern int	eth_hw_init(void);
-extern phy_t	phy;
 
 
 /* Works on Always On power domain only (no PD argument) */
@@ -187,11 +183,8 @@
 		}
 	}
 
-	if (!eth_hw_init()) {
+	if (!eth_hw_init())
 		printf("ethernet init failed!\n");
-	} else {
-		printf("ETH PHY   : %s\n", phy.name);
-	}
 
 	i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1);
 
diff --git a/board/davinci/schmoogie/dv_board.c b/board/davinci/schmoogie/dv_board.c
index 13d2195..3017546 100644
--- a/board/davinci/schmoogie/dv_board.c
+++ b/board/davinci/schmoogie/dv_board.c
@@ -29,14 +29,10 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/emac_defs.h>
 
-#define MACH_TYPE_SCHMOOGIE		1255
-
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void	i2c_init(int speed, int slaveaddr);
 extern void	timer_init(void);
 extern int	eth_hw_init(void);
-extern phy_t	phy;
 
 
 /* Works on Always On power domain only (no PD argument) */
@@ -233,11 +229,8 @@
 		forceenv("serial#", (char *)&tmp[0]);
 	}
 
-	if (!eth_hw_init()) {
+	if (!eth_hw_init())
 		printf("ethernet init failed!\n");
-	} else {
-		printf("ETH PHY   : %s\n", phy.name);
-	}
 
 	return(0);
 }
diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c
index b73484a..f41081f 100644
--- a/board/davinci/sffsdr/sffsdr.c
+++ b/board/davinci/sffsdr/sffsdr.c
@@ -43,7 +43,6 @@
 
 extern void timer_init(void);
 extern int eth_hw_init(void);
-extern phy_t phy;
 
 
 /* Works on Always On power domain only (no PD argument) */
@@ -288,11 +287,8 @@
 		}
 	}
 
-	if (!eth_hw_init()) {
+	if (!eth_hw_init())
 		printf("Ethernet init failed\n");
-	} else {
-		printf("ETH PHY: %s\n", phy.name);
-	}
 
 	/* On this platform, U-Boot is copied in RAM by the UBL,
 	 * so we are always in the relocated state. */
diff --git a/board/davinci/sonata/dv_board.c b/board/davinci/sonata/dv_board.c
index e8665e5..a6f9bc7 100644
--- a/board/davinci/sonata/dv_board.c
+++ b/board/davinci/sonata/dv_board.c
@@ -29,14 +29,10 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/emac_defs.h>
 
-#define MACH_TYPE_SONATA		1254
-
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void	i2c_init(int speed, int slaveaddr);
 extern void	timer_init(void);
 extern int	eth_hw_init(void);
-extern phy_t	phy;
 
 
 /* Works on Always On power domain only (no PD argument) */
@@ -188,11 +184,8 @@
 		}
 	}
 
-	if (!eth_hw_init()) {
+	if (!eth_hw_init())
 		printf("ethernet init failed!\n");
-	} else {
-		printf("ETH PHY   : %s\n", phy.name);
-	}
 
 	return(0);
 }
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 8b13d06..d8631eb 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -1,7 +1,8 @@
 /*
- * Copyright 2006 Freescale Semiconductor
+ * Copyright 2006, 2008 Freescale Semiconductor
  * York Sun (yorksun@freescale.com)
  * Haiying Wang (haiying.wang@freescale.com)
+ * Timur Tabi (timur@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -27,258 +28,443 @@
 #include <i2c.h>
 #include <linux/ctype.h>
 
-typedef struct {
-	u8 id[4];		/* 0x0000 - 0x0003 EEPROM Tag */
-	u8 sn[12];		/* 0x0004 - 0x000F Serial Number */
-	u8 errata[5];		/* 0x0010 - 0x0014 Errata Level */
-	u8 date[6];		/* 0x0015 - 0x001a Build Date */
-	u8 res_0;		/* 0x001b	   Reserved */
-	u8 version[4];		/* 0x001c - 0x001f Version */
-	u8 tempcal[8];		/* 0x0020 - 0x0027 Temperature Calibration Factors*/
-	u8 tempcalsys[2];	/* 0x0028 - 0x0029 System Temperature Calibration Factors*/
-	u8 res_1[22];		/* 0x0020 - 0x003f Reserved */
-	u8 mac_size;		/* 0x0040	   Mac table size */
-	u8 mac_flag;		/* 0x0041	   Mac table flags */
-	u8 mac[8][6];		/* 0x0042 - 0x0071 Mac addresses */
-	u32 crc;		/* 0x0072	   crc32 checksum */
-} EEPROM_data;
+#include "../common/eeprom.h"
 
-static EEPROM_data mac_data;
+#if !defined(CFG_I2C_EEPROM_CCID) && !defined(CFG_I2C_EEPROM_NXID)
+#error "Please define either CFG_I2C_EEPROM_CCID or CFG_I2C_EEPROM_NXID"
+#endif
 
-int mac_show(void)
+/**
+ * static eeprom: EEPROM layout for CCID or NXID formats
+ *
+ * See application note AN3638 for details.
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+#ifdef CFG_I2C_EEPROM_CCID
+	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'CCID' */
+	u8 major;         /* 0x04        Board revision, major */
+	u8 minor;         /* 0x05        Board revision, minor */
+	u8 sn[10];        /* 0x06 - 0x0F Serial Number*/
+	u8 errata[2];     /* 0x10 - 0x11 Errata Level */
+	u8 date[6];       /* 0x12 - 0x17 Build Date */
+	u8 res_0[40];     /* 0x18 - 0x3f Reserved */
+	u8 mac_count;     /* 0x40        Number of MAC addresses */
+	u8 mac_flag;      /* 0x41        MAC table flags */
+	u8 mac[8][6];     /* 0x42 - 0x71 MAC addresses */
+	u32 crc;          /* 0x72        CRC32 checksum */
+#endif
+#ifdef CFG_I2C_EEPROM_NXID
+	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'NXID' */
+	u8 sn[12];        /* 0x04 - 0x0F Serial Number */
+	u8 errata[5];     /* 0x10 - 0x14 Errata Level */
+	u8 date[6];       /* 0x15 - 0x1a Build Date */
+	u8 res_0;         /* 0x1b        Reserved */
+	u32 version;      /* 0x1c - 0x1f NXID Version */
+	u8 tempcal[8];    /* 0x20 - 0x27 Temperature Calibration Factors */
+	u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
+	u8 tempcalflags;  /* 0x2a        Temperature Calibration Flags */
+	u8 res_1[21];     /* 0x2b - 0x3f Reserved */
+	u8 mac_count;     /* 0x40        Number of MAC addresses */
+	u8 mac_flag;      /* 0x41        MAC table flags */
+	u8 mac[8][6];     /* 0x42 - 0x71 MAC addresses */
+	u32 crc;          /* 0x72        CRC32 checksum */
+#endif
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read = 0;
+
+#ifdef CFG_I2C_EEPROM_NXID
+/* Is this a valid NXID EEPROM? */
+#define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D'))
+#endif
+
+#ifdef CFG_I2C_EEPROM_CCID
+/* Is this a valid CCID EEPROM? */
+#define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
+#endif
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
 {
 	int i;
-	u8 mac_size;
-	unsigned char ethaddr[8][18];
-	unsigned char enetvar[32];
+	unsigned int crc;
 
-	/* Show EEPROM tagID,
-	 * always the four characters 'NXID'.
-	 */
-	printf("ID ");
-	for (i = 0; i < 4; i++)
-		printf("%c", mac_data.id[i]);
-	printf("\n");
+	/* EEPROM tag ID, either CCID or NXID */
+#ifdef CFG_I2C_EEPROM_NXID
+	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+		be32_to_cpu(e.version));
+#else
+	printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
+#endif
 
-	/* Show Serial number,
-	 * 0 to 11 charaters of errata information.
-	 */
-	printf("SN ");
-	for (i = 0; i < 12; i++)
-		printf("%c", mac_data.sn[i]);
-	printf("\n");
+	/* Serial number */
+	printf("SN: %s\n", e.sn);
 
-	/* Show Errata Level,
-	 * 0 to 4 characters of errata information.
-	 */
-	printf("Errata ");
-	for (i = 0; i < 5; i++)
-		printf("%c", mac_data.errata[i]);
-	printf("\n");
+	/* Errata level. */
+#ifdef CFG_I2C_EEPROM_NXID
+	printf("Errata: %s\n", e.errata);
+#else
+	printf("Errata: %c%c\n",
+		e.errata[0] ? e.errata[0] : '.',
+		e.errata[1] ? e.errata[1] : '.');
+#endif
 
-	/* Show Build Date,
-	 * BCD date values, as YYMMDDhhmmss.
-	 */
-	printf("Date 20%02x/%02x/%02x %02x:%02x:%02x\n",
-	       mac_data.date[0],
-	       mac_data.date[1],
-	       mac_data.date[2],
-	       mac_data.date[3],
-	       mac_data.date[4],
-	       mac_data.date[5]);
+	/* Build date, BCD date values, as YYMMDDhhmmss */
+	printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+		e.date[0], e.date[1], e.date[2],
+		e.date[3] & 0x7F, e.date[4], e.date[5],
+		e.date[3] & 0x80 ? "PM" : "");
 
-	/* Show MAC table size,
-	 * Value from 0 to 7 indicating how many MAC
-	 * addresses are stored in the system EEPROM.
-	 */
-	if((mac_data.mac_size > 0) && (mac_data.mac_size <= 8))
-		mac_size = mac_data.mac_size;
+	/* Show MAC addresses  */
+	for (i = 0; i < min(e.mac_count, 8); i++) {
+		u8 *p = e.mac[i];
+
+		printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
+			p[0], p[1], p[2], p[3],	p[4], p[5]);
+	}
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+	if (crc == be32_to_cpu(e.crc))
+		printf("CRC: %08x\n", be32_to_cpu(e.crc));
 	else
-		mac_size = 8; /* Set the max size */
-	printf("MACSIZE %x\n", mac_size);
+		printf("CRC: %08x (should be %08x)\n",
+			be32_to_cpu(e.crc), crc);
 
-	/* Show Mac addresses */
-	for (i = 0; i < mac_size; i++) {
-		sprintf((char *)ethaddr[i],
-			"%02x:%02x:%02x:%02x:%02x:%02x",
-			mac_data.mac[i][0],
-			mac_data.mac[i][1],
-			mac_data.mac[i][2],
-			mac_data.mac[i][3],
-			mac_data.mac[i][4],
-			mac_data.mac[i][5]);
-		printf("MAC %d %s\n", i, ethaddr[i]);
-
-		sprintf((char *)enetvar,
-			i ? "eth%daddr" : "ethaddr", i);
-		setenv((char *)enetvar, (char *)ethaddr[i]);
-
+#ifdef DEBUG
+	printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+	for (i = 0; i < sizeof(e); i++) {
+		if ((i % 16) == 0)
+			printf("%02X: ", i);
+		printf("%02X ", ((u8 *)&e)[i]);
+		if (((i % 16) == 15) || (i == sizeof(e) - 1))
+			printf("\n");
 	}
-
-	return 0;
+#endif
 }
 
-int mac_read(void)
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
 {
-	int ret, length;
-	unsigned int crc = 0;
-	unsigned char dev = ID_EEPROM_ADDR, *data;
+	int ret;
+#ifdef CFG_EEPROM_BUS_NUM
+	unsigned int bus;
+#endif
 
-	length = sizeof(EEPROM_data);
-	ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length);
-	if (ret) {
-		printf("Read failed.\n");
-		return -1;
-	}
+	if (has_been_read)
+		return 0;
 
-	data = (unsigned char *)(&mac_data);
-	printf("Check CRC on reading ...");
-	crc = crc32(crc, data, length - 4);
-	if (crc != mac_data.crc) {
-		printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",
-		     mac_data.crc, crc);
-		return -1;
-	} else {
-		printf("CRC OK\n");
-		mac_show();
-	}
-	return 0;
+#ifdef CFG_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CFG_EEPROM_BUS_NUM);
+#endif
+
+	ret = i2c_read(CFG_I2C_EEPROM_ADDR, 0, CFG_I2C_EEPROM_ADDR_LEN,
+		(void *)&e, sizeof(e));
+
+#ifdef CFG_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+	show_eeprom();
+#endif
+
+	has_been_read = (ret == 0) ? 1 : 0;
+
+	return ret;
 }
 
-int mac_prog(void)
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
 {
 	int ret, i, length;
-	unsigned int crc = 0;
-	unsigned char dev = ID_EEPROM_ADDR, *ptr;
-	unsigned char *eeprom_data = (unsigned char *)(&mac_data);
+	unsigned int crc;
+	void *p;
+#ifdef CFG_EEPROM_BUS_NUM
+	unsigned int bus;
+#endif
 
-	mac_data.res_0 = 0;
-	memset((void *)mac_data.res_1, 0, sizeof(mac_data.res_1));
+	/* Set the reserved values to 0xFF   */
+#ifdef CFG_I2C_EEPROM_NXID
+	e.res_0 = 0xFF;
+	memset(e.res_1, 0xFF, sizeof(e.res_1));
+#else
+	memset(e.res_0, 0xFF, sizeof(e.res_0));
+#endif
 
-	length = sizeof(EEPROM_data);
-	crc = crc32(crc, eeprom_data, length - 4);
-	mac_data.crc = crc;
-	for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) {
-		ret = i2c_write(dev, i, 1, ptr, min((length - i),8));
-		udelay(5000);	/* 5ms write cycle timing */
+	length = sizeof(e);
+	crc = crc32(0, (void *)&e, length - 4);
+	e.crc = cpu_to_be32(crc);
+
+#ifdef CFG_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CFG_EEPROM_BUS_NUM);
+#endif
+
+	for (i = 0, p = &e; i < length; i += 8, p += 8) {
+		ret = i2c_write(CFG_I2C_EEPROM_ADDR, i, CFG_I2C_EEPROM_ADDR_LEN,
+			p, min((length - i), 8));
 		if (ret)
 			break;
+		udelay(5000);	/* 5ms write cycle timing */
 	}
+
+#ifdef CFG_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+
 	if (ret) {
 		printf("Programming failed.\n");
 		return -1;
-	} else {
-		printf("Programming %d bytes. Reading back ...\n", length);
-		mac_read();
 	}
+
+	printf("Programming passed.\n");
 	return 0;
 }
 
-int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+	if ((p >= '0') && (p <= '9'))
+		return p - '0';
+
+	if ((p >= 'A') && (p <= 'F'))
+		return (p - 'A') + 10;
+
+	if ((p >= 'a') && (p <= 'f'))
+		return (p - 'a') + 10;
+
+	return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+	unsigned int i;
+
+	if (strlen(string) != 12) {
+		printf("Usage: mac date YYMMDDhhmmss\n");
+		return;
+	}
+
+	for (i = 0; i < 6; i++)
+		e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in one of the MAC address fields of the EEPROM local copy.
+ */
+static void set_mac_address(unsigned int index, const char *string)
+{
+	char *p = (char *) string;
+	unsigned int i;
+
+	if (!string) {
+		printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
+		return;
+	}
+
+	for (i = 0; *p && (i < 6); i++) {
+		e.mac[index][i] = simple_strtoul(p, &p, 16);
+		if (*p == ':')
+			p++;
+	}
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int i;
-	char cmd = 's';
-	unsigned long long mac_val;
+	char cmd;
 
-	if (i2c_probe(ID_EEPROM_ADDR) != 0)
-		return -1;
+	if (argc == 1) {
+		show_eeprom();
+		return 0;
+	}
 
-	if (argc > 1) {
-		cmd = argv[1][0];
+	cmd = argv[1][0];
+
+	if (cmd == 'r') {
+		read_eeprom();
+		return 0;
+	}
+
+	if ((cmd == 'i') && (argc > 2)) {
+		for (i = 0; i < 4; i++)
+			e.id[i] = argv[2][i];
+		return 0;
+	}
+
+	if (!is_valid) {
+		printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
+		return 0;
+	}
+
+	if (argc == 2) {
 		switch (cmd) {
-		case 'r':	/* display */
-			mac_read();
-			break;
 		case 's':	/* save */
-			mac_prog();
+			prog_eeprom();
 			break;
-		case 'i':	/* id */
-			for (i = 0; i < 4; i++) {
-				mac_data.id[i] = argv[2][i];
-			}
-			break;
-		case 'n':	/* serial number */
-			for (i = 0; i < 12; i++) {
-				mac_data.sn[i] = argv[2][i];
-			}
-			break;
-		case 'e':	/* errata */
-			for (i = 0; i < 5; i++) {
-				mac_data.errata[i] = argv[2][i];
-			}
-			break;
-		case 'd':	/* date */
-			mac_val = simple_strtoull(argv[2], NULL, 16);
-			for (i = 0; i < 6; i++) {
-				mac_data.date[i] = (mac_val >> (40 - 8 * i));
-			}
-			break;
-		case 'p':	/* mac table size */
-			mac_data.mac_size =
-			    (unsigned char)simple_strtoul(argv[2], NULL, 16);
-			break;
-		case '0':	/* mac 0 */
-		case '1':	/* mac 1 */
-		case '2':	/* mac 2 */
-		case '3':	/* mac 3 */
-		case '4':	/* mac 4 */
-		case '5':	/* mac 5 */
-		case '6':	/* mac 6 */
-		case '7':	/* mac 7 */
-			mac_val = simple_strtoull(argv[2], NULL, 16);
-			for (i = 0; i < 6; i++) {
-				mac_data.mac[cmd - '0'][i] =
-				    *((unsigned char *)
-				      (((unsigned int)(&mac_val)) + i + 2));
-			}
-			break;
-		case 'h':	/* help */
 		default:
 			printf("Usage:\n%s\n", cmdtp->usage);
 			break;
 		}
-	} else {
-		mac_show();
+
+		return 0;
 	}
+
+	/* We know we have at least one parameter  */
+
+	switch (cmd) {
+	case 'n':	/* serial number */
+		memset(e.sn, 0, sizeof(e.sn));
+		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+		break;
+	case 'e':	/* errata */
+#ifdef CFG_I2C_EEPROM_NXID
+		memset(e.errata, 0, 5);
+		strncpy((char *)e.errata, argv[2], 4);
+#else
+		e.errata[0] = argv[2][0];
+		e.errata[1] = argv[2][1];
+#endif
+		break;
+	case 'd':	/* date BCD format YYMMDDhhmmss */
+		set_date(argv[2]);
+		break;
+	case 'p':	/* MAC table size */
+		e.mac_count = simple_strtoul(argv[2], NULL, 16);
+		break;
+	case '0' ... '7':	/* "mac 0" through "mac 7" */
+		set_mac_address(cmd - '0', argv[2]);
+		break;
+	case 'h':	/* help */
+	default:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		break;
+	}
+
 	return 0;
 }
 
+/**
+ * mac_read_from_eeprom - read the MAC addresses from EEPROM
+ *
+ * This function reads the MAC addresses from EEPROM and sets the
+ * appropriate environment variables for each one read.
+ *
+ * The environment variables are only set if they haven't been set already.
+ * This ensures that any user-saved variables are never overwritten.
+ *
+ * This function must be called after relocation.
+ */
 int mac_read_from_eeprom(void)
 {
-	int length, i;
-	unsigned char dev = ID_EEPROM_ADDR;
-	unsigned char *data;
-	unsigned char ethaddr[4][18];
-	unsigned char enetvar[32];
-	unsigned int crc = 0;
+	unsigned int i;
 
-	length = sizeof(EEPROM_data);
-	if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) {
+	if (read_eeprom()) {
 		printf("Read failed.\n");
 		return -1;
 	}
 
-	data = (unsigned char *)(&mac_data);
-	crc = crc32(crc, data, length - 4);
-	if (crc != mac_data.crc) {
+	if (!is_valid) {
+		printf("Invalid ID (%02x %02x %02x %02x)\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 		return -1;
-	} else {
-		for (i = 0; i < 4; i++) {
-			if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) {
-				sprintf((char *)ethaddr[i],
-					"%02x:%02x:%02x:%02x:%02x:%02x",
-					mac_data.mac[i][0],
-					mac_data.mac[i][1],
-					mac_data.mac[i][2],
-					mac_data.mac[i][3],
-					mac_data.mac[i][4],
-					mac_data.mac[i][5]);
-				sprintf((char *)enetvar,
-					i ? "eth%daddr" : "ethaddr",
-					i);
-				setenv((char *)enetvar, (char *)ethaddr[i]);
-			}
+	}
+
+	if (be32_to_cpu(e.crc) != 0xFFFFFFFF) {
+		u32 crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+		if (crc != be32_to_cpu(e.crc)) {
+			printf("CRC mismatch (%08x != %08x).\n", crc,
+				be32_to_cpu(e.crc));
+			return -1;
 		}
 	}
+
+	for (i = 0; i < min(4, e.mac_count); i++) {
+		if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
+		    memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+			char ethaddr[18];
+			char enetvar[9];
+
+			sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+				e.mac[i][0],
+				e.mac[i][1],
+				e.mac[i][2],
+				e.mac[i][3],
+				e.mac[i][4],
+				e.mac[i][5]);
+			sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
+			/* Only initialize environment variables that are blank
+			 * (i.e. have not yet been set)
+			 */
+			if (!getenv(enetvar))
+				setenv(enetvar, ethaddr);
+		}
+	}
+
 	return 0;
 }
+
+#ifdef CFG_I2C_EEPROM_CCID
+
+/**
+ * get_cpu_board_revision - get the CPU board revision on 85xx boards
+ *
+ * Read the EEPROM to determine the board revision.
+ *
+ * This function is called before relocation, so we need to read a private
+ * copy of the EEPROM into a local variable on the stack.
+ *
+ * Also, we assume that CFG_EEPROM_BUS_NUM == CFG_SPD_BUS_NUM.  The global
+ * variable i2c_bus_num must be compile-time initialized to CFG_SPD_BUS_NUM,
+ * so that the SPD code will work.  This means that all pre-relocation I2C
+ * operations can only occur on the CFG_SPD_BUS_NUM bus.  So if
+ * CFG_EEPROM_BUS_NUM != CFG_SPD_BUS_NUM, then we can't read the EEPROM when
+ * this function is called.  Oh well.
+ */
+unsigned int get_cpu_board_revision(void)
+{
+	struct board_eeprom {
+		u32 id;           /* 0x00 - 0x03 EEPROM Tag 'CCID' */
+		u8 major;         /* 0x04        Board revision, major */
+		u8 minor;         /* 0x05        Board revision, minor */
+	} be;
+
+	i2c_read(CFG_I2C_EEPROM_ADDR, 0, CFG_I2C_EEPROM_ADDR_LEN,
+		(void *)&be, sizeof(be));
+
+	if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
+		return MPC85XX_CPU_BOARD_REV(0, 0);
+
+	if ((be.major == 0xff) && (be.minor == 0xff))
+		return MPC85XX_CPU_BOARD_REV(0, 0);
+
+	return MPC85XX_CPU_BOARD_REV(e.major, e.minor);
+}
+
+#endif
+
diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
index a82dede..54cf36b 100644
--- a/board/freescale/mpc8544ds/law.c
+++ b/board/freescale/mpc8544ds/law.c
@@ -30,7 +30,7 @@
 struct law_entry law_table[] = {
 	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC),
 	SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 8c4b040..c39ce11 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -49,7 +49,10 @@
 	if ((uint)&gur->porpllsr != 0xe00e0000) {
 		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
 	}
-	printf ("Board: MPC8544DS\n");
+	printf ("Board: MPC8544DS, System ID: 0x%02x, "
+		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
+		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
+		in8(PIXIS_BASE + PIXIS_PVER));
 
 	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
 	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
index 61fc609..40e0499 100644
--- a/board/freescale/mpc8544ds/tlb.c
+++ b/board/freescale/mpc8544ds/tlb.c
@@ -79,21 +79,13 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
 
-#ifdef CFG_LBC_CACHE_BASE
 	/*
-	 * TLB 5:	64M	Cacheable, non-guarded
-	 */
-	SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
-#endif
-	/*
-	 * TLB 6:	64M	Non-cacheable, guarded
+	 * TLB 5:	64M	Non-cacheable, guarded
 	 * 0xf8000000	64M	PIXIS 0xF8000000 - 0xFBFFFFFF
 	 */
 	SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_64M, 1),
+		      0, 5, BOOKE_PAGESZ_64M, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds
index 785a006..c66c69f 100644
--- a/board/freescale/mpc8544ds/u-boot.lds
+++ b/board/freescale/mpc8544ds/u-boot.lds
@@ -71,6 +71,7 @@
     lib_generic/crc32.o (.text)
     lib_ppc/extable.o (.text)
     lib_generic/zlib.o (.text)
+    drivers/bios_emulator/atibios.o (.text)
     *(.text)
     *(.fixup)
     *(.got1)
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index 2946ca1..d9e598c 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -33,6 +33,8 @@
 #include <ioports.h>
 #include <spd_sdram.h>
 #include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 long int fixed_sdram (void);
 
@@ -421,7 +423,11 @@
   #ifndef CFG_RAMBOOT
 	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
+#if (CFG_SDRAM_SIZE == 512)
+	ddr->cs0_bnds		= 0x0000000f;
+#else
 	ddr->cs0_bnds		= 0x00000007;
+#endif
 	ddr->cs1_bnds		= 0x0010001f;
 	ddr->cs2_bnds		= 0x00000000;
 	ddr->cs3_bnds		= 0x00000000;
@@ -452,3 +458,29 @@
 	return CFG_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	int node, tmp[2];
+#ifdef CONFIG_PCI
+	const char *path;
+#endif
+
+	ft_cpu_setup(blob, bd);
+
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
+#ifdef CONFIG_PCI
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = hose.last_busno - hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+	}
+}
+#endif
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 3828228..93b144e 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -442,3 +442,90 @@
 		       prop, compat, fdt_strerror(err));
 }
 #endif /* CONFIG_HAS_FSL_DR_USB */
+
+#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx)
+/*
+ * update crypto node properties to a specified revision of the SEC
+ * called with sec_rev == 0 if not on an mpc8xxxE processor
+ */
+void fdt_fixup_crypto_node(void *blob, int sec_rev)
+{
+	const struct sec_rev_prop {
+		u32 sec_rev;
+		u32 num_channels;
+		u32 channel_fifo_len;
+		u32 exec_units_mask;
+		u32 descriptor_types_mask;
+	} sec_rev_prop_list [] = {
+		{ 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
+		{ 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
+		{ 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
+		{ 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
+		{ 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
+		{ 0x0303, 4, 24, 0x97c, 0x03ab0abf }, /* SEC 3.3 */
+	};
+	char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
+			    sizeof("fsl,secX.Y")];
+	int crypto_node, sec_idx, err;
+	char *p;
+	u32 val;
+
+	/* locate crypto node based on lowest common compatible */
+	crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
+	if (crypto_node == -FDT_ERR_NOTFOUND)
+		return;
+
+	/* delete it if not on an E-processor */
+	if (crypto_node > 0 && !sec_rev) {
+		fdt_del_node(blob, crypto_node);
+		return;
+	}
+
+	/* else we got called for possible uprev */
+	for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
+		if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
+			break;
+
+	if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
+		puts("warning: unknown SEC revision number\n");
+		return;
+	}
+
+	val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
+	err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
+	if (err < 0)
+		printf("WARNING: could not set crypto property: %s\n",
+		       fdt_strerror(err));
+
+	val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
+	err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4);
+	if (err < 0)
+		printf("WARNING: could not set crypto property: %s\n",
+		       fdt_strerror(err));
+
+	val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
+	err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
+	if (err < 0)
+		printf("WARNING: could not set crypto property: %s\n",
+		       fdt_strerror(err));
+
+	val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
+	err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
+	if (err < 0)
+		printf("WARNING: could not set crypto property: %s\n",
+		       fdt_strerror(err));
+
+	val = 0;
+	while (sec_idx >= 0) {
+		p = compat_strlist + val;
+		val += sprintf(p, "fsl,sec%d.%d",
+			(sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
+			sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
+		sec_idx--;
+	}
+	err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val);
+	if (err < 0)
+		printf("WARNING: could not set crypto property: %s\n",
+		       fdt_strerror(err));
+}
+#endif /* defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) */
diff --git a/cpu/arm926ejs/davinci/ether.c b/cpu/arm926ejs/davinci/ether.c
index d286ec0..5ae035b 100644
--- a/cpu/arm926ejs/davinci/ether.c
+++ b/cpu/arm926ejs/davinci/ether.c
@@ -357,6 +357,8 @@
 			phy.auto_negotiate = gen_auto_negotiate;
 	}
 
+	printf("Ethernet PHY: %s\n", phy.name);
+
 	return(1);
 }
 
diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c
index 02c4d05..fda85c1 100644
--- a/cpu/mpc83xx/fdt.c
+++ b/cpu/mpc83xx/fdt.c
@@ -26,6 +26,7 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <asm/processor.h>
 
 extern void ft_qe_setup(void *blob);
 
@@ -33,6 +34,23 @@
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
+	immap_t *immr = (immap_t *)CFG_IMMR;
+	int spridr = immr->sysconf.spridr;
+
+	/*
+	 * delete crypto node if not on an E-processor
+	 * initial revisions of the MPC834xE/6xE have the original SEC 2.0.
+	 * EA revisions got the SEC uprevved to 2.4 but since the default device
+	 * tree contains SEC 2.0 properties we uprev them here.
+	 */
+	if (!IS_E_PROCESSOR(spridr))
+		fdt_fixup_crypto_node(blob, 0);
+	else if (IS_E_PROCESSOR(spridr) &&
+		 (SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
+		  SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
+		 REVID_MAJOR(spridr) >= 2)
+		fdt_fixup_crypto_node(blob, 0x0204);
+
 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
 	fdt_fixup_ethernet(blob, bd);
@@ -60,7 +78,7 @@
 
 #ifdef CFG_NS16550
 	do_fixup_by_compat_u32(blob, "ns16550",
-		"clock-frequency", bd->bi_busfreq, 1);
+		"clock-frequency", CFG_NS16550_CLK, 1);
 #endif
 
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 0d50549..bde8e56 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -97,7 +97,7 @@
 	if (cpu) {
 		puts(cpu->name);
 
-		if (svr & 0x80000)
+		if (IS_E_PROCESSOR(svr))
 			puts("E");
 	} else {
 		puts("Unknown");
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 736aef1..4feb751 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -261,37 +261,50 @@
 	volatile uint cache_ctl;
 	uint svr, ver;
 	uint l2srbar;
+	u32 l2siz_field;
 
 	svr = get_svr();
 	ver = SVR_SOC_VER(svr);
 
 	asm("msync;isync");
 	cache_ctl = l2cache->l2ctl;
+	l2siz_field = (cache_ctl >> 28) & 0x3;
 
-	switch (cache_ctl & 0x30000000) {
-	case 0x20000000:
-		if (ver == SVR_8548 || ver == SVR_8548_E ||
-		    ver == SVR_8544 || ver == SVR_8568_E) {
-			puts ("512 KB ");
-			/* set L2E=1, L2I=1, & L2SRAM=0 */
-			cache_ctl = 0xc0000000;
+	switch (l2siz_field) {
+	case 0x0:
+		printf(" unknown size (0x%08x)\n", cache_ctl);
+		return -1;
+		break;
+	case 0x1:
+		if (ver == SVR_8540 || ver == SVR_8560   ||
+		    ver == SVR_8541 || ver == SVR_8541_E ||
+		    ver == SVR_8555 || ver == SVR_8555_E) {
+			puts("128 KB ");
+			/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
+			cache_ctl = 0xc4000000;
 		} else {
 			puts("256 KB ");
-			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
-			cache_ctl = 0xc8000000;
-		}
-		break;
-	case 0x10000000:
-		puts("256 KB ");
-		if (ver == SVR_8544 || ver == SVR_8544_E) {
 			cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 		}
 		break;
-	case 0x30000000:
-	case 0x00000000:
-	default:
-		printf(" unknown size (0x%08x)\n", cache_ctl);
-		return -1;
+	case 0x2:
+		if (ver == SVR_8540 || ver == SVR_8560   ||
+		    ver == SVR_8541 || ver == SVR_8541_E ||
+		    ver == SVR_8555 || ver == SVR_8555_E) {
+			puts("256 KB ");
+			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
+			cache_ctl = 0xc8000000;
+		} else {
+			puts ("512 KB ");
+			/* set L2E=1, L2I=1, & L2SRAM=0 */
+			cache_ctl = 0xc0000000;
+		}
+		break;
+	case 0x3:
+		puts("1024 KB ");
+		/* set L2E=1, L2I=1, & L2SRAM=0 */
+		cache_ctl = 0xc0000000;
+		break;
 	}
 
 	if (l2cache->l2ctl & 0x80000000) {
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 92952e6..c159934 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -29,6 +29,7 @@
 #include <asm/processor.h>
 
 extern void ft_qe_setup(void *blob);
+
 #ifdef CONFIG_MP
 #include "mp.h"
 DECLARE_GLOBAL_DATA_PTR;
@@ -205,6 +206,10 @@
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
+	/* delete crypto node if not on an E-processor */
+	if (!IS_E_PROCESSOR(get_svr()))
+		fdt_fixup_crypto_node(blob, 0);
+
 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
 	fdt_fixup_ethernet(blob, bd);
@@ -224,7 +229,7 @@
 
 #ifdef CFG_NS16550
 	do_fixup_by_compat_u32(blob, "ns16550",
-		"clock-frequency", bd->bi_busfreq, 1);
+		"clock-frequency", CFG_NS16550_CLK, 1);
 #endif
 
 #ifdef CONFIG_CPM2
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 2b5d90e..10fe936 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -188,11 +188,12 @@
 	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h
 	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l
 
-	lis     r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+	/* Align the mapping to 16MB */
+	lis     r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l
 
-	lis     r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(0xff800000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+	lis     r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 
 	mtspr   MAS0,r6
 	mtspr   MAS1,r7
diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c
index 379306e..80a5c78 100644
--- a/cpu/mpc86xx/fdt.c
+++ b/cpu/mpc86xx/fdt.c
@@ -30,6 +30,6 @@
 
 #ifdef CFG_NS16550
 	do_fixup_by_compat_u32(blob, "ns16550",
-			       "clock-frequency", bd->bi_busfreq, 1);
+			       "clock-frequency", CFG_NS16550_CLK, 1);
 #endif
 }
diff --git a/drivers/pci/pci_sh4.c b/drivers/pci/pci_sh4.c
index 1290c0a..057b6dd 100644
--- a/drivers/pci/pci_sh4.c
+++ b/drivers/pci/pci_sh4.c
@@ -74,3 +74,15 @@
 	hose->last_busno = pci_hose_scan(hose);
 	return 0;
 }
+
+int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+	return 0;
+}
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+	return 1;
+}
+#endif /* CONFIG_PCI_SCAN_SHOW */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 10fd478..e617868 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -426,6 +426,7 @@
 /* e500 definitions */
 #define SPRN_L1CFG0	0x203	/* L1 Cache Configuration Register 0 */
 #define SPRN_L1CFG1	0x204	/* L1 Cache Configuration Register 1 */
+#define SPRN_L2CFG0	0x207	/* L2 Cache Configuration Register 0 */
 #define SPRN_L1CSR0	0x3f2	/* L1 Data Cache Control and Status Register 0 */
 #define   L1CSR0_CPE		0x00010000	/* Data Cache Parity Enable */
 #define   L1CSR0_DCFI		0x00000002	/* Data Cache Flash Invalidate */
@@ -434,6 +435,21 @@
 #define   L1CSR1_CPE		0x00010000	/* Instruction Cache Parity Enable */
 #define   L1CSR1_ICFI		0x00000002	/* Instruction Cache Flash Invalidate */
 #define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
+#define SPRN_L1CSR2	0x25e	/* L1 Data Cache Control and Status Register 2 */
+#define SPRN_L2CSR0	0x3f9	/* L2 Data Cache Control and Status Register 0 */
+#define   L2CSR0_L2E		0x80000000	/* L2 Cache Enable */
+#define   L2CSR0_L2PE		0x40000000	/* L2 Cache Parity/ECC Enable */
+#define   L2CSR0_L2WP		0x1c000000	/* L2 I/D Way Partioning */
+#define   L2CSR0_L2CM		0x03000000	/* L2 Cache Coherency Mode */
+#define   L2CSR0_L2FI		0x00200000	/* L2 Cache Flash Invalidate */
+#define   L2CSR0_L2IO		0x00100000	/* L2 Cache Instruction Only */
+#define   L2CSR0_L2DO		0x00010000	/* L2 Cache Data Only */
+#define   L2CSR0_L2REP		0x00003000	/* L2 Line Replacement Algo */
+#define   L2CSR0_L2FL		0x00000800	/* L2 Cache Flush */
+#define   L2CSR0_L2LFC		0x00000400	/* L2 Cache Lock Flash Clear */
+#define   L2CSR0_L2LOA		0x00000080	/* L2 Cache Lock Overflow Allocate */
+#define   L2CSR0_L2LO		0x00000020	/* L2 Cache Lock Overflow */
+#define SPRN_L2CSR1	0x3fa	/* L2 Data Cache Control and Status Register 1 */
 
 #define SPRN_MMUCSR0	0x3f4	/* MMU control and status register 0 */
 #define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
@@ -624,8 +640,12 @@
 #define MCSRR1	SPRN_MCSRR1
 #define L1CSR0	SPRN_L1CSR0
 #define L1CSR1	SPRN_L1CSR1
+#define L1CSR2	SPRN_L1CSR2
 #define L1CFG0	SPRN_L1CFG0
 #define L1CFG1	SPRN_L1CFG1
+#define L2CFG0	SPRN_L2CFG0
+#define L2CSR0	SPRN_L2CSR0
+#define L2CSR1	SPRN_L2CSR1
 #define MCSR	SPRN_MCSR
 #define MMUCSR0	SPRN_MMUCSR0
 #define BUCSR	SPRN_BUCSR
@@ -885,6 +905,15 @@
 /* Some parts define SVR[0:23] as the SOC version */
 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF)	/* SOC Version fields */
 
+/* whether MPC8xxxE (i.e. has SEC) */
+#if defined(CONFIG_MPC85xx)
+#define IS_E_PROCESSOR(svr)	(svr & 0x80000)
+#else
+#if defined(CONFIG_MPC83XX)
+#define IS_E_PROCESSOR(spridr)	(!(spridr & 0x00010000))
+#endif
+#endif
+
 /*
  * SVR_SOC_VER() Version Values
  */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 669f4d7c..091fd2e 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -148,8 +148,6 @@
  */
 #define CFG_BOOT_BLOCK		0xfc000000	/* boot TLB */
 
-#define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable */
-
 #define CFG_FLASH_BASE		0xff800000	/* start of FLASH 8M */
 
 #define CFG_BR0_PRELIM		0xff801001
@@ -158,10 +156,10 @@
 #define CFG_OR0_PRELIM		0xff806e65
 #define CFG_OR1_PRELIM		0xff806e65
 
-#define CFG_FLASH_BANKS_LIST	{0xfe800000,CFG_FLASH_BASE}
+#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE}
 
 #define CFG_FLASH_QUIET_TEST
-#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
 #define CFG_MAX_FLASH_SECT	128		/* sectors per device */
 #undef	CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
@@ -203,30 +201,18 @@
 
 
 /* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM	1
-#define CFG_INIT_L1_LOCK	1
-#define CFG_INIT_L1_ADDR	0xf4010000	/* Initial L1 address */
-#define CFG_INIT_L1_END		0x00004000	/* End of used area in RAM */
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK      1
+#define CFG_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
+#define CFG_INIT_RAM_END       0x00004000      /* End of used area in RAM */
 
-/* define to use L2SRAM as initial stack */
-#undef CONFIG_L2_INIT_RAM
-#define CFG_INIT_L2_ADDR	0xf8fc0000
-#define CFG_INIT_L2_END		0x00040000	/* End of used area in RAM */
-
-#ifdef CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_ADDR	CFG_INIT_L1_ADDR
-#define CFG_INIT_RAM_END	CFG_INIT_L1_END
-#else
-#define CFG_INIT_RAM_ADDR	CFG_INIT_L2_ADDR
-#define CFG_INIT_RAM_END	CFG_INIT_L2_END
-#endif
 
 #define CFG_GBL_DATA_SIZE	128	/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 #define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
@@ -314,6 +300,26 @@
 
 #if defined(CONFIG_PCI)
 
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CFG_PCIE2_IO_PHYS
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET	CFG_PCI1_IO_PHYS*/
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
@@ -382,7 +388,7 @@
 #if CFG_MONITOR_BASE > 0xfff80000
 #define CFG_ENV_ADDR		0xfff80000
 #else
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x70000)
 #endif
 #define CFG_ENV_SIZE		0x2000
 #define CFG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index edf8525..27212162 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -538,29 +538,29 @@
 #define CONFIG_BAUDRATE	115200
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				        \
-   "netdev=eth0\0"                                                      \
-   "consoledev=ttyCPM\0"						\
-   "ramdiskaddr=1000000\0"						\
-   "ramdiskfile=your.ramdisk.u-boot\0"					\
-   "fdtaddr=400000\0"							\
-   "fdtfile=mpc8560ads.dtb\0"
+	"netdev=eth0\0"							\
+	"consoledev=ttyCPM\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=400000\0"						\
+	"fdtfile=mpc8560ads.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \
-   "setenv bootargs root=/dev/nfs rw "                                  \
-      "nfsroot=$serverip:$rootpath "                                    \
-      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"						\
-   "bootm $loadaddr - $fdtaddr"
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND \
-   "setenv bootargs root=/dev/ram rw "                                  \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $ramdiskaddr $ramdiskfile;"                                    \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"						\
-   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
 
 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 98ae34c..06899b1 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -140,11 +140,11 @@
 #endif
 #endif
 
-#define CFG_ID_EEPROM
-#ifdef CFG_ID_EEPROM
 #define CONFIG_ID_EEPROM
-#endif
-#define ID_EEPROM_ADDR		0x57
+#define CFG_I2C_EEPROM_NXID
+#define CFG_ID_EEPROM
+#define CFG_I2C_EEPROM_ADDR     0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
 
 
 #define CFG_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 455e154..cd35494 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -152,11 +152,11 @@
     #define CFG_DDR_CS5_BNDS	0x00000FFF	/* Not done */
 #endif
 
-#define CFG_ID_EEPROM	1
-#ifdef CFG_ID_EEPROM
 #define CONFIG_ID_EEPROM
-#endif
-#define ID_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_NXID
+#define CFG_ID_EEPROM
+#define CFG_I2C_EEPROM_ADDR     0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
 
 /*
  * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index 146eafe..6345cce 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -24,8 +24,8 @@
  * MA 02111-1307 USA
  */
 
-/* mpc8560ads board configuration file */
-/* please refer to doc/README.mpc85xx for more info */
+/* sbc8560 board configuration file */
+/* please refer to doc/README.sbc8560 for more info */
 /* make sure you change the MAC address and other network params first,
  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  */
@@ -102,11 +102,11 @@
 #define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
 #define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
 
-#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
-#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_ECC			/* only for ECC DDR module	*/
+#undef  CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 
 #if defined(CONFIG_MPC85xx_REV1)
-  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
+  #define CONFIG_DDR_DLL		/* possible DLL fix needed	*/
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
@@ -177,8 +177,8 @@
 #define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
-#undef  CONFIG_CONS_ON_SCC			/* define if console on SCC */
-#undef	CONFIG_CONS_NONE			/* define if console on something else */
+#undef  CONFIG_CONS_ON_SCC	/* define if console on SCC */
+#undef	CONFIG_CONS_NONE	/* define if console on something else */
 
 #define CONFIG_CONS_INDEX	1
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
@@ -200,6 +200,11 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT                1
+#define CONFIG_OF_BOARD_SETUP           1
+#define CONFIG_OF_STDOUT_VIA_ALIAS      1
+
 /*
  * I2C
  */
@@ -215,16 +220,28 @@
 #define CFG_PCI_MEM_PHYS	0xC0000000
 #define CFG_PCI_MEM_SIZE	0x10000000
 
-#if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
+#ifdef CONFIG_TSEC_ENET
 
-#  define CONFIG_NET_MULTI	1
-#  define CONFIG_MII		1	/* MII PHY management		*/
-#  define CONFIG_MPC85xx_TSEC1
-#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
-#  define TSEC1_PHY_ADDR	25
-#  define TSEC1_PHYIDX		0
-/* Options are: TSEC0 */
-#  define CONFIG_ETHPRIME		"TSEC0"
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#ifndef CONFIG_MII
+#define CONFIG_MII		1	/* MII PHY management */
+#endif
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0x19
+#define TSEC2_PHY_ADDR		0x1a
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
 
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
 
@@ -272,20 +289,20 @@
  * FLASH and environment organization
  */
 
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant	*/
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver	*/
 #if 0
-#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
-#define CFG_FLASH_PROTECTION		/* use hardware protection		*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)   */
+#define CFG_FLASH_PROTECTION		/* use hardware protection	*/
 #endif
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
 
 #undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/
+#define CFG_FLASH_ERASE_TOUT	200000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	50000	/* Timeout for Flash Write (in ms) */
 
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor	*/
 
 #if 0
 /* XXX This doesn't work and I don't want to fix it */
@@ -315,9 +332,8 @@
   #define CFG_ENV_SIZE		0x2000
 #endif
 
-#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
+#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
 /*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
-#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
 #define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -389,25 +405,57 @@
 #define BOOTFLAG_WARM	0x02		/* Software reboot		*/
 
 #if defined(CONFIG_CMD_KGDB)
-  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
-/*Note: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#  define CONFIG_ETHADDR	00:01:af:07:9b:8a
-#  define CONFIG_HAS_ETH1
-#  define CONFIG_ETH1ADDR	00:01:af:07:9b:8b
-#  define CONFIG_HAS_ETH2
-#  define CONFIG_ETH2ADDR	00:01:af:07:9b:8c
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
 #endif
 
-#define CONFIG_SERVERIP		192.168.0.131
-#define CONFIG_IPADDR		192.168.0.105
-#define CONFIG_GATEWAYIP	0.0.0.0
-#define CONFIG_NETMASK		255.255.255.0
+/* You can compile in a MAC address and your custom net settings by using
+ * the following syntax.  Your board should be marked with the assigned
+ * MAC addresses directly on it.
+ *
+ * #define CONFIG_ETHADDR		de:ad:be:ef:00:00
+ * #define CONFIG_ETH1ADDR		fa:ke:ad:dr:es:s!
+ * #define CONFIG_SERVERIP		<server ip>
+ * #define CONFIG_IPADDR		<board ip>
+ * #define CONFIG_GATEWAYIP		<gateway ip>
+ * #define CONFIG_NETMASK		<your netmask>
+ */
+
 #define CONFIG_HOSTNAME		SBC8560
 #define CONFIG_ROOTPATH		/home/ppc
-#define CONFIG_BOOTFILE		pImage
+#define CONFIG_BOOTFILE		uImage
+
+#define	CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=sbc8560.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_NFSBOOTCOMMAND
 
 #endif	/* __CONFIG_H */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 890993f..a7c6326 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -56,6 +56,12 @@
 static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
 #endif /* CONFIG_HAS_FSL_DR_USB */
 
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83XX)
+void fdt_fixup_crypto_node(void *blob, int sec_rev);
+#else
+static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
+#endif
+
 #ifdef CONFIG_OF_BOARD_SETUP
 void ft_board_setup(void *blob, bd_t *bd);
 void ft_cpu_setup(void *blob, bd_t *bd);
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 939b825..897ecd6 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -61,21 +61,26 @@
 #endif
 
 #define PARTID_NO_E(spridr)		((spridr & 0xFFFE0000) >> 16)
-#define IS_E_PROCESSOR(spridr)		(!(spridr & 0x00010000)) /* has SEC */
+#define SPR_FAMILY(spridr)		((spridr & 0xFFF00000) >> 20)
 
+#define SPR_831X_FAMILY			0x80B
 #define SPR_8311			0x80B2
 #define SPR_8313			0x80B0
 #define SPR_8314			0x80B6
 #define SPR_8315			0x80B4
+#define SPR_832X_FAMILY			0x806
 #define SPR_8321			0x8066
 #define SPR_8323			0x8062
+#define SPR_834X_FAMILY			0x803
 #define SPR_8343			0x8036
 #define SPR_8347_TBGA_			0x8032
 #define SPR_8347_PBGA_			0x8034
 #define SPR_8349			0x8030
+#define SPR_836X_FAMILY			0x804
 #define SPR_8358_TBGA_			0x804A
 #define SPR_8358_PBGA_			0x804E
 #define SPR_8360			0x8048
+#define SPR_837X_FAMILY			0x80C
 #define SPR_8377			0x80C6
 #define SPR_8378			0x80C4
 #define SPR_8379			0x80C2