Fix variable flavor in examples/standalone/Makefile
GNU Makefile have two flavors of variables, recursively expanded that is
defined by using '=', and simply expanded that is defined by using ':='.
The bug is caused by using recursively expanded flavor for BIN and SREC.
As you can see below, they are prepended by $(obj) twice.
We can reproduce this bug with a simplified version of this Makefile:
$ cat >Makefile <<\EOF
obj := /path/to/obj/
ELF := hello_world
BIN_rec = $(addsuffix .bin,$(ELF)) # recursively expanded
BIN_sim := $(addsuffix .bin,$(ELF)) # simply expanded
ELF := $(addprefix $(obj),$(ELF))
BIN_rec := $(addprefix $(obj),$(BIN_rec))
BIN_sim := $(addprefix $(obj),$(BIN_sim))
show:
@echo BIN_rec=$(BIN_rec)
@echo BIN_sim=$(BIN_sim)
.PHONY: show
EOF
$ make show
BIN_rec=/path/to/obj//path/to/obj/hello_world.bin
BIN_sim=/path/to/obj/hello_world.bin
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
1 file changed