* Patch by Steven Scholz, 25 Feb 2004:
- Timeouts in FPGA code should be based on CFG_HZ
- Minor cleanup in code for Altera FPGA ACEX1K
* Patch by Steven Scholz, 25 Feb 2004:
Changed "Directory Hierarchy" section in README
* Patch by Masami Komiya, 25 Feb 2004:
Reduce copy count in nfs_read_reply() of NFS code
diff --git a/common/ACEX1K.c b/common/ACEX1K.c
index 53b2f50..2a421e2 100644
--- a/common/ACEX1K.c
+++ b/common/ACEX1K.c
@@ -31,17 +31,12 @@
#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
/* Define FPGA_DEBUG to get debug printf's */
-/* #define FPGA_DEBUG */
-
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
-#undef CFG_FPGA_CHECK_BUSY
-#define CFG_FPGA_PROG_FEEDBACK
-
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
@@ -52,7 +47,7 @@
#endif
#ifndef CFG_FPGA_WAIT
-#define CFG_FPGA_WAIT 100
+#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */
#endif
static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
@@ -162,7 +157,7 @@
__FUNCTION__, &fn, fn, fn->config, fn->status,
fn->clk, fn->data, fn->done);
#ifdef CFG_FPGA_PROG_FEEDBACK
- printf ("Loading FPGA Device %d (@ %ld)...\n", cookie, ts);
+ printf ("Loading FPGA Device %d...", cookie);
#endif
/*
@@ -246,7 +241,7 @@
CONFIG_FPGA_DELAY ();
#ifdef CFG_FPGA_PROG_FEEDBACK
- putc ('\n'); /* terminate the dotted line */
+ putc (' '); /* terminate the dotted line */
#endif
/*