Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
diff --git a/MAINTAINERS b/MAINTAINERS
index b3a45cc..394be1e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -112,12 +112,10 @@
S: Maintained
T: git git://git.denx.de/u-boot-samsung.git
F: arch/arm/cpu/arm920t/s3c24x0/
-F: arch/arm/cpu/armv7/exynos/
-F: arch/arm/cpu/armv7/s5pc1xx/
+F: arch/arm/mach-exynos/
+F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
-F: arch/arm/include/asm/arch-exynos/
F: arch/arm/include/asm/arch-s3c24x0/
-F: arch/arm/include/asm/arch-s5pc1xx/
ARM STM SPEAR
M: Vipin Kumar <vipin.kumar@st.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b493b17..408e4ff 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -739,7 +739,7 @@
source "arch/arm/mach-rockchip/Kconfig"
-source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
+source "arch/arm/mach-s5pc1xx/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 58f9bbb..18283d1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -53,6 +53,7 @@
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
+machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_TEGRA) += tegra
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index c8d1422..45f346c 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -49,7 +49,6 @@
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/
obj-$(CONFIG_RMOBILE) += rmobile/
-obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_VF610) += vf610/
diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi
index 5175f03..fa0bd7d 100644
--- a/arch/arm/dts/socfpga_arria5.dtsi
+++ b/arch/arm/dts/socfpga_arria5.dtsi
@@ -25,6 +25,8 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ drvsel = <3>;
+ smplsel = <0>;
};
sysmgr@ffd08000 {
diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi
index de36209..040b236 100644
--- a/arch/arm/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5.dtsi
@@ -25,6 +25,8 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ drvsel = <3>;
+ smplsel = <0>;
};
sysmgr@ffd08000 {
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 6782691..05b935d 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -19,6 +19,10 @@
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
};
&gmac1 {
@@ -37,6 +41,7 @@
&mmc0 {
status = "okay";
+ u-boot,dm-pre-reloc;
};
&qspi {
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index f7737bf..9205b1e 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -49,6 +49,9 @@
config TARGET_NAS220
bool "BlackArmor NAS220"
+config TARGET_NSA310S
+ bool "Zyxel NSA310S"
+
endchoice
config SYS_SOC
@@ -69,5 +72,6 @@
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
source "board/Seagate/nas220/Kconfig"
+source "board/zyxel/nsa310s/Kconfig"
endif
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
index 9dde710..1d49cab 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -70,6 +70,8 @@
#define CONFIG_PHYLIB
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT 200
+#define CONFIG_NET_RETRY_COUNT 50
#endif /* CONFIG_CMD_NET */
/*
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig
similarity index 100%
rename from arch/arm/cpu/armv7/s5pc1xx/Kconfig
rename to arch/arm/mach-s5pc1xx/Kconfig
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/mach-s5pc1xx/Makefile
similarity index 100%
rename from arch/arm/cpu/armv7/s5pc1xx/Makefile
rename to arch/arm/mach-s5pc1xx/Makefile
diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c
similarity index 100%
rename from arch/arm/cpu/armv7/s5pc1xx/cache.c
rename to arch/arm/mach-s5pc1xx/cache.c
diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/mach-s5pc1xx/clock.c
similarity index 100%
rename from arch/arm/cpu/armv7/s5pc1xx/clock.c
rename to arch/arm/mach-s5pc1xx/clock.c
diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/mach-s5pc1xx/include/mach/clk.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/clk.h
rename to arch/arm/mach-s5pc1xx/include/mach/clk.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/clock.h b/arch/arm/mach-s5pc1xx/include/mach/clock.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/clock.h
rename to arch/arm/mach-s5pc1xx/include/mach/clock.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/mach-s5pc1xx/include/mach/cpu.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/cpu.h
rename to arch/arm/mach-s5pc1xx/include/mach/cpu.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/mach-s5pc1xx/include/mach/gpio.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/gpio.h
rename to arch/arm/mach-s5pc1xx/include/mach/gpio.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/mach-s5pc1xx/include/mach/mmc.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/mmc.h
rename to arch/arm/mach-s5pc1xx/include/mach/mmc.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h b/arch/arm/mach-s5pc1xx/include/mach/periph.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/periph.h
rename to arch/arm/mach-s5pc1xx/include/mach/periph.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h b/arch/arm/mach-s5pc1xx/include/mach/pinmux.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/pinmux.h
rename to arch/arm/mach-s5pc1xx/include/mach/pinmux.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/power.h b/arch/arm/mach-s5pc1xx/include/mach/power.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/power.h
rename to arch/arm/mach-s5pc1xx/include/mach/power.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/mach-s5pc1xx/include/mach/pwm.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/pwm.h
rename to arch/arm/mach-s5pc1xx/include/mach/pwm.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/sromc.h b/arch/arm/mach-s5pc1xx/include/mach/sromc.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/sromc.h
rename to arch/arm/mach-s5pc1xx/include/mach/sromc.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h b/arch/arm/mach-s5pc1xx/include/mach/sys_proto.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/sys_proto.h
rename to arch/arm/mach-s5pc1xx/include/mach/sys_proto.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/uart.h b/arch/arm/mach-s5pc1xx/include/mach/uart.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/uart.h
rename to arch/arm/mach-s5pc1xx/include/mach/uart.h
diff --git a/arch/arm/include/asm/arch-s5pc1xx/watchdog.h b/arch/arm/mach-s5pc1xx/include/mach/watchdog.h
similarity index 100%
rename from arch/arm/include/asm/arch-s5pc1xx/watchdog.h
rename to arch/arm/mach-s5pc1xx/include/mach/watchdog.h
diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/mach-s5pc1xx/reset.S
similarity index 100%
rename from arch/arm/cpu/armv7/s5pc1xx/reset.S
rename to arch/arm/mach-s5pc1xx/reset.S
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a413ea4..e4cc468 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -22,6 +22,10 @@
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_EBV_SOCRATES
+ bool "EBV SoCrates (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -38,11 +42,13 @@
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+ default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
@@ -55,5 +61,6 @@
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
endif
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
new file mode 100644
index 0000000..a7056d4
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
+#define _SOCFPGA_A10_BASE_HARDWARE_H_
+
+#define SOCFPGA_EMAC0_ADDRESS 0xff800000
+#define SOCFPGA_EMAC1_ADDRESS 0xff802000
+#define SOCFPGA_EMAC2_ADDRESS 0xff804000
+#define SOCFPGA_SDMMC_ADDRESS 0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS 0xff809000
+#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000
+#define SOCFPGA_UART1_ADDRESS 0xffc02100
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400
+#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd06000
+#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200
+#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300
+#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400
+#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
+#define SOCFPGA_MPUSCU_ADDRESS 0xffffc000
+#define SOCFPGA_MPUL2_ADDRESS 0xfffff000
+#define SOCFPGA_I2C0_ADDRESS 0xffc02200
+#define SOCFPGA_I2C1_ADDRESS 0xffc02300
+
+#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#define SOCFPGA_SDR_ADDRESS 0xffcfb000
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400
+#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400
+
+#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
similarity index 100%
rename from arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h
rename to arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 666a2ef..e50fbd8 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -25,6 +25,7 @@
u32 per2_mod_reset;
u32 brg_mod_reset;
u32 misc_mod_reset;
+ u32 padding2[12];
u32 tstscratch;
};
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 945e771..efd3165 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -152,7 +152,7 @@
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
-source "board/lwmon5/Kconfig"
+source "board/liebherr/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 77d4040..3dd0557 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -1795,34 +1795,11 @@
..no_pllset:
#endif /* CONFIG_BUBINGA */
-#ifdef CONFIG_TAIHU
- mfdcr r4, CPC0_BOOT
- andi. r5, r4, CPC0_BOOT_SEP@l
- bne strap_1 /* serial eeprom present */
- addis r5,0,CPLD_REG0_ADDR@h
- ori r5,r5,CPLD_REG0_ADDR@l
- andi. r5, r5, 0x10
- bne _pci_66mhz
-#endif /* CONFIG_TAIHU */
-
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT@l /* */
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
ori r4,r4,PLLMR1_DEFAULT@l /* */
-#ifdef CONFIG_TAIHU
- b 1f
-_pci_66mhz:
- addis r3,0,PLLMR0_DEFAULT_PCI66@h
- ori r3,r3,PLLMR0_DEFAULT_PCI66@l
- addis r4,0,PLLMR1_DEFAULT_PCI66@h
- ori r4,r4,PLLMR1_DEFAULT_PCI66@l
- b 1f
-strap_1:
- mfdcr r3, CPC0_PLLMR0
- mfdcr r4, CPC0_PLLMR1
-#endif /* CONFIG_TAIHU */
-
1:
b pll_write /* Write the CPC0_PLLMR with new value */
diff --git a/board/ebv/socrates/MAINTAINERS b/board/ebv/socrates/MAINTAINERS
new file mode 100644
index 0000000..e48236f
--- /dev/null
+++ b/board/ebv/socrates/MAINTAINERS
@@ -0,0 +1,6 @@
+SOCRATES BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/ebv/socrates/
+F: include/configs/socfpga_socrates.h
+F: configs/socfpga_socrates_defconfig
diff --git a/board/ebv/socrates/Makefile b/board/ebv/socrates/Makefile
new file mode 100644
index 0000000..86f9b78
--- /dev/null
+++ b/board/ebv/socrates/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o
diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h
new file mode 100644
index 0000000..f1bbe68
--- /dev/null
+++ b/board/ebv/socrates/qts/iocsr_config.h
@@ -0,0 +1,660 @@
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00004824,
+ 0x01209000,
+ 0x82400000,
+ 0x00018004,
+ 0x00000000,
+ 0x00004000,
+ 0x00002412,
+ 0x00904800,
+ 0x41200000,
+ 0x80000002,
+ 0x00000904,
+ 0x00002000,
+ 0x00001209,
+ 0x00482400,
+ 0x20900000,
+ 0x40000001,
+ 0x00000482,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x00009048,
+ 0x02412000,
+ 0x048000C0,
+ 0x00000009,
+ 0x00002412,
+ 0x00008000,
+ 0x00004824,
+ 0x01209000,
+ 0x82400000,
+ 0x00000004,
+ 0x00001209,
+ 0x00004000,
+ 0x00002412,
+ 0x00904800,
+ 0x41200000,
+ 0x80000002,
+ 0x00000904,
+ 0x00002000,
+ 0x06001209,
+ 0x00482400,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x80001000,
+ 0x00000904,
+ 0x00241200,
+ 0x90480000,
+ 0x20003000,
+ 0x00000241,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x48240000,
+ 0x90000000,
+ 0x00000120,
+ 0x00000400,
+ 0x00000000,
+ 0x00090480,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x90000200,
+ 0x00600120,
+ 0x00000000,
+ 0x12090000,
+ 0x24000600,
+ 0x00000048,
+ 0x48000100,
+ 0x00300090,
+ 0xC0024120,
+ 0x09048000,
+ 0x12000300,
+ 0x000C0024,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x30009048,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x0C002412,
+ 0x00008000,
+ 0x18004824,
+ 0x00000000,
+ 0x82400000,
+ 0x00018004,
+ 0x06001209,
+ 0x00004000,
+ 0x20002412,
+ 0x00904800,
+ 0x00000030,
+ 0x80000000,
+ 0x03000904,
+ 0x00002000,
+ 0x10001209,
+ 0x00482400,
+ 0x20900000,
+ 0x40010001,
+ 0x00000482,
+ 0x80001000,
+ 0x00000904,
+ 0x00000000,
+ 0x90480000,
+ 0x20008000,
+ 0x00C00241,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x0CC20D80,
+ 0x0C3000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x45034030,
+ 0x12481A01,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A01450,
+ 0x280D0000,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD000001A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000FF0,
+ 0x4810C000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x24086001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x49034030,
+ 0x12481A02,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A00040,
+ 0x280D0002,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD00A281A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xF228A3D5,
+ 0xF6D1451E,
+ 0x0342E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x05140680,
+ 0xD949247A,
+ 0x1EF228A3,
+ 0x88F6D145,
+ 0x000352E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x86120800,
+ 0x00600240,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xF3CF23D5,
+ 0xF4D1451E,
+ 0x034A9248,
+ 0x821A038E,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EF3CF23,
+ 0x88F4D145,
+ 0x000352E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xF228A3D9,
+ 0xF4D1451E,
+ 0x034A9248,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EF228A3,
+ 0x88F4D145,
+ 0x000352E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x08864000,
+ 0x49247A02,
+ 0xF3CF23D9,
+ 0xF4D1451E,
+ 0x0342E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EF3CF23,
+ 0x88F4DE79,
+ 0x000342A2,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x40002000,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x08000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x20001000,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/ebv/socrates/qts/pinmux_config.h b/board/ebv/socrates/qts/pinmux_config.h
new file mode 100644
index 0000000..4bb654f
--- /dev/null
+++ b/board/ebv/socrates/qts/pinmux_config.h
@@ -0,0 +1,219 @@
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 1, /* GENERALIO3 */
+ 1, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 3, /* GENERALIO9 */
+ 3, /* GENERALIO10 */
+ 3, /* GENERALIO11 */
+ 3, /* GENERALIO12 */
+ 2, /* GENERALIO13 */
+ 2, /* GENERALIO14 */
+ 1, /* GENERALIO15 */
+ 1, /* GENERALIO16 */
+ 1, /* GENERALIO17 */
+ 1, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h
new file mode 100644
index 0000000..c5aea9d
--- /dev/null
+++ b/board/ebv/socrates/qts/pll_config.h
@@ -0,0 +1,85 @@
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h
new file mode 100644
index 0000000..cf9d1d3
--- /dev/null
+++ b/board/ebv/socrates/qts/sdram_config.h
@@ -0,0 +1,341 @@
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ 0x4C
+#define RW_MGR_GUARANTEED_READ_CONT 0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7B
+#define RW_MGR_IDLE_LOOP2 0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1 0x61
+#define RW_MGR_READ_B2B_WAIT2 0x6B
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7D
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 375
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 82
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 82
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080221,
+ 0x10080320,
+ 0x10090044,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080241,
+ 0x100802c0,
+ 0x100a0024,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c
new file mode 100644
index 0000000..a1dbc49
--- /dev/null
+++ b/board/ebv/socrates/socfpga.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
+#include <micrel.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret;
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+ if (ret)
+ return ret;
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+struct s3c_plat_otg_data socfpga_otg_data = {
+ .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return s3c_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
diff --git a/board/lwmon5/Kconfig b/board/liebherr/lwmon5/Kconfig
similarity index 78%
rename from board/lwmon5/Kconfig
rename to board/liebherr/lwmon5/Kconfig
index 7b8c605..7f1bb40 100644
--- a/board/lwmon5/Kconfig
+++ b/board/liebherr/lwmon5/Kconfig
@@ -3,6 +3,9 @@
config SYS_BOARD
default "lwmon5"
+config SYS_VENDOR
+ default "liebherr"
+
config SYS_CONFIG_NAME
default "lwmon5"
diff --git a/board/lwmon5/MAINTAINERS b/board/liebherr/lwmon5/MAINTAINERS
similarity index 80%
rename from board/lwmon5/MAINTAINERS
rename to board/liebherr/lwmon5/MAINTAINERS
index 3ea1888..df45730 100644
--- a/board/lwmon5/MAINTAINERS
+++ b/board/liebherr/lwmon5/MAINTAINERS
@@ -1,6 +1,6 @@
LWMON5 BOARD
M: Stefan Roese <sr@denx.de>
S: Maintained
-F: board/lwmon5/
+F: board/liebherr/lwmon5/
F: include/configs/lwmon5.h
F: configs/lwmon5_defconfig
diff --git a/board/lwmon5/Makefile b/board/liebherr/lwmon5/Makefile
similarity index 100%
rename from board/lwmon5/Makefile
rename to board/liebherr/lwmon5/Makefile
diff --git a/board/lwmon5/config.mk b/board/liebherr/lwmon5/config.mk
similarity index 100%
rename from board/lwmon5/config.mk
rename to board/liebherr/lwmon5/config.mk
diff --git a/board/lwmon5/init.S b/board/liebherr/lwmon5/init.S
similarity index 100%
rename from board/lwmon5/init.S
rename to board/liebherr/lwmon5/init.S
diff --git a/board/lwmon5/kbd.c b/board/liebherr/lwmon5/kbd.c
similarity index 100%
rename from board/lwmon5/kbd.c
rename to board/liebherr/lwmon5/kbd.c
diff --git a/board/lwmon5/lwmon5.c b/board/liebherr/lwmon5/lwmon5.c
similarity index 100%
rename from board/lwmon5/lwmon5.c
rename to board/liebherr/lwmon5/lwmon5.c
diff --git a/board/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c
similarity index 100%
rename from board/lwmon5/sdram.c
rename to board/liebherr/lwmon5/sdram.c
diff --git a/board/zyxel/nsa310s/Kconfig b/board/zyxel/nsa310s/Kconfig
new file mode 100644
index 0000000..77e734d
--- /dev/null
+++ b/board/zyxel/nsa310s/Kconfig
@@ -0,0 +1,20 @@
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if TARGET_NSA310S
+
+config SYS_BOARD
+ default "nsa310s"
+
+config SYS_VENDOR
+ default "zyxel"
+
+config SYS_CONFIG_NAME
+ default "nsa310s"
+
+endif
diff --git a/board/zyxel/nsa310s/MAINTAINERS b/board/zyxel/nsa310s/MAINTAINERS
new file mode 100644
index 0000000..d153758
--- /dev/null
+++ b/board/zyxel/nsa310s/MAINTAINERS
@@ -0,0 +1,8 @@
+NSA310S BOARD
+M: Gerald Kerma <dreagle@doukki.net>
+M: Tony Dinh <mibodhi@gmail.com>
+M: Luka Perkov <luka.perkov@sartura.hr>
+S: Maintained
+F: board/zyxel/nsa310s/
+F: include/configs/nsa310s.h
+F: configs/nsa310s_defconfig
diff --git a/board/zyxel/nsa310s/Makefile b/board/zyxel/nsa310s/Makefile
new file mode 100644
index 0000000..43cdb86
--- /dev/null
+++ b/board/zyxel/nsa310s/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nsa310s.o
diff --git a/board/zyxel/nsa310s/kwbimage.cfg b/board/zyxel/nsa310s/kwbimage.cfg
new file mode 100644
index 0000000..e8f4b8a
--- /dev/null
+++ b/board/zyxel/nsa310s/kwbimage.cfg
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer to doc/README.kwbimage for more details about how-to
+# configure and create kirkwood boot images.
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD01400 0x43010c30
+DATA 0xFFD01404 0x39543000
+DATA 0xFFD01408 0x22125451
+DATA 0xFFD0140C 0x00000833
+DATA 0xFFD01410 0x0000000C
+DATA 0xFFD01414 0x00000000
+DATA 0xFFD01418 0x00000000
+DATA 0xFFD0141C 0x00000652
+DATA 0xFFD01420 0x00000004
+DATA 0xFFD01424 0x0000F17F
+DATA 0xFFD01428 0x00085520
+DATA 0xFFD0147c 0x00008552
+DATA 0xFFD01504 0x0FFFFFF1
+DATA 0xFFD01508 0x10000000
+DATA 0xFFD0150C 0x00000000
+DATA 0xFFD01514 0x00000000
+DATA 0xFFD0151C 0x00000000
+DATA 0xFFD01494 0x00010000
+DATA 0xFFD01498 0x00000000
+DATA 0xFFD0149C 0x0000E403
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0x0 0x0
diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c
new file mode 100644
index 0000000..aab33cf
--- /dev/null
+++ b/board/zyxel/nsa310s/nsa310s.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+#include "nsa310s.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
+ NSA310S_OE_LOW, NSA310S_OE_HIGH);
+
+ /* (all LEDs & power off active high) */
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+ u16 reg;
+ u16 phyaddr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* read PHY dev address */
+ if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
+ printf("could not read PHY dev address\n");
+ return;
+ }
+
+ /* set RGMII delay */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
+ miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
+ reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
+ miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+ /* reset PHY */
+ if (miiphy_reset(name, phyaddr))
+ return;
+
+ /*
+ * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
+ * and has an MCU attached to the LED[2] via tristate interrupt
+ */
+
+ /* switch to LED register page */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
+ /* read out LED polarity register */
+ miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®);
+ /* clear 4, set 5 - LED2 low, tri-state */
+ reg &= ~(MV88E1318_LED2_4);
+ reg |= (MV88E1318_LED2_5);
+ /* write back LED polarity register */
+ miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
+ /* jump back to page 0, per the PHY chip documenation. */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+ /* set PHY back to auto-negotiation mode */
+ miiphy_write(name, phyaddr, 0x4, 0x1e1);
+ miiphy_write(name, phyaddr, 0x9, 0x300);
+ /* downshift */
+ miiphy_write(name, phyaddr, 0x10, 0x3860);
+ miiphy_write(name, phyaddr, 0x0, 0x9140);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/zyxel/nsa310s/nsa310s.h b/board/zyxel/nsa310s/nsa310s.h
new file mode 100644
index 0000000..1ea1105
--- /dev/null
+++ b/board/zyxel/nsa310s/nsa310s.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __NSA310S_H
+#define __NSA310S_H
+
+/* low GPIO's */
+#define HDD1_GREEN_LED (1 << 16)
+#define HDD1_RED_LED (1 << 13)
+#define USB_GREEN_LED (1 << 15)
+#define USB_POWER (1 << 21)
+#define SYS_GREEN_LED (1 << 28)
+#define SYS_ORANGE_LED (1 << 29)
+
+#define COPY_GREEN_LED (1 << 22)
+#define COPY_RED_LED (1 << 23)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA310S_OE_LOW (~(0))
+#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/* high GPIO's */
+#define HDD2_GREEN_LED (1 << 2)
+#define HDD2_POWER (1 << 1)
+
+#define NSA310S_OE_HIGH (~(0))
+#define NSA310S_VAL_HIGH (HDD2_POWER)
+
+/* PHY related */
+#define MV88E1318_PGADR_REG 22
+#define MV88E1318_MAC_CTRL_PG 2
+#define MV88E1318_MAC_CTRL_REG 21
+#define MV88E1318_RGMII_TX_CTRL (1 << 4)
+#define MV88E1318_RGMII_RX_CTRL (1 << 5)
+#define MV88E1318_LED_PG 3
+#define MV88E1318_LED_POL_REG 17
+#define MV88E1318_LED2_4 (1 << 4)
+#define MV88E1318_LED2_5 (1 << 5)
+
+#endif /* __NSA310S_H */
diff --git a/common/lcd.c b/common/lcd.c
index d29308a..ed68be9 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -143,6 +143,16 @@
return *line_length * panel_info.vl_row;
}
+/*
+ * Implement a weak default function for boards that optionally
+ * need to skip the lcd console initialization.
+ */
+__weak int board_lcd_console_skip(void)
+{
+ /* As default, don't skip cfb init */
+ return 0;
+}
+
int drv_lcd_init(void)
{
struct stdio_dev lcddev;
@@ -152,6 +162,9 @@
lcd_init(lcd_base);
+ if (board_lcd_console_skip())
+ return 0;
+
/* Device initialization */
memset(&lcddev, 0, sizeof(lcddev));
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
new file mode 100644
index 0000000..6b3f28a
--- /dev/null
+++ b/configs/nsa310s_defconfig
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_TARGET_NSA310S=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_PROMPT="nsa310s => "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_USB=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 462b2fd..d391f46 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -3,7 +3,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
+CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y
@@ -11,6 +11,7 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 8076761..2bd0ebd 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -19,21 +19,23 @@
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
-static void socfpga_dwmci_clksel(struct dwmci_host *host)
-{
+/* socfpga implmentation specific drver private data */
+struct dwmci_socfpga_priv_data {
unsigned int drvsel;
unsigned int smplsel;
+};
+
+static void socfpga_dwmci_clksel(struct dwmci_host *host)
+{
+ struct dwmci_socfpga_priv_data *priv = host->priv;
/* Disable SDMMC clock. */
clrbits_le32(&clock_manager_base->per_pll.en,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
- /* Configures drv_sel and smpl_sel */
- drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
- smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
-
- debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
- writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
+ debug("%s: drvsel %d smplsel %d\n", __func__,
+ priv->drvsel, priv->smplsel);
+ writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
&system_manager_base->sdmmcgrp_ctrl);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
@@ -50,6 +52,7 @@
const unsigned long clk = cm_get_mmc_controller_clk_hz();
struct dwmci_host *host;
+ struct dwmci_socfpga_priv_data *priv;
fdt_addr_t reg_base;
int bus_width, fifo_depth;
@@ -83,6 +86,13 @@
if (!host)
return -ENOMEM;
+ /* Allocate the priv */
+ priv = calloc(1, sizeof(*priv));
+ if (!priv) {
+ free(host);
+ return -ENOMEM;
+ }
+
host->name = "SOCFPGA DWMMC";
host->ioaddr = (void *)reg_base;
host->buswidth = bus_width;
@@ -92,6 +102,9 @@
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+ priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
+ priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
+ host->priv = priv;
return add_dwmci(host, host->bus_hz, 400000);
}
diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c
index 4faeafb..e08ddd4 100644
--- a/drivers/video/ipu_disp.c
+++ b/drivers/video/ipu_disp.c
@@ -1119,7 +1119,7 @@
reg &= 0x0000FFFF;
__raw_writel(reg, DI_STP_REP(disp, 6));
__raw_writel(0, DI_STP_REP(disp, 7));
- __raw_writel(0, DI_STP_REP(disp, 9));
+ __raw_writel(0, DI_STP_REP9(disp));
/* Init template microcode */
if (disp) {
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index c2c134a..0d3fe06 100644
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -338,6 +338,7 @@
#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
+#define DI_STP_REP9(di) (&DI_REG(di)->stp_rep9)
#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h
new file mode 100644
index 0000000..4510b16
--- /dev/null
+++ b/include/configs/nsa310s.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ * Luka Perkov <luka.perkov@sartura.hr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_NSA310S_H
+#define _CONFIG_NSA310S_H
+
+/* high level configuration options */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6192 1 /* SOC Name */
+#define CONFIG_KW88F6702 1 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/* add target to build it automatically upon "make" */
+#define CONFIG_BUILD_TARGET "u-boot.kwb"
+
+/* compression configuration */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+
+/* commands configuration */
+#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* environment variables configuration */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0xe0000
+
+/* default environment variables */
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part root; " \
+ "ubifsmount ubi:rootfs; " \
+ "ubifsload 0x800000 ${kernel}; " \
+ "ubifsload 0x700000 ${fdt}; " \
+ "ubifsumount; " \
+ "fdt addr 0x700000; fdt resize; fdt chosen; " \
+ "bootz 0x800000 - 0x700000"
+
+#define CONFIG_MTDPARTS \
+ "mtdparts=orion_nand:" \
+ "0xe0000@0x0(uboot)," \
+ "0x20000@0xe0000(uboot_env)," \
+ "0x100000@0x100000(second_stage_uboot)," \
+ "-@0x200000(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS \
+ "kernel=/boot/zImage\0" \
+ "fdt=/boot/nsa310s.dtb\0" \
+ "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+/* Ethernet driver configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 1
+#define CONFIG_PHY_GIGE
+#define CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/* SATA driver configuration */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
+/* RTC driver configuration */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_NSA310S_H */
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index 8364c66..ebb6ed5 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
#define __CONFIG_SOCFPGA_ARRIA5_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
@@ -79,7 +79,6 @@
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index b22e3b1..b3f65b6 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -152,8 +152,6 @@
#define CONFIG_DWMMC
#define CONFIG_SOCFPGA_DWMMC
#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index 86b53e2..67bb35f 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
#define __CONFIG_SOCFPGA_CYCLONE5_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
@@ -79,7 +79,6 @@
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index 3ae9b3e..16e146c 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_TERASIC_DE0_H__
#define __CONFIG_TERASIC_DE0_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
@@ -74,7 +74,6 @@
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index 4b270ce..d051eec 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_DENX_MCVEVK_H__
#define __CONFIG_DENX_MCVEVK_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 742c5ae..5bcee05 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -6,7 +6,7 @@
#ifndef __CONFIG_TERASIC_SOCKIT_H__
#define __CONFIG_TERASIC_SOCKIT_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
@@ -79,7 +79,6 @@
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
new file mode 100644
index 0000000..16a2a86
--- /dev/null
+++ b/include/configs/socfpga_socrates.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_SOCRATES_H__
+#define __CONFIG_SOCFPGA_SOCRATES_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "EBV"
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_socrates
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SOCFPGA_SOCRATES_H__ */
diff --git a/include/flash.h b/include/flash.h
index 13e0384..f53ace7 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -8,7 +8,10 @@
#ifndef _FLASH_H_
#define _FLASH_H_
-#ifndef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_SYS_MAX_FLASH_SECT
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#endif
+
/*-----------------------------------------------------------------------
* FLASH Info: contains chip specific data, per FLASH bank
*/
@@ -503,6 +506,4 @@
#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */
#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */
-#endif /* !CONFIG_SYS_NO_FLASH */
-
#endif /* _FLASH_H_ */
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 5f6d91c..369aba7 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -232,11 +232,12 @@
main_hdr = image;
/* Fill in the main header */
- main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz;
- main_hdr->srcaddr = headersz;
+ main_hdr->blocksize =
+ cpu_to_le32(payloadsz + sizeof(uint32_t) - headersz);
+ main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = has_ext;
- main_hdr->destaddr = params->addr;
- main_hdr->execaddr = params->ep;
+ main_hdr->destaddr = cpu_to_le32(params->addr);
+ main_hdr->execaddr = cpu_to_le32(params->ep);
e = image_find_option(IMAGE_CFG_BOOT_FROM);
if (e)
@@ -246,7 +247,7 @@
main_hdr->nandeccmode = e->nandeccmode;
e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
if (e)
- main_hdr->nandpagesize = e->nandpagesz;
+ main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
main_hdr->checksum = image_checksum8(image,
sizeof(struct main_hdr_v0));
@@ -255,15 +256,17 @@
int cfgi, datai;
ext_hdr = image + sizeof(struct main_hdr_v0);
- ext_hdr->offset = 0x40;
+ ext_hdr->offset = cpu_to_le32(0x40);
for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) {
e = &image_cfg[cfgi];
if (e->type != IMAGE_CFG_DATA)
continue;
- ext_hdr->rcfg[datai].raddr = e->regdata.raddr;
- ext_hdr->rcfg[datai].rdata = e->regdata.rdata;
+ ext_hdr->rcfg[datai].raddr =
+ cpu_to_le32(e->regdata.raddr);
+ ext_hdr->rcfg[datai].rdata =
+ cpu_to_le32(e->regdata.rdata);
datai++;
}
@@ -321,8 +324,9 @@
return 0;
}
- headersz += s.st_size +
- binarye->binary.nargs * sizeof(unsigned int);
+ headersz += sizeof(struct opt_hdr_v1) +
+ s.st_size +
+ (binarye->binary.nargs + 2) * sizeof(uint32_t);
if (hasext)
*hasext = 1;
}
@@ -376,12 +380,13 @@
cur += sizeof(struct main_hdr_v1);
/* Fill the main header */
- main_hdr->blocksize = payloadsz - headersz + sizeof(uint32_t);
- main_hdr->headersz_lsb = headersz & 0xFFFF;
+ main_hdr->blocksize =
+ cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
+ main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
- main_hdr->destaddr = params->addr;
- main_hdr->execaddr = params->ep;
- main_hdr->srcaddr = headersz;
+ main_hdr->destaddr = cpu_to_le32(params->addr);
+ main_hdr->execaddr = cpu_to_le32(params->ep);
+ main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = hasext;
main_hdr->version = 1;
e = image_find_option(IMAGE_CFG_BOOT_FROM);
@@ -397,7 +402,7 @@
binarye = image_find_option(IMAGE_CFG_BINARY);
if (binarye) {
struct opt_hdr_v1 *hdr = cur;
- unsigned int *args;
+ uint32_t *args;
size_t binhdrsz;
struct stat s;
int argi;
@@ -415,7 +420,7 @@
fstat(fileno(bin), &s);
binhdrsz = sizeof(struct opt_hdr_v1) +
- (binarye->binary.nargs + 1) * sizeof(unsigned int) +
+ (binarye->binary.nargs + 2) * sizeof(uint32_t) +
s.st_size;
/*
@@ -424,18 +429,18 @@
* next-header byte and 3-byte alignment at the end.
*/
binhdrsz = ALIGN_SUP(binhdrsz, 4) + 4;
- hdr->headersz_lsb = binhdrsz & 0xFFFF;
+ hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
cur += sizeof(struct opt_hdr_v1);
args = cur;
- *args = binarye->binary.nargs;
+ *args = cpu_to_le32(binarye->binary.nargs);
args++;
for (argi = 0; argi < binarye->binary.nargs; argi++)
- args[argi] = binarye->binary.args[argi];
+ args[argi] = cpu_to_le32(binarye->binary.args[argi]);
- cur += (binarye->binary.nargs + 1) * sizeof(unsigned int);
+ cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
ret = fread(cur, s.st_size, 1, bin);
if (ret != 1) {
@@ -720,7 +725,8 @@
free(image_cfg);
/* Build and add image checksum header */
- checksum = image_checksum32((uint32_t *)ptr, sbuf->st_size);
+ checksum =
+ cpu_to_le32(image_checksum32((uint32_t *)ptr, sbuf->st_size));
size = write(ifd, &checksum, sizeof(uint32_t));
if (size != sizeof(uint32_t)) {
fprintf(stderr, "Error:%s - Checksum write %d bytes %s\n",
@@ -810,7 +816,15 @@
tparams->header_size = alloc_len;
tparams->hdr = hdr;
- return 0;
+ /*
+ * The resulting image needs to be 4-byte aligned. At least
+ * the Marvell hdrparser tool complains if its unaligned.
+ * By returning 1 here in this function, called via
+ * tparams->vrec_header() in mkimage.c, mkimage will
+ * automatically pad the the resulting image to a 4-byte
+ * size if necessary.
+ */
+ return 1;
}
/*
diff --git a/tools/kwbimage.h b/tools/kwbimage.h
index 9d2585c..e6e3d1d 100644
--- a/tools/kwbimage.h
+++ b/tools/kwbimage.h
@@ -9,6 +9,7 @@
#ifndef _KWBIMAGE_H_
#define _KWBIMAGE_H_
+#include <compiler.h>
#include <stdint.h>
#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
@@ -115,7 +116,7 @@
#define OPT_HDR_V1_REGISTER_TYPE 0x3
#define KWBHEADER_V1_SIZE(hdr) \
- (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
+ (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
enum kwbimage_cmd {
CMD_INVALID,