diff --git a/Makefile b/Makefile
index 5e49545..666d291 100644
--- a/Makefile
+++ b/Makefile
@@ -6,9 +6,9 @@
 #
 
 VERSION = 2014
-PATCHLEVEL = 07
+PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
diff --git a/README b/README
index f704eb3..1d71359 100644
--- a/README
+++ b/README
@@ -252,15 +252,15 @@
 ---------------------------------------------------
 
 For all supported boards there are ready-to-use default
-configurations available; just type "make <board_name>_config".
+configurations available; just type "make <board_name>_defconfig".
 
 Example: For a TQM823L module type:
 
 	cd u-boot
-	make TQM823L_config
+	make TQM823L_defconfig
 
 For the Cogent platform, you need to specify the CPU type as well;
-e.g. "make cogent_mpc8xx_config". And also configure the cogent
+e.g. "make cogent_mpc8xx_defconfig". And also configure the cogent
 directory according to the instructions in cogent/README.
 
 
@@ -2597,6 +2597,10 @@
 		Enables the driver for the SPI controllers on i.MX and MXC
 		SoCs. Currently i.MX31/35/51 are supported.
 
+		CONFIG_SYS_SPI_MXC_WAIT
+		Timeout for waiting until spi transfer completed.
+		default: (CONFIG_SYS_HZ/100)     /* 10 ms */
+
 - FPGA Support: CONFIG_FPGA
 
 		Enables FPGA subsystem.
@@ -3752,6 +3756,9 @@
 		Pre-relocation malloc() is only supported on sandbox
 		at present but is fairly easy to enable for other archs.
 
+		Pre-relocation malloc() is only supported on ARM at present
+		but is fairly easy to enable for other archs.
+
 - CONFIG_SYS_BOOTM_LEN:
 		Normally compressed uImages are limited to an
 		uncompressed size of 8 MBytes. If this is not enough,
@@ -4840,9 +4847,9 @@
 sources you must configure U-Boot for one specific board type. This
 is done by typing:
 
-	make NAME_config
+	make NAME_defconfig
 
-where "NAME_config" is the name of one of the existing configu-
+where "NAME_defconfig" is the name of one of the existing configu-
 rations; see boards.cfg for supported names.
 
 Note: for some board special configuration names may exist; check if
@@ -4851,10 +4858,10 @@
       or with LCD support. You can select such additional "features"
       when choosing the configuration, i. e.
 
-      make TQM823L_config
+      make TQM823L_defconfig
 	- will configure for a plain TQM823L, i. e. no LCD support
 
-      make TQM823L_LCD_config
+      make TQM823L_LCD_defconfig
 	- will configure for a TQM823L with U-Boot console on LCD
 
       etc.
@@ -4874,14 +4881,14 @@
 1. Add O= to the make command line invocations:
 
 	make O=/tmp/build distclean
-	make O=/tmp/build NAME_config
+	make O=/tmp/build NAME_defconfig
 	make O=/tmp/build all
 
 2. Set environment variable BUILD_DIR to point to the desired location:
 
 	export BUILD_DIR=/tmp/build
 	make distclean
-	make NAME_config
+	make NAME_defconfig
 	make all
 
 Note that the command line "O=" setting overrides the BUILD_DIR environment
@@ -4907,7 +4914,7 @@
     your board
 3.  If you're porting U-Boot to a new CPU, then also create a new
     directory to hold your CPU specific code. Add any files you need.
-4.  Run "make <board>_config" with your new name.
+4.  Run "make <board>_defconfig" with your new name.
 5.  Type "make", and you should get a working "u-boot.srec" file
     to be installed on your target system.
 6.  Debug and solve any problems that might arise.
@@ -5487,7 +5494,7 @@
 
 Example:
 
-	make TQM850L_config
+	make TQM850L_defconfig
 	make oldconfig
 	make dep
 	make uImage
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index da80240..881e2de 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -13,6 +13,7 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
+#include <mvebu_mmc.h>
 
 #define BUFLEN	16
 
@@ -377,3 +378,11 @@
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_MVEBU_MMC
+int board_mmc_init(bd_t *bis)
+{
+	mvebu_mmc_init(bis);
+	return 0;
+}
+#endif /* CONFIG_MVEBU_MMC */
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index bc207f5..3ea51d7 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -39,6 +39,7 @@
 #define KW_EGIGA0_BASE			(KW_REGISTER(0x72000))
 #define KW_EGIGA1_BASE			(KW_REGISTER(0x76000))
 #define KW_SATA_BASE			(KW_REGISTER(0x80000))
+#define KW_SDIO_BASE			(KW_REGISTER(0x90000))
 
 /* Kirkwood Sata controller has two ports */
 #define KW_SATA_PORT0_OFFSET		0x2000
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
index 01fe0f2..ce4186f 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
@@ -139,9 +139,9 @@
 	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
 }
 
-static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
+static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void)
 {
-	return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
+	return (struct s3c24x0_sdi *)S3C2410_SDI_BASE;
 }
 
 #endif /*__S3C2410_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
index 15a7cb4..3f44bdc 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
@@ -137,9 +137,9 @@
 	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
 }
 
-static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
+static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void)
 {
-	return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
+	return (struct s3c24x0_sdi *)S3C2440_SDI_BASE;
 }
 
 #endif /*__S3C2440_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index 86d720c..ed9df34 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -675,7 +675,7 @@
 
 
 /* SD INTERFACE (see S3C2410 manual chapter 19) */
-struct s3c2410_sdi {
+struct s3c24x0_sdi {
 	u32	sdicon;
 	u32	sdipre;
 	u32	sdicarg;
@@ -691,14 +691,19 @@
 	u32	sdidcnt;
 	u32	sdidsta;
 	u32	sdifsta;
-#ifdef __BIG_ENDIAN
-	u8	res[3];
-	u8	sdidat;
-#else
-	u8	sdidat;
-	u8	res[3];
-#endif
+#ifdef CONFIG_S3C2410
+	u32	sdidat;
 	u32	sdiimsk;
+#else
+	u32	sdiimsk;
+	u32	sdidat;
+#endif
 };
 
+#ifdef CONFIG_CMD_MMC
+#include <mmc.h>
+int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
+		      int (*getwp)(struct mmc *));
+#endif
+
 #endif /*__S3C24X0_H__*/
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index d3433da..5f2a5f4 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -7,7 +7,9 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#ifdef __aarch64__
 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
+#endif
 
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index dfc2de9..29cdad0 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -67,10 +67,22 @@
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
 #endif
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
+	mov	r2, sp
 	sub	sp, sp, #GD_SIZE	/* allocate one GD above SP */
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
 	mov	r9, sp		/* GD is above SP */
+	mov	r1, sp
 	mov	r0, #0
+clr_gd:
+	cmp	r1, r2			/* while not at end of GD */
+	strlo	r0, [r1]		/* clear 32-bit GD word */
+	addlo	r1, r1, #4		/* move to next */
+	blo	clr_gd
+#if defined(CONFIG_SYS_MALLOC_F_LEN) && !defined(CONFIG_SPL_BUILD)
+	sub	sp, sp, #CONFIG_SYS_MALLOC_F_LEN
+	str	sp, [r9, #GD_MALLOC_BASE]
+#endif
+	/* mov r0, #0 not needed due to above code */
 	bl	board_init_f
 
 #if ! defined(CONFIG_SPL_BUILD)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 684d400..6274f92 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -310,6 +310,14 @@
 
 
 #if defined(CONFIG_WATCHDOG)
+#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
+void
+init_85xx_watchdog(void)
+{
+	mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
+	      TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
+}
+
 void
 reset_85xx_watchdog(void)
 {
diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c
index a36a4af..daf46a9 100644
--- a/arch/powerpc/cpu/mpc85xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc85xx/interrupts.c
@@ -42,7 +42,7 @@
 	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
 
 	/* PIE is same as DIE, dec interrupt enable */
-	mtspr(SPRN_TCR, TCR_PIE);
+	mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
 
 #ifdef CONFIG_INTERRUPTS
 	pic->iivpr1 = 0x810001;	/* 50220 enable ecm interrupts */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 2445acd..1b98e0f 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -378,11 +378,16 @@
 #else
 #define SPRN_TCR	0x154	/* Book E Timer Control Register */
 #endif /* CONFIG_BOOKE */
+#ifdef CONFIG_E500MC
+#define  TCR_WP(x)		(((64-x)&0x3)<<30)| \
+				(((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
+#else
 #define   TCR_WP(x)		(((x)&0x3)<<30)	/* WDT Period */
 #define     WP_2_17		0		/* 2^17 clocks */
 #define     WP_2_21		1		/* 2^21 clocks */
 #define     WP_2_25		2		/* 2^25 clocks */
 #define     WP_2_29		3		/* 2^29 clocks */
+#endif /* CONFIG_E500 */
 #define   TCR_WRC(x)		(((x)&0x3)<<28)	/* WDT Reset Control */
 #define     WRC_NONE		0		/* No reset will occur */
 #define     WRC_CORE		1		/* Core reset will occur */
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 50eb820..0296205 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -226,6 +226,9 @@
 #if defined(CONFIG_WATCHDOG)
 int init_func_watchdog_init(void)
 {
+#if defined(CONFIG_MPC85xx)
+	init_85xx_watchdog();
+#endif
 	puts("       Watchdog enabled\n");
 	WATCHDOG_RESET();
 	return 0;
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index 6bc8eb8..cd08379 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -80,14 +80,29 @@
 
 #define ZL30158_RST	8
 #define BFTIC4_RST	0
+#define RSTRQSR1_WDT_RR	0x00200000
+#define RSTRQSR1_SW_RR	0x00100000
 
 int board_early_init_f(void)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	bool cpuwd_flag = false;
+
+	/* configure mode for uP reset request */
+	qrio_uprstreq(UPREQ_CORE_RST);
 
 	/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
 	setbits_be32(&gur->ddrclkdr, 0x001f000f);
 
+	/* set reset reason according CPU register */
+	if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+	    RSTRQSR1_WDT_RR)
+		cpuwd_flag = true;
+
+	qrio_cpuwd_flag(cpuwd_flag);
+	/* clear CPU bits by writing 1 */
+	setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
+
 	/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
 	qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
 	/* and enable WD on it */
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h
index afede99..e90e8ab 100644
--- a/board/keymile/kmp204x/kmp204x.h
+++ b/board/keymile/kmp204x/kmp204x.h
@@ -24,5 +24,12 @@
 void qrio_prstcfg(u8 bit, u8 mode);
 void qrio_set_leds(void);
 void qrio_enable_app_buffer(void);
+void qrio_cpuwd_flag(bool flag);
+int qrio_reset_reason(void);
+
+#define UPREQ_UNIT_RST		0x0
+#define UPREQ_CORE_RST		0x1
+
+void qrio_uprstreq(u8 mode);
 
 void pci_of_setup(void *blob, bd_t *bd);
diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c
index b6ba93a..edf3bf1 100644
--- a/board/keymile/kmp204x/qrio.c
+++ b/board/keymile/kmp204x/qrio.c
@@ -173,3 +173,35 @@
 	ctrll |= (CTRLL_WRB_BUFENA);
 	out_8(qrio_base + CTRLL_OFF, ctrll);
 }
+
+#define REASON1_OFF	0x12
+#define REASON1_CPUWD	0x01
+
+void qrio_cpuwd_flag(bool flag)
+{
+	u8 reason1;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+	reason1 = in_8(qrio_base + REASON1_OFF);
+	if (flag)
+		reason1 |= REASON1_CPUWD;
+	else
+		reason1 &= ~REASON1_CPUWD;
+	out_8(qrio_base + REASON1_OFF, reason1);
+}
+
+#define RSTCFG_OFF	0x11
+
+void qrio_uprstreq(u8 mode)
+{
+	u32 rstcfg;
+	void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+	rstcfg = in_8(qrio_base + RSTCFG_OFF);
+
+	if (mode & UPREQ_CORE_RST)
+		rstcfg |= UPREQ_CORE_RST;
+	else
+		rstcfg &= ~UPREQ_CORE_RST;
+
+	out_8(qrio_base + RSTCFG_OFF, rstcfg);
+}
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 7da10e6..a7621a8 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -62,16 +62,36 @@
 	return 0;
 }
 
-static int init_mmc_for_env(struct mmc *mmc)
-{
 #ifdef CONFIG_SYS_MMC_ENV_PART
+__weak uint mmc_get_env_part(struct mmc *mmc)
+{
+	return CONFIG_SYS_MMC_ENV_PART;
+}
+
+static int mmc_set_env_part(struct mmc *mmc)
+{
+	uint part = mmc_get_env_part(mmc);
 	int dev = CONFIG_SYS_MMC_ENV_DEV;
+	int ret = 0;
 
 #ifdef CONFIG_SPL_BUILD
 	dev = 0;
 #endif
+
+	if (part != mmc->part_num) {
+		ret = mmc_switch_part(dev, part);
+		if (ret)
+			puts("MMC partition switch failed\n");
+	}
+
+	return ret;
+}
+#else
+static inline int mmc_set_env_part(struct mmc *mmc) {return 0; };
 #endif
 
+static int init_mmc_for_env(struct mmc *mmc)
+{
 	if (!mmc) {
 		puts("No MMC card found\n");
 		return -1;
@@ -82,16 +102,7 @@
 		return -1;
 	}
 
-#ifdef CONFIG_SYS_MMC_ENV_PART
-	if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) {
-		if (mmc_switch_part(dev, CONFIG_SYS_MMC_ENV_PART)) {
-			puts("MMC partition switch failed\n");
-			return -1;
-		}
-	}
-#endif
-
-	return 0;
+	return mmc_set_env_part(mmc);
 }
 
 static void fini_mmc_for_env(struct mmc *mmc)
diff --git a/doc/README.ARM-SoC b/doc/README.ARM-SoC
deleted file mode 100644
index d6bd624..0000000
--- a/doc/README.ARM-SoC
+++ /dev/null
@@ -1,31 +0,0 @@
-[By Steven Scholz <steven.scholz@imc-berlin.de>, 16 Aug 2004]
-
-Since the cpu/ directory gets clobbered with peripheral driver code I
-started cleaning up arch/arm/cpu/arm920t.
-
-I introduced the concept of Soc (system on a chip) into the ./cpu
-directory. That means that code that is cpu (i.e. core) specific
-resides in
-
-	$(CPUDIR)/
-
-and code that is specific to some SoC (i.e. vendor specific
-peripherals around the core) is moved into
-
-	$(CPUDIR)/$(SOC)/
-
-Thus a library/archive "$(CPUDIR)/$(SOC)/lib$(SOC).a" will be build
-and linked. Examples will be
-
-	arch/arm/cpu/arm920t/imx/
-	arch/arm/cpu/arm920t/s3c24x0
-
-One can select an SoC by passing the name of it to ./mkconfig just
-like
-
-	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0
-
-If there's no VENDOR field (like "mpl" in the above line) one has to
-pass NULL instead:
-
-	@./mkconfig $(@:_config=) arm arm920t mx1ads NULL imx
diff --git a/doc/README.SPL b/doc/README.SPL
index 2b4b0b8..c283dcf 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -13,34 +13,29 @@
 How it works
 ------------
 
-There is a new directory $(srctree)/spl which contains only a Makefile.
-The object files are built separately for SPL and placed in this directory.
+The object files for SPL are built separately and placed in the "spl" directory.
 The final binaries which are generated are u-boot-spl, u-boot-spl.bin and
 u-boot-spl.map.
 
-During the SPL build a variable named CONFIG_SPL_BUILD is exported
-in the make environment and also appended to CPPFLAGS with -DCONFIG_SPL_BUILD.
+A config option named CONFIG_SPL_BUILD is enabled by Kconfig for SPL.
 Source files can therefore be compiled for SPL with different settings.
-ARM-based boards have previously used the option CONFIG_PRELOADER for it.
 
 For example:
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-COBJS-y += board_spl.o
+obj-y += board_spl.o
 else
-COBJS-y += board.o
+obj-y += board.o
 endif
 
-COBJS-$(CONFIG_SPL_BUILD) += foo.o
+obj-$(CONFIG_SPL_BUILD) += foo.o
 
 #ifdef CONFIG_SPL_BUILD
 	foo();
 #endif
 
 
-The building of SPL images can be with:
-
-#define CONFIG_SPL 1
+The building of SPL images can be enabled by CONFIG_SPL option in Kconfig.
 
 Because SPL images normally have a different text base, one has to be
 configured by defining CONFIG_SPL_TEXT_BASE. The linker script has to be
@@ -70,17 +65,6 @@
 CONFIG_SPL_RAM_DEVICE (common/spl/spl.c)
 CONFIG_SPL_WATCHDOG_SUPPORT (drivers/watchdog/libwatchdog.o)
 
-Normally CPU is assumed to be the same between the SPL and normal
-u-boot build.  However it is possible to specify a different CPU for
-the SPL build for cases where the SPL is expected to run on a
-different CPU model from the main u-boot.  This is done by specifying
-an SPL CPU in boards.cfg as follows:
-
-	normal_cpu:spl_cpu
-
-This case CPU will be set to "normal_cpu" during the main u-boot
-build and "spl_cpu" during the SPL build.
-
 
 Debugging
 ---------
diff --git a/doc/device-tree-bindings/spi/spi-bus.txt b/doc/device-tree-bindings/spi/spi-bus.txt
index 800dafe..5c8720a 100644
--- a/doc/device-tree-bindings/spi/spi-bus.txt
+++ b/doc/device-tree-bindings/spi/spi-bus.txt
@@ -59,6 +59,8 @@
                       used for MOSI. Defaults to 1 if not present.
 - spi-rx-bus-width - (optional) The bus width(number of data wires) that
                       used for MISO. Defaults to 1 if not present.
+- spi-half-duplex  - (optional) Indicates that the SPI bus should wait for
+		      a header byte before reading data from the slave.
 
 Some SPI controllers and devices support Dual and Quad SPI transfer mode.
 It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).
diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt
index 16819c7..4ed30df 100644
--- a/doc/feature-removal-schedule.txt
+++ b/doc/feature-removal-schedule.txt
@@ -26,7 +26,7 @@
 	drivers. All new drivers should use this infrastructure, and
 	all old drivers should get converted to use it.
 
-Who:	Andy Fleming <afleming@freescale.com> and driver maintainers
+Who:	Andy Fleming <afleming@gmail.com> and driver maintainers
 
 ---------------------------
 
diff --git a/doc/git-mailrc b/doc/git-mailrc
index ae7e7bf..0985791 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -12,7 +12,7 @@
 # things simple and easy to look up/coordinate.
 alias aaribaud       Albert Aribaud <albert.u.boot@aribaud.net>
 alias abiessmann     Andreas Bießmann <andreas.devel@googlemail.com>
-alias afleming       Andy Fleming <afleming@freescale.com>
+alias afleming       Andy Fleming <afleming@gmail.com>
 alias ag             Anatolij Gustschin <agust@denx.de>
 alias galak          Kumar Gala <galak@kernel.crashing.org>
 alias gruss          Graeme Russ <graeme.russ@gmail.com>
@@ -27,6 +27,7 @@
 alias lukma          Lukasz Majewski <l.majewski@samsung.com>
 alias macpaul        Macpaul Lin <macpaul@andestech.com>
 alias marex          Marek Vasut <marex@denx.de>
+alias masahiro       Masahiro Yamada <yamada.m@jp.panasonic.com>
 alias monstr         Michal Simek <monstr@monstr.eu>
 alias panto          Pantelis Antoniou <panto@antoniou-consulting.com>
 alias prafulla       Prafulla Wadaskar <prafulla@marvell.com>
@@ -110,6 +111,7 @@
 alias kerneldoc      uboot, marex
 alias fdt            uboot, Jerry Van Baren <vanbaren@cideas.com>
 alias i2c            uboot, hs
+alias kconfig        uboot, masahiro
 alias mmc            uboot, panto
 alias nand           uboot, scottwood
 alias net            uboot, jhersh
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 7df709c..015333f 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -98,7 +98,7 @@
 	}
 
 	out = dev->dout;
-	out[0] = cmd_version;
+	out[0] = EC_CMD_VERSION0 + cmd_version;
 	out[1] = cmd;
 	out[2] = (uint8_t)dout_len;
 	memcpy(out + 3, dout, dout_len);
@@ -165,7 +165,7 @@
  */
 int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
 {
-	dev->spi = spi_setup_slave_fdt(blob, dev->parent_node, dev->node);
+	dev->spi = spi_setup_slave_fdt(blob, dev->node, dev->parent_node);
 	if (!dev->spi) {
 		debug("%s: Could not setup SPI slave\n", __func__);
 		return -1;
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 34febf5..464cee1 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -22,6 +22,7 @@
 obj-$(CONFIG_SDHCI) += sdhci.o
 obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
 obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
+obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
 obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
@@ -37,3 +38,4 @@
 else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
+obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c
index 54cfabf..82079d6 100644
--- a/drivers/mmc/bcm2835_sdhci.c
+++ b/drivers/mmc/bcm2835_sdhci.c
@@ -179,7 +179,7 @@
 	host->name = "bcm2835_sdhci";
 	host->ioaddr = (void *)regbase;
 	host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
-		SDHCI_QUIRK_WAIT_SEND_CMD;
+		SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
 	host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 	host->ops = &bcm2835_ops;
 
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 5bf36a0..0df30bc 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -245,7 +245,10 @@
 		return -EINVAL;
 	}
 
-	div = DIV_ROUND_UP(sclk, 2 * freq);
+	if (sclk == freq)
+		div = 0;	/* bypass mode */
+	else
+		div = DIV_ROUND_UP(sclk, 2 * freq);
 
 	dwmci_writel(host, DWMCI_CLKENA, 0);
 	dwmci_writel(host, DWMCI_CLKSRC, 0);
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index a57a9b1..45bcffb 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -58,30 +58,61 @@
 	atmel_mci_t *mci = mmc->priv;
 	u32 bus_hz = get_mci_clk_rate();
 	u32 clkdiv = 255;
+	unsigned int version = atmel_mci_get_version(mci);
+	u32 clkodd = 0;
+	u32 mr;
 
 	debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
 		bus_hz, hz, blklen);
 	if (hz > 0) {
-		/* find lowest clkdiv yielding a rate <= than requested */
-		for (clkdiv=0; clkdiv<255; clkdiv++) {
-			if ((bus_hz / (clkdiv+1) / 2) <= hz)
-				break;
+		if (version >= 0x500) {
+			clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
+			if (clkdiv > 511)
+				clkdiv = 511;
+
+			clkodd = clkdiv & 1;
+			clkdiv >>= 1;
+
+			printf("mci: setting clock %u Hz, block size %u\n",
+			       bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
+		} else {
+			/* find clkdiv yielding a rate <= than requested */
+			for (clkdiv = 0; clkdiv < 255; clkdiv++) {
+				if ((bus_hz / (clkdiv + 1) / 2) <= hz)
+					break;
+			}
+			printf("mci: setting clock %u Hz, block size %u\n",
+			       (bus_hz / (clkdiv + 1)) / 2, blklen);
+
 		}
 	}
-	printf("mci: setting clock %u Hz, block size %u\n",
-		(bus_hz / (clkdiv+1)) / 2, blklen);
 
 	blklen &= 0xfffc;
-	/* On some platforms RDPROOF and WRPROOF are ignored */
-	writel((MMCI_BF(CLKDIV, clkdiv)
-		 | MMCI_BF(BLKLEN, blklen)
-		 | MMCI_BIT(RDPROOF)
-		 | MMCI_BIT(WRPROOF)), &mci->mr);
+
+	mr = MMCI_BF(CLKDIV, clkdiv);
+
+	/* MCI IP version >= 0x200 has R/WPROOF */
+	if (version >= 0x200)
+		mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);
+
 	/*
-	 * On some new platforms BLKLEN in mci->mr is ignored.
-	 * Should use the BLKLEN in the block register.
+	 * MCI IP version >= 0x500 use bit 16 as clkodd.
+	 * MCI IP version < 0x500 use upper 16 bits for blklen.
 	 */
-	writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
+	if (version >= 0x500)
+		mr |= MMCI_BF(CLKODD, clkodd);
+	else
+		mr |= MMCI_BF(BLKLEN, blklen);
+
+	writel(mr, &mci->mr);
+
+	/* MCI IP version >= 0x200 has blkr */
+	if (version >= 0x200)
+		writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
+
+	if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
+		writel(MMCI_BIT(HSMODE), &mci->cfg);
+
 	initialized = 1;
 }
 
@@ -376,8 +407,10 @@
 	/* need to be able to pass these in on a board by board basis */
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	version = atmel_mci_get_version(mci);
-	if ((version & 0xf00) >= 0x300)
+	if ((version & 0xf00) >= 0x300) {
 		cfg->host_caps = MMC_MODE_8BIT;
+		cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+	}
 
 	cfg->host_caps |= MMC_MODE_4BIT;
 
diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c
new file mode 100644
index 0000000..9759198
--- /dev/null
+++ b/drivers/mmc/mvebu_mmc.c
@@ -0,0 +1,361 @@
+/*
+ * Marvell MMC/SD/SDIO driver
+ *
+ * (C) Copyright 2012
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Maen Suleiman, Gerald Kerma
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <part.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <mvebu_mmc.h>
+
+#define DRIVER_NAME "MVEBU_MMC"
+
+static void mvebu_mmc_write(u32 offs, u32 val)
+{
+	writel(val, CONFIG_SYS_MMC_BASE + (offs));
+}
+
+static u32 mvebu_mmc_read(u32 offs)
+{
+	return readl(CONFIG_SYS_MMC_BASE + (offs));
+}
+
+static int mvebu_mmc_setup_data(struct mmc_data *data)
+{
+	u32 ctrl_reg;
+
+	debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
+	      (data->flags & MMC_DATA_READ) ? "read" : "write",
+	      data->blocks, data->blocksize);
+
+	/* default to maximum timeout */
+	ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
+	ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
+	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
+
+	if (data->flags & MMC_DATA_READ) {
+		mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
+		mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
+	} else {
+		mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
+		mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
+	}
+
+	mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
+	mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
+
+	return 0;
+}
+
+static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+			      struct mmc_data *data)
+{
+	int timeout = 10;
+	ushort waittype = 0;
+	ushort resptype = 0;
+	ushort xfertype = 0;
+	ushort resp_indx = 0;
+
+	debug("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
+	      cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
+
+	udelay(10*1000);
+
+	debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
+	      cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
+
+	/* Checking if card is busy */
+	while ((mvebu_mmc_read(SDIO_HW_STATE) & CARD_BUSY)) {
+		if (timeout == 0) {
+			printf("%s: card busy!\n", DRIVER_NAME);
+			return -1;
+		}
+		timeout--;
+		udelay(1000);
+	}
+
+	/* Set up for a data transfer if we have one */
+	if (data) {
+		int err = mvebu_mmc_setup_data(data);
+
+		if (err)
+			return err;
+	}
+
+	resptype = SDIO_CMD_INDEX(cmd->cmdidx);
+
+	/* Analyzing resptype/xfertype/waittype for the command */
+	if (cmd->resp_type & MMC_RSP_BUSY)
+		resptype |= SDIO_CMD_RSP_48BUSY;
+	else if (cmd->resp_type & MMC_RSP_136)
+		resptype |= SDIO_CMD_RSP_136;
+	else if (cmd->resp_type & MMC_RSP_PRESENT)
+		resptype |= SDIO_CMD_RSP_48;
+	else
+		resptype |= SDIO_CMD_RSP_NONE;
+
+	if (cmd->resp_type & MMC_RSP_CRC)
+		resptype |= SDIO_CMD_CHECK_CMDCRC;
+
+	if (cmd->resp_type & MMC_RSP_OPCODE)
+		resptype |= SDIO_CMD_INDX_CHECK;
+
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		resptype |= SDIO_UNEXPECTED_RESP;
+		waittype |= SDIO_NOR_UNEXP_RSP;
+	}
+
+	if (data) {
+		resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
+		xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
+		if (data->flags & MMC_DATA_READ) {
+			xfertype |= SDIO_XFER_MODE_TO_HOST;
+			waittype = SDIO_NOR_DMA_INI;
+		} else {
+			waittype |= SDIO_NOR_XFER_DONE;
+		}
+	} else {
+		waittype |= SDIO_NOR_CMD_DONE;
+	}
+
+	/* Setting cmd arguments */
+	mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
+	mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
+
+	/* Setting Xfer mode */
+	mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
+
+	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
+	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
+
+	/* Sending command */
+	mvebu_mmc_write(SDIO_CMD, resptype);
+
+	mvebu_mmc_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
+	mvebu_mmc_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
+
+	/* Waiting for completion */
+	timeout = 1000000;
+
+	while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
+		if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
+			debug("%s: error! cmdidx : %d, err reg: %04x\n",
+			      DRIVER_NAME, cmd->cmdidx,
+			      mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
+			if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
+				(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
+				return TIMEOUT;
+			return COMM_ERR;
+		}
+
+		timeout--;
+		udelay(1);
+		if (timeout <= 0) {
+			printf("%s: command timed out\n", DRIVER_NAME);
+			return TIMEOUT;
+		}
+	}
+
+	/* Handling response */
+	if (cmd->resp_type & MMC_RSP_136) {
+		uint response[8];
+
+		for (resp_indx = 0; resp_indx < 8; resp_indx++)
+			response[resp_indx]
+				= mvebu_mmc_read(SDIO_RSP(resp_indx));
+
+		cmd->response[0] =	((response[0] & 0x03ff) << 22) |
+					((response[1] & 0xffff) << 6) |
+					((response[2] & 0xfc00) >> 10);
+		cmd->response[1] =	((response[2] & 0x03ff) << 22) |
+					((response[3] & 0xffff) << 6) |
+					((response[4] & 0xfc00) >> 10);
+		cmd->response[2] =	((response[4] & 0x03ff) << 22) |
+					((response[5] & 0xffff) << 6) |
+					((response[6] & 0xfc00) >> 10);
+		cmd->response[3] =	((response[6] & 0x03ff) << 22) |
+					((response[7] & 0x3fff) << 8);
+	} else if (cmd->resp_type & MMC_RSP_PRESENT) {
+		uint response[3];
+
+		for (resp_indx = 0; resp_indx < 3; resp_indx++)
+			response[resp_indx]
+				= mvebu_mmc_read(SDIO_RSP(resp_indx));
+
+		cmd->response[0] =	((response[2] & 0x003f) << (8 - 8)) |
+					((response[1] & 0xffff) << (14 - 8)) |
+					((response[0] & 0x03ff) << (30 - 8));
+		cmd->response[1] =	((response[0] & 0xfc00) >> 10);
+		cmd->response[2] =	0;
+		cmd->response[3] =	0;
+	}
+
+	debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
+	debug("[0x%x] ", cmd->response[0]);
+	debug("[0x%x] ", cmd->response[1]);
+	debug("[0x%x] ", cmd->response[2]);
+	debug("[0x%x] ", cmd->response[3]);
+	debug("\n");
+
+	return 0;
+}
+
+static void mvebu_mmc_power_up(void)
+{
+	debug("%s: power up\n", DRIVER_NAME);
+
+	/* disable interrupts */
+	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
+	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
+
+	/* SW reset */
+	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
+
+	mvebu_mmc_write(SDIO_XFER_MODE, 0);
+
+	/* enable status */
+	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
+	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
+
+	/* enable interrupts status */
+	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
+	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
+}
+
+static void mvebu_mmc_set_clk(unsigned int clock)
+{
+	unsigned int m;
+
+	if (clock == 0) {
+		debug("%s: clock off\n", DRIVER_NAME);
+		mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
+		mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
+	} else {
+		m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
+		if (m > MVEBU_MMC_BASE_DIV_MAX)
+			m = MVEBU_MMC_BASE_DIV_MAX;
+		mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
+	}
+
+	udelay(10*1000);
+}
+
+static void mvebu_mmc_set_bus(unsigned int bus)
+{
+	u32 ctrl_reg = 0;
+
+	ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
+	ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
+
+	switch (bus) {
+	case 4:
+		ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
+		break;
+	case 1:
+	default:
+		ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
+	}
+
+	/* default transfer mode */
+	ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
+	ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
+
+	/* default to maximum timeout */
+	ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
+
+	ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
+
+	ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
+
+	debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
+	      (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
+	      "push-pull" : "open-drain",
+	      (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
+	      "4bit-width" : "1bit-width",
+	      (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
+	      "high-speed" : "");
+
+	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
+	udelay(10*1000);
+}
+
+static void mvebu_mmc_set_ios(struct mmc *mmc)
+{
+	debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
+	      mmc->bus_width, mmc->clock);
+	mvebu_mmc_set_bus(mmc->bus_width);
+	mvebu_mmc_set_clk(mmc->clock);
+}
+
+static int mvebu_mmc_initialize(struct mmc *mmc)
+{
+	debug("%s: mvebu_mmc_initialize", DRIVER_NAME);
+
+	/*
+	 * Setting host parameters
+	 * Initial Host Ctrl : Timeout : max , Normal Speed mode,
+	 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
+	 */
+	mvebu_mmc_write(SDIO_HOST_CTRL,
+			SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
+			SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
+			SDIO_HOST_CTRL_BIG_ENDIAN |
+			SDIO_HOST_CTRL_PUSH_PULL_EN |
+			SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
+
+	mvebu_mmc_write(SDIO_CLK_CTRL, 0);
+
+	/* enable status */
+	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
+	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
+
+	/* disable interrupts */
+	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
+	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
+
+	/* SW reset */
+	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
+
+	udelay(10*1000);
+
+	return 0;
+}
+
+static const struct mmc_ops mvebu_mmc_ops = {
+	.send_cmd	= mvebu_mmc_send_cmd,
+	.set_ios	= mvebu_mmc_set_ios,
+	.init		= mvebu_mmc_initialize,
+};
+
+static struct mmc_config mvebu_mmc_cfg = {
+	.name		= DRIVER_NAME,
+	.ops		= &mvebu_mmc_ops,
+	.f_min		= MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
+	.f_max		= MVEBU_MMC_CLOCKRATE_MAX,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.host_caps	= MMC_MODE_4BIT | MMC_MODE_HS,
+	.part_type	= PART_TYPE_DOS,
+	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
+int mvebu_mmc_init(bd_t *bis)
+{
+	struct mmc *mmc;
+
+	mvebu_mmc_power_up();
+
+	mmc = mmc_create(&mvebu_mmc_cfg, bis);
+	if (mmc == NULL)
+		return -1;
+
+	return 0;
+}
diff --git a/drivers/mmc/s3c_sdi.c b/drivers/mmc/s3c_sdi.c
new file mode 100644
index 0000000..1b5b705
--- /dev/null
+++ b/drivers/mmc/s3c_sdi.c
@@ -0,0 +1,321 @@
+/*
+ * S3C24xx SD/MMC driver
+ *
+ * Based on OpenMoko S3C24xx driver by Harald Welte <laforge@openmoko.org>
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <errno.h>
+#include <asm/arch/s3c24x0_cpu.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
+
+#define S3C2440_SDICON_SDRESET		(1 << 8)
+#define S3C2410_SDICON_FIFORESET	(1 << 1)
+#define S3C2410_SDICON_CLOCKTYPE	(1 << 0)
+
+#define S3C2410_SDICMDCON_LONGRSP	(1 << 10)
+#define S3C2410_SDICMDCON_WAITRSP	(1 << 9)
+#define S3C2410_SDICMDCON_CMDSTART	(1 << 8)
+#define S3C2410_SDICMDCON_SENDERHOST	(1 << 6)
+#define S3C2410_SDICMDCON_INDEX		0x3f
+
+#define S3C2410_SDICMDSTAT_CRCFAIL	(1 << 12)
+#define S3C2410_SDICMDSTAT_CMDSENT	(1 << 11)
+#define S3C2410_SDICMDSTAT_CMDTIMEOUT	(1 << 10)
+#define S3C2410_SDICMDSTAT_RSPFIN	(1 << 9)
+
+#define S3C2440_SDIDCON_DS_WORD		(2 << 22)
+#define S3C2410_SDIDCON_TXAFTERRESP	(1 << 20)
+#define S3C2410_SDIDCON_RXAFTERCMD	(1 << 19)
+#define S3C2410_SDIDCON_BLOCKMODE	(1 << 17)
+#define S3C2410_SDIDCON_WIDEBUS		(1 << 16)
+#define S3C2440_SDIDCON_DATSTART	(1 << 14)
+#define S3C2410_SDIDCON_XFER_RXSTART	(2 << 12)
+#define S3C2410_SDIDCON_XFER_TXSTART	(3 << 12)
+#define S3C2410_SDIDCON_BLKNUM		0x7ff
+
+#define S3C2410_SDIDSTA_FIFOFAIL	(1 << 8)
+#define S3C2410_SDIDSTA_CRCFAIL		(1 << 7)
+#define S3C2410_SDIDSTA_RXCRCFAIL	(1 << 6)
+#define S3C2410_SDIDSTA_DATATIMEOUT	(1 << 5)
+#define S3C2410_SDIDSTA_XFERFINISH	(1 << 4)
+
+#define S3C2410_SDIFSTA_TFHALF		(1 << 11)
+#define S3C2410_SDIFSTA_COUNTMASK	0x7f
+
+/*
+ * WARNING: We only support one SD IP block.
+ * NOTE: It's not likely there will ever exist an S3C24xx with two,
+ *       at least not in this universe all right.
+ */
+static int wide_bus;
+
+static int
+s3cmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
+	uint32_t sdiccon, sdicsta, sdidcon, sdidsta, sdidat, sdifsta;
+	uint32_t sdicsta_wait_bit = S3C2410_SDICMDSTAT_CMDSENT;
+	unsigned int timeout = 100000;
+	int ret = 0, xfer_len, data_offset = 0;
+	const uint32_t sdidsta_err_mask = S3C2410_SDIDSTA_FIFOFAIL |
+		S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL |
+		S3C2410_SDIDSTA_DATATIMEOUT;
+
+
+	writel(0xffffffff, &sdi_regs->sdicsta);
+	writel(0xffffffff, &sdi_regs->sdidsta);
+	writel(0xffffffff, &sdi_regs->sdifsta);
+
+	/* Set up data transfer (if applicable). */
+	if (data) {
+		writel(data->blocksize, &sdi_regs->sdibsize);
+
+		sdidcon = data->blocks & S3C2410_SDIDCON_BLKNUM;
+		sdidcon |= S3C2410_SDIDCON_BLOCKMODE;
+#if defined(CONFIG_S3C2440)
+		sdidcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART;
+#endif
+		if (wide_bus)
+			sdidcon |= S3C2410_SDIDCON_WIDEBUS;
+
+		if (data->flags & MMC_DATA_READ) {
+			sdidcon |= S3C2410_SDIDCON_RXAFTERCMD;
+			sdidcon |= S3C2410_SDIDCON_XFER_RXSTART;
+		} else {
+			sdidcon |= S3C2410_SDIDCON_TXAFTERRESP;
+			sdidcon |= S3C2410_SDIDCON_XFER_TXSTART;
+		}
+
+		writel(sdidcon, &sdi_regs->sdidcon);
+	}
+
+	/* Write CMD arg. */
+	writel(cmd->cmdarg, &sdi_regs->sdicarg);
+
+	/* Write CMD index. */
+	sdiccon = cmd->cmdidx & S3C2410_SDICMDCON_INDEX;
+	sdiccon |= S3C2410_SDICMDCON_SENDERHOST;
+	sdiccon |= S3C2410_SDICMDCON_CMDSTART;
+
+	/* Command with short response. */
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		sdiccon |= S3C2410_SDICMDCON_WAITRSP;
+		sdicsta_wait_bit = S3C2410_SDICMDSTAT_RSPFIN;
+	}
+
+	/* Command with long response. */
+	if (cmd->resp_type & MMC_RSP_136)
+		sdiccon |= S3C2410_SDICMDCON_LONGRSP;
+
+	/* Start the command. */
+	writel(sdiccon, &sdi_regs->sdiccon);
+
+	/* Wait for the command to complete or for response. */
+	for (timeout = 100000; timeout; timeout--) {
+		sdicsta = readl(&sdi_regs->sdicsta);
+		if (sdicsta & sdicsta_wait_bit)
+			break;
+
+		if (sdicsta & S3C2410_SDICMDSTAT_CMDTIMEOUT)
+			timeout = 1;
+	}
+
+	/* Clean the status bits. */
+	setbits_le32(&sdi_regs->sdicsta, 0xf << 9);
+
+	if (!timeout) {
+		puts("S3C SDI: Command timed out!\n");
+		ret = TIMEOUT;
+		goto error;
+	}
+
+	/* Read out the response. */
+	if (cmd->resp_type & MMC_RSP_136) {
+		cmd->response[0] = readl(&sdi_regs->sdirsp0);
+		cmd->response[1] = readl(&sdi_regs->sdirsp1);
+		cmd->response[2] = readl(&sdi_regs->sdirsp2);
+		cmd->response[3] = readl(&sdi_regs->sdirsp3);
+	} else {
+		cmd->response[0] = readl(&sdi_regs->sdirsp0);
+	}
+
+	/* If there are no data, we're done. */
+	if (!data)
+		return 0;
+
+	xfer_len = data->blocksize * data->blocks;
+
+	while (xfer_len > 0) {
+		sdidsta = readl(&sdi_regs->sdidsta);
+		sdifsta = readl(&sdi_regs->sdifsta);
+
+		if (sdidsta & sdidsta_err_mask) {
+			printf("S3C SDI: Data error (sdta=0x%08x)\n", sdidsta);
+			ret = -EIO;
+			goto error;
+		}
+
+		if (data->flags & MMC_DATA_READ) {
+			if ((sdifsta & S3C2410_SDIFSTA_COUNTMASK) < 4)
+				continue;
+			sdidat = readl(&sdi_regs->sdidat);
+			put_unaligned_le32(sdidat, data->dest + data_offset);
+		} else {	/* Write */
+			/* TX FIFO half full. */
+			if (!(sdifsta & S3C2410_SDIFSTA_TFHALF))
+				continue;
+
+			/* TX FIFO is below 32b full, write. */
+			sdidat = get_unaligned_le32(data->src + data_offset);
+			writel(sdidat, &sdi_regs->sdidat);
+		}
+		data_offset += 4;
+		xfer_len -= 4;
+	}
+
+	/* Wait for the command to complete or for response. */
+	for (timeout = 100000; timeout; timeout--) {
+		sdidsta = readl(&sdi_regs->sdidsta);
+		if (sdidsta & S3C2410_SDIDSTA_XFERFINISH)
+			break;
+
+		if (sdidsta & S3C2410_SDIDSTA_DATATIMEOUT)
+			timeout = 1;
+	}
+
+	/* Clear status bits. */
+	writel(0x6f8, &sdi_regs->sdidsta);
+
+	if (!timeout) {
+		puts("S3C SDI: Command timed out!\n");
+		ret = TIMEOUT;
+		goto error;
+	}
+
+	writel(0, &sdi_regs->sdidcon);
+
+	return 0;
+error:
+	return ret;
+}
+
+static void s3cmmc_set_ios(struct mmc *mmc)
+{
+	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
+	uint32_t divider = 0;
+
+	wide_bus = (mmc->bus_width == 4);
+
+	if (!mmc->clock)
+		return;
+
+	divider = DIV_ROUND_UP(get_PCLK(), mmc->clock);
+	if (divider)
+		divider--;
+
+	writel(divider, &sdi_regs->sdipre);
+	mdelay(125);
+}
+
+static int s3cmmc_init(struct mmc *mmc)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
+
+	/* Start the clock. */
+	setbits_le32(&clk_power->clkcon, 1 << 9);
+
+#if defined(CONFIG_S3C2440)
+	writel(S3C2440_SDICON_SDRESET, &sdi_regs->sdicon);
+	mdelay(10);
+	writel(0x7fffff, &sdi_regs->sdidtimer);
+#else
+	writel(0xffff, &sdi_regs->sdidtimer);
+#endif
+	writel(MMC_MAX_BLOCK_LEN, &sdi_regs->sdibsize);
+	writel(0x0, &sdi_regs->sdiimsk);
+
+	writel(S3C2410_SDICON_FIFORESET | S3C2410_SDICON_CLOCKTYPE,
+	       &sdi_regs->sdicon);
+
+	mdelay(125);
+
+	return 0;
+}
+
+struct s3cmmc_priv {
+	struct mmc_config	cfg;
+	int (*getcd)(struct mmc *);
+	int (*getwp)(struct mmc *);
+};
+
+static int s3cmmc_getcd(struct mmc *mmc)
+{
+	struct s3cmmc_priv *priv = mmc->priv;
+	if (priv->getcd)
+		return priv->getcd(mmc);
+	else
+		return 0;
+}
+
+static int s3cmmc_getwp(struct mmc *mmc)
+{
+	struct s3cmmc_priv *priv = mmc->priv;
+	if (priv->getwp)
+		return priv->getwp(mmc);
+	else
+		return 0;
+}
+
+static const struct mmc_ops s3cmmc_ops = {
+	.send_cmd	= s3cmmc_send_cmd,
+	.set_ios	= s3cmmc_set_ios,
+	.init		= s3cmmc_init,
+	.getcd		= s3cmmc_getcd,
+	.getwp		= s3cmmc_getwp,
+};
+
+int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
+		      int (*getwp)(struct mmc *))
+{
+	struct s3cmmc_priv	*priv;
+	struct mmc		*mmc;
+	struct mmc_config	*cfg;
+
+	priv = calloc(1, sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
+	cfg = &priv->cfg;
+
+	cfg->name = "S3C MMC";
+	cfg->ops = &s3cmmc_ops;
+	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS;
+	cfg->f_min = 400000;
+	cfg->f_max = get_PCLK() / 2;
+	cfg->b_max = 0x80;
+
+#if defined(CONFIG_S3C2410)
+	/*
+	 * S3C2410 has some bug that prevents reliable
+	 * operation at higher speed
+	 */
+	cfg->f_max /= 2;
+#endif
+
+	mmc = mmc_create(cfg, priv);
+	if (!mmc) {
+		free(priv);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index ef91b92..85cf22d 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -421,6 +421,7 @@
 		data += read_len;
 	}
 
+	free(cmd);
 	return ret;
 }
 
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index de9c0e9..5f910c2 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2012 Freescale Semiconductor, Inc.
- *	Andy Fleming <afleming@freescale.com>
+ *	Andy Fleming <afleming@gmail.com>
  *	Roy Zang <tie-fei.zang@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c
index faec317..095f00c 100644
--- a/drivers/net/fm/tgec_phy.c
+++ b/drivers/net/fm/tgec_phy.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *	Andy Fleming <afleming@freescale.com>
+ *	Andy Fleming <afleming@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  * Some part is taken from tsec.c
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index c92276f..2969184 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -428,10 +428,6 @@
 	clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
 	debug("Activate CS, bus %d\n", spi_slave->slave.bus);
 	spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
-
-	/* Remember time of this transaction so we can honour the bus delay */
-	if (spi_slave->bus->deactivate_delay_us)
-		spi_slave->last_transaction_us = timer_get_us();
 }
 
 /**
@@ -445,6 +441,11 @@
 	struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
 
 	setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+
+	/* Remember time of this transaction so we can honour the bus delay */
+	if (spi_slave->bus->deactivate_delay_us)
+		spi_slave->last_transaction_us = timer_get_us();
+
 	debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
 }
 
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index f3f029d..2d5f385 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -30,6 +30,10 @@
 #define reg_read readl
 #define reg_write(a, v) writel(v, a)
 
+#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
+#define CONFIG_SYS_SPI_MXC_WAIT		(CONFIG_SYS_HZ/100)	/* 10 ms */
+#endif
+
 struct mxc_spi_slave {
 	struct spi_slave slave;
 	unsigned long	base;
@@ -212,6 +216,8 @@
 	int nbytes = DIV_ROUND_UP(bitlen, 8);
 	u32 data, cnt, i;
 	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
+	u32 ts;
+	int status;
 
 	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 		__func__, bitlen, (u32)dout, (u32)din);
@@ -272,9 +278,16 @@
 	reg_write(&regs->ctrl, mxcs->ctrl_reg |
 		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
 
+	ts = get_timer(0);
+	status = reg_read(&regs->stat);
 	/* Wait until the TC (Transfer completed) bit is set */
-	while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
-		;
+	while ((status & MXC_CSPICTRL_TC) == 0) {
+		if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
+			printf("spi_xchg_single: Timeout!\n");
+			return -1;
+		}
+		status = reg_read(&regs->stat);
+	}
 
 	/* Transfer completed, clear any pending request */
 	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 7ddea9b..7d81fbd 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -53,6 +53,8 @@
 		mode |= SPI_CPHA;
 	if (fdtdec_get_bool(blob, node, "spi-cs-high"))
 		mode |= SPI_CS_HIGH;
+	if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
+		mode |= SPI_PREAMBLE;
 	return spi_setup_slave(busnum, cs, max_hz, mode);
 }
 #endif
diff --git a/include/atmel_mci.h b/include/atmel_mci.h
index 090574d..de24148 100644
--- a/include/atmel_mci.h
+++ b/include/atmel_mci.h
@@ -36,7 +36,9 @@
 	u32	ier;	/* 0x44 */
 	u32	idr;	/* 0x48 */
 	u32	imr;	/* 0x4c */
-	u32	reserved[43];
+	u32	dma;	/* 0x50 */
+	u32	cfg;	/* 0x54 */
+	u32	reserved[41];
 	u32	version;
 } atmel_mci_t;
 
@@ -67,6 +69,10 @@
 #define MMCI_PDCPADV_SIZE			1
 #define MMCI_PDCMODE_OFFSET			15
 #define MMCI_PDCMODE_SIZE			1
+/* MCI IP version >= 0x500, MR bit 16 used for CLKODD */
+#define MMCI_CLKODD_OFFSET			16
+#define MMCI_CLKODD_SIZE			1
+/* MCI IP version < 0x200, MR higher 16bits for BLKLEN */
 #define MMCI_BLKLEN_OFFSET			16
 #define MMCI_BLKLEN_SIZE			16
 
@@ -185,6 +191,16 @@
 #define MMCI_TRTYP_MULTI_BLOCK			1
 #define MMCI_TRTYP_STREAM			2
 
+/* Bitfields in CFG */
+#define MMCI_FIFOMODE_OFFSET			0
+#define MMCI_FIFOMODE_SIZE			1
+#define MMCI_FERRCTRL_OFFSET			4
+#define MMCI_FERRCTRL_SIZE			1
+#define MMCI_HSMODE_OFFSET			8
+#define MMCI_HSMODE_SIZE			1
+#define MMCI_LSYNC_OFFSET			12
+#define MMCI_LSYNC_SIZE				1
+
 /* Bit manipulation macros */
 #define MMCI_BIT(name)					\
 	(1 << MMCI_##name##_OFFSET)
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index efd9635..a0f9d29 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -377,6 +377,14 @@
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
 
 /*
+ * Hardware Watchdog
+ */
+#define CONFIG_WATCHDOG			/* enable CPU watchdog */
+#define CONFIG_WATCHDOG_PRESC 34	/* wdog prescaler 2^(64-34) (~10min) */
+#define CONFIG_WATCHDOG_RC WRC_CHIP	/* reset chip on watchdog event */
+
+
+/*
  * additionnal command line configuration.
  */
 #define CONFIG_CMD_PCI
diff --git a/include/configs/openrd.h b/include/configs/openrd.h
index 8fab6e6..3eb408f 100644
--- a/include/configs/openrd.h
+++ b/include/configs/openrd.h
@@ -49,6 +49,7 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
@@ -123,4 +124,11 @@
 #define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
 #endif /*CONFIG_MVSATA_IDE*/
 
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MVEBU_MMC
+#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
+#endif /* CONFIG_CMD_MMC */
+
 #endif /* _CONFIG_OPENRD_BASE_H */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index ecc93bc..3d6ff09 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -31,6 +31,7 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
@@ -82,6 +83,16 @@
 #endif /* CONFIG_CMD_NET */
 
 /*
+ * SDIO/MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MVEBU_MMC
+#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
+#endif /* CONFIG_CMD_MMC */
+
+/*
  * File system
  */
 #define CONFIG_CMD_EXT2
diff --git a/include/environment.h b/include/environment.h
index 08679ae..1fdbdad 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -180,6 +180,15 @@
 extern void env_reloc(void);
 #endif
 
+#ifdef CONFIG_ENV_IS_IN_MMC
+#include <mmc.h>
+
+extern int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
+# ifdef CONFIG_SYS_MMC_ENV_PART
+extern uint mmc_get_env_part(struct mmc *mmc);
+# endif
+#endif
+
 #ifndef DO_DEPS_ONLY
 
 #include <env_attr.h>
diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h
new file mode 100644
index 0000000..28d98fe
--- /dev/null
+++ b/include/mvebu_mmc.h
@@ -0,0 +1,278 @@
+/*
+ * Marvell MMC/SD/SDIO driver
+ *
+ * (C) Copyright 2012
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Maen Suleiman, Gerald Kerma
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MVEBU_MMC_H__
+#define __MVEBU_MMC_H__
+
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+#define MMC_BLOCK_SIZE				512
+
+/*
+ * Clock rates
+ */
+
+#define MVEBU_MMC_CLOCKRATE_MAX			50000000
+#define MVEBU_MMC_BASE_DIV_MAX			0x7ff
+#define MVEBU_MMC_BASE_FAST_CLOCK		CONFIG_SYS_TCLK
+#define MVEBU_MMC_BASE_FAST_CLK_100		100000000
+#define MVEBU_MMC_BASE_FAST_CLK_200		200000000
+
+/* SDIO register */
+#define SDIO_SYS_ADDR_LOW			0x000
+#define SDIO_SYS_ADDR_HI			0x004
+#define SDIO_BLK_SIZE				0x008
+#define SDIO_BLK_COUNT				0x00c
+#define SDIO_ARG_LOW				0x010
+#define SDIO_ARG_HI				0x014
+#define SDIO_XFER_MODE				0x018
+#define SDIO_CMD				0x01c
+#define SDIO_RSP(i)				(0x020 + ((i)<<2))
+#define SDIO_RSP0				0x020
+#define SDIO_RSP1				0x024
+#define SDIO_RSP2				0x028
+#define SDIO_RSP3				0x02c
+#define SDIO_RSP4				0x030
+#define SDIO_RSP5				0x034
+#define SDIO_RSP6				0x038
+#define SDIO_RSP7				0x03c
+#define SDIO_BUF_DATA_PORT			0x040
+#define SDIO_RSVED				0x044
+#define SDIO_HW_STATE				0x048
+#define SDIO_PRESENT_STATE0			0x048
+#define SDIO_PRESENT_STATE1			0x04c
+#define SDIO_HOST_CTRL				0x050
+#define SDIO_BLK_GAP_CTRL			0x054
+#define SDIO_CLK_CTRL				0x058
+#define SDIO_SW_RESET				0x05c
+#define SDIO_NOR_INTR_STATUS			0x060
+#define SDIO_ERR_INTR_STATUS			0x064
+#define SDIO_NOR_STATUS_EN			0x068
+#define SDIO_ERR_STATUS_EN			0x06c
+#define SDIO_NOR_INTR_EN			0x070
+#define SDIO_ERR_INTR_EN			0x074
+#define SDIO_AUTOCMD12_ERR_STATUS		0x078
+#define SDIO_CURR_BYTE_LEFT			0x07c
+#define SDIO_CURR_BLK_LEFT			0x080
+#define SDIO_AUTOCMD12_ARG_LOW			0x084
+#define SDIO_AUTOCMD12_ARG_HI			0x088
+#define SDIO_AUTOCMD12_INDEX			0x08c
+#define SDIO_AUTO_RSP(i)			(0x090 + ((i)<<2))
+#define SDIO_AUTO_RSP0				0x090
+#define SDIO_AUTO_RSP1				0x094
+#define SDIO_AUTO_RSP2				0x098
+#define SDIO_CLK_DIV				0x128
+
+#define WINDOW_CTRL(i)				(0x108 + ((i) << 3))
+#define WINDOW_BASE(i)				(0x10c + ((i) << 3))
+
+/* SDIO_PRESENT_STATE */
+#define CARD_BUSY				(1 << 1)
+#define CMD_INHIBIT				(1 << 0)
+#define CMD_TXACTIVE				(1 << 8)
+#define CMD_RXACTIVE				(1 << 9)
+#define CMD_AUTOCMD12ACTIVE			(1 << 14)
+#define CMD_BUS_BUSY				(CMD_AUTOCMD12ACTIVE |	\
+						CMD_RXACTIVE |	\
+						CMD_TXACTIVE |	\
+						CMD_INHIBIT |	\
+						CARD_BUSY)
+
+/*
+ * SDIO_CMD
+ */
+
+#define SDIO_CMD_RSP_NONE			(0 << 0)
+#define SDIO_CMD_RSP_136			(1 << 0)
+#define SDIO_CMD_RSP_48				(2 << 0)
+#define SDIO_CMD_RSP_48BUSY			(3 << 0)
+
+#define SDIO_CMD_CHECK_DATACRC16		(1 << 2)
+#define SDIO_CMD_CHECK_CMDCRC			(1 << 3)
+#define SDIO_CMD_INDX_CHECK			(1 << 4)
+#define SDIO_CMD_DATA_PRESENT			(1 << 5)
+#define SDIO_UNEXPECTED_RESP			(1 << 7)
+
+#define SDIO_CMD_INDEX(x)			((x) << 8)
+
+/*
+ * SDIO_XFER_MODE
+ */
+
+#define SDIO_XFER_MODE_STOP_CLK			(1 << 5)
+#define SDIO_XFER_MODE_HW_WR_DATA_EN		(1 << 1)
+#define SDIO_XFER_MODE_AUTO_CMD12		(1 << 2)
+#define SDIO_XFER_MODE_INT_CHK_EN		(1 << 3)
+#define SDIO_XFER_MODE_TO_HOST			(1 << 4)
+#define SDIO_XFER_MODE_DMA			(0 << 6)
+
+/*
+ * SDIO_HOST_CTRL
+ */
+
+#define SDIO_HOST_CTRL_PUSH_PULL_EN		(1 << 0)
+
+#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY	(0 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY	(1 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO	(2 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC		(3 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_MASK		(3 << 1)
+
+#define SDIO_HOST_CTRL_BIG_ENDIAN		(1 << 3)
+#define SDIO_HOST_CTRL_LSB_FIRST		(1 << 4)
+#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT		(0 << 9)
+#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS	(1 << 9)
+#define SDIO_HOST_CTRL_HI_SPEED_EN		(1 << 10)
+
+#define SDIO_HOST_CTRL_TMOUT_MAX		0xf
+#define SDIO_HOST_CTRL_TMOUT_MASK		(0xf << 11)
+#define SDIO_HOST_CTRL_TMOUT(x)			((x) << 11)
+#define SDIO_HOST_CTRL_TMOUT_EN			(1 << 15)
+
+/*
+ * SDIO_SW_RESET
+ */
+
+#define SDIO_SW_RESET_NOW			(1 << 8)
+
+/*
+ * Normal interrupt status bits
+ */
+
+#define SDIO_NOR_ERROR				(1 << 15)
+#define SDIO_NOR_UNEXP_RSP			(1 << 14)
+#define SDIO_NOR_AUTOCMD12_DONE			(1 << 13)
+#define SDIO_NOR_SUSPEND_ON			(1 << 12)
+#define SDIO_NOR_LMB_FF_8W_AVAIL		(1 << 11)
+#define SDIO_NOR_LMB_FF_8W_FILLED		(1 << 10)
+#define SDIO_NOR_READ_WAIT_ON			(1 << 9)
+#define SDIO_NOR_CARD_INT			(1 << 8)
+#define SDIO_NOR_READ_READY			(1 << 5)
+#define SDIO_NOR_WRITE_READY			(1 << 4)
+#define SDIO_NOR_DMA_INI			(1 << 3)
+#define SDIO_NOR_BLK_GAP_EVT			(1 << 2)
+#define SDIO_NOR_XFER_DONE			(1 << 1)
+#define SDIO_NOR_CMD_DONE			(1 << 0)
+
+/*
+ * Error status bits
+ */
+
+#define SDIO_ERR_CRC_STATUS			(1 << 14)
+#define SDIO_ERR_CRC_STARTBIT			(1 << 13)
+#define SDIO_ERR_CRC_ENDBIT			(1 << 12)
+#define SDIO_ERR_RESP_TBIT			(1 << 11)
+#define SDIO_ERR_XFER_SIZE			(1 << 10)
+#define SDIO_ERR_CMD_STARTBIT			(1 << 9)
+#define SDIO_ERR_AUTOCMD12			(1 << 8)
+#define SDIO_ERR_DATA_ENDBIT			(1 << 6)
+#define SDIO_ERR_DATA_CRC			(1 << 5)
+#define SDIO_ERR_DATA_TIMEOUT			(1 << 4)
+#define SDIO_ERR_CMD_INDEX			(1 << 3)
+#define SDIO_ERR_CMD_ENDBIT			(1 << 2)
+#define SDIO_ERR_CMD_CRC			(1 << 1)
+#define SDIO_ERR_CMD_TIMEOUT			(1 << 0)
+/* enable all for polling */
+#define SDIO_POLL_MASK				0xffff
+
+/*
+ * CMD12 error status bits
+ */
+
+#define SDIO_AUTOCMD12_ERR_NOTEXE		(1 << 0)
+#define SDIO_AUTOCMD12_ERR_TIMEOUT		(1 << 1)
+#define SDIO_AUTOCMD12_ERR_CRC			(1 << 2)
+#define SDIO_AUTOCMD12_ERR_ENDBIT		(1 << 3)
+#define SDIO_AUTOCMD12_ERR_INDEX		(1 << 4)
+#define SDIO_AUTOCMD12_ERR_RESP_T_BIT		(1 << 5)
+#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT	(1 << 6)
+
+#define MMC_RSP_PRESENT				(1 << 0)
+/* 136 bit response */
+#define MMC_RSP_136				(1 << 1)
+/* expect valid crc */
+#define MMC_RSP_CRC				(1 << 2)
+/* card may send busy */
+#define MMC_RSP_BUSY				(1 << 3)
+/* response contains opcode */
+#define MMC_RSP_OPCODE				(1 << 4)
+
+#define MMC_BUSMODE_OPENDRAIN			1
+#define MMC_BUSMODE_PUSHPULL			2
+
+#define MMC_BUS_WIDTH_1				0
+#define MMC_BUS_WIDTH_4				2
+#define MMC_BUS_WIDTH_8				3
+
+/* Can the host do 4 bit transfers */
+#define MMC_CAP_4_BIT_DATA			(1 << 0)
+/* Can do MMC high-speed timing */
+#define MMC_CAP_MMC_HIGHSPEED			(1 << 1)
+/* Can do SD high-speed timing */
+#define MMC_CAP_SD_HIGHSPEED			(1 << 2)
+/* Can signal pending SDIO IRQs */
+#define MMC_CAP_SDIO_IRQ			(1 << 3)
+/* Talks only SPI protocols */
+#define MMC_CAP_SPI				(1 << 4)
+/* Needs polling for card-detection */
+#define MMC_CAP_NEEDS_POLL			(1 << 5)
+/* Can the host do 8 bit transfers */
+#define MMC_CAP_8_BIT_DATA			(1 << 6)
+
+/* Nonremovable e.g. eMMC */
+#define MMC_CAP_NONREMOVABLE			(1 << 8)
+/* Waits while card is busy */
+#define MMC_CAP_WAIT_WHILE_BUSY			(1 << 9)
+/* Allow erase/trim commands */
+#define MMC_CAP_ERASE				(1 << 10)
+/* can support DDR mode at 1.8V */
+#define MMC_CAP_1_8V_DDR			(1 << 11)
+/* can support DDR mode at 1.2V */
+#define MMC_CAP_1_2V_DDR			(1 << 12)
+/* Can power off after boot */
+#define MMC_CAP_POWER_OFF_CARD			(1 << 13)
+/* CMD14/CMD19 bus width ok */
+#define MMC_CAP_BUS_WIDTH_TEST			(1 << 14)
+/* Host supports UHS SDR12 mode */
+#define MMC_CAP_UHS_SDR12			(1 << 15)
+/* Host supports UHS SDR25 mode */
+#define MMC_CAP_UHS_SDR25			(1 << 16)
+/* Host supports UHS SDR50 mode */
+#define MMC_CAP_UHS_SDR50			(1 << 17)
+/* Host supports UHS SDR104 mode */
+#define MMC_CAP_UHS_SDR104			(1 << 18)
+/* Host supports UHS DDR50 mode */
+#define MMC_CAP_UHS_DDR50			(1 << 19)
+/* Host supports Driver Type A */
+#define MMC_CAP_DRIVER_TYPE_A			(1 << 23)
+/* Host supports Driver Type C */
+#define MMC_CAP_DRIVER_TYPE_C			(1 << 24)
+/* Host supports Driver Type D */
+#define MMC_CAP_DRIVER_TYPE_D			(1 << 25)
+/* CMD23 supported. */
+#define MMC_CAP_CMD23				(1 << 30)
+/* Hardware reset */
+#define MMC_CAP_HW_RESET			(1 << 31)
+
+struct mvebu_mmc_cfg {
+	u32	mvebu_mmc_base;
+	u32	mvebu_mmc_clk;
+	u8	max_bus_width;
+	struct mmc_config cfg;
+};
+
+/*
+ * Functions prototypes
+ */
+
+int mvebu_mmc_init(bd_t *bis);
+
+#endif /* __MVEBU_MMC_H__ */
diff --git a/include/phy.h b/include/phy.h
index d3ecd63..2fcc328 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -1,6 +1,6 @@
 /*
  * Copyright 2011 Freescale Semiconductor, Inc.
- *	Andy Fleming <afleming@freescale.com>
+ *	Andy Fleming <afleming@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
diff --git a/include/watchdog.h b/include/watchdog.h
index aacacb9..bd0a8d6 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -95,4 +95,8 @@
 #if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
 	void hw_watchdog_init(void);
 #endif
+
+#if defined(CONFIG_MPC85xx) && !defined(__ASSEMBLY__)
+	void init_85xx_watchdog(void);
+#endif
 #endif /* _WATCHDOG_H_ */