Merge branch 'master' of git://git.denx.de/u-boot-avr32
diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts
index 5a39e93..8be6adb 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -163,12 +163,15 @@
spi@7000d400 {
status = "okay";
+ spi-deactivate-delay = <200>;
+ spi-max-frequency = <3000000>;
cros_ec: cros-ec@0 {
compatible = "google,cros-ec-spi";
spi-max-frequency = <3000000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
+ ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
reg = <0>;
google,cros-ec-spi-msg-delay = <2000>;
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 04011ae..f9dd3c8 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -336,4 +336,12 @@
void tegra30_set_up_pllp(void);
+/**
+ * Enable output clock for external peripherals
+ *
+ * @param clk_id Clock ID to output (1, 2 or 3)
+ * @return 0 if OK. -ve on error
+ */
+int clock_external_output(int clk_id);
+
#endif /* _TEGRA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h
index 83f9f47..b64f9d8 100644
--- a/arch/arm/include/asm/arch-tegra/sys_proto.h
+++ b/arch/arm/include/asm/arch-tegra/sys_proto.h
@@ -25,4 +25,11 @@
*/
int tegra_lcd_pmic_init(int board_id);
+/**
+ * nvidia_board_init() - perform any board-specific init
+ *
+ * @return 0 if OK, -ve on error
+ */
+int nvidia_board_init(void);
+
#endif
diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
index 7005855..3c67e72 100644
--- a/arch/arm/include/asm/arch-tegra124/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -285,12 +285,12 @@
/* 184 */
PERIPH_ID_GPU,
PERIPH_ID_AMX1,
- PERIPH_ID_X_RESERVED26,
- PERIPH_ID_X_RESERVED27,
- PERIPH_ID_X_RESERVED28,
- PERIPH_ID_X_RESERVED29,
- PERIPH_ID_X_RESERVED30,
- PERIPH_ID_X_RESERVED31,
+ PERIPH_ID_AFC5,
+ PERIPH_ID_AFC4,
+ PERIPH_ID_AFC3,
+ PERIPH_ID_AFC2,
+ PERIPH_ID_AFC1,
+ PERIPH_ID_AFC0,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h
index d6f515f..7818b1b 100644
--- a/arch/arm/include/asm/arch-tegra124/flow.h
+++ b/arch/arm/include/asm/arch-tegra124/flow.h
@@ -26,6 +26,12 @@
u32 cpu_pwr_csr; /* offset 0x38 */
u32 mpid; /* offset 0x3c */
u32 ram_repair; /* offset 0x40 */
+ u32 flow_dbg_sel; /* offset 0x44 */
+ u32 flow_dbg_cnt0; /* offset 0x48 */
+ u32 flow_dbg_cnt1; /* offset 0x4c */
+ u32 flow_dbg_qual; /* offset 0x50 */
+ u32 flow_ctlr_spare; /* offset 0x54 */
+ u32 ram_repair_cluster1;/* offset 0x58 */
};
/* HALT_COP_EVENTS_0, 0x04 */
@@ -43,4 +49,10 @@
#define CSR_WAIT_WFI_SHIFT 8
#define CSR_PWR_OFF_STS (1 << 16)
+/* RAM_REPAIR, 0x40, 0x58 */
+enum {
+ RAM_REPAIR_REQ = 0x1 << 0,
+ RAM_REPAIR_STS = 0x1 << 1,
+};
+
#endif /* _TEGRA124_FLOW_H_ */
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 131802a..ebcee4e 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -107,6 +107,11 @@
return 0;
}
+__weak int nvidia_board_init(void)
+{
+ return 0;
+}
+
/*
* Routine: board_init
* Description: Early hardware init.
@@ -180,8 +185,7 @@
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
-
- return 0;
+ return nvidia_board_init();
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index cdd5438..24047b8 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -17,11 +17,13 @@
/* Tegra SoC common clock control functions */
#include <common.h>
+#include <errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/timer.h>
#include <div64.h>
#include <fdtdec.h>
@@ -82,7 +84,7 @@
assert(clock_id_is_pll(clkid));
if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
- debug("%s: Invalid PLL\n", __func__);
+ debug("%s: Invalid PLL %d\n", __func__, clkid);
return NULL;
}
return &clkrst->crc_pll[clkid];
@@ -118,9 +120,12 @@
unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon)
{
- struct clk_pll *pll = get_pll(clkid);
+ struct clk_pll *pll = NULL;
u32 misc_data, data;
+ if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
+ pll = get_pll(clkid);
+
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
* This works only because:
@@ -702,3 +707,18 @@
set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
}
+
+int clock_external_output(int clk_id)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ if (clk_id >= 1 && clk_id <= 3) {
+ setbits_le32(&pmc->pmc_clk_out_cntrl,
+ 1 << (2 + (clk_id - 1) * 8));
+ } else {
+ printf("%s: Unknown output clock id %d\n", __func__, clk_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 6331cd4..30ae036 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -9,7 +9,7 @@
#include <asm/io.h>
#include <asm/types.h>
-
+#include <asm/arch/flow.h>
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
@@ -75,11 +75,29 @@
return 0;
}
+static void tegra_powergate_ram_repair(void)
+{
+#ifdef CONFIG_TEGRA124
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+
+ /* Request RAM repair for cluster 0 and wait until complete */
+ setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+ while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
+ ;
+
+ /* Same for cluster 1 */
+ setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+ while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
+ ;
+#endif
+}
+
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph)
{
int err;
+ tegra_powergate_ram_repair();
reset_set_enable(periph, 1);
err = tegra_powergate_power_on(id);
diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
index 6579e3f..f3324ff 100644
--- a/arch/arm/mach-tegra/tegra124/Kconfig
+++ b/arch/arm/mach-tegra/tegra124/Kconfig
@@ -10,7 +10,7 @@
select CPU_V7_HAS_VIRT if !SPL_BUILD
config TARGET_NYAN_BIG
- bool "Google/NVIDIA Nyan-big Chrombook"
+ bool "Google/NVIDIA Nyan-big Chromebook"
help
Nyan Big is a Tegra124 clamshell board that is very similar
to venice2, but it has a different panel, the sdcard CD and WP
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 2d17550..b955848 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -475,7 +475,7 @@
PERIPHC_ACTMON,
/* 120 */
- NONE(EXTPERIPH1),
+ PERIPHC_EXTPERIPH1,
NONE(EXTPERIPH2),
NONE(EXTPERIPH3),
NONE(OOB),
diff --git a/board/nvidia/nyan-big/MAINTAINERS b/board/nvidia/nyan-big/MAINTAINERS
index ff74627..7790777 100644
--- a/board/nvidia/nyan-big/MAINTAINERS
+++ b/board/nvidia/nyan-big/MAINTAINERS
@@ -1,4 +1,4 @@
-NORRIN BOARD
+NYAN-BIG BOARD
M: Allen Martin <amartin@nvidia.com>
S: Maintained
F: board/nvidia/nyan-big/
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index ae8874b..ba96401 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -8,7 +8,12 @@
#include <common.h>
#include <errno.h>
#include <asm/gpio.h>
+#include <asm/io.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
#include <power/as3722.h>
#include <power/pmic.h>
#include "pinmux-config-nyan-big.h"
@@ -57,3 +62,67 @@
return 0;
}
+
+/* Setup required information for Linux kernel */
+static void setup_kernel_info(void)
+{
+ struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
+
+ /* The kernel graphics driver needs this region locked down */
+ writel(0, &mc->mc_video_protect_bom);
+ writel(0, &mc->mc_video_protect_size_mb);
+ writel(1, &mc->mc_video_protect_reg_ctrl);
+}
+
+/*
+ * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
+ * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
+ * Otherwise reading AHUB devices will hang when the kernel boots.
+ */
+static void enable_required_clocks(void)
+{
+ static enum periph_id ids[] = {
+ PERIPH_ID_I2S0,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_AUDIO,
+ PERIPH_ID_APBIF,
+ PERIPH_ID_DAM0,
+ PERIPH_ID_DAM1,
+ PERIPH_ID_DAM2,
+ PERIPH_ID_AMX0,
+ PERIPH_ID_AMX1,
+ PERIPH_ID_ADX0,
+ PERIPH_ID_ADX1,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_AFC0,
+ PERIPH_ID_AFC1,
+ PERIPH_ID_AFC2,
+ PERIPH_ID_AFC3,
+ PERIPH_ID_AFC4,
+ PERIPH_ID_AFC5,
+ PERIPH_ID_EXTPERIPH1
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ids); i++)
+ clock_enable(ids[i]);
+ udelay(2);
+ for (i = 0; i < ARRAY_SIZE(ids); i++)
+ reset_set_enable(ids[i], 0);
+}
+
+int nvidia_board_init(void)
+{
+ clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
+ clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
+
+ /* For external MAX98090 audio codec */
+ clock_external_output(1);
+ setup_kernel_info();
+ enable_required_clocks();
+
+ return 0;
+}
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 92acab2..81949e8 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -6,3 +6,8 @@
CONFIG_CMD_NET=y
CONFIG_DISPLAY_PORT=y
CONFIG_VIDEO_TEGRA124=y
+CONFIG_DM_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 4bec663..d7eecd5 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -143,24 +143,30 @@
{
struct tegra_spi_platdata *plat = dev_get_platdata(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs;
+ ulong rate;
priv->regs = (struct spi_regs *)plat->base;
+ regs = priv->regs;
priv->last_transaction_us = timer_get_us();
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
- return 0;
-}
-
-static int tegra114_spi_claim_bus(struct udevice *dev)
-{
- struct udevice *bus = dev->parent;
- struct tegra114_spi_priv *priv = dev_get_priv(bus);
- struct spi_regs *regs = priv->regs;
-
- /* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
+ /*
+ * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
+ * back to the oscillator if that is too fast.
+ */
+ rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
+ if (rate > priv->freq + 100000) {
+ rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
+ priv->freq);
+ if (rate != priv->freq) {
+ printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
+ bus->name, priv->freq, rate);
+ }
+ }
/* Clear stale status here */
setbits_le32(®s->fifo_status,
@@ -175,9 +181,8 @@
SPI_FIFO_STS_RX_FIFO_EMPTY);
debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
- /* Set master mode and sw controlled CS */
- setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
- (priv->mode << SPI_CMD1_MODE_SHIFT));
+ setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
+ (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1));
return 0;
@@ -249,6 +254,9 @@
ret = 0;
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(dev);
+
/* clear all error status bits */
reg = readl(®s->fifo_status);
writel(reg, ®s->fifo_status);
@@ -260,9 +268,6 @@
/* set xfer size to 1 block (32 bits) */
writel(0, ®s->dma_blk);
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(dev);
-
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
int bytes;
@@ -385,7 +390,6 @@
}
static const struct dm_spi_ops tegra114_spi_ops = {
- .claim_bus = tegra114_spi_claim_bus,
.xfer = tegra114_spi_xfer,
.set_speed = tegra114_spi_set_speed,
.set_mode = tegra114_spi_set_mode,
diff --git a/drivers/video/tegra124/tegra124-lcd.c b/drivers/video/tegra124/tegra124-lcd.c
index 2733590..cfdc77f 100644
--- a/drivers/video/tegra124/tegra124-lcd.c
+++ b/drivers/video/tegra124/tegra124-lcd.c
@@ -51,15 +51,13 @@
int ret;
clock_set_up_plldp();
- clock_adjust_periph_pll_div(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
- 408000000, NULL);
+ clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
clock_enable(PERIPH_ID_HOST1X);
clock_enable(PERIPH_ID_DISP1);
clock_enable(PERIPH_ID_PWM);
clock_enable(PERIPH_ID_DPAUX);
clock_enable(PERIPH_ID_SOR0);
-
udelay(2);
reset_set_enable(PERIPH_ID_HOST1X, 0);
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index a92112f..b99d762 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -47,6 +47,7 @@
#define CONFIG_AS3722_POWER
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CMD_BMP
/* Align LCD to 1MB boundary */
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
@@ -77,8 +78,14 @@
#define CONFIG_CMD_DHCP
#define CONFIG_FIT
+#define CONFIG_FIT_BEST_MATCH
#define CONFIG_OF_LIBFDT
+#define CONFIG_KEYBOARD
+
+#undef CONFIG_LOADADDR
+#define CONFIG_LOADADDR 0x82408000
+
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index 0cea795..483222f 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -40,8 +40,14 @@
#define STDOUT_LCD ""
#endif
+#ifdef CONFIG_CROS_EC_KEYB
+#define STDOUT_CROS_EC ",cros-ec-keyb"
+#else
+#define STDOUT_CROS_EC ""
+#endif
+
#define TEGRA_DEVICE_SETTINGS \
- "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
+ "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \
"stdout=serial" STDOUT_LCD "\0" \
"stderr=serial" STDOUT_LCD "\0" \
""
@@ -52,13 +58,18 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
+#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA_DEVICE_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
"fdt_high=ffffffff\0" \
"initrd_high=ffffffff\0" \
BOOTENV \
- BOARD_EXTRA_ENV_SETTINGS
+ BOARD_EXTRA_ENV_SETTINGS \
+ CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
#define CONFIG_TEGRA_SPI
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 0bac9ad..2d58422 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -104,7 +104,7 @@
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)