commit 23c34af48ff0dbff3bbaa8e94df3bf40350a709f
author Richard Retanubun <RichardRetanubun@RuggedCom.com> Wed Jun 17 16:00:41 2009 -0400
committer Ben Warren <biggerbadderben@gmail.com> Mon May 03 14:52:48 2010 -0700
tree fa46b9363c78c501e8309cba893691612cb029f6
parent 9739946cc5b616c026d433bd07d193cf452ddea0

83xx: UEC: Added support for bitBang MII driver access to PHYs

This patch enabled support for having PHYs on bitBang MII and uec MII
operating at the same time. Modeled after the MPC8360ADS implementation.

Added the ability to specify which ethernet interfaces have bitbang SMI
on the board header file.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

drivers/qe/uec.c

diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 27dc500..ccbf27d 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -595,8 +595,7 @@
 	adjust_link(dev);
 }
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
-	&& !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 
 /*
  * Find a device index from the devlist by name
@@ -1388,8 +1387,7 @@
 		return err;
 	}
 
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
-	&& !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 	miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
 #endif
 

drivers/qe/uec_phy.c

diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index fa48fea..3baffe4 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -93,6 +93,27 @@
 	CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
 };
 
+/*--------------------------------------------------------------------+
+ * BitBang MII support for ethernet ports
+ *
+ * Based from MPC8560ADS implementation
+ *--------------------------------------------------------------------*/
+/*
+ * Example board header file to define bitbang ethernet ports:
+ *
+ * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
+ * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("FSL UEC0")
+*/
+#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
+#define CONFIG_SYS_BITBANG_PHY_PORTS	/* default is an empty array */
+#endif
+
+#if defined(CONFIG_BITBANGMII)
+static const char *bitbang_phy_port[] = {
+	CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
+};
+#endif /* CONFIG_BITBANGMII */
+
 static void config_genmii_advert (struct uec_mii_info *mii_info);
 static void genmii_setup_forced (struct uec_mii_info *mii_info);
 static void genmii_restart_aneg (struct uec_mii_info *mii_info);
@@ -113,6 +134,19 @@
 	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
 	u32 tmp_reg;
 
+
+#if defined(CONFIG_BITBANGMII)
+	u32 i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+		if (strncmp(dev->name, bitbang_phy_port[i],
+			sizeof(dev->name)) == 0) {
+			(void)bb_miiphy_write(NULL, mii_id, regnum, value);
+			return;
+		}
+	}
+#endif /* CONFIG_BITBANGMII */
+
 	ug_regs = ugeth->uec_mii_regs;
 
 	/* Stop the MII management read cycle */
@@ -140,6 +174,19 @@
 	u32 tmp_reg;
 	u16 value;
 
+
+#if defined(CONFIG_BITBANGMII)
+	u32 i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+		if (strncmp(dev->name, bitbang_phy_port[i],
+			sizeof(dev->name)) == 0) {
+			(void)bb_miiphy_read(NULL, mii_id, regnum, &value);
+			return (value);
+		}
+	}
+#endif /* CONFIG_BITBANGMII */
+
 	ug_regs = ugeth->uec_mii_regs;
 
 	/* Setting up the MII Mangement Address Register */