Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze
diff --git a/.travis.yml b/.travis.yml
new file mode 100644
index 0000000..90f0fd7
--- /dev/null
+++ b/.travis.yml
@@ -0,0 +1,150 @@
+# Copyright Roger Meier <r.meier@siemens.com>
+# SPDX-License-Identifier: GPL-2.0+
+
+# build U-Boot on Travis CI - https://travis-ci.org/
+
+language: c
+
+cache:
+ - apt
+
+install:
+ # install U-Boot build dependencies
+ - sudo apt-get install -qq cppcheck sloccount sparse bc libsdl-dev gcc-arm-linux-gnueabi gcc-arm-linux-gnueabihf
+ # install latest device tree compiler
+ - git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ - make -j4 -C /tmp/dtc
+ # prepare buildman environment
+ - export BUILDMAN_ROOT="root:"
+ - export BUILDMAN_MIPS="mips:"
+ - export BUILDMAN_PPC="ppc:"
+ - echo -e "[toolchain]\\n${BUILDMAN_ROOT} /\n" > ~/.buildman
+ - echo -e "${BUILDMAN_MIPS} /opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/" >> ~/.buildman
+ - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/" >> ~/.buildman
+ - export BUILDMAN_ALIAS="x86:"
+ - echo -e "[toolchain-alias]\\n${BUILDMAN_ALIAS} i386" >> ~/.buildman
+ - cat ~/.buildman
+
+env:
+ global:
+ - PATH=/tmp/dtc:$PATH
+ - BUILD_DIR=build
+ - CROSS_COMPILE=""
+ - HOSTCC="cc"
+ - HOSTCXX="c++"
+ - TEST_CONFIG_CMD=""
+
+before_script:
+ # install toolchains based on INSTALL_TOOLCHAIN} variable
+ - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/mips/eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh ; fi
+ - if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then sh eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh -y ; fi
+
+script:
+ # the execution sequence for each test
+ - echo ${TEST_CONFIG_CMD}
+ - ${TEST_CONFIG_CMD}
+ - echo ${TEST_CMD}
+ - ${TEST_CMD}
+
+matrix:
+ include:
+ # we need to build by vendor due to 50min time limit for builds
+ # each env setting here is a dedicated build
+ - env:
+ - TEST_CMD="./MAKEALL -a arm -v atmel"
+ CROSS_COMPILE="arm-linux-gnueabi-"
+ - env:
+ - TEST_CMD="./MAKEALL -a arm -v denx"
+ CROSS_COMPILE="arm-linux-gnueabi-"
+ - env:
+ - TEST_CMD="./MAKEALL -a arm -v freescale"
+ CROSS_COMPILE="arm-linux-gnueabi-"
+ - env:
+ - TEST_CMD="./MAKEALL -a arm -v siemens"
+ CROSS_COMPILE="arm-linux-gnueabi-"
+ - env:
+ - TEST_CMD="./MAKEALL -a arm -v ti"
+ CROSS_COMPILE="arm-linux-gnueabi-"
+ - env:
+ - TEST_CONFIG_CMD="make sandbox_defconfig"
+ TEST_CMD="make -j4"
+ HOSTCC = "gcc"
+ HOSTCXX = "g++"
+ - env:
+ - TEST_CONFIG_CMD="make sandbox_defconfig"
+ TEST_CMD="make -j4"
+ HOSTCC = "clang"
+ HOSTCXX = "clang++"
+ - env:
+ - TEST_CMD="./MAKEALL -a mips"
+ INSTALL_TOOLCHAIN="mips"
+ CROSS_COMPILE="/opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/mips-linux-"
+ - env:
+ - TEST_CMD="tools/buildman/buildman --list-error-boards atmel"
+ - env:
+ - TEST_CMD="tools/buildman/buildman --list-error-boards denx"
+ - env:
+ - TEST_CMD="tools/buildman/buildman --list-error-boards freescale arm"
+ - env:
+ - TEST_CMD="tools/buildman/buildman --list-error-boards siemens"
+ - env:
+ - TEST_CMD="tools/buildman/buildman --list-error-boards ti"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mips"
+ INSTALL_TOOLCHAIN="mips"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mpc5xx"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mpc8xx"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mpc5xxx"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mpc512x"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mpc824x"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mpc8260"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mpc83xx"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mpc85xx"
+ INSTALL_TOOLCHAIN="ppc"
+ - env:
+ - TEST_CMD="tools/buildman/buildman mpc86xx"
+ INSTALL_TOOLCHAIN="ppc"
+
+ - env:
+ - TEST_CMD="tools/buildman/buildman --list-error-boards sandbox x86"
+
+ # QA jobs for code analytics
+ # static code analysis with cppcheck (we can add --enable=all later)
+ - env:
+ - TEST_CMD="cppcheck --force --quiet --inline-suppr ."
+ # search for TODO within source tree
+ - env:
+ - TEST_CMD="grep -r TODO ."
+ # search for FIXME within source tree
+ - env:
+ - TEST_CMD="grep -r FIXME ."
+ # search for HACK within source tree and ignore HACKKIT board
+ - env:
+ - TEST_CMD="grep -r HACK . | grep -v HACKKIT"
+ script:
+ - grep -r HACK . | grep -v HACKKIT
+ # some statistics about the code base
+ - env:
+ - TEST_CMD="sloccount ."
+
+notifications:
+ email: false
+
+# TODO make it perfect ;-r
diff --git a/Kconfig b/Kconfig
index 60cf1dd..4157da3 100644
--- a/Kconfig
+++ b/Kconfig
@@ -143,6 +143,12 @@
help
TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
+config SYS_CLK_FREQ
+ depends on ARC
+ int "CPU clock frequency"
+ help
+ TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
+
endmenu # Boot images
source "arch/Kconfig"
diff --git a/MAINTAINERS b/MAINTAINERS
index 701ec33..1f77359 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -319,12 +319,6 @@
T: git git://git.denx.de/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
-POWERPC PPC74XX PPC7XX
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-T: git git://git.denx.de/u-boot-74xx-7xx.git
-F: arch/powerpc/cpu/74xx_7xx/
-
POWERPC PPC4XX
M: Stefan Roese <sr@denx.de>
S: Maintained
diff --git a/MAKEALL b/MAKEALL
index 4d643d1..c5f665f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -316,12 +316,6 @@
LIST_86xx="$(targets_by_cpu mpc86xx)"
#########################################################################
-## 74xx/7xx Systems
-#########################################################################
-
-LIST_74xx_7xx="$(targets_by_cpu 74xx_7xx)"
-
-#########################################################################
## PowerPC groups
#########################################################################
@@ -342,7 +336,6 @@
${LIST_85xx} \
${LIST_86xx} \
${LIST_4xx} \
- ${LIST_74xx_7xx}\
"
# Alias "ppc" -> "powerpc" to not break compatibility with older scripts
diff --git a/README b/README
index 0fec497..fefa71c 100644
--- a/README
+++ b/README
@@ -182,7 +182,6 @@
/lib Architecture specific library files
/powerpc Files generic to PowerPC architecture
/cpu CPU specific files
- /74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs
/mpc5xx Files specific to Freescale MPC5xx CPUs
/mpc5xxx Files specific to Freescale MPC5xxx CPUs
/mpc8xx Files specific to Freescale MPC8xx CPUs
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index d3ef58b..c6b1efe 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -4,6 +4,9 @@
config SYS_ARCH
default "arc"
+config SYS_CPU
+ default "arcv1"
+
choice
prompt "Target select"
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 03ea6db..a59231e 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -2,8 +2,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-head-y := arch/arc/cpu/$(CPU)/start.o
-
libs-y += arch/arc/cpu/$(CPU)/
libs-y += arch/arc/lib/
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
index e408800..5321987 100644
--- a/arch/arc/config.mk
+++ b/arch/arc/config.mk
@@ -21,6 +21,10 @@
CROSS_COMPILE := $(ARC_CROSS_COMPILE)
endif
+ifdef CONFIG_ARC_MMU_VER
+CONFIG_MMU = 1
+endif
+
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
# Needed for relocation
diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile
deleted file mode 100644
index cdc5002..0000000
--- a/arch/arc/cpu/arc700/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y += start.o
-
-obj-y += cache.o
-obj-y += cpu.o
-obj-y += interrupts.o
-obj-y += reset.o
-obj-y += timer.o
diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/cpu/arc700/cache.c
deleted file mode 100644
index 39d522d..0000000
--- a/arch/arc/cpu/arc700/cache.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arcregs.h>
-
-/* Bit values in IC_CTRL */
-#define IC_CTRL_CACHE_DISABLE (1 << 0)
-
-/* Bit values in DC_CTRL */
-#define DC_CTRL_CACHE_DISABLE (1 << 0)
-#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
-#define DC_CTRL_FLUSH_STATUS (1 << 8)
-
-int icache_status(void)
-{
- return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
- IC_CTRL_CACHE_DISABLE;
-}
-
-void icache_enable(void)
-{
- write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
- ~IC_CTRL_CACHE_DISABLE);
-}
-
-void icache_disable(void)
-{
- write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
- IC_CTRL_CACHE_DISABLE);
-}
-
-void invalidate_icache_all(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- /* Any write to IC_IVIC register triggers invalidation of entire I$ */
- write_aux_reg(ARC_AUX_IC_IVIC, 1);
-#endif /* CONFIG_SYS_ICACHE_OFF */
-}
-
-int dcache_status(void)
-{
- return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
- DC_CTRL_CACHE_DISABLE;
-}
-
-void dcache_enable(void)
-{
- write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
- ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
-}
-
-void dcache_disable(void)
-{
- write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
- DC_CTRL_CACHE_DISABLE);
-}
-
-void flush_dcache_all(void)
-{
- /* Do flush of entire cache */
- write_aux_reg(ARC_AUX_DC_FLSH, 1);
-
- /* Wait flush end */
- while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
- ;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-static void dcache_flush_line(unsigned addr)
-{
-#if (CONFIG_ARC_MMU_VER > 2)
- write_aux_reg(ARC_AUX_DC_PTAG, addr);
-#endif
- write_aux_reg(ARC_AUX_DC_FLDL, addr);
-
- /* Wait flush end */
- while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
- ;
-
-#ifndef CONFIG_SYS_ICACHE_OFF
- /*
- * Invalidate I$ for addresses range just flushed from D$.
- * If we try to execute data flushed above it will be valid/correct
- */
-#if (CONFIG_ARC_MMU_VER > 2)
- write_aux_reg(ARC_AUX_IC_PTAG, addr);
-#endif
- write_aux_reg(ARC_AUX_IC_IVIL, addr);
-#endif /* CONFIG_SYS_ICACHE_OFF */
-}
-#endif /* CONFIG_SYS_DCACHE_OFF */
-
-void flush_dcache_range(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- unsigned int addr;
-
- start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
- end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
- dcache_flush_line(addr);
-#endif /* CONFIG_SYS_DCACHE_OFF */
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- unsigned int addr;
-
- start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
- end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
-
- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
-#if (CONFIG_ARC_MMU_VER > 2)
- write_aux_reg(ARC_AUX_DC_PTAG, addr);
-#endif
- write_aux_reg(ARC_AUX_DC_IVDL, addr);
- }
-#endif /* CONFIG_SYS_DCACHE_OFF */
-}
-
-void invalidate_dcache_all(void)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
- write_aux_reg(ARC_AUX_DC_IVDC, 1);
-#endif /* CONFIG_SYS_DCACHE_OFF */
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
- flush_dcache_range(start, start + size);
-}
diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/cpu/arc700/interrupts.c
deleted file mode 100644
index d93a6eb..0000000
--- a/arch/arc/cpu/arc700/interrupts.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arcregs.h>
-#include <asm/ptrace.h>
-
-/* Bit values in STATUS32 */
-#define E1_MASK (1 << 1) /* Level 1 interrupts enable */
-#define E2_MASK (1 << 2) /* Level 2 interrupts enable */
-
-int interrupt_init(void)
-{
- return 0;
-}
-
-/*
- * returns true if interrupts had been enabled before we disabled them
- */
-int disable_interrupts(void)
-{
- int status = read_aux_reg(ARC_AUX_STATUS32);
- int state = (status | E1_MASK | E2_MASK) ? 1 : 0;
-
- status &= ~(E1_MASK | E2_MASK);
- /* STATUS32 register is updated indirectly with "FLAG" instruction */
- __asm__("flag %0" : : "r" (status));
- return state;
-}
-
-void enable_interrupts(void)
-{
- unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
-
- status |= E1_MASK | E2_MASK;
- /* STATUS32 register is updated indirectly with "FLAG" instruction */
- __asm__("flag %0" : : "r" (status));
-}
-
-static void print_reg_file(long *reg_rev, int start_num)
-{
- unsigned int i;
-
- /* Print 3 registers per line */
- for (i = start_num; i < start_num + 25; i++) {
- printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
- if (((i + 1) % 3) == 0)
- printf("\n");
-
- /* Because pt_regs has registers reversed */
- reg_rev--;
- }
-
- /* Add new-line if none was inserted in the end of loop above */
- if (((i + 1) % 3) != 0)
- printf("\n");
-}
-
-void show_regs(struct pt_regs *regs)
-{
- printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
- regs->ret, regs->blink, regs->status32);
- printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
- printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
- regs->sp, regs->fp);
- printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
- regs->lp_end, regs->lp_count);
-
- print_reg_file(&(regs->r0), 0);
-}
-
-void bad_mode(struct pt_regs *regs)
-{
- if (regs)
- show_regs(regs);
-
- panic("Resetting CPU ...\n");
-}
-
-void do_memory_error(unsigned long address, struct pt_regs *regs)
-{
- printf("Memory error exception @ 0x%lx\n", address);
- bad_mode(regs);
-}
-
-void do_instruction_error(unsigned long address, struct pt_regs *regs)
-{
- printf("Instruction error exception @ 0x%lx\n", address);
- bad_mode(regs);
-}
-
-void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
-{
- printf("Machine check exception @ 0x%lx\n", address);
- bad_mode(regs);
-}
-
-void do_interrupt_handler(void)
-{
- printf("Interrupt fired\n");
- bad_mode(0);
-}
-
-void do_itlb_miss(struct pt_regs *regs)
-{
- printf("I TLB miss exception\n");
- bad_mode(regs);
-}
-
-void do_dtlb_miss(struct pt_regs *regs)
-{
- printf("D TLB miss exception\n");
- bad_mode(regs);
-}
-
-void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
-{
- printf("TLB protection violation or misaligned access @ 0x%lx\n",
- address);
- bad_mode(regs);
-}
-
-void do_privilege_violation(struct pt_regs *regs)
-{
- printf("Privilege violation exception\n");
- bad_mode(regs);
-}
-
-void do_trap(struct pt_regs *regs)
-{
- printf("Trap exception\n");
- bad_mode(regs);
-}
-
-void do_extension(struct pt_regs *regs)
-{
- printf("Extension instruction exception\n");
- bad_mode(regs);
-}
diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S
deleted file mode 100644
index 563513b..0000000
--- a/arch/arc/cpu/arc700/start.S
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/arcregs.h>
-
-/*
- * Note on the LD/ST addressing modes with address register write-back
- *
- * LD.a same as LD.aw
- *
- * LD.a reg1, [reg2, x] => Pre Incr
- * Eff Addr for load = [reg2 + x]
- *
- * LD.ab reg1, [reg2, x] => Post Incr
- * Eff Addr for load = [reg2]
- */
-
-.macro PUSH reg
- st.a \reg, [%sp, -4]
-.endm
-
-.macro PUSHAX aux
- lr %r9, [\aux]
- PUSH %r9
-.endm
-
-.macro SAVE_R1_TO_R24
- PUSH %r1
- PUSH %r2
- PUSH %r3
- PUSH %r4
- PUSH %r5
- PUSH %r6
- PUSH %r7
- PUSH %r8
- PUSH %r9
- PUSH %r10
- PUSH %r11
- PUSH %r12
- PUSH %r13
- PUSH %r14
- PUSH %r15
- PUSH %r16
- PUSH %r17
- PUSH %r18
- PUSH %r19
- PUSH %r20
- PUSH %r21
- PUSH %r22
- PUSH %r23
- PUSH %r24
-.endm
-
-.macro SAVE_ALL_SYS
-
- st %r0, [%sp]
- lr %r0, [%ecr]
- st %r0, [%sp, 8] /* ECR */
- st %sp, [%sp, 4]
-
- SAVE_R1_TO_R24
- PUSH %r25
- PUSH %gp
- PUSH %fp
- PUSH %blink
- PUSHAX %eret
- PUSHAX %erstatus
- PUSH %lp_count
- PUSHAX %lp_end
- PUSHAX %lp_start
- PUSHAX %erbta
-.endm
-
-.align 4
-.globl _start
-_start:
- /* Critical system events */
- j reset /* 0 - 0x000 */
- j memory_error /* 1 - 0x008 */
- j instruction_error /* 2 - 0x010 */
-
- /* Device interrupts */
-.rept 29
- j interrupt_handler /* 3:31 - 0x018:0xF8 */
-.endr
- /* Exceptions */
- j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
- j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
- j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
- j EV_TLBProtV /* 0x118, Protection Violation (0x23)
- or Misaligned Access */
- j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
- j EV_Trap /* 0x128, Trap exception (0x25) */
- j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
-
-memory_error:
- SAVE_ALL_SYS
- lr %r0, [%efa]
- mov %r1, %sp
- j do_memory_error
-
-instruction_error:
- SAVE_ALL_SYS
- lr %r0, [%efa]
- mov %r1, %sp
- j do_instruction_error
-
-interrupt_handler:
- /* Todo - save and restore CPU context when interrupts will be in use */
- bl do_interrupt_handler
- rtie
-
-EV_MachineCheck:
- SAVE_ALL_SYS
- lr %r0, [%efa]
- mov %r1, %sp
- j do_machine_check_fault
-
-EV_TLBMissI:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_itlb_miss
-
-EV_TLBMissD:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_dtlb_miss
-
-EV_TLBProtV:
- SAVE_ALL_SYS
- lr %r0, [%efa]
- mov %r1, %sp
- j do_tlb_prot_violation
-
-EV_PrivilegeV:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_privilege_violation
-
-EV_Trap:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_trap
-
-EV_Extension:
- SAVE_ALL_SYS
- mov %r0, %sp
- j do_extension
-
-
-reset:
- /* Setup interrupt vector base that matches "__text_start" */
- sr __text_start, [ARC_AUX_INTR_VEC_BASE]
-
- /* Setup stack pointer */
- mov %sp, CONFIG_SYS_INIT_SP_ADDR
- mov %fp, %sp
-
- /* Clear bss */
- mov %r0, __bss_start
- mov %r1, __bss_end
-
-clear_bss:
- st.ab 0, [%r0, 4]
- brlt %r0, %r1, clear_bss
-
- /* Zero the one and only argument of "board_init_f" */
- mov_s %r0, 0
- j board_init_f
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r0 = start_addr_sp
- * r1 = new__gd
- * r2 = relocaddr
- */
-.align 4
-.globl relocate_code
-relocate_code:
- /*
- * r0-r12 might be clobbered by C functions
- * so we use r13-r16 for storage here
- */
- mov %r13, %r0 /* save addr_sp */
- mov %r14, %r1 /* save addr of gd */
- mov %r15, %r2 /* save addr of destination */
-
- mov %r16, %r2 /* %r9 - relocation offset */
- sub %r16, %r16, __image_copy_start
-
-/* Set up the stack */
-stack_setup:
- mov %sp, %r13
- mov %fp, %sp
-
-/* Check if monitor is loaded right in place for relocation */
- mov %r0, __image_copy_start
- cmp %r0, %r15 /* skip relocation if code loaded */
- bz do_board_init_r /* in target location already */
-
-/* Copy data (__image_copy_start - __image_copy_end) to new location */
- mov %r1, %r15
- mov %r2, __image_copy_end
- sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */
- asr %r2, %r2, 2 /* r3 <- amount of words to copy */
- mov %lp_count, %r2
- lp copy_end
- ld.ab %r2,[%r0,4]
- st.ab %r2,[%r1,4]
-copy_end:
-
-/* Fix relocations related issues */
- bl do_elf_reloc_fixups
-#ifndef CONFIG_SYS_ICACHE_OFF
- bl invalidate_icache_all
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- bl flush_dcache_all
-#endif
-
-/* Update position of intterupt vector table */
- lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */
- add %r0, %r0, %r16 /* Update address */
- sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */
-
-do_board_init_r:
-/* Prepare for exection of "board_init_r" in relocated monitor */
- mov %r2, board_init_r /* old address of "board_init_r()" */
- add %r2, %r2, %r16 /* new address of "board_init_r()" */
- mov %r0, %r14 /* 1-st parameter: gd_t */
- mov %r1, %r15 /* 2-nd parameter: dest_addr */
- j [%r2]
diff --git a/arch/arc/cpu/arc700/u-boot.lds b/arch/arc/cpu/arc700/u-boot.lds
deleted file mode 100644
index 2d01b21..0000000
--- a/arch/arc/cpu/arc700/u-boot.lds
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
-OUTPUT_ARCH(arc)
-ENTRY(_start)
-SECTIONS
-{
- . = ALIGN(4);
- .text : {
- *(.__text_start)
- *(.__image_copy_start)
- CPUDIR/start.o (.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .text_end :
- {
- *(.__text_end)
- }
-
- . = ALIGN(4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
- .rel_dyn_start : {
- *(.__rel_dyn_start)
- }
-
- .rela.dyn : {
- *(.rela.dyn)
- }
-
- .rel_dyn_end : {
- *(.__rel_dyn_end)
- }
-
- . = ALIGN(4);
- .bss_start : {
- *(.__bss_start);
- }
-
- .bss : {
- *(.bss*)
- }
-
- .bss_end : {
- *(.__bss_end);
- }
-
- . = ALIGN(4);
- .image_copy_end : {
- *(.__image_copy_end)
- *(.__init_end)
- }
-}
diff --git a/arch/arc/cpu/arcv1/Makefile b/arch/arc/cpu/arcv1/Makefile
new file mode 100644
index 0000000..3704ebe
--- /dev/null
+++ b/arch/arc/cpu/arcv1/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += start.o
diff --git a/arch/arc/cpu/arc700/config.mk b/arch/arc/cpu/arcv1/config.mk
similarity index 100%
rename from arch/arc/cpu/arc700/config.mk
rename to arch/arc/cpu/arcv1/config.mk
diff --git a/arch/arc/cpu/arcv1/start.S b/arch/arc/cpu/arcv1/start.S
new file mode 100644
index 0000000..01cfba4
--- /dev/null
+++ b/arch/arc/cpu/arcv1/start.S
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a reg1, [reg2, x] => Pre Incr
+ * Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab reg1, [reg2, x] => Post Incr
+ * Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+ st.a \reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+ lr %r9, [\aux]
+ PUSH %r9
+.endm
+
+.macro SAVE_R1_TO_R24
+ PUSH %r1
+ PUSH %r2
+ PUSH %r3
+ PUSH %r4
+ PUSH %r5
+ PUSH %r6
+ PUSH %r7
+ PUSH %r8
+ PUSH %r9
+ PUSH %r10
+ PUSH %r11
+ PUSH %r12
+ PUSH %r13
+ PUSH %r14
+ PUSH %r15
+ PUSH %r16
+ PUSH %r17
+ PUSH %r18
+ PUSH %r19
+ PUSH %r20
+ PUSH %r21
+ PUSH %r22
+ PUSH %r23
+ PUSH %r24
+.endm
+
+.macro SAVE_ALL_SYS
+ /* saving %r0 to reg->r0 in advance since we read %ecr into it */
+ st %r0, [%sp, -8]
+ lr %r0, [%ecr] /* all stack addressing is manual so far */
+ st %r0, [%sp]
+ st %sp, [%sp, -4]
+ /* now move %sp to reg->r0 position so we can do "push" automatically */
+ sub %sp, %sp, 8
+
+ SAVE_R1_TO_R24
+ PUSH %r25
+ PUSH %gp
+ PUSH %fp
+ PUSH %blink
+ PUSHAX %eret
+ PUSHAX %erstatus
+ PUSH %lp_count
+ PUSHAX %lp_end
+ PUSHAX %lp_start
+ PUSHAX %erbta
+.endm
+
+.macro SAVE_EXCEPTION_SOURCE
+#ifdef CONFIG_MMU
+ /* If MMU exists exception faulting address is loaded in EFA reg */
+ lr %r0, [%efa]
+#else
+ /* Otherwise in ERET (exception return) reg */
+ lr %r0, [%eret]
+#endif
+.endm
+
+.section .ivt, "ax",@progbits
+.align 4
+_ivt:
+ /* Critical system events */
+ j _start /* 0 - 0x000 */
+ j memory_error /* 1 - 0x008 */
+ j instruction_error /* 2 - 0x010 */
+
+ /* Device interrupts */
+.rept 29
+ j interrupt_handler /* 3:31 - 0x018:0xF8 */
+.endr
+ /* Exceptions */
+ j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
+ j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
+ j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
+ j EV_TLBProtV /* 0x118, Protection Violation (0x23)
+ or Misaligned Access */
+ j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
+ j EV_Trap /* 0x128, Trap exception (0x25) */
+ j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
+
+.text
+.globl _start
+_start:
+ /* Setup interrupt vector base that matches "__text_start" */
+ sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
+
+ /* Setup stack pointer */
+ mov %sp, CONFIG_SYS_INIT_SP_ADDR
+ mov %fp, %sp
+
+ /* Clear bss */
+ mov %r0, __bss_start
+ mov %r1, __bss_end
+
+clear_bss:
+ st.ab 0, [%r0, 4]
+ brlt %r0, %r1, clear_bss
+
+ /* Zero the one and only argument of "board_init_f" */
+ mov_s %r0, 0
+ j board_init_f
+
+memory_error:
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_memory_error
+
+instruction_error:
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_instruction_error
+
+interrupt_handler:
+ /* Todo - save and restore CPU context when interrupts will be in use */
+ bl do_interrupt_handler
+ rtie
+
+EV_MachineCheck:
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_machine_check_fault
+
+EV_TLBMissI:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_itlb_miss
+
+EV_TLBMissD:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_dtlb_miss
+
+EV_TLBProtV:
+ SAVE_ALL_SYS
+ SAVE_EXCEPTION_SOURCE
+ mov %r1, %sp
+ j do_tlb_prot_violation
+
+EV_PrivilegeV:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_privilege_violation
+
+EV_Trap:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_trap
+
+EV_Extension:
+ SAVE_ALL_SYS
+ mov %r0, %sp
+ j do_extension
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl relocate_code
+relocate_code:
+ /*
+ * r0-r12 might be clobbered by C functions
+ * so we use r13-r16 for storage here
+ */
+ mov %r13, %r0 /* save addr_sp */
+ mov %r14, %r1 /* save addr of gd */
+ mov %r15, %r2 /* save addr of destination */
+
+ mov %r16, %r2 /* %r9 - relocation offset */
+ sub %r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+ mov %sp, %r13
+ mov %fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+ mov %r0, __image_copy_start
+ cmp %r0, %r15 /* skip relocation if code loaded */
+ bz do_board_init_r /* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+ mov %r1, %r15
+ mov %r2, __image_copy_end
+ sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */
+ asr %r2, %r2, 2 /* r3 <- amount of words to copy */
+ mov %lp_count, %r2
+ lp copy_end
+ ld.ab %r2,[%r0,4]
+ st.ab %r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+ bl do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+ bl invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ bl flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+ lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */
+ add %r0, %r0, %r16 /* Update address */
+ sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+ mov %r2, board_init_r /* old address of "board_init_r()" */
+ add %r2, %r2, %r16 /* new address of "board_init_r()" */
+ mov %r0, %r14 /* 1-st parameter: gd_t */
+ mov %r1, %r15 /* 2-nd parameter: dest_addr */
+ j [%r2]
diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds
new file mode 100644
index 0000000..ccddbf7
--- /dev/null
+++ b/arch/arc/cpu/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
+OUTPUT_ARCH(arc)
+ENTRY(_start)
+SECTIONS
+{
+ . = ALIGN(4);
+ .text : {
+ *(.__text_start)
+ *(.__image_copy_start)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .text_end :
+ {
+ *(.__text_end)
+ }
+
+ . = ALIGN(1024);
+ .ivt_start : {
+ *(.__ivt_start)
+ }
+
+ .ivt :
+ {
+ *(.ivt)
+ }
+
+ .ivt_end : {
+ *(.__ivt_end)
+ }
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+ .rel_dyn_start : {
+ *(.__rel_dyn_start)
+ }
+
+ .rela.dyn : {
+ *(.rela.dyn)
+ }
+
+ .rel_dyn_end : {
+ *(.__rel_dyn_end)
+ }
+
+ . = ALIGN(4);
+ .bss_start : {
+ *(.__bss_start);
+ }
+
+ .bss : {
+ *(.bss*)
+ }
+
+ .bss_end : {
+ *(.__bss_end);
+ }
+
+ . = ALIGN(4);
+ .image_copy_end : {
+ *(.__image_copy_end)
+ *(.__init_end)
+ }
+}
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 5d48d11..8ace87f 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -24,6 +24,7 @@
#if (CONFIG_ARC_MMU_VER > 2)
#define ARC_AUX_IC_PTAG 0x1E
#endif
+#define ARC_BCR_IC_BUILD 0x77
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
@@ -42,6 +43,7 @@
#if (CONFIG_ARC_MMU_VER > 2)
#define ARC_AUX_DC_PTAG 0x5C
#endif
+#define ARC_BCR_DC_BUILD 0x72
#ifndef __ASSEMBLY__
/* Accessors for auxiliary registers */
diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h
index 18484a1..b8f2a85 100644
--- a/arch/arc/include/asm/sections.h
+++ b/arch/arc/include/asm/sections.h
@@ -10,5 +10,8 @@
#include <asm-generic/sections.h>
extern ulong __text_end;
+extern ulong __ivt_start;
+extern ulong __ivt_end;
+extern ulong __image_copy_start;
#endif /* __ASM_ARC_SECTIONS_H */
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
index 7675f85..bae4419 100644
--- a/arch/arc/lib/Makefile
+++ b/arch/arc/lib/Makefile
@@ -4,6 +4,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += cache.o
+obj-y += cpu.o
+obj-y += interrupts.o
obj-y += sections.o
obj-y += relocate.o
obj-y += strchr-700.o
@@ -13,4 +16,7 @@
obj-y += memcmp.o
obj-y += memcpy-700.o
obj-y += memset.o
+obj-y += reset.o
+obj-y += timer.o
+
obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
new file mode 100644
index 0000000..fa19a13
--- /dev/null
+++ b/arch/arc/lib/cache.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arcregs.h>
+
+/* Bit values in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE (1 << 0)
+
+/* Bit values in DC_CTRL */
+#define DC_CTRL_CACHE_DISABLE (1 << 0)
+#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
+#define DC_CTRL_FLUSH_STATUS (1 << 8)
+#define CACHE_VER_NUM_MASK 0xF
+
+int icache_status(void)
+{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+ return 0;
+
+ return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
+ IC_CTRL_CACHE_DISABLE;
+}
+
+void icache_enable(void)
+{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
+ write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+ ~IC_CTRL_CACHE_DISABLE);
+}
+
+void icache_disable(void)
+{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
+ write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+ IC_CTRL_CACHE_DISABLE);
+}
+
+void invalidate_icache_all(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ /* Any write to IC_IVIC register triggers invalidation of entire I$ */
+ write_aux_reg(ARC_AUX_IC_IVIC, 1);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+
+int dcache_status(void)
+{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ return 0;
+
+ return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
+ DC_CTRL_CACHE_DISABLE;
+}
+
+void dcache_enable(void)
+{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
+ write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
+ ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
+}
+
+void dcache_disable(void)
+{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
+ write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
+ DC_CTRL_CACHE_DISABLE);
+}
+
+void flush_dcache_all(void)
+{
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
+ /* Do flush of entire cache */
+ write_aux_reg(ARC_AUX_DC_FLSH, 1);
+
+ /* Wait flush end */
+ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+ ;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+static void dcache_flush_line(unsigned addr)
+{
+#if (CONFIG_ARC_MMU_VER > 2)
+ write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+ write_aux_reg(ARC_AUX_DC_FLDL, addr);
+
+ /* Wait flush end */
+ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+ ;
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+ /*
+ * Invalidate I$ for addresses range just flushed from D$.
+ * If we try to execute data flushed above it will be valid/correct
+ */
+#if (CONFIG_ARC_MMU_VER > 2)
+ write_aux_reg(ARC_AUX_IC_PTAG, addr);
+#endif
+ write_aux_reg(ARC_AUX_IC_IVIL, addr);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ unsigned int addr;
+
+ start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+ end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+ for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
+ dcache_flush_line(addr);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ unsigned int addr;
+
+ start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+ end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+ for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
+#if (CONFIG_ARC_MMU_VER > 2)
+ write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+ write_aux_reg(ARC_AUX_DC_IVDL, addr);
+ }
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_all(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
+ write_aux_reg(ARC_AUX_DC_IVDC, 1);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
diff --git a/arch/arc/cpu/arc700/cpu.c b/arch/arc/lib/cpu.c
similarity index 100%
rename from arch/arc/cpu/arc700/cpu.c
rename to arch/arc/lib/cpu.c
diff --git a/arch/arc/lib/interrupts.c b/arch/arc/lib/interrupts.c
new file mode 100644
index 0000000..d7cab3b
--- /dev/null
+++ b/arch/arc/lib/interrupts.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/ptrace.h>
+
+/* Bit values in STATUS32 */
+#define E1_MASK (1 << 1) /* Level 1 interrupts enable */
+#define E2_MASK (1 << 2) /* Level 2 interrupts enable */
+
+int interrupt_init(void)
+{
+ return 0;
+}
+
+/*
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts(void)
+{
+ int status = read_aux_reg(ARC_AUX_STATUS32);
+ int state = (status & (E1_MASK | E2_MASK)) ? 1 : 0;
+
+ status &= ~(E1_MASK | E2_MASK);
+ /* STATUS32 register is updated indirectly with "FLAG" instruction */
+ __asm__("flag %0" : : "r" (status));
+ return state;
+}
+
+void enable_interrupts(void)
+{
+ unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
+
+ status |= E1_MASK | E2_MASK;
+ /* STATUS32 register is updated indirectly with "FLAG" instruction */
+ __asm__("flag %0" : : "r" (status));
+}
+
+static void print_reg_file(long *reg_rev, int start_num)
+{
+ unsigned int i;
+
+ /* Print 3 registers per line */
+ for (i = start_num; i < start_num + 25; i++) {
+ printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
+ if (((i + 1) % 3) == 0)
+ printf("\n");
+
+ /* Because pt_regs has registers reversed */
+ reg_rev--;
+ }
+
+ /* Add new-line if none was inserted in the end of loop above */
+ if (((i + 1) % 3) != 0)
+ printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+ printf("ECR:\t0x%08lx\n", regs->ecr);
+ printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
+ regs->ret, regs->blink, regs->status32);
+ printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
+ printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
+ regs->sp, regs->fp);
+ printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
+ regs->lp_end, regs->lp_count);
+
+ print_reg_file(&(regs->r0), 0);
+}
+
+void bad_mode(struct pt_regs *regs)
+{
+ if (regs)
+ show_regs(regs);
+
+ panic("Resetting CPU ...\n");
+}
+
+void do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+ printf("Memory error exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_instruction_error(unsigned long address, struct pt_regs *regs)
+{
+ printf("Instruction error exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
+{
+ printf("Machine check exception @ 0x%lx\n", address);
+ bad_mode(regs);
+}
+
+void do_interrupt_handler(void)
+{
+ printf("Interrupt fired\n");
+ bad_mode(0);
+}
+
+void do_itlb_miss(struct pt_regs *regs)
+{
+ printf("I TLB miss exception\n");
+ bad_mode(regs);
+}
+
+void do_dtlb_miss(struct pt_regs *regs)
+{
+ printf("D TLB miss exception\n");
+ bad_mode(regs);
+}
+
+void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
+{
+ printf("TLB protection violation or misaligned access @ 0x%lx\n",
+ address);
+ bad_mode(regs);
+}
+
+void do_privilege_violation(struct pt_regs *regs)
+{
+ printf("Privilege violation exception\n");
+ bad_mode(regs);
+}
+
+void do_trap(struct pt_regs *regs)
+{
+ printf("Trap exception\n");
+ bad_mode(regs);
+}
+
+void do_extension(struct pt_regs *regs)
+{
+ printf("Extension instruction exception\n");
+ bad_mode(regs);
+}
diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c
index 2482bcd..7797782 100644
--- a/arch/arc/lib/relocate.c
+++ b/arch/arc/lib/relocate.c
@@ -26,7 +26,7 @@
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* Check that the location of the relocation is in .text */
- if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
+ if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
offset_ptr_rom > last_offset) {
unsigned int val;
/* Switch to the in-RAM version */
@@ -44,29 +44,22 @@
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
if ((unsigned int)offset_ptr_rom <
- (unsigned int)&__text_end)
+ (unsigned int)&__ivt_end)
val = (val << 16) | (val >> 16);
#endif
- /* Check that the target points into .text */
- if (val >= CONFIG_SYS_TEXT_BASE && val <=
- (unsigned int)&__bss_end) {
+ /* Check that the target points into executable */
+ if (val >= (unsigned int)&__image_copy_start && val <=
+ (unsigned int)&__image_copy_end) {
val += gd->reloc_off;
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
if ((unsigned int)offset_ptr_rom <
- (unsigned int)&__text_end)
+ (unsigned int)&__ivt_end)
val = (val << 16) | (val >> 16);
#endif
memcpy(offset_ptr_ram, &val, sizeof(int));
- } else {
- debug(" %p: rom reloc %x, ram %p, value %x, limit %x\n",
- re_src, re_src->r_offset, offset_ptr_ram,
- val, (unsigned int)&__bss_end);
}
- } else {
- debug(" %p: rom reloc %x, last %p\n", re_src,
- re_src->r_offset, last_offset);
}
last_offset = offset_ptr_rom;
diff --git a/arch/arc/cpu/arc700/reset.c b/arch/arc/lib/reset.c
similarity index 100%
rename from arch/arc/cpu/arc700/reset.c
rename to arch/arc/lib/reset.c
diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c
index b0b46a4..a72c694 100644
--- a/arch/arc/lib/sections.c
+++ b/arch/arc/lib/sections.c
@@ -19,3 +19,5 @@
char __text_start[0] __attribute__((section(".__text_start")));
char __text_end[0] __attribute__((section(".__text_end")));
char __init_end[0] __attribute__((section(".__init_end")));
+char __ivt_start[0] __attribute__((section(".__ivt_start")));
+char __ivt_end[0] __attribute__((section(".__ivt_end")));
diff --git a/arch/arc/cpu/arc700/timer.c b/arch/arc/lib/timer.c
similarity index 100%
rename from arch/arc/cpu/arc700/timer.c
rename to arch/arc/lib/timer.c
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
index 6c037a1..45c6687 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
@@ -57,6 +57,9 @@
config TARGET_GOFLEXHOME
bool "GoFlex Home Board"
+config TARGET_NAS220
+ bool "BlackArmor NAS220"
+
endchoice
config SYS_SOC
@@ -80,5 +83,6 @@
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
+source "board/Seagate/nas220/Kconfig"
endif
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 9e412bb..4c9d3fd 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -181,7 +181,7 @@
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- char *rev;
+ char *rev = "??";
u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
@@ -192,7 +192,13 @@
switch (revid) {
case 0:
- rev = "Z0";
+ if (devid == 0x6281)
+ rev = "Z0";
+ else if (devid == 0x6282)
+ rev = "A0";
+ break;
+ case 1:
+ rev = "A1";
break;
case 2:
rev = "A0";
@@ -201,7 +207,6 @@
rev = "A1";
break;
default:
- rev = "??";
break;
}
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index eaf09d1..81477aa 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -285,14 +285,6 @@
#ifdef CONFIG_NOR_BOOT
enable_norboot_pin_mux();
#endif
- /*
- * Save the boot parameters passed from romcode.
- * We cannot delay the saving further than this,
- * to prevent overwrites.
- */
-#ifdef CONFIG_SPL_BUILD
- save_omap_boot_params();
-#endif
watchdog_disable();
set_uart_mux_conf();
setup_clocks_for_console();
@@ -301,9 +293,6 @@
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
-#elif defined(CONFIG_SPL_BUILD)
- gd = &gdata;
- preloader_console_init();
#endif
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fc66872..85cceae 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -76,13 +76,13 @@
}
/*
- * Configure EMIF4D5 registers and MR registers
+ * Configure EMIF4D5 registers and MR registers For details about these magic
+ * values please see the EMIF registers section of the TRM.
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
- writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
@@ -106,10 +106,45 @@
writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
}
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+ /*
+ * Sequence to ensure that the PHY is in a known state prior to
+ * startting hardware leveling. Also acts as to latch some state from
+ * the EMIF into the PHY.
+ */
+ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+ writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+
+ clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+ EMIF_REG_INITREF_DIS_MASK);
+
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+
+ /* Perform hardware leveling. */
+ udelay(1000);
+ writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
+ 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+ writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
+ 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
+
+ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+
+ /* Enable read leveling */
+ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+
+ /*
+ * Enable full read and write leveling. Wait for read and write
+ * leveling bit to clear RDWRLVLFULL_START bit 31
+ */
+ while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
+ ;
+
+ /* Check the timeout register to see if leveling is complete */
+ if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
+ puts("DDR3 H/W leveling incomplete with errors\n");
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
configure_mr(nr, 0);
@@ -123,21 +158,15 @@
void config_sdram(const struct emif_regs *regs, int nr)
{
if (regs->zq_config) {
- /*
- * A value of 0x2800 for the REF CTRL will give us
- * about 570us for a delay, which will be long enough
- * to configure things.
- */
- writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
}
+ writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
- writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
}
/**
@@ -153,46 +182,55 @@
writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}
-void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
-{
-}
-
/*
- * Configure EXT PHY registers
+ * Configure EXT PHY registers for hardware leveling
*/
static void ext_phy_settings(const struct emif_regs *regs, int nr)
{
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- const u32 *ext_phy_ctrl_const_regs;
- u32 i = 0;
- u32 size;
-
- ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base =
- (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
+ /*
+ * Enable hardware leveling on the EMIF. For details about these
+ * magic values please see the EMIF registers section of the TRM.
+ */
+ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+ writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
+ writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
+ writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
+ writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
+ writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
+ writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
+ writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
+ writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
+ writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
+ writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
+ writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
/*
- * external phy 6-24 registers do not change with
- * ddr frequency
+ * Sequence to ensure that the PHY is again in a known state after
+ * hardware leveling.
*/
- emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
-
- if (!size)
- return;
-
- for (i = 0; i < size; i++) {
- writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
- }
+ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
+ writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
+ writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
}
/**
@@ -201,11 +239,17 @@
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
/*
- * disable initialization and refreshes for now until we
+ * Disable initialization and refreshes for now until we
* finish programming EMIF regs.
+ * Also set time between rising edge of DDR_RESET to rising
+ * edge of DDR_CKE to > 500us per memory spec.
*/
+#ifndef CONFIG_AM43XX
setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
EMIF_REG_INITREF_DIS_MASK);
+#endif
+ if (regs->zq_config)
+ writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 8b7527c..9cf816c 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -112,17 +112,20 @@
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
;
- writel(0x80000000, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+
+ /* Allow EMIF to control DDR_RESET */
+ writel(0x00000000, &ddrctrl->ddrioctrl);
#endif
/* Program EMIF instance */
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 989780d..71a1753 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -15,6 +15,8 @@
#include <fsl_esdhc.h>
#endif
#include <tsec.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -77,9 +79,24 @@
int off;
int val;
const char *sysclk_path;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr;
+ svr = in_be32(&gur->svr);
unsigned long busclk = get_bus_freq(0);
+ /* delete crypto node if not on an E-processor */
+ if (!IS_E_PROCESSOR(svr))
+ fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+ else {
+ ccsr_sec_t __iomem *sec;
+
+ sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
+ }
+#endif
+
fdt_fixup_ethernet(blob);
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
@@ -107,6 +124,25 @@
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
+#define UBOOT_HEAD_LEN 0x1000
+ /*
+ * Reserved memory in SD boot deep sleep case.
+ * Second stage uboot binary and malloc space should be reserved.
+ * If the memory they occupied has not been reserved, then this
+ * space would be used by kernel and overwritten in uboot when
+ * deep sleep resume, which cause deep sleep failed.
+ * Since second uboot binary has a head, that space need to be
+ * reserved either(assuming its size is less than 0x1000).
+ */
+ off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
+ CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
+ UBOOT_HEAD_LEN);
+ if (off < 0)
+ printf("Failed to reserve memory for SD boot deep sleep: %s\n",
+ fdt_strerror(off));
+#endif
+
#if defined(CONFIG_FSL_ESDHC)
fdt_fixup_esdhc(blob, bd);
#endif
@@ -133,4 +169,17 @@
do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
"clock-frequency", busclk / 2, 1);
+
+#ifdef CONFIG_QSPI_BOOT
+ off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
+ CONFIG_SYS_IFC_ADDR);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+#else
+ off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
+ QSPI0_BASE_ADDR);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
+ DSPI1_BASE_ADDR);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+#endif
}
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 00a1082..17500f2 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -106,6 +106,16 @@
void spl_board_init(void)
{
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+ save_omap_boot_params();
+
+ /* Prepare console output */
+ preloader_console_init();
+
#ifdef CONFIG_SPL_NAND_SUPPORT
gpmc_init();
#endif
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index dd52e93..cb35c19 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -111,14 +111,6 @@
*/
void s_init(void)
{
- /*
- * Save the boot parameters passed from romcode.
- * We cannot delay the saving further than this,
- * to prevent overwrites.
- */
-#ifdef CONFIG_SPL_BUILD
- save_omap_boot_params();
-#endif
init_omap_revision();
hw_data_init();
@@ -133,9 +125,6 @@
srcomp_enable();
setup_clocks_for_console();
- gd = &gdata;
-
- preloader_console_init();
do_io_settings();
#endif
prcm_init();
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 53a9e5d..90d6ae7 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -119,6 +119,7 @@
void spl_board_init(void)
{
+ preloader_console_init();
#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif
@@ -264,14 +265,6 @@
ehci_clocks_enable();
#endif
-#ifdef CONFIG_SPL_BUILD
- gd = &gdata;
-
- preloader_console_init();
-
- timer_init();
-#endif
-
if (!in_sdram)
mem_init();
}
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 3b6ae47..1c4b763 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -10,18 +10,21 @@
obj-y += timer.o
obj-y += board.o
obj-y += clock.o
+obj-y += cpu_info.o
obj-y += pinmux.o
+obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
+obj-$(CONFIG_MACH_SUN8I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
ifndef CONFIG_SPL_BUILD
-obj-y += cpu_info.o
ifdef CONFIG_ARMV7_PSCI
obj-y += psci.o
endif
@@ -32,6 +35,7 @@
obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 9b3e80c..6e28bcd 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -27,28 +27,7 @@
#include <linux/compiler.h>
-#ifdef CONFIG_SPL_BUILD
-/* Pointer to the global data structure for SPL */
-DECLARE_GLOBAL_DATA_PTR;
-
-/* The sunxi internal brom will try to loader external bootloader
- * from mmc0, nand flash, mmc2.
- * Unfortunately we can't check how SPL was loaded so assume
- * it's always the first SD/MMC controller
- */
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_MMC1;
-}
-
-/* No confirmation data available in SPL yet. Hardcode bootmode */
-u32 spl_boot_mode(void)
-{
- return MMCSD_MODE_RAW;
-}
-#endif
-
-int gpio_init(void)
+static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
@@ -86,6 +65,62 @@
return 0;
}
+void s_init(void)
+{
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+ /* Magic (undocmented) value taken from boot0, without this DRAM
+ * access gets messed up (seems cache related) */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
+ defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
+ /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #1 << 6\n"
+ "mcr p15, 0, r0, c1, c0, 1\n");
+#endif
+
+ clock_init();
+ timer_init();
+ gpio_init();
+ i2c_init_board();
+}
+
+#ifdef CONFIG_SPL_BUILD
+/* The sunxi internal brom will try to loader external bootloader
+ * from mmc0, nand flash, mmc2.
+ * Unfortunately we can't check how SPL was loaded so assume
+ * it's always the first SD/MMC controller
+ */
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+
+/* No confirmation data available in SPL yet. Hardcode bootmode */
+u32 spl_boot_mode(void)
+{
+ return MMCSD_MODE_RAW;
+}
+
+void board_init_f(ulong dummy)
+{
+ preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ /* Needed early by sunxi_board_init if PMU is enabled */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+ sunxi_board_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
+#endif
+
void reset_cpu(ulong addr)
{
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
@@ -111,40 +146,6 @@
#endif
}
-/* do some early init */
-void s_init(void)
-{
-#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
- /* Magic (undocmented) value taken from boot0, without this DRAM
- * access gets messed up (seems cache related) */
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-#endif
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-#endif
-
- clock_init();
- timer_init();
- gpio_init();
- i2c_init_board();
-
-#ifdef CONFIG_SPL_BUILD
- gd = &gdata;
- preloader_console_init();
-
-#ifdef CONFIG_SPL_I2C_SUPPORT
- /* Needed early by sunxi_board_init if PMU is enabled */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
- sunxi_board_init();
-#endif
-}
-
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 8e949c6..e2a7867 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -45,10 +45,10 @@
void clock_init_uart(void)
{
+#if CONFIG_CONS_INDEX < 5
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-#if CONFIG_CONS_INDEX < 5
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
APB2_CLK_RATE_N_1|
@@ -68,9 +68,6 @@
/* enable R_PIO and R_UART clocks, and de-assert resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
#endif
-
- /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
- writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
}
int clock_twi_onoff(int port, int state)
@@ -97,6 +94,7 @@
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int p = 0;
int k = 1;
int m = 1;
@@ -113,8 +111,11 @@
CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
&ccm->cpu_axi_cfg);
- /* PLL1 rate = 24000000 * n * k / m */
- writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
+ /*
+ * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
+ * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
+ */
+ writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
sdelay(200);
@@ -144,15 +145,25 @@
&ccm->pll3_cfg);
}
-void clock_set_pll5(unsigned int clk)
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- const int k = 2;
- const int m = 1;
+ const int max_n = 32;
+ int k = 1, m = 2;
+
+ if (sigma_delta_enable)
+ writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
/* PLL5 rate = 24000000 * n * k / m */
- writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+ if (clk > 24000000 * k * max_n / m) {
+ m = 1;
+ if (clk > 24000000 * k * max_n / m)
+ k = 2;
+ }
+ writel(CCM_PLL5_CTRL_EN |
+ (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
+ CCM_PLL5_CTRL_UPD |
CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
new file mode 100644
index 0000000..27179ba
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
@@ -0,0 +1,68 @@
+/*
+ * sun9i specific clock code
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void clock_init_uart(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* open the clock for uart */
+ setbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+ /* deassert uart reset */
+ setbits_le32(&ccm->apb1_reset_cfg,
+ 1 << (APB1_RESET_UART_SHIFT +
+ CONFIG_CONS_INDEX - 1));
+
+ /* Dup with clock_init_safe(), drop once sun9i SPL support lands */
+ writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (port > 4)
+ return -1;
+
+ /* set the apb reset and clock gate for twi */
+ if (state) {
+ setbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+ setbits_le32(&ccm->apb1_reset_cfg,
+ 1 << (APB1_RESET_UART_SHIFT + port));
+ } else {
+ clrbits_le32(&ccm->apb1_reset_cfg,
+ 1 << (APB1_RESET_UART_SHIFT + port));
+ clrbits_le32(&ccm->apb1_gate,
+ CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+ }
+
+ return 0;
+}
+
+unsigned int clock_get_pll4_periph0(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ uint32_t rval = readl(&ccm->pll4_periph0_cfg);
+ int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT);
+ int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT);
+ int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1;
+ const int k = 1;
+
+ return ((24000000 * n * k) >> p) / m;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 41b9add..b6cb9de 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -9,6 +9,33 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <axp221.h>
+
+#ifdef CONFIG_MACH_SUN6I
+int sunxi_get_ss_bonding_id(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ static int bonding_id = -1;
+
+ if (bonding_id != -1)
+ return bonding_id;
+
+ /* Enable Security System */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
+
+ bonding_id = readl(SUNXI_SS_BASE);
+ bonding_id = (bonding_id >> 16) & 0x7;
+
+ /* Disable Security System again */
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
+
+ return bonding_id;
+}
+#endif
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
@@ -24,7 +51,17 @@
default: puts("CPU: Allwinner A1X (SUN5I)\n");
}
#elif defined CONFIG_MACH_SUN6I
- puts("CPU: Allwinner A31 (SUN6I)\n");
+ switch (sunxi_get_ss_bonding_id()) {
+ case SUNXI_SS_BOND_ID_A31:
+ puts("CPU: Allwinner A31 (SUN6I)\n");
+ break;
+ case SUNXI_SS_BOND_ID_A31S:
+ puts("CPU: Allwinner A31s (SUN6I)\n");
+ break;
+ default:
+ printf("CPU: Allwinner A31? (SUN6I, id: %d)\n",
+ sunxi_get_ss_bonding_id());
+ }
#elif defined CONFIG_MACH_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
#elif defined CONFIG_MACH_SUN8I
@@ -36,3 +73,21 @@
return 0;
}
#endif
+
+int sunxi_get_sid(unsigned int *sid)
+{
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_AXP221_POWER
+ return axp221_get_sid(sid);
+#else
+ return -ENODEV;
+#endif
+#else
+ int i;
+
+ for (i = 0; i< 4; i++)
+ sid[i] = readl(SUNXI_SID_BASE + 4 * i);
+
+ return 0;
+#endif
+}
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
index ec8aaa7..c736fa3 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun4i.c
@@ -36,24 +36,11 @@
#define CPU_CFG_CHIP_REV_B 0x3
/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-static void await_completion(u32 *reg, u32 mask, u32 val)
-{
- unsigned long tmo = timer_get_us() + 1000000;
-
- while ((readl(reg) & mask) != val) {
- if (timer_get_us() > tmo)
- panic("Timeout initialising DRAM\n");
- }
-}
-
-/*
* Wait up to 1s for mask to be clear in given reg.
*/
static inline void await_bits_clear(u32 *reg, u32 mask)
{
- await_completion(reg, mask, 0);
+ mctl_await_completion(reg, mask, 0);
}
/*
@@ -61,7 +48,7 @@
*/
static inline void await_bits_set(u32 *reg, u32 mask)
{
- await_completion(reg, mask, mask);
+ mctl_await_completion(reg, mask, mask);
}
/*
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
index 699173c..5dbbf61 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
@@ -17,9 +17,7 @@
#include <asm/arch/dram.h>
#include <asm/arch/prcm.h>
-/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */
-#define DRAM_CLK_DEFAULT 312000000
-#define DRAM_ZQ_DEFAULT 0x78
+#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
struct dram_sun6i_para {
u8 bus_width;
@@ -29,31 +27,18 @@
u16 page_size;
};
-/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-static void await_completion(u32 *reg, u32 mask, u32 val)
-{
- unsigned long tmo = timer_get_us() + 1000000;
-
- while ((readl(reg) & mask) != val) {
- if (timer_get_us() > tmo)
- panic("Timeout initialising DRAM\n");
- }
-}
-
static void mctl_sys_init(void)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int dram_clk_div = 2;
- clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div);
+ clock_set_pll5(DRAM_CLK * dram_clk_div, false);
clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
CCM_DRAMCLK_CFG_UPD);
- await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+ mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
@@ -109,8 +94,8 @@
const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
- await_completion(gsr0, done, done);
- await_completion(gsr0 + 0x10, done, done);
+ mctl_await_completion(gsr0, done, done);
+ mctl_await_completion(gsr0 + 0x10, done, done);
return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
}
@@ -131,7 +116,7 @@
}
writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
- await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
+ mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
/* PHY initialization */
writel(MCTL_PGCR, &mctl_phy->pgcr);
@@ -168,14 +153,14 @@
writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
- await_completion(&mctl_phy->pgsr, 0x03, 0x03);
+ mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03);
- writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1);
+ writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1);
setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
writel(MCTL_PIR_STEP1, &mctl_phy->pir);
udelay(10);
- await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
+ mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
/* rank detect */
if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
@@ -206,19 +191,19 @@
setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
writel(MCTL_PIR_STEP2, &mctl_phy->pir);
udelay(10);
- await_completion(&mctl_phy->pgsr, 0x11, 0x11);
+ mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11);
if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
panic("Training error initialising DRAM\n");
/* Move to configure state */
writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
- await_completion(&mctl_ctl->sstat, 0x07, 0x01);
+ mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01);
/* Set number of clks per micro-second */
- writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u);
+ writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u);
/* Set number of clks per 100 nano-seconds */
- writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n);
+ writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n);
/* Set memory timing registers */
writel(MCTL_TREFI, &mctl_ctl->trefi);
writel(MCTL_TMRD, &mctl_ctl->tmrd);
@@ -272,7 +257,7 @@
/* Move to access state */
writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
- await_completion(&mctl_ctl->sstat, 0x07, 0x03);
+ mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03);
}
static void mctl_com_init(struct dram_sun6i_para *para)
@@ -341,20 +326,6 @@
writel(0x00000307, &mctl_com->mbagcr[5]);
}
-static bool mctl_mem_matches(u32 offset)
-{
- const int match_count = 64;
- int i, matches = 0;
-
- for (i = 0; i < match_count; i++) {
- if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) ==
- readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4))
- matches++;
- }
-
- return matches == match_count;
-}
-
unsigned long sunxi_dram_init(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
@@ -371,18 +342,26 @@
.rows = 16,
};
+ /* A31s only has one channel */
+ if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S)
+ para.chan = 1;
+
mctl_sys_init();
mctl_dll_init(0, ¶);
- mctl_dll_init(1, ¶);
+ setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
- setbits_le32(&mctl_com->ccr,
- MCTL_CCR_MASTER_CLK_EN |
- MCTL_CCR_CH0_CLK_EN |
- MCTL_CCR_CH1_CLK_EN);
+ if (para.chan == 2) {
+ mctl_dll_init(1, ¶);
+ setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
+ }
+
+ setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN);
mctl_channel_init(0, ¶);
- mctl_channel_init(1, ¶);
+ if (para.chan == 2)
+ mctl_channel_init(1, ¶);
+
mctl_com_init(¶);
mctl_port_cfg();
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
new file mode 100644
index 0000000..3d7964d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c
@@ -0,0 +1,345 @@
+/*
+ * Sun8i platform dram controller init.
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Note this code uses a lot of magic hex values, that is because this code
+ * simply replays the init sequence as done by the Allwinner boot0 code, so
+ * we do not know what these values mean. There are no symbolic constants for
+ * these magic values, since we do not know how to name them and making up
+ * names for them is not useful.
+ *
+ * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
+ * found in the TI Keystone2 documentation:
+ * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
+ * "Table4-2 DDR3 PHY Registers"
+ * This may be used as a (possible) reference for future work / cleanups.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+static const struct dram_para dram_para = {
+ .clock = CONFIG_DRAM_CLK,
+ .type = 3,
+ .zq = CONFIG_DRAM_ZQ,
+ .odt_en = 1,
+ .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .mr0 = 6736,
+ .mr1 = 4,
+ .mr2 = 16,
+ .mr3 = 0,
+ /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
+ .tpr0 = 0x2ab83def,
+ .tpr1 = 0x18082356,
+ .tpr2 = 0x00034156,
+ .tpr3 = 0x448c5533,
+ .tpr4 = 0x08010d00,
+ .tpr5 = 0x0340b20f,
+ .tpr6 = 0x20d118cc,
+ .tpr7 = 0x14062485,
+ .tpr8 = 0x220d1d52,
+ .tpr9 = 0x1e078c22,
+ .tpr10 = 0x3c,
+ .tpr11 = 0, /* not used */
+ .tpr12 = 0, /* not used */
+ .tpr13 = 0x30000,
+};
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* enable pll5, note the divide by 2 is deliberate! */
+ clock_set_pll5(dram_para.clock * 1000000 / 2,
+ dram_para.tpr13 & 0x40000);
+
+ /* deassert ahb mctl reset */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+
+ /* enable ahb mctl clock */
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_apply_odt_correction(u32 *reg, int correction)
+{
+ int val;
+
+ val = (readl(reg) >> 8) & 0xff;
+ val += correction;
+
+ /* clamp */
+ if (val < 0)
+ val = 0;
+ else if (val > 255)
+ val = 255;
+
+ clrsetbits_le32(reg, 0xff00, val << 8);
+}
+
+static void mctl_init(u32 *bus_width)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ int correction;
+
+ if (dram_para.tpr13 & 0x20)
+ writel(0x40b, &mctl_phy->dcr);
+ else
+ writel(0x1000040b, &mctl_phy->dcr);
+
+ if (dram_para.clock >= 480)
+ writel(0x5c000, &mctl_phy->dllgcr);
+ else
+ writel(0xdc000, &mctl_phy->dllgcr);
+
+ writel(0x0a003e3f, &mctl_phy->pgcr0);
+ writel(0x03008421, &mctl_phy->pgcr1);
+
+ writel(dram_para.mr0, &mctl_phy->mr0);
+ writel(dram_para.mr1, &mctl_phy->mr1);
+ writel(dram_para.mr2, &mctl_phy->mr2);
+ writel(dram_para.mr3, &mctl_phy->mr3);
+
+ if (!(dram_para.tpr13 & 0x10000)) {
+ clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000);
+ clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000);
+ }
+
+ /*
+ * All the masking and shifting below converts what I assume are DDR
+ * timing constants from Allwinner dram_para tpr format to the actual
+ * timing registers format.
+ */
+
+ writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2);
+ writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3);
+ writel((dram_para.tpr0 & 0x3ff00000) >> 2 |
+ (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4);
+
+ writel(dram_para.tpr3, &mctl_phy->dtpr0);
+ writel(dram_para.tpr4, &mctl_phy->dtpr2);
+
+ writel(0x01000081, &mctl_phy->dtcr);
+
+ if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) {
+ clrbits_le32(&mctl_phy->dx0gcr, 0x600);
+ clrbits_le32(&mctl_phy->dx1gcr, 0x600);
+ }
+ if (dram_para.clock <= 240) {
+ writel(0, &mctl_phy->odtcr);
+ writel(0, &mctl_ctl->odtmap);
+ }
+
+ writel(((dram_para.tpr5 & 0x0f00) << 12) |
+ ((dram_para.tpr5 & 0x00f8) << 9) |
+ ((dram_para.tpr5 & 0x0007) << 8),
+ &mctl_ctl->rfshctl0);
+
+ writel(((dram_para.tpr5 & 0x0003f000) << 12) |
+ ((dram_para.tpr5 & 0x00fc0000) >> 2) |
+ ((dram_para.tpr5 & 0x3f000000) >> 16) |
+ ((dram_para.tpr6 & 0x0000003f) >> 0),
+ &mctl_ctl->dramtmg0);
+
+ writel(((dram_para.tpr6 & 0x000007c0) << 10) |
+ ((dram_para.tpr6 & 0x0000f800) >> 3) |
+ ((dram_para.tpr6 & 0x003f0000) >> 16),
+ &mctl_ctl->dramtmg1);
+
+ writel(((dram_para.tpr6 & 0x0fc00000) << 2) |
+ ((dram_para.tpr7 & 0x0000001f) << 16) |
+ ((dram_para.tpr7 & 0x000003e0) << 3) |
+ ((dram_para.tpr7 & 0x0000fc00) >> 10),
+ &mctl_ctl->dramtmg2);
+
+ writel(((dram_para.tpr7 & 0x03ff0000) >> 16) |
+ ((dram_para.tpr6 & 0xf0000000) >> 16),
+ &mctl_ctl->dramtmg3);
+
+ writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) |
+ ((dram_para.tpr8 & 0x00000007) << 16) |
+ ((dram_para.tpr8 & 0x00000038) << 5) |
+ ((dram_para.tpr8 & 0x000003c0) >> 6),
+ &mctl_ctl->dramtmg4);
+
+ writel(((dram_para.tpr8 & 0x00003c00) << 14) |
+ ((dram_para.tpr8 & 0x0003c000) << 2) |
+ ((dram_para.tpr8 & 0x00fc0000) >> 10) |
+ ((dram_para.tpr8 & 0x0f000000) >> 24),
+ &mctl_ctl->dramtmg5);
+
+ writel(0x00000008, &mctl_ctl->dramtmg8);
+
+ writel(((dram_para.tpr8 & 0xf0000000) >> 4) |
+ ((dram_para.tpr9 & 0x00007c00) << 6) |
+ ((dram_para.tpr9 & 0x000003e0) << 3) |
+ ((dram_para.tpr9 & 0x0000001f) >> 0),
+ &mctl_ctl->pitmg0);
+
+ setbits_le32(&mctl_ctl->pitmg1, 0x80000);
+
+ writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001,
+ &mctl_ctl->sched);
+
+ writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
+ writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4);
+
+ writel(0x00000000, &mctl_ctl->pimisc);
+ writel(0x80000000, &mctl_ctl->upd0);
+
+ writel(((dram_para.tpr9 & 0xffc00000) >> 22) |
+ ((dram_para.tpr10 & 0x00000fff) << 16),
+ &mctl_ctl->rfshtmg);
+
+ if (dram_para.tpr13 & 0x20)
+ writel(0x01040001, &mctl_ctl->mstr);
+ else
+ writel(0x01040401, &mctl_ctl->mstr);
+
+ if (!(dram_para.tpr13 & 0x20000)) {
+ writel(0x00000002, &mctl_ctl->pwrctl);
+ writel(0x00008001, &mctl_ctl->pwrtmg);
+ }
+
+ writel(0x00000001, &mctl_ctl->rfshctl3);
+ writel(0x00000001, &mctl_ctl->pimisc);
+
+ /* deassert dram_clk_cfg reset */
+ setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+
+ setbits_le32(&mctl_com->ccr, 0x80000);
+
+ /* zq stuff */
+ writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1);
+
+ writel(0x00000003, &mctl_phy->pir);
+ udelay(10);
+ mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09);
+
+ writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2);
+ writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
+
+ /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */
+ writel(0x000005f3, &mctl_phy->pir);
+ udelay(10);
+ mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03);
+
+ if (readl(&mctl_phy->dx1gsr0) & 0x1000000) {
+ *bus_width = 8;
+ writel(0, &mctl_phy->dx1gcr);
+ writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
+ writel(0x5f3, &mctl_phy->pir);
+ udelay(10000);
+ setbits_le32(&mctl_ctl->mstr, 0x1000);
+ } else
+ *bus_width = 16;
+
+ correction = (dram_para.odt_en >> 8) & 0xff;
+ if (correction) {
+ if (dram_para.odt_en & 0x80000000)
+ correction = -correction;
+
+ mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction);
+ mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction);
+ }
+
+ mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);
+
+ writel(0x08003e3f, &mctl_phy->pgcr0);
+ writel(0x00000000, &mctl_ctl->rfshctl3);
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ const u32 columns = 13;
+ u32 bus, bus_width, offset, page_size, rows;
+
+ mctl_sys_init();
+ mctl_init(&bus_width);
+
+ if (bus_width == 16) {
+ page_size = 8;
+ bus = 1;
+ } else {
+ page_size = 7;
+ bus = 0;
+ }
+
+ if (!(dram_para.tpr13 & 0x80000000)) {
+ /* Detect and set rows */
+ writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size),
+ &mctl_com->cr);
+ setbits_le32(&mctl_com->swonr, 0x0003ffff);
+ for (rows = 11; rows < 16; rows++) {
+ offset = 1 << (rows + columns + bus);
+ if (mctl_mem_matches(offset))
+ break;
+ }
+ clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
+ MCTL_CR_ROW(rows));
+ } else {
+ rows = (dram_para.para1 >> 16) & 0xff;
+ writel(((dram_para.para2 & 0x000000f0) << 11) |
+ ((rows - 1) << 4) |
+ ((dram_para.para1 & 0x0f000000) >> 22) |
+ 0x31000 | MCTL_CR_PAGE_SIZE(page_size),
+ &mctl_com->cr);
+ setbits_le32(&mctl_com->swonr, 0x0003ffff);
+ }
+
+ /* Setup DRAM master priority? If this is left out things still work */
+ writel(0x00000008, &mctl_com->mcr0_0);
+ writel(0x0001000d, &mctl_com->mcr1_0);
+ writel(0x00000004, &mctl_com->mcr0_1);
+ writel(0x00000080, &mctl_com->mcr1_1);
+ writel(0x00000004, &mctl_com->mcr0_2);
+ writel(0x00000019, &mctl_com->mcr1_2);
+ writel(0x00000004, &mctl_com->mcr0_3);
+ writel(0x00000080, &mctl_com->mcr1_3);
+ writel(0x00000004, &mctl_com->mcr0_4);
+ writel(0x01010040, &mctl_com->mcr1_4);
+ writel(0x00000004, &mctl_com->mcr0_5);
+ writel(0x0001002f, &mctl_com->mcr1_5);
+ writel(0x00000004, &mctl_com->mcr0_6);
+ writel(0x00010020, &mctl_com->mcr1_6);
+ writel(0x00000004, &mctl_com->mcr0_7);
+ writel(0x00010020, &mctl_com->mcr1_7);
+ writel(0x00000008, &mctl_com->mcr0_8);
+ writel(0x00000001, &mctl_com->mcr1_8);
+ writel(0x00000008, &mctl_com->mcr0_9);
+ writel(0x00000005, &mctl_com->mcr1_9);
+ writel(0x00000008, &mctl_com->mcr0_10);
+ writel(0x00000003, &mctl_com->mcr1_10);
+ writel(0x00000008, &mctl_com->mcr0_11);
+ writel(0x00000005, &mctl_com->mcr1_11);
+ writel(0x00000008, &mctl_com->mcr0_12);
+ writel(0x00000003, &mctl_com->mcr1_12);
+ writel(0x00000008, &mctl_com->mcr0_13);
+ writel(0x00000004, &mctl_com->mcr1_13);
+ writel(0x00000008, &mctl_com->mcr0_14);
+ writel(0x00000002, &mctl_com->mcr1_14);
+ writel(0x00000008, &mctl_com->mcr0_15);
+ writel(0x00000003, &mctl_com->mcr1_15);
+ writel(0x00010138, &mctl_com->bwcr);
+
+ return 1 << (rows + columns + bus);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c
index 48613bd..26a9cfc 100644
--- a/arch/arm/cpu/armv7/sunxi/p2wi.c
+++ b/arch/arm/cpu/armv7/sunxi/p2wi.c
@@ -26,13 +26,13 @@
void p2wi_init(void)
{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
/* Enable p2wi and PIO clk, and de-assert their resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
writel(P2WI_CTRL_RESET, &p2wi->ctrl);
@@ -43,7 +43,7 @@
int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
unsigned long tmo = timer_get_us() + 1000000;
writel(P2WI_PM_DEV_ADDR(slave_addr) |
@@ -62,7 +62,7 @@
static int p2wi_await_trans(void)
{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
unsigned long tmo = timer_get_us() + 1000000;
int ret;
u8 reg;
@@ -88,7 +88,7 @@
int p2wi_read(const u8 addr, u8 *data)
{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
int ret;
writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
@@ -105,7 +105,7 @@
int p2wi_write(const u8 addr, u8 data)
{
- struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index b9ea78b..5be497b 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -18,6 +18,7 @@
*/
#include <config.h>
+#include <asm/gic.h>
#include <asm/psci.h>
#include <asm/arch/cpu.h>
@@ -38,6 +39,8 @@
#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000)
#define TEN_MS (10 * ONE_MS)
+#define GICD_BASE 0x1c81000
+#define GICC_BASE 0x1c82000
.macro timer_wait reg, ticks
@ Program CNTP_TVAL
@@ -59,25 +62,77 @@
isb
.endm
-.globl psci_arch_init
-psci_arch_init:
- mrc p15, 0, r5, c1, c1, 0 @ Read SCR
- bic r5, r5, #1 @ Secure mode
- mcr p15, 0, r5, c1, c1, 0 @ Write SCR
+.globl psci_fiq_enter
+psci_fiq_enter:
+ push {r0-r12}
+
+ @ Switch to secure
+ mrc p15, 0, r7, c1, c1, 0
+ bic r8, r7, #1
+ mcr p15, 0, r8, c1, c1, 0
isb
- mrc p15, 0, r4, c0, c0, 5 @ MPIDR
- and r4, r4, #3 @ cpu number in cluster
- mov r5, #400 @ 1kB of stack per CPU
- mul r4, r4, r5
+ @ Validate reason based on IAR and acknowledge
+ movw r8, #(GICC_BASE & 0xffff)
+ movt r8, #(GICC_BASE >> 16)
+ ldr r9, [r8, #GICC_IAR]
+ movw r10, #0x3ff
+ movt r10, #0
+ cmp r9, r10 @ skip spurious interrupt 1023
+ beq out
+ movw r10, #0x3fe @ ...and 1022
+ cmp r9, r10
+ beq out
+ str r9, [r8, #GICC_EOIR] @ acknowledge the interrupt
+ dsb
- adr r5, text_end @ end of text
- add r5, r5, #0x2000 @ Skip two pages
- lsr r5, r5, #12 @ Align to start of page
- lsl r5, r5, #12
- sub sp, r5, r4 @ here's our stack!
+ @ Compute CPU number
+ lsr r9, r9, #10
+ and r9, r9, #0xf
- bx lr
+ movw r8, #(SUN7I_CPUCFG_BASE & 0xffff)
+ movt r8, #(SUN7I_CPUCFG_BASE >> 16)
+
+ @ Wait for the core to enter WFI
+ lsl r11, r9, #6 @ x64
+ add r11, r11, r8
+
+1: ldr r10, [r11, #0x48]
+ tst r10, #(1 << 2)
+ bne 2f
+ timer_wait r10, ONE_MS
+ b 1b
+
+ @ Reset CPU
+2: mov r10, #0
+ str r10, [r11, #0x40]
+
+ @ Lock CPU
+ mov r10, #1
+ lsl r9, r10, r9 @ r9 is now CPU mask
+ ldr r10, [r8, #0x1e4]
+ bic r10, r10, r9
+ str r10, [r8, #0x1e4]
+
+ @ Set power gating
+ ldr r10, [r8, #0x1b4]
+ orr r10, r10, #1
+ str r10, [r8, #0x1b4]
+ timer_wait r10, ONE_MS
+
+ @ Activate power clamp
+ mov r10, #1
+1: str r10, [r8, #0x1b0]
+ lsl r10, r10, #1
+ orr r10, r10, #1
+ tst r10, #0x100
+ beq 1b
+
+ @ Restore security level
+out: mcr p15, 0, r7, c1, c1, 0
+
+ pop {r0-r12}
+ subs pc, lr, #4
@ r1 = target CPU
@ r2 = target PC
@@ -144,6 +199,53 @@
_target_pc:
.word 0
+/* Imported from Linux kernel */
+v7_flush_dcache_all:
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ ands r3, r0, #0x7000000 @ extract loc from clidr
+ mov r3, r3, lsr #23 @ left align loc bit field
+ beq finished @ if loc is 0, then no need to clean
+ mov r10, #0 @ start clean at cache level 0
+flush_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt skip @ skip if no cache, or just i-cache
+ mrs r9, cpsr @ make cssr&csidr read atomic
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ msr cpsr_c, r9
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ ldr r4, =0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+loop1:
+ mov r9, r7 @ create working copy of max index
+loop2:
+ orr r11, r10, r4, lsl r5 @ factor way and cache number into r11
+ orr r11, r11, r9, lsl r2 @ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge loop2
+ subs r4, r4, #1 @ decrement the way
+ bge loop1
+skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt flush_levels
+finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ bx lr
+
_sunxi_cpu_entry:
@ Set SMP bit
mrc p15, 0, r0, c1, c0, 1
@@ -158,5 +260,74 @@
ldr r0, [r0]
b _do_nonsec_entry
+.globl psci_cpu_off
+psci_cpu_off:
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR
+ bic r0, r0, #(1 << 2) @ Clear C bit
+ mcr p15, 0, r0, c1, c0, 0 @ SCTLR
+ isb
+ dsb
+
+ bl v7_flush_dcache_all
+
+ clrex @ Why???
+
+ mrc p15, 0, r0, c1, c0, 1 @ ACTLR
+ bic r0, r0, #(1 << 6) @ Clear SMP bit
+ mcr p15, 0, r0, c1, c0, 1 @ ACTLR
+ isb
+ dsb
+
+ @ Ask CPU0 to pull the rug...
+ movw r0, #(GICD_BASE & 0xffff)
+ movt r0, #(GICD_BASE >> 16)
+ movw r1, #15 @ SGI15
+ movt r1, #1 @ Target is CPU0
+ str r1, [r0, #GICD_SGIR]
+ dsb
+
+1: wfi
+ b 1b
+
+.globl psci_arch_init
+psci_arch_init:
+ movw r4, #(GICD_BASE & 0xffff)
+ movt r4, #(GICD_BASE >> 16)
+
+ ldr r5, [r4, #GICD_IGROUPRn]
+ bic r5, r5, #(1 << 15) @ SGI15 as Group-0
+ str r5, [r4, #GICD_IGROUPRn]
+
+ mov r5, #0 @ Set SGI15 priority to 0
+ strb r5, [r4, #(GICD_IPRIORITYRn + 15)]
+
+ add r4, r4, #0x1000 @ GICC address
+
+ mov r5, #0xff
+ str r5, [r4, #GICC_PMR] @ Be cool with non-secure
+
+ ldr r5, [r4, #GICC_CTLR]
+ orr r5, r5, #(1 << 3) @ Switch FIQEn on
+ str r5, [r4, #GICC_CTLR]
+
+ mrc p15, 0, r5, c1, c1, 0 @ Read SCR
+ orr r5, r5, #4 @ Enable FIQ in monitor mode
+ bic r5, r5, #1 @ Secure mode
+ mcr p15, 0, r5, c1, c1, 0 @ Write SCR
+ isb
+
+ mrc p15, 0, r4, c0, c0, 5 @ MPIDR
+ and r4, r4, #3 @ cpu number in cluster
+ mov r5, #0x400 @ 1kB of stack per CPU
+ mul r4, r4, r5
+
+ adr r5, text_end @ end of text
+ add r5, r5, #0x2000 @ Skip two pages
+ lsr r5, r5, #12 @ Align to start of page
+ lsl r5, r5, #12
+ sub sp, r5, r4 @ here's our stack!
+
+ bx lr
+
text_end:
.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
new file mode 100644
index 0000000..b72bb9d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * lixiang <lixiang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/rsb.h>
+
+static void rsb_cfg_io(void)
+{
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
+ sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+}
+
+static void rsb_set_clk(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ u32 div = 0;
+ u32 cd_odly = 0;
+
+ /* Source is Hosc24M, set RSB clk to 3Mhz */
+ div = 24000000 / 3000000 / 2 - 1;
+ cd_odly = div >> 1;
+ if (!cd_odly)
+ cd_odly = 1;
+
+ writel((cd_odly << 8) | div, &rsb->ccr);
+}
+
+void rsb_init(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ rsb_cfg_io();
+
+ /* Enable RSB and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+ writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
+ rsb_set_clk();
+}
+
+static int rsb_await_trans(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 1000000;
+ u32 stat;
+ int ret;
+
+ while (1) {
+ stat = readl(&rsb->stat);
+ if (stat & RSB_STAT_LBSY_INT) {
+ ret = -EBUSY;
+ break;
+ }
+ if (stat & RSB_STAT_TERR_INT) {
+ ret = -EIO;
+ break;
+ }
+ if (stat & RSB_STAT_TOVER_INT) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(stat, &rsb->stat); /* Clear status bits */
+
+ return ret;
+}
+
+int rsb_set_device_mode(u32 device_mode_data)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
+
+ while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return rsb_await_trans();
+}
+
+static int rsb_do_trans(void)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
+ return rsb_await_trans();
+}
+
+int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
+ RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
+ writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
+
+ return rsb_do_trans();
+}
+
+int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
+ writel(reg_addr, &rsb->addr);
+ writel(data, &rsb->data);
+ writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
+
+ return rsb_do_trans();
+}
+
+int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
+{
+ struct sunxi_rsb_reg * const rsb =
+ (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
+ int ret;
+
+ writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
+ writel(reg_addr, &rsb->addr);
+ writel(RSB_CMD_BYTE_READ, &rsb->cmd);
+
+ ret = rsb_do_trans();
+ if (ret)
+ return ret;
+
+ *data = readl(&rsb->data) & 0xff;
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c
new file mode 100644
index 0000000..14de9f9
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/usbc.c
@@ -0,0 +1,272 @@
+/*
+ * Sunxi usb-controller code shared between the ehci and musb controllers
+ *
+ * Copyright (C) 2014 Roman Byshko
+ *
+ * Roman Byshko <rbyshko@gmail.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/usbc.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <common.h>
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
+#ifdef CONFIG_AXP221_POWER
+#include <axp221.h>
+#endif
+
+#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
+#define SUNXI_USB_CSR 0x404
+#define SUNXI_USB_PASSBY_EN 1
+
+#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
+#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
+#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
+#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
+
+static struct sunxi_usbc_hcd {
+ struct usb_hcd *hcd;
+ int usb_rst_mask;
+ int ahb_clk_mask;
+ int gpio_vbus;
+ int irq;
+ int id;
+} sunxi_usbc_hcd[] = {
+ {
+ .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
+ .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB0,
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+ .irq = 71,
+#else
+ .irq = 38,
+#endif
+ .id = 0,
+ },
+ {
+ .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
+ .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+ .irq = 72,
+#else
+ .irq = 39,
+#endif
+ .id = 1,
+ },
+#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
+ {
+ .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
+ .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
+#ifdef CONFIG_MACH_SUN6I
+ .irq = 74,
+#else
+ .irq = 40,
+#endif
+ .id = 2,
+ }
+#endif
+};
+
+static int enabled_hcd_count;
+
+static bool use_axp_drivebus(int index)
+{
+ return index == 0 &&
+ strcmp(CONFIG_USB0_VBUS_PIN, "axp_drivebus") == 0;
+}
+
+void *sunxi_usbc_get_io_base(int index)
+{
+ switch (index) {
+ case 0:
+ return (void *)SUNXI_USB0_BASE;
+ case 1:
+ return (void *)SUNXI_USB1_BASE;
+ case 2:
+ return (void *)SUNXI_USB2_BASE;
+ default:
+ return NULL;
+ }
+}
+
+static int get_vbus_gpio(int index)
+{
+ if (use_axp_drivebus(index))
+ return -1;
+
+ switch (index) {
+ case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
+ case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
+ case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+ }
+ return -1;
+}
+
+static void usb_phy_write(struct sunxi_usbc_hcd *sunxi_usbc, int addr,
+ int data, int len)
+{
+ int j = 0, usbc_bit = 0;
+ void *dest = sunxi_usbc_get_io_base(0) + SUNXI_USB_CSR;
+
+ usbc_bit = 1 << (sunxi_usbc->id * 2);
+ for (j = 0; j < len; j++) {
+ /* set the bit address to be written */
+ clrbits_le32(dest, 0xff << 8);
+ setbits_le32(dest, (addr + j) << 8);
+
+ clrbits_le32(dest, usbc_bit);
+ /* set data bit */
+ if (data & 0x1)
+ setbits_le32(dest, 1 << 7);
+ else
+ clrbits_le32(dest, 1 << 7);
+
+ setbits_le32(dest, usbc_bit);
+
+ clrbits_le32(dest, usbc_bit);
+
+ data >>= 1;
+ }
+}
+
+static void sunxi_usb_phy_init(struct sunxi_usbc_hcd *sunxi_usbc)
+{
+ /* The following comments are machine
+ * translated from Chinese, you have been warned!
+ */
+
+ /* Regulation 45 ohms */
+ if (sunxi_usbc->id == 0)
+ usb_phy_write(sunxi_usbc, 0x0c, 0x01, 1);
+
+ /* adjust PHY's magnitude and rate */
+ usb_phy_write(sunxi_usbc, 0x20, 0x14, 5);
+
+ /* threshold adjustment disconnect */
+#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I
+ usb_phy_write(sunxi_usbc, 0x2a, 3, 2);
+#else
+ usb_phy_write(sunxi_usbc, 0x2a, 2, 2);
+#endif
+
+ return;
+}
+
+static void sunxi_usb_passby(struct sunxi_usbc_hcd *sunxi_usbc, int enable)
+{
+ unsigned long bits = 0;
+ void *addr = sunxi_usbc_get_io_base(sunxi_usbc->id) +
+ SUNXI_USB_PMU_IRQ_ENABLE;
+
+ bits = SUNXI_EHCI_AHB_ICHR8_EN |
+ SUNXI_EHCI_AHB_INCR4_BURST_EN |
+ SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
+ SUNXI_EHCI_ULPI_BYPASS_EN;
+
+ if (enable)
+ setbits_le32(addr, bits);
+ else
+ clrbits_le32(addr, bits);
+
+ return;
+}
+
+int sunxi_usbc_request_resources(int index)
+{
+ struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+
+ sunxi_usbc->gpio_vbus = get_vbus_gpio(index);
+ if (sunxi_usbc->gpio_vbus != -1)
+ return gpio_request(sunxi_usbc->gpio_vbus, "usbc_vbus");
+
+ return 0;
+}
+
+int sunxi_usbc_free_resources(int index)
+{
+ struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+
+ if (sunxi_usbc->gpio_vbus != -1)
+ return gpio_free(sunxi_usbc->gpio_vbus);
+
+ return 0;
+}
+
+void sunxi_usbc_enable(int index)
+{
+ struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* enable common PHY only once */
+ if (enabled_hcd_count == 0)
+ setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+
+ setbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask);
+ setbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+ setbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
+#endif
+
+ sunxi_usb_phy_init(sunxi_usbc);
+
+ if (sunxi_usbc->id != 0)
+ sunxi_usb_passby(sunxi_usbc, SUNXI_USB_PASSBY_EN);
+
+ enabled_hcd_count++;
+}
+
+void sunxi_usbc_disable(int index)
+{
+ struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (sunxi_usbc->id != 0)
+ sunxi_usb_passby(sunxi_usbc, !SUNXI_USB_PASSBY_EN);
+
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+ clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
+#endif
+ clrbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);
+ clrbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask);
+
+ /* disable common PHY only once, for the last enabled hcd */
+ if (enabled_hcd_count == 1)
+ clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+
+ enabled_hcd_count--;
+}
+
+void sunxi_usbc_vbus_enable(int index)
+{
+ struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+
+#ifdef AXP_DRIVEBUS
+ if (use_axp_drivebus(index))
+ axp_drivebus_enable();
+#endif
+ if (sunxi_usbc->gpio_vbus != -1)
+ gpio_direction_output(sunxi_usbc->gpio_vbus, 1);
+}
+
+void sunxi_usbc_vbus_disable(int index)
+{
+ struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+
+#ifdef AXP_DRIVEBUS
+ if (use_axp_drivebus(index))
+ axp_drivebus_disable();
+#endif
+ if (sunxi_usbc->gpio_vbus != -1)
+ gpio_direction_output(sunxi_usbc->gpio_vbus, 0);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.S b/arch/arm/cpu/armv7/uniphier/init_page_table.S
new file mode 100644
index 0000000..2638bcd
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/init_page_table.S
@@ -0,0 +1,26 @@
+#include <config.h>
+#include <linux/linkage.h>
+
+/* page table */
+#define NR_SECTIONS 4096
+#define SECTION_SHIFT 20
+#define DEVICE 0x00002002 /* Non-shareable Device */
+#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
+
+#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
+#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT))
+
+ .section ".rodata"
+ .align 14
+ENTRY(init_page_table)
+ section = 0
+ .rept NR_SECTIONS
+ .if section == TEXT_SECTION || section == STACK_SECTION
+ attr = NORMAL
+ .else
+ attr = DEVICE
+ .endif
+ .word (section << SECTION_SHIFT) | attr
+ section = section + 1
+ .endr
+END(init_page_table)
diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.c b/arch/arm/cpu/armv7/uniphier/init_page_table.c
deleted file mode 100644
index febb3c8..0000000
--- a/arch/arm/cpu/armv7/uniphier/init_page_table.c
+++ /dev/null
@@ -1,1069 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/* encoding without TEX remap */
-#define NO_MAP 0x00000000 /* No Map */
-#define DEVICE 0x00002002 /* Non-shareable Device */
-#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
-
-#define SSC NORMAL /* System Cache: Normal */
-#define EXT DEVICE /* External Bus: Device */
-#define REG DEVICE /* IO Register: Device */
-#define DDR DEVICE /* DDR SDRAM: Device */
-
-#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SPL_TEXT_BASE) >> 20))
-
-#define IS_INIT_STACK_AREA(x) ((x) == ((CONFIG_SYS_INIT_SP_ADDR) >> 20))
-
-#define IS_SSC(x) ((IS_SPL_TEXT_AREA(x)) || \
- (IS_INIT_STACK_AREA(x)))
-#define IS_EXT(x) ((x) < 0x100)
-
-/* 0x20000000-0x2fffffff, 0xf0000000-0xffffffff are only used by PH1-sLD3 */
-#define IS_REG(x) (0x200 <= (x) && (x) < 0x300) || \
- (0x500 <= (x) && (x) < 0x700) || \
- (0xf00 <= (x))
-
-#define IS_DDR(x) (0x800 <= (x) && (x) < 0xf00)
-
-#define MMU_FLAGS(x) (IS_SSC(x)) ? SSC : \
- (IS_EXT(x)) ? EXT : \
- (IS_REG(x)) ? REG : \
- (IS_DDR(x)) ? DDR : \
- NO_MAP
-
-#define TBL_ENTRY(x) (((x) << 20) | (MMU_FLAGS(x)))
-
-const u32 __aligned(PGTABLE_SIZE) init_page_table[PGTABLE_SIZE / sizeof(u32)]
- = {
- TBL_ENTRY(0x000), TBL_ENTRY(0x001), TBL_ENTRY(0x002), TBL_ENTRY(0x003),
- TBL_ENTRY(0x004), TBL_ENTRY(0x005), TBL_ENTRY(0x006), TBL_ENTRY(0x007),
- TBL_ENTRY(0x008), TBL_ENTRY(0x009), TBL_ENTRY(0x00a), TBL_ENTRY(0x00b),
- TBL_ENTRY(0x00c), TBL_ENTRY(0x00d), TBL_ENTRY(0x00e), TBL_ENTRY(0x00f),
- TBL_ENTRY(0x010), TBL_ENTRY(0x011), TBL_ENTRY(0x012), TBL_ENTRY(0x013),
- TBL_ENTRY(0x014), TBL_ENTRY(0x015), TBL_ENTRY(0x016), TBL_ENTRY(0x017),
- TBL_ENTRY(0x018), TBL_ENTRY(0x019), TBL_ENTRY(0x01a), TBL_ENTRY(0x01b),
- TBL_ENTRY(0x01c), TBL_ENTRY(0x01d), TBL_ENTRY(0x01e), TBL_ENTRY(0x01f),
- TBL_ENTRY(0x020), TBL_ENTRY(0x021), TBL_ENTRY(0x022), TBL_ENTRY(0x023),
- TBL_ENTRY(0x024), TBL_ENTRY(0x025), TBL_ENTRY(0x026), TBL_ENTRY(0x027),
- TBL_ENTRY(0x028), TBL_ENTRY(0x029), TBL_ENTRY(0x02a), TBL_ENTRY(0x02b),
- TBL_ENTRY(0x02c), TBL_ENTRY(0x02d), TBL_ENTRY(0x02e), TBL_ENTRY(0x02f),
- TBL_ENTRY(0x030), TBL_ENTRY(0x031), TBL_ENTRY(0x032), TBL_ENTRY(0x033),
- TBL_ENTRY(0x034), TBL_ENTRY(0x035), TBL_ENTRY(0x036), TBL_ENTRY(0x037),
- TBL_ENTRY(0x038), TBL_ENTRY(0x039), TBL_ENTRY(0x03a), TBL_ENTRY(0x03b),
- TBL_ENTRY(0x03c), TBL_ENTRY(0x03d), TBL_ENTRY(0x03e), TBL_ENTRY(0x03f),
- TBL_ENTRY(0x040), TBL_ENTRY(0x041), TBL_ENTRY(0x042), TBL_ENTRY(0x043),
- TBL_ENTRY(0x044), TBL_ENTRY(0x045), TBL_ENTRY(0x046), TBL_ENTRY(0x047),
- TBL_ENTRY(0x048), TBL_ENTRY(0x049), TBL_ENTRY(0x04a), TBL_ENTRY(0x04b),
- TBL_ENTRY(0x04c), TBL_ENTRY(0x04d), TBL_ENTRY(0x04e), TBL_ENTRY(0x04f),
- TBL_ENTRY(0x050), TBL_ENTRY(0x051), TBL_ENTRY(0x052), TBL_ENTRY(0x053),
- TBL_ENTRY(0x054), TBL_ENTRY(0x055), TBL_ENTRY(0x056), TBL_ENTRY(0x057),
- TBL_ENTRY(0x058), TBL_ENTRY(0x059), TBL_ENTRY(0x05a), TBL_ENTRY(0x05b),
- TBL_ENTRY(0x05c), TBL_ENTRY(0x05d), TBL_ENTRY(0x05e), TBL_ENTRY(0x05f),
- TBL_ENTRY(0x060), TBL_ENTRY(0x061), TBL_ENTRY(0x062), TBL_ENTRY(0x063),
- TBL_ENTRY(0x064), TBL_ENTRY(0x065), TBL_ENTRY(0x066), TBL_ENTRY(0x067),
- TBL_ENTRY(0x068), TBL_ENTRY(0x069), TBL_ENTRY(0x06a), TBL_ENTRY(0x06b),
- TBL_ENTRY(0x06c), TBL_ENTRY(0x06d), TBL_ENTRY(0x06e), TBL_ENTRY(0x06f),
- TBL_ENTRY(0x070), TBL_ENTRY(0x071), TBL_ENTRY(0x072), TBL_ENTRY(0x073),
- TBL_ENTRY(0x074), TBL_ENTRY(0x075), TBL_ENTRY(0x076), TBL_ENTRY(0x077),
- TBL_ENTRY(0x078), TBL_ENTRY(0x079), TBL_ENTRY(0x07a), TBL_ENTRY(0x07b),
- TBL_ENTRY(0x07c), TBL_ENTRY(0x07d), TBL_ENTRY(0x07e), TBL_ENTRY(0x07f),
- TBL_ENTRY(0x080), TBL_ENTRY(0x081), TBL_ENTRY(0x082), TBL_ENTRY(0x083),
- TBL_ENTRY(0x084), TBL_ENTRY(0x085), TBL_ENTRY(0x086), TBL_ENTRY(0x087),
- TBL_ENTRY(0x088), TBL_ENTRY(0x089), TBL_ENTRY(0x08a), TBL_ENTRY(0x08b),
- TBL_ENTRY(0x08c), TBL_ENTRY(0x08d), TBL_ENTRY(0x08e), TBL_ENTRY(0x08f),
- TBL_ENTRY(0x090), TBL_ENTRY(0x091), TBL_ENTRY(0x092), TBL_ENTRY(0x093),
- TBL_ENTRY(0x094), TBL_ENTRY(0x095), TBL_ENTRY(0x096), TBL_ENTRY(0x097),
- TBL_ENTRY(0x098), TBL_ENTRY(0x099), TBL_ENTRY(0x09a), TBL_ENTRY(0x09b),
- TBL_ENTRY(0x09c), TBL_ENTRY(0x09d), TBL_ENTRY(0x09e), TBL_ENTRY(0x09f),
- TBL_ENTRY(0x0a0), TBL_ENTRY(0x0a1), TBL_ENTRY(0x0a2), TBL_ENTRY(0x0a3),
- TBL_ENTRY(0x0a4), TBL_ENTRY(0x0a5), TBL_ENTRY(0x0a6), TBL_ENTRY(0x0a7),
- TBL_ENTRY(0x0a8), TBL_ENTRY(0x0a9), TBL_ENTRY(0x0aa), TBL_ENTRY(0x0ab),
- TBL_ENTRY(0x0ac), TBL_ENTRY(0x0ad), TBL_ENTRY(0x0ae), TBL_ENTRY(0x0af),
- TBL_ENTRY(0x0b0), TBL_ENTRY(0x0b1), TBL_ENTRY(0x0b2), TBL_ENTRY(0x0b3),
- TBL_ENTRY(0x0b4), TBL_ENTRY(0x0b5), TBL_ENTRY(0x0b6), TBL_ENTRY(0x0b7),
- TBL_ENTRY(0x0b8), TBL_ENTRY(0x0b9), TBL_ENTRY(0x0ba), TBL_ENTRY(0x0bb),
- TBL_ENTRY(0x0bc), TBL_ENTRY(0x0bd), TBL_ENTRY(0x0be), TBL_ENTRY(0x0bf),
- TBL_ENTRY(0x0c0), TBL_ENTRY(0x0c1), TBL_ENTRY(0x0c2), TBL_ENTRY(0x0c3),
- TBL_ENTRY(0x0c4), TBL_ENTRY(0x0c5), TBL_ENTRY(0x0c6), TBL_ENTRY(0x0c7),
- TBL_ENTRY(0x0c8), TBL_ENTRY(0x0c9), TBL_ENTRY(0x0ca), TBL_ENTRY(0x0cb),
- TBL_ENTRY(0x0cc), TBL_ENTRY(0x0cd), TBL_ENTRY(0x0ce), TBL_ENTRY(0x0cf),
- TBL_ENTRY(0x0d0), TBL_ENTRY(0x0d1), TBL_ENTRY(0x0d2), TBL_ENTRY(0x0d3),
- TBL_ENTRY(0x0d4), TBL_ENTRY(0x0d5), TBL_ENTRY(0x0d6), TBL_ENTRY(0x0d7),
- TBL_ENTRY(0x0d8), TBL_ENTRY(0x0d9), TBL_ENTRY(0x0da), TBL_ENTRY(0x0db),
- TBL_ENTRY(0x0dc), TBL_ENTRY(0x0dd), TBL_ENTRY(0x0de), TBL_ENTRY(0x0df),
- TBL_ENTRY(0x0e0), TBL_ENTRY(0x0e1), TBL_ENTRY(0x0e2), TBL_ENTRY(0x0e3),
- TBL_ENTRY(0x0e4), TBL_ENTRY(0x0e5), TBL_ENTRY(0x0e6), TBL_ENTRY(0x0e7),
- TBL_ENTRY(0x0e8), TBL_ENTRY(0x0e9), TBL_ENTRY(0x0ea), TBL_ENTRY(0x0eb),
- TBL_ENTRY(0x0ec), TBL_ENTRY(0x0ed), TBL_ENTRY(0x0ee), TBL_ENTRY(0x0ef),
- TBL_ENTRY(0x0f0), TBL_ENTRY(0x0f1), TBL_ENTRY(0x0f2), TBL_ENTRY(0x0f3),
- TBL_ENTRY(0x0f4), TBL_ENTRY(0x0f5), TBL_ENTRY(0x0f6), TBL_ENTRY(0x0f7),
- TBL_ENTRY(0x0f8), TBL_ENTRY(0x0f9), TBL_ENTRY(0x0fa), TBL_ENTRY(0x0fb),
- TBL_ENTRY(0x0fc), TBL_ENTRY(0x0fd), TBL_ENTRY(0x0fe), TBL_ENTRY(0x0ff),
- TBL_ENTRY(0x100), TBL_ENTRY(0x101), TBL_ENTRY(0x102), TBL_ENTRY(0x103),
- TBL_ENTRY(0x104), TBL_ENTRY(0x105), TBL_ENTRY(0x106), TBL_ENTRY(0x107),
- TBL_ENTRY(0x108), TBL_ENTRY(0x109), TBL_ENTRY(0x10a), TBL_ENTRY(0x10b),
- TBL_ENTRY(0x10c), TBL_ENTRY(0x10d), TBL_ENTRY(0x10e), TBL_ENTRY(0x10f),
- TBL_ENTRY(0x110), TBL_ENTRY(0x111), TBL_ENTRY(0x112), TBL_ENTRY(0x113),
- TBL_ENTRY(0x114), TBL_ENTRY(0x115), TBL_ENTRY(0x116), TBL_ENTRY(0x117),
- TBL_ENTRY(0x118), TBL_ENTRY(0x119), TBL_ENTRY(0x11a), TBL_ENTRY(0x11b),
- TBL_ENTRY(0x11c), TBL_ENTRY(0x11d), TBL_ENTRY(0x11e), TBL_ENTRY(0x11f),
- TBL_ENTRY(0x120), TBL_ENTRY(0x121), TBL_ENTRY(0x122), TBL_ENTRY(0x123),
- TBL_ENTRY(0x124), TBL_ENTRY(0x125), TBL_ENTRY(0x126), TBL_ENTRY(0x127),
- TBL_ENTRY(0x128), TBL_ENTRY(0x129), TBL_ENTRY(0x12a), TBL_ENTRY(0x12b),
- TBL_ENTRY(0x12c), TBL_ENTRY(0x12d), TBL_ENTRY(0x12e), TBL_ENTRY(0x12f),
- TBL_ENTRY(0x130), TBL_ENTRY(0x131), TBL_ENTRY(0x132), TBL_ENTRY(0x133),
- TBL_ENTRY(0x134), TBL_ENTRY(0x135), TBL_ENTRY(0x136), TBL_ENTRY(0x137),
- TBL_ENTRY(0x138), TBL_ENTRY(0x139), TBL_ENTRY(0x13a), TBL_ENTRY(0x13b),
- TBL_ENTRY(0x13c), TBL_ENTRY(0x13d), TBL_ENTRY(0x13e), TBL_ENTRY(0x13f),
- TBL_ENTRY(0x140), TBL_ENTRY(0x141), TBL_ENTRY(0x142), TBL_ENTRY(0x143),
- TBL_ENTRY(0x144), TBL_ENTRY(0x145), TBL_ENTRY(0x146), TBL_ENTRY(0x147),
- TBL_ENTRY(0x148), TBL_ENTRY(0x149), TBL_ENTRY(0x14a), TBL_ENTRY(0x14b),
- TBL_ENTRY(0x14c), TBL_ENTRY(0x14d), TBL_ENTRY(0x14e), TBL_ENTRY(0x14f),
- TBL_ENTRY(0x150), TBL_ENTRY(0x151), TBL_ENTRY(0x152), TBL_ENTRY(0x153),
- TBL_ENTRY(0x154), TBL_ENTRY(0x155), TBL_ENTRY(0x156), TBL_ENTRY(0x157),
- TBL_ENTRY(0x158), TBL_ENTRY(0x159), TBL_ENTRY(0x15a), TBL_ENTRY(0x15b),
- TBL_ENTRY(0x15c), TBL_ENTRY(0x15d), TBL_ENTRY(0x15e), TBL_ENTRY(0x15f),
- TBL_ENTRY(0x160), TBL_ENTRY(0x161), TBL_ENTRY(0x162), TBL_ENTRY(0x163),
- TBL_ENTRY(0x164), TBL_ENTRY(0x165), TBL_ENTRY(0x166), TBL_ENTRY(0x167),
- TBL_ENTRY(0x168), TBL_ENTRY(0x169), TBL_ENTRY(0x16a), TBL_ENTRY(0x16b),
- TBL_ENTRY(0x16c), TBL_ENTRY(0x16d), TBL_ENTRY(0x16e), TBL_ENTRY(0x16f),
- TBL_ENTRY(0x170), TBL_ENTRY(0x171), TBL_ENTRY(0x172), TBL_ENTRY(0x173),
- TBL_ENTRY(0x174), TBL_ENTRY(0x175), TBL_ENTRY(0x176), TBL_ENTRY(0x177),
- TBL_ENTRY(0x178), TBL_ENTRY(0x179), TBL_ENTRY(0x17a), TBL_ENTRY(0x17b),
- TBL_ENTRY(0x17c), TBL_ENTRY(0x17d), TBL_ENTRY(0x17e), TBL_ENTRY(0x17f),
- TBL_ENTRY(0x180), TBL_ENTRY(0x181), TBL_ENTRY(0x182), TBL_ENTRY(0x183),
- TBL_ENTRY(0x184), TBL_ENTRY(0x185), TBL_ENTRY(0x186), TBL_ENTRY(0x187),
- TBL_ENTRY(0x188), TBL_ENTRY(0x189), TBL_ENTRY(0x18a), TBL_ENTRY(0x18b),
- TBL_ENTRY(0x18c), TBL_ENTRY(0x18d), TBL_ENTRY(0x18e), TBL_ENTRY(0x18f),
- TBL_ENTRY(0x190), TBL_ENTRY(0x191), TBL_ENTRY(0x192), TBL_ENTRY(0x193),
- TBL_ENTRY(0x194), TBL_ENTRY(0x195), TBL_ENTRY(0x196), TBL_ENTRY(0x197),
- TBL_ENTRY(0x198), TBL_ENTRY(0x199), TBL_ENTRY(0x19a), TBL_ENTRY(0x19b),
- TBL_ENTRY(0x19c), TBL_ENTRY(0x19d), TBL_ENTRY(0x19e), TBL_ENTRY(0x19f),
- TBL_ENTRY(0x1a0), TBL_ENTRY(0x1a1), TBL_ENTRY(0x1a2), TBL_ENTRY(0x1a3),
- TBL_ENTRY(0x1a4), TBL_ENTRY(0x1a5), TBL_ENTRY(0x1a6), TBL_ENTRY(0x1a7),
- TBL_ENTRY(0x1a8), TBL_ENTRY(0x1a9), TBL_ENTRY(0x1aa), TBL_ENTRY(0x1ab),
- TBL_ENTRY(0x1ac), TBL_ENTRY(0x1ad), TBL_ENTRY(0x1ae), TBL_ENTRY(0x1af),
- TBL_ENTRY(0x1b0), TBL_ENTRY(0x1b1), TBL_ENTRY(0x1b2), TBL_ENTRY(0x1b3),
- TBL_ENTRY(0x1b4), TBL_ENTRY(0x1b5), TBL_ENTRY(0x1b6), TBL_ENTRY(0x1b7),
- TBL_ENTRY(0x1b8), TBL_ENTRY(0x1b9), TBL_ENTRY(0x1ba), TBL_ENTRY(0x1bb),
- TBL_ENTRY(0x1bc), TBL_ENTRY(0x1bd), TBL_ENTRY(0x1be), TBL_ENTRY(0x1bf),
- TBL_ENTRY(0x1c0), TBL_ENTRY(0x1c1), TBL_ENTRY(0x1c2), TBL_ENTRY(0x1c3),
- TBL_ENTRY(0x1c4), TBL_ENTRY(0x1c5), TBL_ENTRY(0x1c6), TBL_ENTRY(0x1c7),
- TBL_ENTRY(0x1c8), TBL_ENTRY(0x1c9), TBL_ENTRY(0x1ca), TBL_ENTRY(0x1cb),
- TBL_ENTRY(0x1cc), TBL_ENTRY(0x1cd), TBL_ENTRY(0x1ce), TBL_ENTRY(0x1cf),
- TBL_ENTRY(0x1d0), TBL_ENTRY(0x1d1), TBL_ENTRY(0x1d2), TBL_ENTRY(0x1d3),
- TBL_ENTRY(0x1d4), TBL_ENTRY(0x1d5), TBL_ENTRY(0x1d6), TBL_ENTRY(0x1d7),
- TBL_ENTRY(0x1d8), TBL_ENTRY(0x1d9), TBL_ENTRY(0x1da), TBL_ENTRY(0x1db),
- TBL_ENTRY(0x1dc), TBL_ENTRY(0x1dd), TBL_ENTRY(0x1de), TBL_ENTRY(0x1df),
- TBL_ENTRY(0x1e0), TBL_ENTRY(0x1e1), TBL_ENTRY(0x1e2), TBL_ENTRY(0x1e3),
- TBL_ENTRY(0x1e4), TBL_ENTRY(0x1e5), TBL_ENTRY(0x1e6), TBL_ENTRY(0x1e7),
- TBL_ENTRY(0x1e8), TBL_ENTRY(0x1e9), TBL_ENTRY(0x1ea), TBL_ENTRY(0x1eb),
- TBL_ENTRY(0x1ec), TBL_ENTRY(0x1ed), TBL_ENTRY(0x1ee), TBL_ENTRY(0x1ef),
- TBL_ENTRY(0x1f0), TBL_ENTRY(0x1f1), TBL_ENTRY(0x1f2), TBL_ENTRY(0x1f3),
- TBL_ENTRY(0x1f4), TBL_ENTRY(0x1f5), TBL_ENTRY(0x1f6), TBL_ENTRY(0x1f7),
- TBL_ENTRY(0x1f8), TBL_ENTRY(0x1f9), TBL_ENTRY(0x1fa), TBL_ENTRY(0x1fb),
- TBL_ENTRY(0x1fc), TBL_ENTRY(0x1fd), TBL_ENTRY(0x1fe), TBL_ENTRY(0x1ff),
- TBL_ENTRY(0x200), TBL_ENTRY(0x201), TBL_ENTRY(0x202), TBL_ENTRY(0x203),
- TBL_ENTRY(0x204), TBL_ENTRY(0x205), TBL_ENTRY(0x206), TBL_ENTRY(0x207),
- TBL_ENTRY(0x208), TBL_ENTRY(0x209), TBL_ENTRY(0x20a), TBL_ENTRY(0x20b),
- TBL_ENTRY(0x20c), TBL_ENTRY(0x20d), TBL_ENTRY(0x20e), TBL_ENTRY(0x20f),
- TBL_ENTRY(0x210), TBL_ENTRY(0x211), TBL_ENTRY(0x212), TBL_ENTRY(0x213),
- TBL_ENTRY(0x214), TBL_ENTRY(0x215), TBL_ENTRY(0x216), TBL_ENTRY(0x217),
- TBL_ENTRY(0x218), TBL_ENTRY(0x219), TBL_ENTRY(0x21a), TBL_ENTRY(0x21b),
- TBL_ENTRY(0x21c), TBL_ENTRY(0x21d), TBL_ENTRY(0x21e), TBL_ENTRY(0x21f),
- TBL_ENTRY(0x220), TBL_ENTRY(0x221), TBL_ENTRY(0x222), TBL_ENTRY(0x223),
- TBL_ENTRY(0x224), TBL_ENTRY(0x225), TBL_ENTRY(0x226), TBL_ENTRY(0x227),
- TBL_ENTRY(0x228), TBL_ENTRY(0x229), TBL_ENTRY(0x22a), TBL_ENTRY(0x22b),
- TBL_ENTRY(0x22c), TBL_ENTRY(0x22d), TBL_ENTRY(0x22e), TBL_ENTRY(0x22f),
- TBL_ENTRY(0x230), TBL_ENTRY(0x231), TBL_ENTRY(0x232), TBL_ENTRY(0x233),
- TBL_ENTRY(0x234), TBL_ENTRY(0x235), TBL_ENTRY(0x236), TBL_ENTRY(0x237),
- TBL_ENTRY(0x238), TBL_ENTRY(0x239), TBL_ENTRY(0x23a), TBL_ENTRY(0x23b),
- TBL_ENTRY(0x23c), TBL_ENTRY(0x23d), TBL_ENTRY(0x23e), TBL_ENTRY(0x23f),
- TBL_ENTRY(0x240), TBL_ENTRY(0x241), TBL_ENTRY(0x242), TBL_ENTRY(0x243),
- TBL_ENTRY(0x244), TBL_ENTRY(0x245), TBL_ENTRY(0x246), TBL_ENTRY(0x247),
- TBL_ENTRY(0x248), TBL_ENTRY(0x249), TBL_ENTRY(0x24a), TBL_ENTRY(0x24b),
- TBL_ENTRY(0x24c), TBL_ENTRY(0x24d), TBL_ENTRY(0x24e), TBL_ENTRY(0x24f),
- TBL_ENTRY(0x250), TBL_ENTRY(0x251), TBL_ENTRY(0x252), TBL_ENTRY(0x253),
- TBL_ENTRY(0x254), TBL_ENTRY(0x255), TBL_ENTRY(0x256), TBL_ENTRY(0x257),
- TBL_ENTRY(0x258), TBL_ENTRY(0x259), TBL_ENTRY(0x25a), TBL_ENTRY(0x25b),
- TBL_ENTRY(0x25c), TBL_ENTRY(0x25d), TBL_ENTRY(0x25e), TBL_ENTRY(0x25f),
- TBL_ENTRY(0x260), TBL_ENTRY(0x261), TBL_ENTRY(0x262), TBL_ENTRY(0x263),
- TBL_ENTRY(0x264), TBL_ENTRY(0x265), TBL_ENTRY(0x266), TBL_ENTRY(0x267),
- TBL_ENTRY(0x268), TBL_ENTRY(0x269), TBL_ENTRY(0x26a), TBL_ENTRY(0x26b),
- TBL_ENTRY(0x26c), TBL_ENTRY(0x26d), TBL_ENTRY(0x26e), TBL_ENTRY(0x26f),
- TBL_ENTRY(0x270), TBL_ENTRY(0x271), TBL_ENTRY(0x272), TBL_ENTRY(0x273),
- TBL_ENTRY(0x274), TBL_ENTRY(0x275), TBL_ENTRY(0x276), TBL_ENTRY(0x277),
- TBL_ENTRY(0x278), TBL_ENTRY(0x279), TBL_ENTRY(0x27a), TBL_ENTRY(0x27b),
- TBL_ENTRY(0x27c), TBL_ENTRY(0x27d), TBL_ENTRY(0x27e), TBL_ENTRY(0x27f),
- TBL_ENTRY(0x280), TBL_ENTRY(0x281), TBL_ENTRY(0x282), TBL_ENTRY(0x283),
- TBL_ENTRY(0x284), TBL_ENTRY(0x285), TBL_ENTRY(0x286), TBL_ENTRY(0x287),
- TBL_ENTRY(0x288), TBL_ENTRY(0x289), TBL_ENTRY(0x28a), TBL_ENTRY(0x28b),
- TBL_ENTRY(0x28c), TBL_ENTRY(0x28d), TBL_ENTRY(0x28e), TBL_ENTRY(0x28f),
- TBL_ENTRY(0x290), TBL_ENTRY(0x291), TBL_ENTRY(0x292), TBL_ENTRY(0x293),
- TBL_ENTRY(0x294), TBL_ENTRY(0x295), TBL_ENTRY(0x296), TBL_ENTRY(0x297),
- TBL_ENTRY(0x298), TBL_ENTRY(0x299), TBL_ENTRY(0x29a), TBL_ENTRY(0x29b),
- TBL_ENTRY(0x29c), TBL_ENTRY(0x29d), TBL_ENTRY(0x29e), TBL_ENTRY(0x29f),
- TBL_ENTRY(0x2a0), TBL_ENTRY(0x2a1), TBL_ENTRY(0x2a2), TBL_ENTRY(0x2a3),
- TBL_ENTRY(0x2a4), TBL_ENTRY(0x2a5), TBL_ENTRY(0x2a6), TBL_ENTRY(0x2a7),
- TBL_ENTRY(0x2a8), TBL_ENTRY(0x2a9), TBL_ENTRY(0x2aa), TBL_ENTRY(0x2ab),
- TBL_ENTRY(0x2ac), TBL_ENTRY(0x2ad), TBL_ENTRY(0x2ae), TBL_ENTRY(0x2af),
- TBL_ENTRY(0x2b0), TBL_ENTRY(0x2b1), TBL_ENTRY(0x2b2), TBL_ENTRY(0x2b3),
- TBL_ENTRY(0x2b4), TBL_ENTRY(0x2b5), TBL_ENTRY(0x2b6), TBL_ENTRY(0x2b7),
- TBL_ENTRY(0x2b8), TBL_ENTRY(0x2b9), TBL_ENTRY(0x2ba), TBL_ENTRY(0x2bb),
- TBL_ENTRY(0x2bc), TBL_ENTRY(0x2bd), TBL_ENTRY(0x2be), TBL_ENTRY(0x2bf),
- TBL_ENTRY(0x2c0), TBL_ENTRY(0x2c1), TBL_ENTRY(0x2c2), TBL_ENTRY(0x2c3),
- TBL_ENTRY(0x2c4), TBL_ENTRY(0x2c5), TBL_ENTRY(0x2c6), TBL_ENTRY(0x2c7),
- TBL_ENTRY(0x2c8), TBL_ENTRY(0x2c9), TBL_ENTRY(0x2ca), TBL_ENTRY(0x2cb),
- TBL_ENTRY(0x2cc), TBL_ENTRY(0x2cd), TBL_ENTRY(0x2ce), TBL_ENTRY(0x2cf),
- TBL_ENTRY(0x2d0), TBL_ENTRY(0x2d1), TBL_ENTRY(0x2d2), TBL_ENTRY(0x2d3),
- TBL_ENTRY(0x2d4), TBL_ENTRY(0x2d5), TBL_ENTRY(0x2d6), TBL_ENTRY(0x2d7),
- TBL_ENTRY(0x2d8), TBL_ENTRY(0x2d9), TBL_ENTRY(0x2da), TBL_ENTRY(0x2db),
- TBL_ENTRY(0x2dc), TBL_ENTRY(0x2dd), TBL_ENTRY(0x2de), TBL_ENTRY(0x2df),
- TBL_ENTRY(0x2e0), TBL_ENTRY(0x2e1), TBL_ENTRY(0x2e2), TBL_ENTRY(0x2e3),
- TBL_ENTRY(0x2e4), TBL_ENTRY(0x2e5), TBL_ENTRY(0x2e6), TBL_ENTRY(0x2e7),
- TBL_ENTRY(0x2e8), TBL_ENTRY(0x2e9), TBL_ENTRY(0x2ea), TBL_ENTRY(0x2eb),
- TBL_ENTRY(0x2ec), TBL_ENTRY(0x2ed), TBL_ENTRY(0x2ee), TBL_ENTRY(0x2ef),
- TBL_ENTRY(0x2f0), TBL_ENTRY(0x2f1), TBL_ENTRY(0x2f2), TBL_ENTRY(0x2f3),
- TBL_ENTRY(0x2f4), TBL_ENTRY(0x2f5), TBL_ENTRY(0x2f6), TBL_ENTRY(0x2f7),
- TBL_ENTRY(0x2f8), TBL_ENTRY(0x2f9), TBL_ENTRY(0x2fa), TBL_ENTRY(0x2fb),
- TBL_ENTRY(0x2fc), TBL_ENTRY(0x2fd), TBL_ENTRY(0x2fe), TBL_ENTRY(0x2ff),
- TBL_ENTRY(0x300), TBL_ENTRY(0x301), TBL_ENTRY(0x302), TBL_ENTRY(0x303),
- TBL_ENTRY(0x304), TBL_ENTRY(0x305), TBL_ENTRY(0x306), TBL_ENTRY(0x307),
- TBL_ENTRY(0x308), TBL_ENTRY(0x309), TBL_ENTRY(0x30a), TBL_ENTRY(0x30b),
- TBL_ENTRY(0x30c), TBL_ENTRY(0x30d), TBL_ENTRY(0x30e), TBL_ENTRY(0x30f),
- TBL_ENTRY(0x310), TBL_ENTRY(0x311), TBL_ENTRY(0x312), TBL_ENTRY(0x313),
- TBL_ENTRY(0x314), TBL_ENTRY(0x315), TBL_ENTRY(0x316), TBL_ENTRY(0x317),
- TBL_ENTRY(0x318), TBL_ENTRY(0x319), TBL_ENTRY(0x31a), TBL_ENTRY(0x31b),
- TBL_ENTRY(0x31c), TBL_ENTRY(0x31d), TBL_ENTRY(0x31e), TBL_ENTRY(0x31f),
- TBL_ENTRY(0x320), TBL_ENTRY(0x321), TBL_ENTRY(0x322), TBL_ENTRY(0x323),
- TBL_ENTRY(0x324), TBL_ENTRY(0x325), TBL_ENTRY(0x326), TBL_ENTRY(0x327),
- TBL_ENTRY(0x328), TBL_ENTRY(0x329), TBL_ENTRY(0x32a), TBL_ENTRY(0x32b),
- TBL_ENTRY(0x32c), TBL_ENTRY(0x32d), TBL_ENTRY(0x32e), TBL_ENTRY(0x32f),
- TBL_ENTRY(0x330), TBL_ENTRY(0x331), TBL_ENTRY(0x332), TBL_ENTRY(0x333),
- TBL_ENTRY(0x334), TBL_ENTRY(0x335), TBL_ENTRY(0x336), TBL_ENTRY(0x337),
- TBL_ENTRY(0x338), TBL_ENTRY(0x339), TBL_ENTRY(0x33a), TBL_ENTRY(0x33b),
- TBL_ENTRY(0x33c), TBL_ENTRY(0x33d), TBL_ENTRY(0x33e), TBL_ENTRY(0x33f),
- TBL_ENTRY(0x340), TBL_ENTRY(0x341), TBL_ENTRY(0x342), TBL_ENTRY(0x343),
- TBL_ENTRY(0x344), TBL_ENTRY(0x345), TBL_ENTRY(0x346), TBL_ENTRY(0x347),
- TBL_ENTRY(0x348), TBL_ENTRY(0x349), TBL_ENTRY(0x34a), TBL_ENTRY(0x34b),
- TBL_ENTRY(0x34c), TBL_ENTRY(0x34d), TBL_ENTRY(0x34e), TBL_ENTRY(0x34f),
- TBL_ENTRY(0x350), TBL_ENTRY(0x351), TBL_ENTRY(0x352), TBL_ENTRY(0x353),
- TBL_ENTRY(0x354), TBL_ENTRY(0x355), TBL_ENTRY(0x356), TBL_ENTRY(0x357),
- TBL_ENTRY(0x358), TBL_ENTRY(0x359), TBL_ENTRY(0x35a), TBL_ENTRY(0x35b),
- TBL_ENTRY(0x35c), TBL_ENTRY(0x35d), TBL_ENTRY(0x35e), TBL_ENTRY(0x35f),
- TBL_ENTRY(0x360), TBL_ENTRY(0x361), TBL_ENTRY(0x362), TBL_ENTRY(0x363),
- TBL_ENTRY(0x364), TBL_ENTRY(0x365), TBL_ENTRY(0x366), TBL_ENTRY(0x367),
- TBL_ENTRY(0x368), TBL_ENTRY(0x369), TBL_ENTRY(0x36a), TBL_ENTRY(0x36b),
- TBL_ENTRY(0x36c), TBL_ENTRY(0x36d), TBL_ENTRY(0x36e), TBL_ENTRY(0x36f),
- TBL_ENTRY(0x370), TBL_ENTRY(0x371), TBL_ENTRY(0x372), TBL_ENTRY(0x373),
- TBL_ENTRY(0x374), TBL_ENTRY(0x375), TBL_ENTRY(0x376), TBL_ENTRY(0x377),
- TBL_ENTRY(0x378), TBL_ENTRY(0x379), TBL_ENTRY(0x37a), TBL_ENTRY(0x37b),
- TBL_ENTRY(0x37c), TBL_ENTRY(0x37d), TBL_ENTRY(0x37e), TBL_ENTRY(0x37f),
- TBL_ENTRY(0x380), TBL_ENTRY(0x381), TBL_ENTRY(0x382), TBL_ENTRY(0x383),
- TBL_ENTRY(0x384), TBL_ENTRY(0x385), TBL_ENTRY(0x386), TBL_ENTRY(0x387),
- TBL_ENTRY(0x388), TBL_ENTRY(0x389), TBL_ENTRY(0x38a), TBL_ENTRY(0x38b),
- TBL_ENTRY(0x38c), TBL_ENTRY(0x38d), TBL_ENTRY(0x38e), TBL_ENTRY(0x38f),
- TBL_ENTRY(0x390), TBL_ENTRY(0x391), TBL_ENTRY(0x392), TBL_ENTRY(0x393),
- TBL_ENTRY(0x394), TBL_ENTRY(0x395), TBL_ENTRY(0x396), TBL_ENTRY(0x397),
- TBL_ENTRY(0x398), TBL_ENTRY(0x399), TBL_ENTRY(0x39a), TBL_ENTRY(0x39b),
- TBL_ENTRY(0x39c), TBL_ENTRY(0x39d), TBL_ENTRY(0x39e), TBL_ENTRY(0x39f),
- TBL_ENTRY(0x3a0), TBL_ENTRY(0x3a1), TBL_ENTRY(0x3a2), TBL_ENTRY(0x3a3),
- TBL_ENTRY(0x3a4), TBL_ENTRY(0x3a5), TBL_ENTRY(0x3a6), TBL_ENTRY(0x3a7),
- TBL_ENTRY(0x3a8), TBL_ENTRY(0x3a9), TBL_ENTRY(0x3aa), TBL_ENTRY(0x3ab),
- TBL_ENTRY(0x3ac), TBL_ENTRY(0x3ad), TBL_ENTRY(0x3ae), TBL_ENTRY(0x3af),
- TBL_ENTRY(0x3b0), TBL_ENTRY(0x3b1), TBL_ENTRY(0x3b2), TBL_ENTRY(0x3b3),
- TBL_ENTRY(0x3b4), TBL_ENTRY(0x3b5), TBL_ENTRY(0x3b6), TBL_ENTRY(0x3b7),
- TBL_ENTRY(0x3b8), TBL_ENTRY(0x3b9), TBL_ENTRY(0x3ba), TBL_ENTRY(0x3bb),
- TBL_ENTRY(0x3bc), TBL_ENTRY(0x3bd), TBL_ENTRY(0x3be), TBL_ENTRY(0x3bf),
- TBL_ENTRY(0x3c0), TBL_ENTRY(0x3c1), TBL_ENTRY(0x3c2), TBL_ENTRY(0x3c3),
- TBL_ENTRY(0x3c4), TBL_ENTRY(0x3c5), TBL_ENTRY(0x3c6), TBL_ENTRY(0x3c7),
- TBL_ENTRY(0x3c8), TBL_ENTRY(0x3c9), TBL_ENTRY(0x3ca), TBL_ENTRY(0x3cb),
- TBL_ENTRY(0x3cc), TBL_ENTRY(0x3cd), TBL_ENTRY(0x3ce), TBL_ENTRY(0x3cf),
- TBL_ENTRY(0x3d0), TBL_ENTRY(0x3d1), TBL_ENTRY(0x3d2), TBL_ENTRY(0x3d3),
- TBL_ENTRY(0x3d4), TBL_ENTRY(0x3d5), TBL_ENTRY(0x3d6), TBL_ENTRY(0x3d7),
- TBL_ENTRY(0x3d8), TBL_ENTRY(0x3d9), TBL_ENTRY(0x3da), TBL_ENTRY(0x3db),
- TBL_ENTRY(0x3dc), TBL_ENTRY(0x3dd), TBL_ENTRY(0x3de), TBL_ENTRY(0x3df),
- TBL_ENTRY(0x3e0), TBL_ENTRY(0x3e1), TBL_ENTRY(0x3e2), TBL_ENTRY(0x3e3),
- TBL_ENTRY(0x3e4), TBL_ENTRY(0x3e5), TBL_ENTRY(0x3e6), TBL_ENTRY(0x3e7),
- TBL_ENTRY(0x3e8), TBL_ENTRY(0x3e9), TBL_ENTRY(0x3ea), TBL_ENTRY(0x3eb),
- TBL_ENTRY(0x3ec), TBL_ENTRY(0x3ed), TBL_ENTRY(0x3ee), TBL_ENTRY(0x3ef),
- TBL_ENTRY(0x3f0), TBL_ENTRY(0x3f1), TBL_ENTRY(0x3f2), TBL_ENTRY(0x3f3),
- TBL_ENTRY(0x3f4), TBL_ENTRY(0x3f5), TBL_ENTRY(0x3f6), TBL_ENTRY(0x3f7),
- TBL_ENTRY(0x3f8), TBL_ENTRY(0x3f9), TBL_ENTRY(0x3fa), TBL_ENTRY(0x3fb),
- TBL_ENTRY(0x3fc), TBL_ENTRY(0x3fd), TBL_ENTRY(0x3fe), TBL_ENTRY(0x3ff),
- TBL_ENTRY(0x400), TBL_ENTRY(0x401), TBL_ENTRY(0x402), TBL_ENTRY(0x403),
- TBL_ENTRY(0x404), TBL_ENTRY(0x405), TBL_ENTRY(0x406), TBL_ENTRY(0x407),
- TBL_ENTRY(0x408), TBL_ENTRY(0x409), TBL_ENTRY(0x40a), TBL_ENTRY(0x40b),
- TBL_ENTRY(0x40c), TBL_ENTRY(0x40d), TBL_ENTRY(0x40e), TBL_ENTRY(0x40f),
- TBL_ENTRY(0x410), TBL_ENTRY(0x411), TBL_ENTRY(0x412), TBL_ENTRY(0x413),
- TBL_ENTRY(0x414), TBL_ENTRY(0x415), TBL_ENTRY(0x416), TBL_ENTRY(0x417),
- TBL_ENTRY(0x418), TBL_ENTRY(0x419), TBL_ENTRY(0x41a), TBL_ENTRY(0x41b),
- TBL_ENTRY(0x41c), TBL_ENTRY(0x41d), TBL_ENTRY(0x41e), TBL_ENTRY(0x41f),
- TBL_ENTRY(0x420), TBL_ENTRY(0x421), TBL_ENTRY(0x422), TBL_ENTRY(0x423),
- TBL_ENTRY(0x424), TBL_ENTRY(0x425), TBL_ENTRY(0x426), TBL_ENTRY(0x427),
- TBL_ENTRY(0x428), TBL_ENTRY(0x429), TBL_ENTRY(0x42a), TBL_ENTRY(0x42b),
- TBL_ENTRY(0x42c), TBL_ENTRY(0x42d), TBL_ENTRY(0x42e), TBL_ENTRY(0x42f),
- TBL_ENTRY(0x430), TBL_ENTRY(0x431), TBL_ENTRY(0x432), TBL_ENTRY(0x433),
- TBL_ENTRY(0x434), TBL_ENTRY(0x435), TBL_ENTRY(0x436), TBL_ENTRY(0x437),
- TBL_ENTRY(0x438), TBL_ENTRY(0x439), TBL_ENTRY(0x43a), TBL_ENTRY(0x43b),
- TBL_ENTRY(0x43c), TBL_ENTRY(0x43d), TBL_ENTRY(0x43e), TBL_ENTRY(0x43f),
- TBL_ENTRY(0x440), TBL_ENTRY(0x441), TBL_ENTRY(0x442), TBL_ENTRY(0x443),
- TBL_ENTRY(0x444), TBL_ENTRY(0x445), TBL_ENTRY(0x446), TBL_ENTRY(0x447),
- TBL_ENTRY(0x448), TBL_ENTRY(0x449), TBL_ENTRY(0x44a), TBL_ENTRY(0x44b),
- TBL_ENTRY(0x44c), TBL_ENTRY(0x44d), TBL_ENTRY(0x44e), TBL_ENTRY(0x44f),
- TBL_ENTRY(0x450), TBL_ENTRY(0x451), TBL_ENTRY(0x452), TBL_ENTRY(0x453),
- TBL_ENTRY(0x454), TBL_ENTRY(0x455), TBL_ENTRY(0x456), TBL_ENTRY(0x457),
- TBL_ENTRY(0x458), TBL_ENTRY(0x459), TBL_ENTRY(0x45a), TBL_ENTRY(0x45b),
- TBL_ENTRY(0x45c), TBL_ENTRY(0x45d), TBL_ENTRY(0x45e), TBL_ENTRY(0x45f),
- TBL_ENTRY(0x460), TBL_ENTRY(0x461), TBL_ENTRY(0x462), TBL_ENTRY(0x463),
- TBL_ENTRY(0x464), TBL_ENTRY(0x465), TBL_ENTRY(0x466), TBL_ENTRY(0x467),
- TBL_ENTRY(0x468), TBL_ENTRY(0x469), TBL_ENTRY(0x46a), TBL_ENTRY(0x46b),
- TBL_ENTRY(0x46c), TBL_ENTRY(0x46d), TBL_ENTRY(0x46e), TBL_ENTRY(0x46f),
- TBL_ENTRY(0x470), TBL_ENTRY(0x471), TBL_ENTRY(0x472), TBL_ENTRY(0x473),
- TBL_ENTRY(0x474), TBL_ENTRY(0x475), TBL_ENTRY(0x476), TBL_ENTRY(0x477),
- TBL_ENTRY(0x478), TBL_ENTRY(0x479), TBL_ENTRY(0x47a), TBL_ENTRY(0x47b),
- TBL_ENTRY(0x47c), TBL_ENTRY(0x47d), TBL_ENTRY(0x47e), TBL_ENTRY(0x47f),
- TBL_ENTRY(0x480), TBL_ENTRY(0x481), TBL_ENTRY(0x482), TBL_ENTRY(0x483),
- TBL_ENTRY(0x484), TBL_ENTRY(0x485), TBL_ENTRY(0x486), TBL_ENTRY(0x487),
- TBL_ENTRY(0x488), TBL_ENTRY(0x489), TBL_ENTRY(0x48a), TBL_ENTRY(0x48b),
- TBL_ENTRY(0x48c), TBL_ENTRY(0x48d), TBL_ENTRY(0x48e), TBL_ENTRY(0x48f),
- TBL_ENTRY(0x490), TBL_ENTRY(0x491), TBL_ENTRY(0x492), TBL_ENTRY(0x493),
- TBL_ENTRY(0x494), TBL_ENTRY(0x495), TBL_ENTRY(0x496), TBL_ENTRY(0x497),
- TBL_ENTRY(0x498), TBL_ENTRY(0x499), TBL_ENTRY(0x49a), TBL_ENTRY(0x49b),
- TBL_ENTRY(0x49c), TBL_ENTRY(0x49d), TBL_ENTRY(0x49e), TBL_ENTRY(0x49f),
- TBL_ENTRY(0x4a0), TBL_ENTRY(0x4a1), TBL_ENTRY(0x4a2), TBL_ENTRY(0x4a3),
- TBL_ENTRY(0x4a4), TBL_ENTRY(0x4a5), TBL_ENTRY(0x4a6), TBL_ENTRY(0x4a7),
- TBL_ENTRY(0x4a8), TBL_ENTRY(0x4a9), TBL_ENTRY(0x4aa), TBL_ENTRY(0x4ab),
- TBL_ENTRY(0x4ac), TBL_ENTRY(0x4ad), TBL_ENTRY(0x4ae), TBL_ENTRY(0x4af),
- TBL_ENTRY(0x4b0), TBL_ENTRY(0x4b1), TBL_ENTRY(0x4b2), TBL_ENTRY(0x4b3),
- TBL_ENTRY(0x4b4), TBL_ENTRY(0x4b5), TBL_ENTRY(0x4b6), TBL_ENTRY(0x4b7),
- TBL_ENTRY(0x4b8), TBL_ENTRY(0x4b9), TBL_ENTRY(0x4ba), TBL_ENTRY(0x4bb),
- TBL_ENTRY(0x4bc), TBL_ENTRY(0x4bd), TBL_ENTRY(0x4be), TBL_ENTRY(0x4bf),
- TBL_ENTRY(0x4c0), TBL_ENTRY(0x4c1), TBL_ENTRY(0x4c2), TBL_ENTRY(0x4c3),
- TBL_ENTRY(0x4c4), TBL_ENTRY(0x4c5), TBL_ENTRY(0x4c6), TBL_ENTRY(0x4c7),
- TBL_ENTRY(0x4c8), TBL_ENTRY(0x4c9), TBL_ENTRY(0x4ca), TBL_ENTRY(0x4cb),
- TBL_ENTRY(0x4cc), TBL_ENTRY(0x4cd), TBL_ENTRY(0x4ce), TBL_ENTRY(0x4cf),
- TBL_ENTRY(0x4d0), TBL_ENTRY(0x4d1), TBL_ENTRY(0x4d2), TBL_ENTRY(0x4d3),
- TBL_ENTRY(0x4d4), TBL_ENTRY(0x4d5), TBL_ENTRY(0x4d6), TBL_ENTRY(0x4d7),
- TBL_ENTRY(0x4d8), TBL_ENTRY(0x4d9), TBL_ENTRY(0x4da), TBL_ENTRY(0x4db),
- TBL_ENTRY(0x4dc), TBL_ENTRY(0x4dd), TBL_ENTRY(0x4de), TBL_ENTRY(0x4df),
- TBL_ENTRY(0x4e0), TBL_ENTRY(0x4e1), TBL_ENTRY(0x4e2), TBL_ENTRY(0x4e3),
- TBL_ENTRY(0x4e4), TBL_ENTRY(0x4e5), TBL_ENTRY(0x4e6), TBL_ENTRY(0x4e7),
- TBL_ENTRY(0x4e8), TBL_ENTRY(0x4e9), TBL_ENTRY(0x4ea), TBL_ENTRY(0x4eb),
- TBL_ENTRY(0x4ec), TBL_ENTRY(0x4ed), TBL_ENTRY(0x4ee), TBL_ENTRY(0x4ef),
- TBL_ENTRY(0x4f0), TBL_ENTRY(0x4f1), TBL_ENTRY(0x4f2), TBL_ENTRY(0x4f3),
- TBL_ENTRY(0x4f4), TBL_ENTRY(0x4f5), TBL_ENTRY(0x4f6), TBL_ENTRY(0x4f7),
- TBL_ENTRY(0x4f8), TBL_ENTRY(0x4f9), TBL_ENTRY(0x4fa), TBL_ENTRY(0x4fb),
- TBL_ENTRY(0x4fc), TBL_ENTRY(0x4fd), TBL_ENTRY(0x4fe), TBL_ENTRY(0x4ff),
- TBL_ENTRY(0x500), TBL_ENTRY(0x501), TBL_ENTRY(0x502), TBL_ENTRY(0x503),
- TBL_ENTRY(0x504), TBL_ENTRY(0x505), TBL_ENTRY(0x506), TBL_ENTRY(0x507),
- TBL_ENTRY(0x508), TBL_ENTRY(0x509), TBL_ENTRY(0x50a), TBL_ENTRY(0x50b),
- TBL_ENTRY(0x50c), TBL_ENTRY(0x50d), TBL_ENTRY(0x50e), TBL_ENTRY(0x50f),
- TBL_ENTRY(0x510), TBL_ENTRY(0x511), TBL_ENTRY(0x512), TBL_ENTRY(0x513),
- TBL_ENTRY(0x514), TBL_ENTRY(0x515), TBL_ENTRY(0x516), TBL_ENTRY(0x517),
- TBL_ENTRY(0x518), TBL_ENTRY(0x519), TBL_ENTRY(0x51a), TBL_ENTRY(0x51b),
- TBL_ENTRY(0x51c), TBL_ENTRY(0x51d), TBL_ENTRY(0x51e), TBL_ENTRY(0x51f),
- TBL_ENTRY(0x520), TBL_ENTRY(0x521), TBL_ENTRY(0x522), TBL_ENTRY(0x523),
- TBL_ENTRY(0x524), TBL_ENTRY(0x525), TBL_ENTRY(0x526), TBL_ENTRY(0x527),
- TBL_ENTRY(0x528), TBL_ENTRY(0x529), TBL_ENTRY(0x52a), TBL_ENTRY(0x52b),
- TBL_ENTRY(0x52c), TBL_ENTRY(0x52d), TBL_ENTRY(0x52e), TBL_ENTRY(0x52f),
- TBL_ENTRY(0x530), TBL_ENTRY(0x531), TBL_ENTRY(0x532), TBL_ENTRY(0x533),
- TBL_ENTRY(0x534), TBL_ENTRY(0x535), TBL_ENTRY(0x536), TBL_ENTRY(0x537),
- TBL_ENTRY(0x538), TBL_ENTRY(0x539), TBL_ENTRY(0x53a), TBL_ENTRY(0x53b),
- TBL_ENTRY(0x53c), TBL_ENTRY(0x53d), TBL_ENTRY(0x53e), TBL_ENTRY(0x53f),
- TBL_ENTRY(0x540), TBL_ENTRY(0x541), TBL_ENTRY(0x542), TBL_ENTRY(0x543),
- TBL_ENTRY(0x544), TBL_ENTRY(0x545), TBL_ENTRY(0x546), TBL_ENTRY(0x547),
- TBL_ENTRY(0x548), TBL_ENTRY(0x549), TBL_ENTRY(0x54a), TBL_ENTRY(0x54b),
- TBL_ENTRY(0x54c), TBL_ENTRY(0x54d), TBL_ENTRY(0x54e), TBL_ENTRY(0x54f),
- TBL_ENTRY(0x550), TBL_ENTRY(0x551), TBL_ENTRY(0x552), TBL_ENTRY(0x553),
- TBL_ENTRY(0x554), TBL_ENTRY(0x555), TBL_ENTRY(0x556), TBL_ENTRY(0x557),
- TBL_ENTRY(0x558), TBL_ENTRY(0x559), TBL_ENTRY(0x55a), TBL_ENTRY(0x55b),
- TBL_ENTRY(0x55c), TBL_ENTRY(0x55d), TBL_ENTRY(0x55e), TBL_ENTRY(0x55f),
- TBL_ENTRY(0x560), TBL_ENTRY(0x561), TBL_ENTRY(0x562), TBL_ENTRY(0x563),
- TBL_ENTRY(0x564), TBL_ENTRY(0x565), TBL_ENTRY(0x566), TBL_ENTRY(0x567),
- TBL_ENTRY(0x568), TBL_ENTRY(0x569), TBL_ENTRY(0x56a), TBL_ENTRY(0x56b),
- TBL_ENTRY(0x56c), TBL_ENTRY(0x56d), TBL_ENTRY(0x56e), TBL_ENTRY(0x56f),
- TBL_ENTRY(0x570), TBL_ENTRY(0x571), TBL_ENTRY(0x572), TBL_ENTRY(0x573),
- TBL_ENTRY(0x574), TBL_ENTRY(0x575), TBL_ENTRY(0x576), TBL_ENTRY(0x577),
- TBL_ENTRY(0x578), TBL_ENTRY(0x579), TBL_ENTRY(0x57a), TBL_ENTRY(0x57b),
- TBL_ENTRY(0x57c), TBL_ENTRY(0x57d), TBL_ENTRY(0x57e), TBL_ENTRY(0x57f),
- TBL_ENTRY(0x580), TBL_ENTRY(0x581), TBL_ENTRY(0x582), TBL_ENTRY(0x583),
- TBL_ENTRY(0x584), TBL_ENTRY(0x585), TBL_ENTRY(0x586), TBL_ENTRY(0x587),
- TBL_ENTRY(0x588), TBL_ENTRY(0x589), TBL_ENTRY(0x58a), TBL_ENTRY(0x58b),
- TBL_ENTRY(0x58c), TBL_ENTRY(0x58d), TBL_ENTRY(0x58e), TBL_ENTRY(0x58f),
- TBL_ENTRY(0x590), TBL_ENTRY(0x591), TBL_ENTRY(0x592), TBL_ENTRY(0x593),
- TBL_ENTRY(0x594), TBL_ENTRY(0x595), TBL_ENTRY(0x596), TBL_ENTRY(0x597),
- TBL_ENTRY(0x598), TBL_ENTRY(0x599), TBL_ENTRY(0x59a), TBL_ENTRY(0x59b),
- TBL_ENTRY(0x59c), TBL_ENTRY(0x59d), TBL_ENTRY(0x59e), TBL_ENTRY(0x59f),
- TBL_ENTRY(0x5a0), TBL_ENTRY(0x5a1), TBL_ENTRY(0x5a2), TBL_ENTRY(0x5a3),
- TBL_ENTRY(0x5a4), TBL_ENTRY(0x5a5), TBL_ENTRY(0x5a6), TBL_ENTRY(0x5a7),
- TBL_ENTRY(0x5a8), TBL_ENTRY(0x5a9), TBL_ENTRY(0x5aa), TBL_ENTRY(0x5ab),
- TBL_ENTRY(0x5ac), TBL_ENTRY(0x5ad), TBL_ENTRY(0x5ae), TBL_ENTRY(0x5af),
- TBL_ENTRY(0x5b0), TBL_ENTRY(0x5b1), TBL_ENTRY(0x5b2), TBL_ENTRY(0x5b3),
- TBL_ENTRY(0x5b4), TBL_ENTRY(0x5b5), TBL_ENTRY(0x5b6), TBL_ENTRY(0x5b7),
- TBL_ENTRY(0x5b8), TBL_ENTRY(0x5b9), TBL_ENTRY(0x5ba), TBL_ENTRY(0x5bb),
- TBL_ENTRY(0x5bc), TBL_ENTRY(0x5bd), TBL_ENTRY(0x5be), TBL_ENTRY(0x5bf),
- TBL_ENTRY(0x5c0), TBL_ENTRY(0x5c1), TBL_ENTRY(0x5c2), TBL_ENTRY(0x5c3),
- TBL_ENTRY(0x5c4), TBL_ENTRY(0x5c5), TBL_ENTRY(0x5c6), TBL_ENTRY(0x5c7),
- TBL_ENTRY(0x5c8), TBL_ENTRY(0x5c9), TBL_ENTRY(0x5ca), TBL_ENTRY(0x5cb),
- TBL_ENTRY(0x5cc), TBL_ENTRY(0x5cd), TBL_ENTRY(0x5ce), TBL_ENTRY(0x5cf),
- TBL_ENTRY(0x5d0), TBL_ENTRY(0x5d1), TBL_ENTRY(0x5d2), TBL_ENTRY(0x5d3),
- TBL_ENTRY(0x5d4), TBL_ENTRY(0x5d5), TBL_ENTRY(0x5d6), TBL_ENTRY(0x5d7),
- TBL_ENTRY(0x5d8), TBL_ENTRY(0x5d9), TBL_ENTRY(0x5da), TBL_ENTRY(0x5db),
- TBL_ENTRY(0x5dc), TBL_ENTRY(0x5dd), TBL_ENTRY(0x5de), TBL_ENTRY(0x5df),
- TBL_ENTRY(0x5e0), TBL_ENTRY(0x5e1), TBL_ENTRY(0x5e2), TBL_ENTRY(0x5e3),
- TBL_ENTRY(0x5e4), TBL_ENTRY(0x5e5), TBL_ENTRY(0x5e6), TBL_ENTRY(0x5e7),
- TBL_ENTRY(0x5e8), TBL_ENTRY(0x5e9), TBL_ENTRY(0x5ea), TBL_ENTRY(0x5eb),
- TBL_ENTRY(0x5ec), TBL_ENTRY(0x5ed), TBL_ENTRY(0x5ee), TBL_ENTRY(0x5ef),
- TBL_ENTRY(0x5f0), TBL_ENTRY(0x5f1), TBL_ENTRY(0x5f2), TBL_ENTRY(0x5f3),
- TBL_ENTRY(0x5f4), TBL_ENTRY(0x5f5), TBL_ENTRY(0x5f6), TBL_ENTRY(0x5f7),
- TBL_ENTRY(0x5f8), TBL_ENTRY(0x5f9), TBL_ENTRY(0x5fa), TBL_ENTRY(0x5fb),
- TBL_ENTRY(0x5fc), TBL_ENTRY(0x5fd), TBL_ENTRY(0x5fe), TBL_ENTRY(0x5ff),
- TBL_ENTRY(0x600), TBL_ENTRY(0x601), TBL_ENTRY(0x602), TBL_ENTRY(0x603),
- TBL_ENTRY(0x604), TBL_ENTRY(0x605), TBL_ENTRY(0x606), TBL_ENTRY(0x607),
- TBL_ENTRY(0x608), TBL_ENTRY(0x609), TBL_ENTRY(0x60a), TBL_ENTRY(0x60b),
- TBL_ENTRY(0x60c), TBL_ENTRY(0x60d), TBL_ENTRY(0x60e), TBL_ENTRY(0x60f),
- TBL_ENTRY(0x610), TBL_ENTRY(0x611), TBL_ENTRY(0x612), TBL_ENTRY(0x613),
- TBL_ENTRY(0x614), TBL_ENTRY(0x615), TBL_ENTRY(0x616), TBL_ENTRY(0x617),
- TBL_ENTRY(0x618), TBL_ENTRY(0x619), TBL_ENTRY(0x61a), TBL_ENTRY(0x61b),
- TBL_ENTRY(0x61c), TBL_ENTRY(0x61d), TBL_ENTRY(0x61e), TBL_ENTRY(0x61f),
- TBL_ENTRY(0x620), TBL_ENTRY(0x621), TBL_ENTRY(0x622), TBL_ENTRY(0x623),
- TBL_ENTRY(0x624), TBL_ENTRY(0x625), TBL_ENTRY(0x626), TBL_ENTRY(0x627),
- TBL_ENTRY(0x628), TBL_ENTRY(0x629), TBL_ENTRY(0x62a), TBL_ENTRY(0x62b),
- TBL_ENTRY(0x62c), TBL_ENTRY(0x62d), TBL_ENTRY(0x62e), TBL_ENTRY(0x62f),
- TBL_ENTRY(0x630), TBL_ENTRY(0x631), TBL_ENTRY(0x632), TBL_ENTRY(0x633),
- TBL_ENTRY(0x634), TBL_ENTRY(0x635), TBL_ENTRY(0x636), TBL_ENTRY(0x637),
- TBL_ENTRY(0x638), TBL_ENTRY(0x639), TBL_ENTRY(0x63a), TBL_ENTRY(0x63b),
- TBL_ENTRY(0x63c), TBL_ENTRY(0x63d), TBL_ENTRY(0x63e), TBL_ENTRY(0x63f),
- TBL_ENTRY(0x640), TBL_ENTRY(0x641), TBL_ENTRY(0x642), TBL_ENTRY(0x643),
- TBL_ENTRY(0x644), TBL_ENTRY(0x645), TBL_ENTRY(0x646), TBL_ENTRY(0x647),
- TBL_ENTRY(0x648), TBL_ENTRY(0x649), TBL_ENTRY(0x64a), TBL_ENTRY(0x64b),
- TBL_ENTRY(0x64c), TBL_ENTRY(0x64d), TBL_ENTRY(0x64e), TBL_ENTRY(0x64f),
- TBL_ENTRY(0x650), TBL_ENTRY(0x651), TBL_ENTRY(0x652), TBL_ENTRY(0x653),
- TBL_ENTRY(0x654), TBL_ENTRY(0x655), TBL_ENTRY(0x656), TBL_ENTRY(0x657),
- TBL_ENTRY(0x658), TBL_ENTRY(0x659), TBL_ENTRY(0x65a), TBL_ENTRY(0x65b),
- TBL_ENTRY(0x65c), TBL_ENTRY(0x65d), TBL_ENTRY(0x65e), TBL_ENTRY(0x65f),
- TBL_ENTRY(0x660), TBL_ENTRY(0x661), TBL_ENTRY(0x662), TBL_ENTRY(0x663),
- TBL_ENTRY(0x664), TBL_ENTRY(0x665), TBL_ENTRY(0x666), TBL_ENTRY(0x667),
- TBL_ENTRY(0x668), TBL_ENTRY(0x669), TBL_ENTRY(0x66a), TBL_ENTRY(0x66b),
- TBL_ENTRY(0x66c), TBL_ENTRY(0x66d), TBL_ENTRY(0x66e), TBL_ENTRY(0x66f),
- TBL_ENTRY(0x670), TBL_ENTRY(0x671), TBL_ENTRY(0x672), TBL_ENTRY(0x673),
- TBL_ENTRY(0x674), TBL_ENTRY(0x675), TBL_ENTRY(0x676), TBL_ENTRY(0x677),
- TBL_ENTRY(0x678), TBL_ENTRY(0x679), TBL_ENTRY(0x67a), TBL_ENTRY(0x67b),
- TBL_ENTRY(0x67c), TBL_ENTRY(0x67d), TBL_ENTRY(0x67e), TBL_ENTRY(0x67f),
- TBL_ENTRY(0x680), TBL_ENTRY(0x681), TBL_ENTRY(0x682), TBL_ENTRY(0x683),
- TBL_ENTRY(0x684), TBL_ENTRY(0x685), TBL_ENTRY(0x686), TBL_ENTRY(0x687),
- TBL_ENTRY(0x688), TBL_ENTRY(0x689), TBL_ENTRY(0x68a), TBL_ENTRY(0x68b),
- TBL_ENTRY(0x68c), TBL_ENTRY(0x68d), TBL_ENTRY(0x68e), TBL_ENTRY(0x68f),
- TBL_ENTRY(0x690), TBL_ENTRY(0x691), TBL_ENTRY(0x692), TBL_ENTRY(0x693),
- TBL_ENTRY(0x694), TBL_ENTRY(0x695), TBL_ENTRY(0x696), TBL_ENTRY(0x697),
- TBL_ENTRY(0x698), TBL_ENTRY(0x699), TBL_ENTRY(0x69a), TBL_ENTRY(0x69b),
- TBL_ENTRY(0x69c), TBL_ENTRY(0x69d), TBL_ENTRY(0x69e), TBL_ENTRY(0x69f),
- TBL_ENTRY(0x6a0), TBL_ENTRY(0x6a1), TBL_ENTRY(0x6a2), TBL_ENTRY(0x6a3),
- TBL_ENTRY(0x6a4), TBL_ENTRY(0x6a5), TBL_ENTRY(0x6a6), TBL_ENTRY(0x6a7),
- TBL_ENTRY(0x6a8), TBL_ENTRY(0x6a9), TBL_ENTRY(0x6aa), TBL_ENTRY(0x6ab),
- TBL_ENTRY(0x6ac), TBL_ENTRY(0x6ad), TBL_ENTRY(0x6ae), TBL_ENTRY(0x6af),
- TBL_ENTRY(0x6b0), TBL_ENTRY(0x6b1), TBL_ENTRY(0x6b2), TBL_ENTRY(0x6b3),
- TBL_ENTRY(0x6b4), TBL_ENTRY(0x6b5), TBL_ENTRY(0x6b6), TBL_ENTRY(0x6b7),
- TBL_ENTRY(0x6b8), TBL_ENTRY(0x6b9), TBL_ENTRY(0x6ba), TBL_ENTRY(0x6bb),
- TBL_ENTRY(0x6bc), TBL_ENTRY(0x6bd), TBL_ENTRY(0x6be), TBL_ENTRY(0x6bf),
- TBL_ENTRY(0x6c0), TBL_ENTRY(0x6c1), TBL_ENTRY(0x6c2), TBL_ENTRY(0x6c3),
- TBL_ENTRY(0x6c4), TBL_ENTRY(0x6c5), TBL_ENTRY(0x6c6), TBL_ENTRY(0x6c7),
- TBL_ENTRY(0x6c8), TBL_ENTRY(0x6c9), TBL_ENTRY(0x6ca), TBL_ENTRY(0x6cb),
- TBL_ENTRY(0x6cc), TBL_ENTRY(0x6cd), TBL_ENTRY(0x6ce), TBL_ENTRY(0x6cf),
- TBL_ENTRY(0x6d0), TBL_ENTRY(0x6d1), TBL_ENTRY(0x6d2), TBL_ENTRY(0x6d3),
- TBL_ENTRY(0x6d4), TBL_ENTRY(0x6d5), TBL_ENTRY(0x6d6), TBL_ENTRY(0x6d7),
- TBL_ENTRY(0x6d8), TBL_ENTRY(0x6d9), TBL_ENTRY(0x6da), TBL_ENTRY(0x6db),
- TBL_ENTRY(0x6dc), TBL_ENTRY(0x6dd), TBL_ENTRY(0x6de), TBL_ENTRY(0x6df),
- TBL_ENTRY(0x6e0), TBL_ENTRY(0x6e1), TBL_ENTRY(0x6e2), TBL_ENTRY(0x6e3),
- TBL_ENTRY(0x6e4), TBL_ENTRY(0x6e5), TBL_ENTRY(0x6e6), TBL_ENTRY(0x6e7),
- TBL_ENTRY(0x6e8), TBL_ENTRY(0x6e9), TBL_ENTRY(0x6ea), TBL_ENTRY(0x6eb),
- TBL_ENTRY(0x6ec), TBL_ENTRY(0x6ed), TBL_ENTRY(0x6ee), TBL_ENTRY(0x6ef),
- TBL_ENTRY(0x6f0), TBL_ENTRY(0x6f1), TBL_ENTRY(0x6f2), TBL_ENTRY(0x6f3),
- TBL_ENTRY(0x6f4), TBL_ENTRY(0x6f5), TBL_ENTRY(0x6f6), TBL_ENTRY(0x6f7),
- TBL_ENTRY(0x6f8), TBL_ENTRY(0x6f9), TBL_ENTRY(0x6fa), TBL_ENTRY(0x6fb),
- TBL_ENTRY(0x6fc), TBL_ENTRY(0x6fd), TBL_ENTRY(0x6fe), TBL_ENTRY(0x6ff),
- TBL_ENTRY(0x700), TBL_ENTRY(0x701), TBL_ENTRY(0x702), TBL_ENTRY(0x703),
- TBL_ENTRY(0x704), TBL_ENTRY(0x705), TBL_ENTRY(0x706), TBL_ENTRY(0x707),
- TBL_ENTRY(0x708), TBL_ENTRY(0x709), TBL_ENTRY(0x70a), TBL_ENTRY(0x70b),
- TBL_ENTRY(0x70c), TBL_ENTRY(0x70d), TBL_ENTRY(0x70e), TBL_ENTRY(0x70f),
- TBL_ENTRY(0x710), TBL_ENTRY(0x711), TBL_ENTRY(0x712), TBL_ENTRY(0x713),
- TBL_ENTRY(0x714), TBL_ENTRY(0x715), TBL_ENTRY(0x716), TBL_ENTRY(0x717),
- TBL_ENTRY(0x718), TBL_ENTRY(0x719), TBL_ENTRY(0x71a), TBL_ENTRY(0x71b),
- TBL_ENTRY(0x71c), TBL_ENTRY(0x71d), TBL_ENTRY(0x71e), TBL_ENTRY(0x71f),
- TBL_ENTRY(0x720), TBL_ENTRY(0x721), TBL_ENTRY(0x722), TBL_ENTRY(0x723),
- TBL_ENTRY(0x724), TBL_ENTRY(0x725), TBL_ENTRY(0x726), TBL_ENTRY(0x727),
- TBL_ENTRY(0x728), TBL_ENTRY(0x729), TBL_ENTRY(0x72a), TBL_ENTRY(0x72b),
- TBL_ENTRY(0x72c), TBL_ENTRY(0x72d), TBL_ENTRY(0x72e), TBL_ENTRY(0x72f),
- TBL_ENTRY(0x730), TBL_ENTRY(0x731), TBL_ENTRY(0x732), TBL_ENTRY(0x733),
- TBL_ENTRY(0x734), TBL_ENTRY(0x735), TBL_ENTRY(0x736), TBL_ENTRY(0x737),
- TBL_ENTRY(0x738), TBL_ENTRY(0x739), TBL_ENTRY(0x73a), TBL_ENTRY(0x73b),
- TBL_ENTRY(0x73c), TBL_ENTRY(0x73d), TBL_ENTRY(0x73e), TBL_ENTRY(0x73f),
- TBL_ENTRY(0x740), TBL_ENTRY(0x741), TBL_ENTRY(0x742), TBL_ENTRY(0x743),
- TBL_ENTRY(0x744), TBL_ENTRY(0x745), TBL_ENTRY(0x746), TBL_ENTRY(0x747),
- TBL_ENTRY(0x748), TBL_ENTRY(0x749), TBL_ENTRY(0x74a), TBL_ENTRY(0x74b),
- TBL_ENTRY(0x74c), TBL_ENTRY(0x74d), TBL_ENTRY(0x74e), TBL_ENTRY(0x74f),
- TBL_ENTRY(0x750), TBL_ENTRY(0x751), TBL_ENTRY(0x752), TBL_ENTRY(0x753),
- TBL_ENTRY(0x754), TBL_ENTRY(0x755), TBL_ENTRY(0x756), TBL_ENTRY(0x757),
- TBL_ENTRY(0x758), TBL_ENTRY(0x759), TBL_ENTRY(0x75a), TBL_ENTRY(0x75b),
- TBL_ENTRY(0x75c), TBL_ENTRY(0x75d), TBL_ENTRY(0x75e), TBL_ENTRY(0x75f),
- TBL_ENTRY(0x760), TBL_ENTRY(0x761), TBL_ENTRY(0x762), TBL_ENTRY(0x763),
- TBL_ENTRY(0x764), TBL_ENTRY(0x765), TBL_ENTRY(0x766), TBL_ENTRY(0x767),
- TBL_ENTRY(0x768), TBL_ENTRY(0x769), TBL_ENTRY(0x76a), TBL_ENTRY(0x76b),
- TBL_ENTRY(0x76c), TBL_ENTRY(0x76d), TBL_ENTRY(0x76e), TBL_ENTRY(0x76f),
- TBL_ENTRY(0x770), TBL_ENTRY(0x771), TBL_ENTRY(0x772), TBL_ENTRY(0x773),
- TBL_ENTRY(0x774), TBL_ENTRY(0x775), TBL_ENTRY(0x776), TBL_ENTRY(0x777),
- TBL_ENTRY(0x778), TBL_ENTRY(0x779), TBL_ENTRY(0x77a), TBL_ENTRY(0x77b),
- TBL_ENTRY(0x77c), TBL_ENTRY(0x77d), TBL_ENTRY(0x77e), TBL_ENTRY(0x77f),
- TBL_ENTRY(0x780), TBL_ENTRY(0x781), TBL_ENTRY(0x782), TBL_ENTRY(0x783),
- TBL_ENTRY(0x784), TBL_ENTRY(0x785), TBL_ENTRY(0x786), TBL_ENTRY(0x787),
- TBL_ENTRY(0x788), TBL_ENTRY(0x789), TBL_ENTRY(0x78a), TBL_ENTRY(0x78b),
- TBL_ENTRY(0x78c), TBL_ENTRY(0x78d), TBL_ENTRY(0x78e), TBL_ENTRY(0x78f),
- TBL_ENTRY(0x790), TBL_ENTRY(0x791), TBL_ENTRY(0x792), TBL_ENTRY(0x793),
- TBL_ENTRY(0x794), TBL_ENTRY(0x795), TBL_ENTRY(0x796), TBL_ENTRY(0x797),
- TBL_ENTRY(0x798), TBL_ENTRY(0x799), TBL_ENTRY(0x79a), TBL_ENTRY(0x79b),
- TBL_ENTRY(0x79c), TBL_ENTRY(0x79d), TBL_ENTRY(0x79e), TBL_ENTRY(0x79f),
- TBL_ENTRY(0x7a0), TBL_ENTRY(0x7a1), TBL_ENTRY(0x7a2), TBL_ENTRY(0x7a3),
- TBL_ENTRY(0x7a4), TBL_ENTRY(0x7a5), TBL_ENTRY(0x7a6), TBL_ENTRY(0x7a7),
- TBL_ENTRY(0x7a8), TBL_ENTRY(0x7a9), TBL_ENTRY(0x7aa), TBL_ENTRY(0x7ab),
- TBL_ENTRY(0x7ac), TBL_ENTRY(0x7ad), TBL_ENTRY(0x7ae), TBL_ENTRY(0x7af),
- TBL_ENTRY(0x7b0), TBL_ENTRY(0x7b1), TBL_ENTRY(0x7b2), TBL_ENTRY(0x7b3),
- TBL_ENTRY(0x7b4), TBL_ENTRY(0x7b5), TBL_ENTRY(0x7b6), TBL_ENTRY(0x7b7),
- TBL_ENTRY(0x7b8), TBL_ENTRY(0x7b9), TBL_ENTRY(0x7ba), TBL_ENTRY(0x7bb),
- TBL_ENTRY(0x7bc), TBL_ENTRY(0x7bd), TBL_ENTRY(0x7be), TBL_ENTRY(0x7bf),
- TBL_ENTRY(0x7c0), TBL_ENTRY(0x7c1), TBL_ENTRY(0x7c2), TBL_ENTRY(0x7c3),
- TBL_ENTRY(0x7c4), TBL_ENTRY(0x7c5), TBL_ENTRY(0x7c6), TBL_ENTRY(0x7c7),
- TBL_ENTRY(0x7c8), TBL_ENTRY(0x7c9), TBL_ENTRY(0x7ca), TBL_ENTRY(0x7cb),
- TBL_ENTRY(0x7cc), TBL_ENTRY(0x7cd), TBL_ENTRY(0x7ce), TBL_ENTRY(0x7cf),
- TBL_ENTRY(0x7d0), TBL_ENTRY(0x7d1), TBL_ENTRY(0x7d2), TBL_ENTRY(0x7d3),
- TBL_ENTRY(0x7d4), TBL_ENTRY(0x7d5), TBL_ENTRY(0x7d6), TBL_ENTRY(0x7d7),
- TBL_ENTRY(0x7d8), TBL_ENTRY(0x7d9), TBL_ENTRY(0x7da), TBL_ENTRY(0x7db),
- TBL_ENTRY(0x7dc), TBL_ENTRY(0x7dd), TBL_ENTRY(0x7de), TBL_ENTRY(0x7df),
- TBL_ENTRY(0x7e0), TBL_ENTRY(0x7e1), TBL_ENTRY(0x7e2), TBL_ENTRY(0x7e3),
- TBL_ENTRY(0x7e4), TBL_ENTRY(0x7e5), TBL_ENTRY(0x7e6), TBL_ENTRY(0x7e7),
- TBL_ENTRY(0x7e8), TBL_ENTRY(0x7e9), TBL_ENTRY(0x7ea), TBL_ENTRY(0x7eb),
- TBL_ENTRY(0x7ec), TBL_ENTRY(0x7ed), TBL_ENTRY(0x7ee), TBL_ENTRY(0x7ef),
- TBL_ENTRY(0x7f0), TBL_ENTRY(0x7f1), TBL_ENTRY(0x7f2), TBL_ENTRY(0x7f3),
- TBL_ENTRY(0x7f4), TBL_ENTRY(0x7f5), TBL_ENTRY(0x7f6), TBL_ENTRY(0x7f7),
- TBL_ENTRY(0x7f8), TBL_ENTRY(0x7f9), TBL_ENTRY(0x7fa), TBL_ENTRY(0x7fb),
- TBL_ENTRY(0x7fc), TBL_ENTRY(0x7fd), TBL_ENTRY(0x7fe), TBL_ENTRY(0x7ff),
- TBL_ENTRY(0x800), TBL_ENTRY(0x801), TBL_ENTRY(0x802), TBL_ENTRY(0x803),
- TBL_ENTRY(0x804), TBL_ENTRY(0x805), TBL_ENTRY(0x806), TBL_ENTRY(0x807),
- TBL_ENTRY(0x808), TBL_ENTRY(0x809), TBL_ENTRY(0x80a), TBL_ENTRY(0x80b),
- TBL_ENTRY(0x80c), TBL_ENTRY(0x80d), TBL_ENTRY(0x80e), TBL_ENTRY(0x80f),
- TBL_ENTRY(0x810), TBL_ENTRY(0x811), TBL_ENTRY(0x812), TBL_ENTRY(0x813),
- TBL_ENTRY(0x814), TBL_ENTRY(0x815), TBL_ENTRY(0x816), TBL_ENTRY(0x817),
- TBL_ENTRY(0x818), TBL_ENTRY(0x819), TBL_ENTRY(0x81a), TBL_ENTRY(0x81b),
- TBL_ENTRY(0x81c), TBL_ENTRY(0x81d), TBL_ENTRY(0x81e), TBL_ENTRY(0x81f),
- TBL_ENTRY(0x820), TBL_ENTRY(0x821), TBL_ENTRY(0x822), TBL_ENTRY(0x823),
- TBL_ENTRY(0x824), TBL_ENTRY(0x825), TBL_ENTRY(0x826), TBL_ENTRY(0x827),
- TBL_ENTRY(0x828), TBL_ENTRY(0x829), TBL_ENTRY(0x82a), TBL_ENTRY(0x82b),
- TBL_ENTRY(0x82c), TBL_ENTRY(0x82d), TBL_ENTRY(0x82e), TBL_ENTRY(0x82f),
- TBL_ENTRY(0x830), TBL_ENTRY(0x831), TBL_ENTRY(0x832), TBL_ENTRY(0x833),
- TBL_ENTRY(0x834), TBL_ENTRY(0x835), TBL_ENTRY(0x836), TBL_ENTRY(0x837),
- TBL_ENTRY(0x838), TBL_ENTRY(0x839), TBL_ENTRY(0x83a), TBL_ENTRY(0x83b),
- TBL_ENTRY(0x83c), TBL_ENTRY(0x83d), TBL_ENTRY(0x83e), TBL_ENTRY(0x83f),
- TBL_ENTRY(0x840), TBL_ENTRY(0x841), TBL_ENTRY(0x842), TBL_ENTRY(0x843),
- TBL_ENTRY(0x844), TBL_ENTRY(0x845), TBL_ENTRY(0x846), TBL_ENTRY(0x847),
- TBL_ENTRY(0x848), TBL_ENTRY(0x849), TBL_ENTRY(0x84a), TBL_ENTRY(0x84b),
- TBL_ENTRY(0x84c), TBL_ENTRY(0x84d), TBL_ENTRY(0x84e), TBL_ENTRY(0x84f),
- TBL_ENTRY(0x850), TBL_ENTRY(0x851), TBL_ENTRY(0x852), TBL_ENTRY(0x853),
- TBL_ENTRY(0x854), TBL_ENTRY(0x855), TBL_ENTRY(0x856), TBL_ENTRY(0x857),
- TBL_ENTRY(0x858), TBL_ENTRY(0x859), TBL_ENTRY(0x85a), TBL_ENTRY(0x85b),
- TBL_ENTRY(0x85c), TBL_ENTRY(0x85d), TBL_ENTRY(0x85e), TBL_ENTRY(0x85f),
- TBL_ENTRY(0x860), TBL_ENTRY(0x861), TBL_ENTRY(0x862), TBL_ENTRY(0x863),
- TBL_ENTRY(0x864), TBL_ENTRY(0x865), TBL_ENTRY(0x866), TBL_ENTRY(0x867),
- TBL_ENTRY(0x868), TBL_ENTRY(0x869), TBL_ENTRY(0x86a), TBL_ENTRY(0x86b),
- TBL_ENTRY(0x86c), TBL_ENTRY(0x86d), TBL_ENTRY(0x86e), TBL_ENTRY(0x86f),
- TBL_ENTRY(0x870), TBL_ENTRY(0x871), TBL_ENTRY(0x872), TBL_ENTRY(0x873),
- TBL_ENTRY(0x874), TBL_ENTRY(0x875), TBL_ENTRY(0x876), TBL_ENTRY(0x877),
- TBL_ENTRY(0x878), TBL_ENTRY(0x879), TBL_ENTRY(0x87a), TBL_ENTRY(0x87b),
- TBL_ENTRY(0x87c), TBL_ENTRY(0x87d), TBL_ENTRY(0x87e), TBL_ENTRY(0x87f),
- TBL_ENTRY(0x880), TBL_ENTRY(0x881), TBL_ENTRY(0x882), TBL_ENTRY(0x883),
- TBL_ENTRY(0x884), TBL_ENTRY(0x885), TBL_ENTRY(0x886), TBL_ENTRY(0x887),
- TBL_ENTRY(0x888), TBL_ENTRY(0x889), TBL_ENTRY(0x88a), TBL_ENTRY(0x88b),
- TBL_ENTRY(0x88c), TBL_ENTRY(0x88d), TBL_ENTRY(0x88e), TBL_ENTRY(0x88f),
- TBL_ENTRY(0x890), TBL_ENTRY(0x891), TBL_ENTRY(0x892), TBL_ENTRY(0x893),
- TBL_ENTRY(0x894), TBL_ENTRY(0x895), TBL_ENTRY(0x896), TBL_ENTRY(0x897),
- TBL_ENTRY(0x898), TBL_ENTRY(0x899), TBL_ENTRY(0x89a), TBL_ENTRY(0x89b),
- TBL_ENTRY(0x89c), TBL_ENTRY(0x89d), TBL_ENTRY(0x89e), TBL_ENTRY(0x89f),
- TBL_ENTRY(0x8a0), TBL_ENTRY(0x8a1), TBL_ENTRY(0x8a2), TBL_ENTRY(0x8a3),
- TBL_ENTRY(0x8a4), TBL_ENTRY(0x8a5), TBL_ENTRY(0x8a6), TBL_ENTRY(0x8a7),
- TBL_ENTRY(0x8a8), TBL_ENTRY(0x8a9), TBL_ENTRY(0x8aa), TBL_ENTRY(0x8ab),
- TBL_ENTRY(0x8ac), TBL_ENTRY(0x8ad), TBL_ENTRY(0x8ae), TBL_ENTRY(0x8af),
- TBL_ENTRY(0x8b0), TBL_ENTRY(0x8b1), TBL_ENTRY(0x8b2), TBL_ENTRY(0x8b3),
- TBL_ENTRY(0x8b4), TBL_ENTRY(0x8b5), TBL_ENTRY(0x8b6), TBL_ENTRY(0x8b7),
- TBL_ENTRY(0x8b8), TBL_ENTRY(0x8b9), TBL_ENTRY(0x8ba), TBL_ENTRY(0x8bb),
- TBL_ENTRY(0x8bc), TBL_ENTRY(0x8bd), TBL_ENTRY(0x8be), TBL_ENTRY(0x8bf),
- TBL_ENTRY(0x8c0), TBL_ENTRY(0x8c1), TBL_ENTRY(0x8c2), TBL_ENTRY(0x8c3),
- TBL_ENTRY(0x8c4), TBL_ENTRY(0x8c5), TBL_ENTRY(0x8c6), TBL_ENTRY(0x8c7),
- TBL_ENTRY(0x8c8), TBL_ENTRY(0x8c9), TBL_ENTRY(0x8ca), TBL_ENTRY(0x8cb),
- TBL_ENTRY(0x8cc), TBL_ENTRY(0x8cd), TBL_ENTRY(0x8ce), TBL_ENTRY(0x8cf),
- TBL_ENTRY(0x8d0), TBL_ENTRY(0x8d1), TBL_ENTRY(0x8d2), TBL_ENTRY(0x8d3),
- TBL_ENTRY(0x8d4), TBL_ENTRY(0x8d5), TBL_ENTRY(0x8d6), TBL_ENTRY(0x8d7),
- TBL_ENTRY(0x8d8), TBL_ENTRY(0x8d9), TBL_ENTRY(0x8da), TBL_ENTRY(0x8db),
- TBL_ENTRY(0x8dc), TBL_ENTRY(0x8dd), TBL_ENTRY(0x8de), TBL_ENTRY(0x8df),
- TBL_ENTRY(0x8e0), TBL_ENTRY(0x8e1), TBL_ENTRY(0x8e2), TBL_ENTRY(0x8e3),
- TBL_ENTRY(0x8e4), TBL_ENTRY(0x8e5), TBL_ENTRY(0x8e6), TBL_ENTRY(0x8e7),
- TBL_ENTRY(0x8e8), TBL_ENTRY(0x8e9), TBL_ENTRY(0x8ea), TBL_ENTRY(0x8eb),
- TBL_ENTRY(0x8ec), TBL_ENTRY(0x8ed), TBL_ENTRY(0x8ee), TBL_ENTRY(0x8ef),
- TBL_ENTRY(0x8f0), TBL_ENTRY(0x8f1), TBL_ENTRY(0x8f2), TBL_ENTRY(0x8f3),
- TBL_ENTRY(0x8f4), TBL_ENTRY(0x8f5), TBL_ENTRY(0x8f6), TBL_ENTRY(0x8f7),
- TBL_ENTRY(0x8f8), TBL_ENTRY(0x8f9), TBL_ENTRY(0x8fa), TBL_ENTRY(0x8fb),
- TBL_ENTRY(0x8fc), TBL_ENTRY(0x8fd), TBL_ENTRY(0x8fe), TBL_ENTRY(0x8ff),
- TBL_ENTRY(0x900), TBL_ENTRY(0x901), TBL_ENTRY(0x902), TBL_ENTRY(0x903),
- TBL_ENTRY(0x904), TBL_ENTRY(0x905), TBL_ENTRY(0x906), TBL_ENTRY(0x907),
- TBL_ENTRY(0x908), TBL_ENTRY(0x909), TBL_ENTRY(0x90a), TBL_ENTRY(0x90b),
- TBL_ENTRY(0x90c), TBL_ENTRY(0x90d), TBL_ENTRY(0x90e), TBL_ENTRY(0x90f),
- TBL_ENTRY(0x910), TBL_ENTRY(0x911), TBL_ENTRY(0x912), TBL_ENTRY(0x913),
- TBL_ENTRY(0x914), TBL_ENTRY(0x915), TBL_ENTRY(0x916), TBL_ENTRY(0x917),
- TBL_ENTRY(0x918), TBL_ENTRY(0x919), TBL_ENTRY(0x91a), TBL_ENTRY(0x91b),
- TBL_ENTRY(0x91c), TBL_ENTRY(0x91d), TBL_ENTRY(0x91e), TBL_ENTRY(0x91f),
- TBL_ENTRY(0x920), TBL_ENTRY(0x921), TBL_ENTRY(0x922), TBL_ENTRY(0x923),
- TBL_ENTRY(0x924), TBL_ENTRY(0x925), TBL_ENTRY(0x926), TBL_ENTRY(0x927),
- TBL_ENTRY(0x928), TBL_ENTRY(0x929), TBL_ENTRY(0x92a), TBL_ENTRY(0x92b),
- TBL_ENTRY(0x92c), TBL_ENTRY(0x92d), TBL_ENTRY(0x92e), TBL_ENTRY(0x92f),
- TBL_ENTRY(0x930), TBL_ENTRY(0x931), TBL_ENTRY(0x932), TBL_ENTRY(0x933),
- TBL_ENTRY(0x934), TBL_ENTRY(0x935), TBL_ENTRY(0x936), TBL_ENTRY(0x937),
- TBL_ENTRY(0x938), TBL_ENTRY(0x939), TBL_ENTRY(0x93a), TBL_ENTRY(0x93b),
- TBL_ENTRY(0x93c), TBL_ENTRY(0x93d), TBL_ENTRY(0x93e), TBL_ENTRY(0x93f),
- TBL_ENTRY(0x940), TBL_ENTRY(0x941), TBL_ENTRY(0x942), TBL_ENTRY(0x943),
- TBL_ENTRY(0x944), TBL_ENTRY(0x945), TBL_ENTRY(0x946), TBL_ENTRY(0x947),
- TBL_ENTRY(0x948), TBL_ENTRY(0x949), TBL_ENTRY(0x94a), TBL_ENTRY(0x94b),
- TBL_ENTRY(0x94c), TBL_ENTRY(0x94d), TBL_ENTRY(0x94e), TBL_ENTRY(0x94f),
- TBL_ENTRY(0x950), TBL_ENTRY(0x951), TBL_ENTRY(0x952), TBL_ENTRY(0x953),
- TBL_ENTRY(0x954), TBL_ENTRY(0x955), TBL_ENTRY(0x956), TBL_ENTRY(0x957),
- TBL_ENTRY(0x958), TBL_ENTRY(0x959), TBL_ENTRY(0x95a), TBL_ENTRY(0x95b),
- TBL_ENTRY(0x95c), TBL_ENTRY(0x95d), TBL_ENTRY(0x95e), TBL_ENTRY(0x95f),
- TBL_ENTRY(0x960), TBL_ENTRY(0x961), TBL_ENTRY(0x962), TBL_ENTRY(0x963),
- TBL_ENTRY(0x964), TBL_ENTRY(0x965), TBL_ENTRY(0x966), TBL_ENTRY(0x967),
- TBL_ENTRY(0x968), TBL_ENTRY(0x969), TBL_ENTRY(0x96a), TBL_ENTRY(0x96b),
- TBL_ENTRY(0x96c), TBL_ENTRY(0x96d), TBL_ENTRY(0x96e), TBL_ENTRY(0x96f),
- TBL_ENTRY(0x970), TBL_ENTRY(0x971), TBL_ENTRY(0x972), TBL_ENTRY(0x973),
- TBL_ENTRY(0x974), TBL_ENTRY(0x975), TBL_ENTRY(0x976), TBL_ENTRY(0x977),
- TBL_ENTRY(0x978), TBL_ENTRY(0x979), TBL_ENTRY(0x97a), TBL_ENTRY(0x97b),
- TBL_ENTRY(0x97c), TBL_ENTRY(0x97d), TBL_ENTRY(0x97e), TBL_ENTRY(0x97f),
- TBL_ENTRY(0x980), TBL_ENTRY(0x981), TBL_ENTRY(0x982), TBL_ENTRY(0x983),
- TBL_ENTRY(0x984), TBL_ENTRY(0x985), TBL_ENTRY(0x986), TBL_ENTRY(0x987),
- TBL_ENTRY(0x988), TBL_ENTRY(0x989), TBL_ENTRY(0x98a), TBL_ENTRY(0x98b),
- TBL_ENTRY(0x98c), TBL_ENTRY(0x98d), TBL_ENTRY(0x98e), TBL_ENTRY(0x98f),
- TBL_ENTRY(0x990), TBL_ENTRY(0x991), TBL_ENTRY(0x992), TBL_ENTRY(0x993),
- TBL_ENTRY(0x994), TBL_ENTRY(0x995), TBL_ENTRY(0x996), TBL_ENTRY(0x997),
- TBL_ENTRY(0x998), TBL_ENTRY(0x999), TBL_ENTRY(0x99a), TBL_ENTRY(0x99b),
- TBL_ENTRY(0x99c), TBL_ENTRY(0x99d), TBL_ENTRY(0x99e), TBL_ENTRY(0x99f),
- TBL_ENTRY(0x9a0), TBL_ENTRY(0x9a1), TBL_ENTRY(0x9a2), TBL_ENTRY(0x9a3),
- TBL_ENTRY(0x9a4), TBL_ENTRY(0x9a5), TBL_ENTRY(0x9a6), TBL_ENTRY(0x9a7),
- TBL_ENTRY(0x9a8), TBL_ENTRY(0x9a9), TBL_ENTRY(0x9aa), TBL_ENTRY(0x9ab),
- TBL_ENTRY(0x9ac), TBL_ENTRY(0x9ad), TBL_ENTRY(0x9ae), TBL_ENTRY(0x9af),
- TBL_ENTRY(0x9b0), TBL_ENTRY(0x9b1), TBL_ENTRY(0x9b2), TBL_ENTRY(0x9b3),
- TBL_ENTRY(0x9b4), TBL_ENTRY(0x9b5), TBL_ENTRY(0x9b6), TBL_ENTRY(0x9b7),
- TBL_ENTRY(0x9b8), TBL_ENTRY(0x9b9), TBL_ENTRY(0x9ba), TBL_ENTRY(0x9bb),
- TBL_ENTRY(0x9bc), TBL_ENTRY(0x9bd), TBL_ENTRY(0x9be), TBL_ENTRY(0x9bf),
- TBL_ENTRY(0x9c0), TBL_ENTRY(0x9c1), TBL_ENTRY(0x9c2), TBL_ENTRY(0x9c3),
- TBL_ENTRY(0x9c4), TBL_ENTRY(0x9c5), TBL_ENTRY(0x9c6), TBL_ENTRY(0x9c7),
- TBL_ENTRY(0x9c8), TBL_ENTRY(0x9c9), TBL_ENTRY(0x9ca), TBL_ENTRY(0x9cb),
- TBL_ENTRY(0x9cc), TBL_ENTRY(0x9cd), TBL_ENTRY(0x9ce), TBL_ENTRY(0x9cf),
- TBL_ENTRY(0x9d0), TBL_ENTRY(0x9d1), TBL_ENTRY(0x9d2), TBL_ENTRY(0x9d3),
- TBL_ENTRY(0x9d4), TBL_ENTRY(0x9d5), TBL_ENTRY(0x9d6), TBL_ENTRY(0x9d7),
- TBL_ENTRY(0x9d8), TBL_ENTRY(0x9d9), TBL_ENTRY(0x9da), TBL_ENTRY(0x9db),
- TBL_ENTRY(0x9dc), TBL_ENTRY(0x9dd), TBL_ENTRY(0x9de), TBL_ENTRY(0x9df),
- TBL_ENTRY(0x9e0), TBL_ENTRY(0x9e1), TBL_ENTRY(0x9e2), TBL_ENTRY(0x9e3),
- TBL_ENTRY(0x9e4), TBL_ENTRY(0x9e5), TBL_ENTRY(0x9e6), TBL_ENTRY(0x9e7),
- TBL_ENTRY(0x9e8), TBL_ENTRY(0x9e9), TBL_ENTRY(0x9ea), TBL_ENTRY(0x9eb),
- TBL_ENTRY(0x9ec), TBL_ENTRY(0x9ed), TBL_ENTRY(0x9ee), TBL_ENTRY(0x9ef),
- TBL_ENTRY(0x9f0), TBL_ENTRY(0x9f1), TBL_ENTRY(0x9f2), TBL_ENTRY(0x9f3),
- TBL_ENTRY(0x9f4), TBL_ENTRY(0x9f5), TBL_ENTRY(0x9f6), TBL_ENTRY(0x9f7),
- TBL_ENTRY(0x9f8), TBL_ENTRY(0x9f9), TBL_ENTRY(0x9fa), TBL_ENTRY(0x9fb),
- TBL_ENTRY(0x9fc), TBL_ENTRY(0x9fd), TBL_ENTRY(0x9fe), TBL_ENTRY(0x9ff),
- TBL_ENTRY(0xa00), TBL_ENTRY(0xa01), TBL_ENTRY(0xa02), TBL_ENTRY(0xa03),
- TBL_ENTRY(0xa04), TBL_ENTRY(0xa05), TBL_ENTRY(0xa06), TBL_ENTRY(0xa07),
- TBL_ENTRY(0xa08), TBL_ENTRY(0xa09), TBL_ENTRY(0xa0a), TBL_ENTRY(0xa0b),
- TBL_ENTRY(0xa0c), TBL_ENTRY(0xa0d), TBL_ENTRY(0xa0e), TBL_ENTRY(0xa0f),
- TBL_ENTRY(0xa10), TBL_ENTRY(0xa11), TBL_ENTRY(0xa12), TBL_ENTRY(0xa13),
- TBL_ENTRY(0xa14), TBL_ENTRY(0xa15), TBL_ENTRY(0xa16), TBL_ENTRY(0xa17),
- TBL_ENTRY(0xa18), TBL_ENTRY(0xa19), TBL_ENTRY(0xa1a), TBL_ENTRY(0xa1b),
- TBL_ENTRY(0xa1c), TBL_ENTRY(0xa1d), TBL_ENTRY(0xa1e), TBL_ENTRY(0xa1f),
- TBL_ENTRY(0xa20), TBL_ENTRY(0xa21), TBL_ENTRY(0xa22), TBL_ENTRY(0xa23),
- TBL_ENTRY(0xa24), TBL_ENTRY(0xa25), TBL_ENTRY(0xa26), TBL_ENTRY(0xa27),
- TBL_ENTRY(0xa28), TBL_ENTRY(0xa29), TBL_ENTRY(0xa2a), TBL_ENTRY(0xa2b),
- TBL_ENTRY(0xa2c), TBL_ENTRY(0xa2d), TBL_ENTRY(0xa2e), TBL_ENTRY(0xa2f),
- TBL_ENTRY(0xa30), TBL_ENTRY(0xa31), TBL_ENTRY(0xa32), TBL_ENTRY(0xa33),
- TBL_ENTRY(0xa34), TBL_ENTRY(0xa35), TBL_ENTRY(0xa36), TBL_ENTRY(0xa37),
- TBL_ENTRY(0xa38), TBL_ENTRY(0xa39), TBL_ENTRY(0xa3a), TBL_ENTRY(0xa3b),
- TBL_ENTRY(0xa3c), TBL_ENTRY(0xa3d), TBL_ENTRY(0xa3e), TBL_ENTRY(0xa3f),
- TBL_ENTRY(0xa40), TBL_ENTRY(0xa41), TBL_ENTRY(0xa42), TBL_ENTRY(0xa43),
- TBL_ENTRY(0xa44), TBL_ENTRY(0xa45), TBL_ENTRY(0xa46), TBL_ENTRY(0xa47),
- TBL_ENTRY(0xa48), TBL_ENTRY(0xa49), TBL_ENTRY(0xa4a), TBL_ENTRY(0xa4b),
- TBL_ENTRY(0xa4c), TBL_ENTRY(0xa4d), TBL_ENTRY(0xa4e), TBL_ENTRY(0xa4f),
- TBL_ENTRY(0xa50), TBL_ENTRY(0xa51), TBL_ENTRY(0xa52), TBL_ENTRY(0xa53),
- TBL_ENTRY(0xa54), TBL_ENTRY(0xa55), TBL_ENTRY(0xa56), TBL_ENTRY(0xa57),
- TBL_ENTRY(0xa58), TBL_ENTRY(0xa59), TBL_ENTRY(0xa5a), TBL_ENTRY(0xa5b),
- TBL_ENTRY(0xa5c), TBL_ENTRY(0xa5d), TBL_ENTRY(0xa5e), TBL_ENTRY(0xa5f),
- TBL_ENTRY(0xa60), TBL_ENTRY(0xa61), TBL_ENTRY(0xa62), TBL_ENTRY(0xa63),
- TBL_ENTRY(0xa64), TBL_ENTRY(0xa65), TBL_ENTRY(0xa66), TBL_ENTRY(0xa67),
- TBL_ENTRY(0xa68), TBL_ENTRY(0xa69), TBL_ENTRY(0xa6a), TBL_ENTRY(0xa6b),
- TBL_ENTRY(0xa6c), TBL_ENTRY(0xa6d), TBL_ENTRY(0xa6e), TBL_ENTRY(0xa6f),
- TBL_ENTRY(0xa70), TBL_ENTRY(0xa71), TBL_ENTRY(0xa72), TBL_ENTRY(0xa73),
- TBL_ENTRY(0xa74), TBL_ENTRY(0xa75), TBL_ENTRY(0xa76), TBL_ENTRY(0xa77),
- TBL_ENTRY(0xa78), TBL_ENTRY(0xa79), TBL_ENTRY(0xa7a), TBL_ENTRY(0xa7b),
- TBL_ENTRY(0xa7c), TBL_ENTRY(0xa7d), TBL_ENTRY(0xa7e), TBL_ENTRY(0xa7f),
- TBL_ENTRY(0xa80), TBL_ENTRY(0xa81), TBL_ENTRY(0xa82), TBL_ENTRY(0xa83),
- TBL_ENTRY(0xa84), TBL_ENTRY(0xa85), TBL_ENTRY(0xa86), TBL_ENTRY(0xa87),
- TBL_ENTRY(0xa88), TBL_ENTRY(0xa89), TBL_ENTRY(0xa8a), TBL_ENTRY(0xa8b),
- TBL_ENTRY(0xa8c), TBL_ENTRY(0xa8d), TBL_ENTRY(0xa8e), TBL_ENTRY(0xa8f),
- TBL_ENTRY(0xa90), TBL_ENTRY(0xa91), TBL_ENTRY(0xa92), TBL_ENTRY(0xa93),
- TBL_ENTRY(0xa94), TBL_ENTRY(0xa95), TBL_ENTRY(0xa96), TBL_ENTRY(0xa97),
- TBL_ENTRY(0xa98), TBL_ENTRY(0xa99), TBL_ENTRY(0xa9a), TBL_ENTRY(0xa9b),
- TBL_ENTRY(0xa9c), TBL_ENTRY(0xa9d), TBL_ENTRY(0xa9e), TBL_ENTRY(0xa9f),
- TBL_ENTRY(0xaa0), TBL_ENTRY(0xaa1), TBL_ENTRY(0xaa2), TBL_ENTRY(0xaa3),
- TBL_ENTRY(0xaa4), TBL_ENTRY(0xaa5), TBL_ENTRY(0xaa6), TBL_ENTRY(0xaa7),
- TBL_ENTRY(0xaa8), TBL_ENTRY(0xaa9), TBL_ENTRY(0xaaa), TBL_ENTRY(0xaab),
- TBL_ENTRY(0xaac), TBL_ENTRY(0xaad), TBL_ENTRY(0xaae), TBL_ENTRY(0xaaf),
- TBL_ENTRY(0xab0), TBL_ENTRY(0xab1), TBL_ENTRY(0xab2), TBL_ENTRY(0xab3),
- TBL_ENTRY(0xab4), TBL_ENTRY(0xab5), TBL_ENTRY(0xab6), TBL_ENTRY(0xab7),
- TBL_ENTRY(0xab8), TBL_ENTRY(0xab9), TBL_ENTRY(0xaba), TBL_ENTRY(0xabb),
- TBL_ENTRY(0xabc), TBL_ENTRY(0xabd), TBL_ENTRY(0xabe), TBL_ENTRY(0xabf),
- TBL_ENTRY(0xac0), TBL_ENTRY(0xac1), TBL_ENTRY(0xac2), TBL_ENTRY(0xac3),
- TBL_ENTRY(0xac4), TBL_ENTRY(0xac5), TBL_ENTRY(0xac6), TBL_ENTRY(0xac7),
- TBL_ENTRY(0xac8), TBL_ENTRY(0xac9), TBL_ENTRY(0xaca), TBL_ENTRY(0xacb),
- TBL_ENTRY(0xacc), TBL_ENTRY(0xacd), TBL_ENTRY(0xace), TBL_ENTRY(0xacf),
- TBL_ENTRY(0xad0), TBL_ENTRY(0xad1), TBL_ENTRY(0xad2), TBL_ENTRY(0xad3),
- TBL_ENTRY(0xad4), TBL_ENTRY(0xad5), TBL_ENTRY(0xad6), TBL_ENTRY(0xad7),
- TBL_ENTRY(0xad8), TBL_ENTRY(0xad9), TBL_ENTRY(0xada), TBL_ENTRY(0xadb),
- TBL_ENTRY(0xadc), TBL_ENTRY(0xadd), TBL_ENTRY(0xade), TBL_ENTRY(0xadf),
- TBL_ENTRY(0xae0), TBL_ENTRY(0xae1), TBL_ENTRY(0xae2), TBL_ENTRY(0xae3),
- TBL_ENTRY(0xae4), TBL_ENTRY(0xae5), TBL_ENTRY(0xae6), TBL_ENTRY(0xae7),
- TBL_ENTRY(0xae8), TBL_ENTRY(0xae9), TBL_ENTRY(0xaea), TBL_ENTRY(0xaeb),
- TBL_ENTRY(0xaec), TBL_ENTRY(0xaed), TBL_ENTRY(0xaee), TBL_ENTRY(0xaef),
- TBL_ENTRY(0xaf0), TBL_ENTRY(0xaf1), TBL_ENTRY(0xaf2), TBL_ENTRY(0xaf3),
- TBL_ENTRY(0xaf4), TBL_ENTRY(0xaf5), TBL_ENTRY(0xaf6), TBL_ENTRY(0xaf7),
- TBL_ENTRY(0xaf8), TBL_ENTRY(0xaf9), TBL_ENTRY(0xafa), TBL_ENTRY(0xafb),
- TBL_ENTRY(0xafc), TBL_ENTRY(0xafd), TBL_ENTRY(0xafe), TBL_ENTRY(0xaff),
- TBL_ENTRY(0xb00), TBL_ENTRY(0xb01), TBL_ENTRY(0xb02), TBL_ENTRY(0xb03),
- TBL_ENTRY(0xb04), TBL_ENTRY(0xb05), TBL_ENTRY(0xb06), TBL_ENTRY(0xb07),
- TBL_ENTRY(0xb08), TBL_ENTRY(0xb09), TBL_ENTRY(0xb0a), TBL_ENTRY(0xb0b),
- TBL_ENTRY(0xb0c), TBL_ENTRY(0xb0d), TBL_ENTRY(0xb0e), TBL_ENTRY(0xb0f),
- TBL_ENTRY(0xb10), TBL_ENTRY(0xb11), TBL_ENTRY(0xb12), TBL_ENTRY(0xb13),
- TBL_ENTRY(0xb14), TBL_ENTRY(0xb15), TBL_ENTRY(0xb16), TBL_ENTRY(0xb17),
- TBL_ENTRY(0xb18), TBL_ENTRY(0xb19), TBL_ENTRY(0xb1a), TBL_ENTRY(0xb1b),
- TBL_ENTRY(0xb1c), TBL_ENTRY(0xb1d), TBL_ENTRY(0xb1e), TBL_ENTRY(0xb1f),
- TBL_ENTRY(0xb20), TBL_ENTRY(0xb21), TBL_ENTRY(0xb22), TBL_ENTRY(0xb23),
- TBL_ENTRY(0xb24), TBL_ENTRY(0xb25), TBL_ENTRY(0xb26), TBL_ENTRY(0xb27),
- TBL_ENTRY(0xb28), TBL_ENTRY(0xb29), TBL_ENTRY(0xb2a), TBL_ENTRY(0xb2b),
- TBL_ENTRY(0xb2c), TBL_ENTRY(0xb2d), TBL_ENTRY(0xb2e), TBL_ENTRY(0xb2f),
- TBL_ENTRY(0xb30), TBL_ENTRY(0xb31), TBL_ENTRY(0xb32), TBL_ENTRY(0xb33),
- TBL_ENTRY(0xb34), TBL_ENTRY(0xb35), TBL_ENTRY(0xb36), TBL_ENTRY(0xb37),
- TBL_ENTRY(0xb38), TBL_ENTRY(0xb39), TBL_ENTRY(0xb3a), TBL_ENTRY(0xb3b),
- TBL_ENTRY(0xb3c), TBL_ENTRY(0xb3d), TBL_ENTRY(0xb3e), TBL_ENTRY(0xb3f),
- TBL_ENTRY(0xb40), TBL_ENTRY(0xb41), TBL_ENTRY(0xb42), TBL_ENTRY(0xb43),
- TBL_ENTRY(0xb44), TBL_ENTRY(0xb45), TBL_ENTRY(0xb46), TBL_ENTRY(0xb47),
- TBL_ENTRY(0xb48), TBL_ENTRY(0xb49), TBL_ENTRY(0xb4a), TBL_ENTRY(0xb4b),
- TBL_ENTRY(0xb4c), TBL_ENTRY(0xb4d), TBL_ENTRY(0xb4e), TBL_ENTRY(0xb4f),
- TBL_ENTRY(0xb50), TBL_ENTRY(0xb51), TBL_ENTRY(0xb52), TBL_ENTRY(0xb53),
- TBL_ENTRY(0xb54), TBL_ENTRY(0xb55), TBL_ENTRY(0xb56), TBL_ENTRY(0xb57),
- TBL_ENTRY(0xb58), TBL_ENTRY(0xb59), TBL_ENTRY(0xb5a), TBL_ENTRY(0xb5b),
- TBL_ENTRY(0xb5c), TBL_ENTRY(0xb5d), TBL_ENTRY(0xb5e), TBL_ENTRY(0xb5f),
- TBL_ENTRY(0xb60), TBL_ENTRY(0xb61), TBL_ENTRY(0xb62), TBL_ENTRY(0xb63),
- TBL_ENTRY(0xb64), TBL_ENTRY(0xb65), TBL_ENTRY(0xb66), TBL_ENTRY(0xb67),
- TBL_ENTRY(0xb68), TBL_ENTRY(0xb69), TBL_ENTRY(0xb6a), TBL_ENTRY(0xb6b),
- TBL_ENTRY(0xb6c), TBL_ENTRY(0xb6d), TBL_ENTRY(0xb6e), TBL_ENTRY(0xb6f),
- TBL_ENTRY(0xb70), TBL_ENTRY(0xb71), TBL_ENTRY(0xb72), TBL_ENTRY(0xb73),
- TBL_ENTRY(0xb74), TBL_ENTRY(0xb75), TBL_ENTRY(0xb76), TBL_ENTRY(0xb77),
- TBL_ENTRY(0xb78), TBL_ENTRY(0xb79), TBL_ENTRY(0xb7a), TBL_ENTRY(0xb7b),
- TBL_ENTRY(0xb7c), TBL_ENTRY(0xb7d), TBL_ENTRY(0xb7e), TBL_ENTRY(0xb7f),
- TBL_ENTRY(0xb80), TBL_ENTRY(0xb81), TBL_ENTRY(0xb82), TBL_ENTRY(0xb83),
- TBL_ENTRY(0xb84), TBL_ENTRY(0xb85), TBL_ENTRY(0xb86), TBL_ENTRY(0xb87),
- TBL_ENTRY(0xb88), TBL_ENTRY(0xb89), TBL_ENTRY(0xb8a), TBL_ENTRY(0xb8b),
- TBL_ENTRY(0xb8c), TBL_ENTRY(0xb8d), TBL_ENTRY(0xb8e), TBL_ENTRY(0xb8f),
- TBL_ENTRY(0xb90), TBL_ENTRY(0xb91), TBL_ENTRY(0xb92), TBL_ENTRY(0xb93),
- TBL_ENTRY(0xb94), TBL_ENTRY(0xb95), TBL_ENTRY(0xb96), TBL_ENTRY(0xb97),
- TBL_ENTRY(0xb98), TBL_ENTRY(0xb99), TBL_ENTRY(0xb9a), TBL_ENTRY(0xb9b),
- TBL_ENTRY(0xb9c), TBL_ENTRY(0xb9d), TBL_ENTRY(0xb9e), TBL_ENTRY(0xb9f),
- TBL_ENTRY(0xba0), TBL_ENTRY(0xba1), TBL_ENTRY(0xba2), TBL_ENTRY(0xba3),
- TBL_ENTRY(0xba4), TBL_ENTRY(0xba5), TBL_ENTRY(0xba6), TBL_ENTRY(0xba7),
- TBL_ENTRY(0xba8), TBL_ENTRY(0xba9), TBL_ENTRY(0xbaa), TBL_ENTRY(0xbab),
- TBL_ENTRY(0xbac), TBL_ENTRY(0xbad), TBL_ENTRY(0xbae), TBL_ENTRY(0xbaf),
- TBL_ENTRY(0xbb0), TBL_ENTRY(0xbb1), TBL_ENTRY(0xbb2), TBL_ENTRY(0xbb3),
- TBL_ENTRY(0xbb4), TBL_ENTRY(0xbb5), TBL_ENTRY(0xbb6), TBL_ENTRY(0xbb7),
- TBL_ENTRY(0xbb8), TBL_ENTRY(0xbb9), TBL_ENTRY(0xbba), TBL_ENTRY(0xbbb),
- TBL_ENTRY(0xbbc), TBL_ENTRY(0xbbd), TBL_ENTRY(0xbbe), TBL_ENTRY(0xbbf),
- TBL_ENTRY(0xbc0), TBL_ENTRY(0xbc1), TBL_ENTRY(0xbc2), TBL_ENTRY(0xbc3),
- TBL_ENTRY(0xbc4), TBL_ENTRY(0xbc5), TBL_ENTRY(0xbc6), TBL_ENTRY(0xbc7),
- TBL_ENTRY(0xbc8), TBL_ENTRY(0xbc9), TBL_ENTRY(0xbca), TBL_ENTRY(0xbcb),
- TBL_ENTRY(0xbcc), TBL_ENTRY(0xbcd), TBL_ENTRY(0xbce), TBL_ENTRY(0xbcf),
- TBL_ENTRY(0xbd0), TBL_ENTRY(0xbd1), TBL_ENTRY(0xbd2), TBL_ENTRY(0xbd3),
- TBL_ENTRY(0xbd4), TBL_ENTRY(0xbd5), TBL_ENTRY(0xbd6), TBL_ENTRY(0xbd7),
- TBL_ENTRY(0xbd8), TBL_ENTRY(0xbd9), TBL_ENTRY(0xbda), TBL_ENTRY(0xbdb),
- TBL_ENTRY(0xbdc), TBL_ENTRY(0xbdd), TBL_ENTRY(0xbde), TBL_ENTRY(0xbdf),
- TBL_ENTRY(0xbe0), TBL_ENTRY(0xbe1), TBL_ENTRY(0xbe2), TBL_ENTRY(0xbe3),
- TBL_ENTRY(0xbe4), TBL_ENTRY(0xbe5), TBL_ENTRY(0xbe6), TBL_ENTRY(0xbe7),
- TBL_ENTRY(0xbe8), TBL_ENTRY(0xbe9), TBL_ENTRY(0xbea), TBL_ENTRY(0xbeb),
- TBL_ENTRY(0xbec), TBL_ENTRY(0xbed), TBL_ENTRY(0xbee), TBL_ENTRY(0xbef),
- TBL_ENTRY(0xbf0), TBL_ENTRY(0xbf1), TBL_ENTRY(0xbf2), TBL_ENTRY(0xbf3),
- TBL_ENTRY(0xbf4), TBL_ENTRY(0xbf5), TBL_ENTRY(0xbf6), TBL_ENTRY(0xbf7),
- TBL_ENTRY(0xbf8), TBL_ENTRY(0xbf9), TBL_ENTRY(0xbfa), TBL_ENTRY(0xbfb),
- TBL_ENTRY(0xbfc), TBL_ENTRY(0xbfd), TBL_ENTRY(0xbfe), TBL_ENTRY(0xbff),
- TBL_ENTRY(0xc00), TBL_ENTRY(0xc01), TBL_ENTRY(0xc02), TBL_ENTRY(0xc03),
- TBL_ENTRY(0xc04), TBL_ENTRY(0xc05), TBL_ENTRY(0xc06), TBL_ENTRY(0xc07),
- TBL_ENTRY(0xc08), TBL_ENTRY(0xc09), TBL_ENTRY(0xc0a), TBL_ENTRY(0xc0b),
- TBL_ENTRY(0xc0c), TBL_ENTRY(0xc0d), TBL_ENTRY(0xc0e), TBL_ENTRY(0xc0f),
- TBL_ENTRY(0xc10), TBL_ENTRY(0xc11), TBL_ENTRY(0xc12), TBL_ENTRY(0xc13),
- TBL_ENTRY(0xc14), TBL_ENTRY(0xc15), TBL_ENTRY(0xc16), TBL_ENTRY(0xc17),
- TBL_ENTRY(0xc18), TBL_ENTRY(0xc19), TBL_ENTRY(0xc1a), TBL_ENTRY(0xc1b),
- TBL_ENTRY(0xc1c), TBL_ENTRY(0xc1d), TBL_ENTRY(0xc1e), TBL_ENTRY(0xc1f),
- TBL_ENTRY(0xc20), TBL_ENTRY(0xc21), TBL_ENTRY(0xc22), TBL_ENTRY(0xc23),
- TBL_ENTRY(0xc24), TBL_ENTRY(0xc25), TBL_ENTRY(0xc26), TBL_ENTRY(0xc27),
- TBL_ENTRY(0xc28), TBL_ENTRY(0xc29), TBL_ENTRY(0xc2a), TBL_ENTRY(0xc2b),
- TBL_ENTRY(0xc2c), TBL_ENTRY(0xc2d), TBL_ENTRY(0xc2e), TBL_ENTRY(0xc2f),
- TBL_ENTRY(0xc30), TBL_ENTRY(0xc31), TBL_ENTRY(0xc32), TBL_ENTRY(0xc33),
- TBL_ENTRY(0xc34), TBL_ENTRY(0xc35), TBL_ENTRY(0xc36), TBL_ENTRY(0xc37),
- TBL_ENTRY(0xc38), TBL_ENTRY(0xc39), TBL_ENTRY(0xc3a), TBL_ENTRY(0xc3b),
- TBL_ENTRY(0xc3c), TBL_ENTRY(0xc3d), TBL_ENTRY(0xc3e), TBL_ENTRY(0xc3f),
- TBL_ENTRY(0xc40), TBL_ENTRY(0xc41), TBL_ENTRY(0xc42), TBL_ENTRY(0xc43),
- TBL_ENTRY(0xc44), TBL_ENTRY(0xc45), TBL_ENTRY(0xc46), TBL_ENTRY(0xc47),
- TBL_ENTRY(0xc48), TBL_ENTRY(0xc49), TBL_ENTRY(0xc4a), TBL_ENTRY(0xc4b),
- TBL_ENTRY(0xc4c), TBL_ENTRY(0xc4d), TBL_ENTRY(0xc4e), TBL_ENTRY(0xc4f),
- TBL_ENTRY(0xc50), TBL_ENTRY(0xc51), TBL_ENTRY(0xc52), TBL_ENTRY(0xc53),
- TBL_ENTRY(0xc54), TBL_ENTRY(0xc55), TBL_ENTRY(0xc56), TBL_ENTRY(0xc57),
- TBL_ENTRY(0xc58), TBL_ENTRY(0xc59), TBL_ENTRY(0xc5a), TBL_ENTRY(0xc5b),
- TBL_ENTRY(0xc5c), TBL_ENTRY(0xc5d), TBL_ENTRY(0xc5e), TBL_ENTRY(0xc5f),
- TBL_ENTRY(0xc60), TBL_ENTRY(0xc61), TBL_ENTRY(0xc62), TBL_ENTRY(0xc63),
- TBL_ENTRY(0xc64), TBL_ENTRY(0xc65), TBL_ENTRY(0xc66), TBL_ENTRY(0xc67),
- TBL_ENTRY(0xc68), TBL_ENTRY(0xc69), TBL_ENTRY(0xc6a), TBL_ENTRY(0xc6b),
- TBL_ENTRY(0xc6c), TBL_ENTRY(0xc6d), TBL_ENTRY(0xc6e), TBL_ENTRY(0xc6f),
- TBL_ENTRY(0xc70), TBL_ENTRY(0xc71), TBL_ENTRY(0xc72), TBL_ENTRY(0xc73),
- TBL_ENTRY(0xc74), TBL_ENTRY(0xc75), TBL_ENTRY(0xc76), TBL_ENTRY(0xc77),
- TBL_ENTRY(0xc78), TBL_ENTRY(0xc79), TBL_ENTRY(0xc7a), TBL_ENTRY(0xc7b),
- TBL_ENTRY(0xc7c), TBL_ENTRY(0xc7d), TBL_ENTRY(0xc7e), TBL_ENTRY(0xc7f),
- TBL_ENTRY(0xc80), TBL_ENTRY(0xc81), TBL_ENTRY(0xc82), TBL_ENTRY(0xc83),
- TBL_ENTRY(0xc84), TBL_ENTRY(0xc85), TBL_ENTRY(0xc86), TBL_ENTRY(0xc87),
- TBL_ENTRY(0xc88), TBL_ENTRY(0xc89), TBL_ENTRY(0xc8a), TBL_ENTRY(0xc8b),
- TBL_ENTRY(0xc8c), TBL_ENTRY(0xc8d), TBL_ENTRY(0xc8e), TBL_ENTRY(0xc8f),
- TBL_ENTRY(0xc90), TBL_ENTRY(0xc91), TBL_ENTRY(0xc92), TBL_ENTRY(0xc93),
- TBL_ENTRY(0xc94), TBL_ENTRY(0xc95), TBL_ENTRY(0xc96), TBL_ENTRY(0xc97),
- TBL_ENTRY(0xc98), TBL_ENTRY(0xc99), TBL_ENTRY(0xc9a), TBL_ENTRY(0xc9b),
- TBL_ENTRY(0xc9c), TBL_ENTRY(0xc9d), TBL_ENTRY(0xc9e), TBL_ENTRY(0xc9f),
- TBL_ENTRY(0xca0), TBL_ENTRY(0xca1), TBL_ENTRY(0xca2), TBL_ENTRY(0xca3),
- TBL_ENTRY(0xca4), TBL_ENTRY(0xca5), TBL_ENTRY(0xca6), TBL_ENTRY(0xca7),
- TBL_ENTRY(0xca8), TBL_ENTRY(0xca9), TBL_ENTRY(0xcaa), TBL_ENTRY(0xcab),
- TBL_ENTRY(0xcac), TBL_ENTRY(0xcad), TBL_ENTRY(0xcae), TBL_ENTRY(0xcaf),
- TBL_ENTRY(0xcb0), TBL_ENTRY(0xcb1), TBL_ENTRY(0xcb2), TBL_ENTRY(0xcb3),
- TBL_ENTRY(0xcb4), TBL_ENTRY(0xcb5), TBL_ENTRY(0xcb6), TBL_ENTRY(0xcb7),
- TBL_ENTRY(0xcb8), TBL_ENTRY(0xcb9), TBL_ENTRY(0xcba), TBL_ENTRY(0xcbb),
- TBL_ENTRY(0xcbc), TBL_ENTRY(0xcbd), TBL_ENTRY(0xcbe), TBL_ENTRY(0xcbf),
- TBL_ENTRY(0xcc0), TBL_ENTRY(0xcc1), TBL_ENTRY(0xcc2), TBL_ENTRY(0xcc3),
- TBL_ENTRY(0xcc4), TBL_ENTRY(0xcc5), TBL_ENTRY(0xcc6), TBL_ENTRY(0xcc7),
- TBL_ENTRY(0xcc8), TBL_ENTRY(0xcc9), TBL_ENTRY(0xcca), TBL_ENTRY(0xccb),
- TBL_ENTRY(0xccc), TBL_ENTRY(0xccd), TBL_ENTRY(0xcce), TBL_ENTRY(0xccf),
- TBL_ENTRY(0xcd0), TBL_ENTRY(0xcd1), TBL_ENTRY(0xcd2), TBL_ENTRY(0xcd3),
- TBL_ENTRY(0xcd4), TBL_ENTRY(0xcd5), TBL_ENTRY(0xcd6), TBL_ENTRY(0xcd7),
- TBL_ENTRY(0xcd8), TBL_ENTRY(0xcd9), TBL_ENTRY(0xcda), TBL_ENTRY(0xcdb),
- TBL_ENTRY(0xcdc), TBL_ENTRY(0xcdd), TBL_ENTRY(0xcde), TBL_ENTRY(0xcdf),
- TBL_ENTRY(0xce0), TBL_ENTRY(0xce1), TBL_ENTRY(0xce2), TBL_ENTRY(0xce3),
- TBL_ENTRY(0xce4), TBL_ENTRY(0xce5), TBL_ENTRY(0xce6), TBL_ENTRY(0xce7),
- TBL_ENTRY(0xce8), TBL_ENTRY(0xce9), TBL_ENTRY(0xcea), TBL_ENTRY(0xceb),
- TBL_ENTRY(0xcec), TBL_ENTRY(0xced), TBL_ENTRY(0xcee), TBL_ENTRY(0xcef),
- TBL_ENTRY(0xcf0), TBL_ENTRY(0xcf1), TBL_ENTRY(0xcf2), TBL_ENTRY(0xcf3),
- TBL_ENTRY(0xcf4), TBL_ENTRY(0xcf5), TBL_ENTRY(0xcf6), TBL_ENTRY(0xcf7),
- TBL_ENTRY(0xcf8), TBL_ENTRY(0xcf9), TBL_ENTRY(0xcfa), TBL_ENTRY(0xcfb),
- TBL_ENTRY(0xcfc), TBL_ENTRY(0xcfd), TBL_ENTRY(0xcfe), TBL_ENTRY(0xcff),
- TBL_ENTRY(0xd00), TBL_ENTRY(0xd01), TBL_ENTRY(0xd02), TBL_ENTRY(0xd03),
- TBL_ENTRY(0xd04), TBL_ENTRY(0xd05), TBL_ENTRY(0xd06), TBL_ENTRY(0xd07),
- TBL_ENTRY(0xd08), TBL_ENTRY(0xd09), TBL_ENTRY(0xd0a), TBL_ENTRY(0xd0b),
- TBL_ENTRY(0xd0c), TBL_ENTRY(0xd0d), TBL_ENTRY(0xd0e), TBL_ENTRY(0xd0f),
- TBL_ENTRY(0xd10), TBL_ENTRY(0xd11), TBL_ENTRY(0xd12), TBL_ENTRY(0xd13),
- TBL_ENTRY(0xd14), TBL_ENTRY(0xd15), TBL_ENTRY(0xd16), TBL_ENTRY(0xd17),
- TBL_ENTRY(0xd18), TBL_ENTRY(0xd19), TBL_ENTRY(0xd1a), TBL_ENTRY(0xd1b),
- TBL_ENTRY(0xd1c), TBL_ENTRY(0xd1d), TBL_ENTRY(0xd1e), TBL_ENTRY(0xd1f),
- TBL_ENTRY(0xd20), TBL_ENTRY(0xd21), TBL_ENTRY(0xd22), TBL_ENTRY(0xd23),
- TBL_ENTRY(0xd24), TBL_ENTRY(0xd25), TBL_ENTRY(0xd26), TBL_ENTRY(0xd27),
- TBL_ENTRY(0xd28), TBL_ENTRY(0xd29), TBL_ENTRY(0xd2a), TBL_ENTRY(0xd2b),
- TBL_ENTRY(0xd2c), TBL_ENTRY(0xd2d), TBL_ENTRY(0xd2e), TBL_ENTRY(0xd2f),
- TBL_ENTRY(0xd30), TBL_ENTRY(0xd31), TBL_ENTRY(0xd32), TBL_ENTRY(0xd33),
- TBL_ENTRY(0xd34), TBL_ENTRY(0xd35), TBL_ENTRY(0xd36), TBL_ENTRY(0xd37),
- TBL_ENTRY(0xd38), TBL_ENTRY(0xd39), TBL_ENTRY(0xd3a), TBL_ENTRY(0xd3b),
- TBL_ENTRY(0xd3c), TBL_ENTRY(0xd3d), TBL_ENTRY(0xd3e), TBL_ENTRY(0xd3f),
- TBL_ENTRY(0xd40), TBL_ENTRY(0xd41), TBL_ENTRY(0xd42), TBL_ENTRY(0xd43),
- TBL_ENTRY(0xd44), TBL_ENTRY(0xd45), TBL_ENTRY(0xd46), TBL_ENTRY(0xd47),
- TBL_ENTRY(0xd48), TBL_ENTRY(0xd49), TBL_ENTRY(0xd4a), TBL_ENTRY(0xd4b),
- TBL_ENTRY(0xd4c), TBL_ENTRY(0xd4d), TBL_ENTRY(0xd4e), TBL_ENTRY(0xd4f),
- TBL_ENTRY(0xd50), TBL_ENTRY(0xd51), TBL_ENTRY(0xd52), TBL_ENTRY(0xd53),
- TBL_ENTRY(0xd54), TBL_ENTRY(0xd55), TBL_ENTRY(0xd56), TBL_ENTRY(0xd57),
- TBL_ENTRY(0xd58), TBL_ENTRY(0xd59), TBL_ENTRY(0xd5a), TBL_ENTRY(0xd5b),
- TBL_ENTRY(0xd5c), TBL_ENTRY(0xd5d), TBL_ENTRY(0xd5e), TBL_ENTRY(0xd5f),
- TBL_ENTRY(0xd60), TBL_ENTRY(0xd61), TBL_ENTRY(0xd62), TBL_ENTRY(0xd63),
- TBL_ENTRY(0xd64), TBL_ENTRY(0xd65), TBL_ENTRY(0xd66), TBL_ENTRY(0xd67),
- TBL_ENTRY(0xd68), TBL_ENTRY(0xd69), TBL_ENTRY(0xd6a), TBL_ENTRY(0xd6b),
- TBL_ENTRY(0xd6c), TBL_ENTRY(0xd6d), TBL_ENTRY(0xd6e), TBL_ENTRY(0xd6f),
- TBL_ENTRY(0xd70), TBL_ENTRY(0xd71), TBL_ENTRY(0xd72), TBL_ENTRY(0xd73),
- TBL_ENTRY(0xd74), TBL_ENTRY(0xd75), TBL_ENTRY(0xd76), TBL_ENTRY(0xd77),
- TBL_ENTRY(0xd78), TBL_ENTRY(0xd79), TBL_ENTRY(0xd7a), TBL_ENTRY(0xd7b),
- TBL_ENTRY(0xd7c), TBL_ENTRY(0xd7d), TBL_ENTRY(0xd7e), TBL_ENTRY(0xd7f),
- TBL_ENTRY(0xd80), TBL_ENTRY(0xd81), TBL_ENTRY(0xd82), TBL_ENTRY(0xd83),
- TBL_ENTRY(0xd84), TBL_ENTRY(0xd85), TBL_ENTRY(0xd86), TBL_ENTRY(0xd87),
- TBL_ENTRY(0xd88), TBL_ENTRY(0xd89), TBL_ENTRY(0xd8a), TBL_ENTRY(0xd8b),
- TBL_ENTRY(0xd8c), TBL_ENTRY(0xd8d), TBL_ENTRY(0xd8e), TBL_ENTRY(0xd8f),
- TBL_ENTRY(0xd90), TBL_ENTRY(0xd91), TBL_ENTRY(0xd92), TBL_ENTRY(0xd93),
- TBL_ENTRY(0xd94), TBL_ENTRY(0xd95), TBL_ENTRY(0xd96), TBL_ENTRY(0xd97),
- TBL_ENTRY(0xd98), TBL_ENTRY(0xd99), TBL_ENTRY(0xd9a), TBL_ENTRY(0xd9b),
- TBL_ENTRY(0xd9c), TBL_ENTRY(0xd9d), TBL_ENTRY(0xd9e), TBL_ENTRY(0xd9f),
- TBL_ENTRY(0xda0), TBL_ENTRY(0xda1), TBL_ENTRY(0xda2), TBL_ENTRY(0xda3),
- TBL_ENTRY(0xda4), TBL_ENTRY(0xda5), TBL_ENTRY(0xda6), TBL_ENTRY(0xda7),
- TBL_ENTRY(0xda8), TBL_ENTRY(0xda9), TBL_ENTRY(0xdaa), TBL_ENTRY(0xdab),
- TBL_ENTRY(0xdac), TBL_ENTRY(0xdad), TBL_ENTRY(0xdae), TBL_ENTRY(0xdaf),
- TBL_ENTRY(0xdb0), TBL_ENTRY(0xdb1), TBL_ENTRY(0xdb2), TBL_ENTRY(0xdb3),
- TBL_ENTRY(0xdb4), TBL_ENTRY(0xdb5), TBL_ENTRY(0xdb6), TBL_ENTRY(0xdb7),
- TBL_ENTRY(0xdb8), TBL_ENTRY(0xdb9), TBL_ENTRY(0xdba), TBL_ENTRY(0xdbb),
- TBL_ENTRY(0xdbc), TBL_ENTRY(0xdbd), TBL_ENTRY(0xdbe), TBL_ENTRY(0xdbf),
- TBL_ENTRY(0xdc0), TBL_ENTRY(0xdc1), TBL_ENTRY(0xdc2), TBL_ENTRY(0xdc3),
- TBL_ENTRY(0xdc4), TBL_ENTRY(0xdc5), TBL_ENTRY(0xdc6), TBL_ENTRY(0xdc7),
- TBL_ENTRY(0xdc8), TBL_ENTRY(0xdc9), TBL_ENTRY(0xdca), TBL_ENTRY(0xdcb),
- TBL_ENTRY(0xdcc), TBL_ENTRY(0xdcd), TBL_ENTRY(0xdce), TBL_ENTRY(0xdcf),
- TBL_ENTRY(0xdd0), TBL_ENTRY(0xdd1), TBL_ENTRY(0xdd2), TBL_ENTRY(0xdd3),
- TBL_ENTRY(0xdd4), TBL_ENTRY(0xdd5), TBL_ENTRY(0xdd6), TBL_ENTRY(0xdd7),
- TBL_ENTRY(0xdd8), TBL_ENTRY(0xdd9), TBL_ENTRY(0xdda), TBL_ENTRY(0xddb),
- TBL_ENTRY(0xddc), TBL_ENTRY(0xddd), TBL_ENTRY(0xdde), TBL_ENTRY(0xddf),
- TBL_ENTRY(0xde0), TBL_ENTRY(0xde1), TBL_ENTRY(0xde2), TBL_ENTRY(0xde3),
- TBL_ENTRY(0xde4), TBL_ENTRY(0xde5), TBL_ENTRY(0xde6), TBL_ENTRY(0xde7),
- TBL_ENTRY(0xde8), TBL_ENTRY(0xde9), TBL_ENTRY(0xdea), TBL_ENTRY(0xdeb),
- TBL_ENTRY(0xdec), TBL_ENTRY(0xded), TBL_ENTRY(0xdee), TBL_ENTRY(0xdef),
- TBL_ENTRY(0xdf0), TBL_ENTRY(0xdf1), TBL_ENTRY(0xdf2), TBL_ENTRY(0xdf3),
- TBL_ENTRY(0xdf4), TBL_ENTRY(0xdf5), TBL_ENTRY(0xdf6), TBL_ENTRY(0xdf7),
- TBL_ENTRY(0xdf8), TBL_ENTRY(0xdf9), TBL_ENTRY(0xdfa), TBL_ENTRY(0xdfb),
- TBL_ENTRY(0xdfc), TBL_ENTRY(0xdfd), TBL_ENTRY(0xdfe), TBL_ENTRY(0xdff),
- TBL_ENTRY(0xe00), TBL_ENTRY(0xe01), TBL_ENTRY(0xe02), TBL_ENTRY(0xe03),
- TBL_ENTRY(0xe04), TBL_ENTRY(0xe05), TBL_ENTRY(0xe06), TBL_ENTRY(0xe07),
- TBL_ENTRY(0xe08), TBL_ENTRY(0xe09), TBL_ENTRY(0xe0a), TBL_ENTRY(0xe0b),
- TBL_ENTRY(0xe0c), TBL_ENTRY(0xe0d), TBL_ENTRY(0xe0e), TBL_ENTRY(0xe0f),
- TBL_ENTRY(0xe10), TBL_ENTRY(0xe11), TBL_ENTRY(0xe12), TBL_ENTRY(0xe13),
- TBL_ENTRY(0xe14), TBL_ENTRY(0xe15), TBL_ENTRY(0xe16), TBL_ENTRY(0xe17),
- TBL_ENTRY(0xe18), TBL_ENTRY(0xe19), TBL_ENTRY(0xe1a), TBL_ENTRY(0xe1b),
- TBL_ENTRY(0xe1c), TBL_ENTRY(0xe1d), TBL_ENTRY(0xe1e), TBL_ENTRY(0xe1f),
- TBL_ENTRY(0xe20), TBL_ENTRY(0xe21), TBL_ENTRY(0xe22), TBL_ENTRY(0xe23),
- TBL_ENTRY(0xe24), TBL_ENTRY(0xe25), TBL_ENTRY(0xe26), TBL_ENTRY(0xe27),
- TBL_ENTRY(0xe28), TBL_ENTRY(0xe29), TBL_ENTRY(0xe2a), TBL_ENTRY(0xe2b),
- TBL_ENTRY(0xe2c), TBL_ENTRY(0xe2d), TBL_ENTRY(0xe2e), TBL_ENTRY(0xe2f),
- TBL_ENTRY(0xe30), TBL_ENTRY(0xe31), TBL_ENTRY(0xe32), TBL_ENTRY(0xe33),
- TBL_ENTRY(0xe34), TBL_ENTRY(0xe35), TBL_ENTRY(0xe36), TBL_ENTRY(0xe37),
- TBL_ENTRY(0xe38), TBL_ENTRY(0xe39), TBL_ENTRY(0xe3a), TBL_ENTRY(0xe3b),
- TBL_ENTRY(0xe3c), TBL_ENTRY(0xe3d), TBL_ENTRY(0xe3e), TBL_ENTRY(0xe3f),
- TBL_ENTRY(0xe40), TBL_ENTRY(0xe41), TBL_ENTRY(0xe42), TBL_ENTRY(0xe43),
- TBL_ENTRY(0xe44), TBL_ENTRY(0xe45), TBL_ENTRY(0xe46), TBL_ENTRY(0xe47),
- TBL_ENTRY(0xe48), TBL_ENTRY(0xe49), TBL_ENTRY(0xe4a), TBL_ENTRY(0xe4b),
- TBL_ENTRY(0xe4c), TBL_ENTRY(0xe4d), TBL_ENTRY(0xe4e), TBL_ENTRY(0xe4f),
- TBL_ENTRY(0xe50), TBL_ENTRY(0xe51), TBL_ENTRY(0xe52), TBL_ENTRY(0xe53),
- TBL_ENTRY(0xe54), TBL_ENTRY(0xe55), TBL_ENTRY(0xe56), TBL_ENTRY(0xe57),
- TBL_ENTRY(0xe58), TBL_ENTRY(0xe59), TBL_ENTRY(0xe5a), TBL_ENTRY(0xe5b),
- TBL_ENTRY(0xe5c), TBL_ENTRY(0xe5d), TBL_ENTRY(0xe5e), TBL_ENTRY(0xe5f),
- TBL_ENTRY(0xe60), TBL_ENTRY(0xe61), TBL_ENTRY(0xe62), TBL_ENTRY(0xe63),
- TBL_ENTRY(0xe64), TBL_ENTRY(0xe65), TBL_ENTRY(0xe66), TBL_ENTRY(0xe67),
- TBL_ENTRY(0xe68), TBL_ENTRY(0xe69), TBL_ENTRY(0xe6a), TBL_ENTRY(0xe6b),
- TBL_ENTRY(0xe6c), TBL_ENTRY(0xe6d), TBL_ENTRY(0xe6e), TBL_ENTRY(0xe6f),
- TBL_ENTRY(0xe70), TBL_ENTRY(0xe71), TBL_ENTRY(0xe72), TBL_ENTRY(0xe73),
- TBL_ENTRY(0xe74), TBL_ENTRY(0xe75), TBL_ENTRY(0xe76), TBL_ENTRY(0xe77),
- TBL_ENTRY(0xe78), TBL_ENTRY(0xe79), TBL_ENTRY(0xe7a), TBL_ENTRY(0xe7b),
- TBL_ENTRY(0xe7c), TBL_ENTRY(0xe7d), TBL_ENTRY(0xe7e), TBL_ENTRY(0xe7f),
- TBL_ENTRY(0xe80), TBL_ENTRY(0xe81), TBL_ENTRY(0xe82), TBL_ENTRY(0xe83),
- TBL_ENTRY(0xe84), TBL_ENTRY(0xe85), TBL_ENTRY(0xe86), TBL_ENTRY(0xe87),
- TBL_ENTRY(0xe88), TBL_ENTRY(0xe89), TBL_ENTRY(0xe8a), TBL_ENTRY(0xe8b),
- TBL_ENTRY(0xe8c), TBL_ENTRY(0xe8d), TBL_ENTRY(0xe8e), TBL_ENTRY(0xe8f),
- TBL_ENTRY(0xe90), TBL_ENTRY(0xe91), TBL_ENTRY(0xe92), TBL_ENTRY(0xe93),
- TBL_ENTRY(0xe94), TBL_ENTRY(0xe95), TBL_ENTRY(0xe96), TBL_ENTRY(0xe97),
- TBL_ENTRY(0xe98), TBL_ENTRY(0xe99), TBL_ENTRY(0xe9a), TBL_ENTRY(0xe9b),
- TBL_ENTRY(0xe9c), TBL_ENTRY(0xe9d), TBL_ENTRY(0xe9e), TBL_ENTRY(0xe9f),
- TBL_ENTRY(0xea0), TBL_ENTRY(0xea1), TBL_ENTRY(0xea2), TBL_ENTRY(0xea3),
- TBL_ENTRY(0xea4), TBL_ENTRY(0xea5), TBL_ENTRY(0xea6), TBL_ENTRY(0xea7),
- TBL_ENTRY(0xea8), TBL_ENTRY(0xea9), TBL_ENTRY(0xeaa), TBL_ENTRY(0xeab),
- TBL_ENTRY(0xeac), TBL_ENTRY(0xead), TBL_ENTRY(0xeae), TBL_ENTRY(0xeaf),
- TBL_ENTRY(0xeb0), TBL_ENTRY(0xeb1), TBL_ENTRY(0xeb2), TBL_ENTRY(0xeb3),
- TBL_ENTRY(0xeb4), TBL_ENTRY(0xeb5), TBL_ENTRY(0xeb6), TBL_ENTRY(0xeb7),
- TBL_ENTRY(0xeb8), TBL_ENTRY(0xeb9), TBL_ENTRY(0xeba), TBL_ENTRY(0xebb),
- TBL_ENTRY(0xebc), TBL_ENTRY(0xebd), TBL_ENTRY(0xebe), TBL_ENTRY(0xebf),
- TBL_ENTRY(0xec0), TBL_ENTRY(0xec1), TBL_ENTRY(0xec2), TBL_ENTRY(0xec3),
- TBL_ENTRY(0xec4), TBL_ENTRY(0xec5), TBL_ENTRY(0xec6), TBL_ENTRY(0xec7),
- TBL_ENTRY(0xec8), TBL_ENTRY(0xec9), TBL_ENTRY(0xeca), TBL_ENTRY(0xecb),
- TBL_ENTRY(0xecc), TBL_ENTRY(0xecd), TBL_ENTRY(0xece), TBL_ENTRY(0xecf),
- TBL_ENTRY(0xed0), TBL_ENTRY(0xed1), TBL_ENTRY(0xed2), TBL_ENTRY(0xed3),
- TBL_ENTRY(0xed4), TBL_ENTRY(0xed5), TBL_ENTRY(0xed6), TBL_ENTRY(0xed7),
- TBL_ENTRY(0xed8), TBL_ENTRY(0xed9), TBL_ENTRY(0xeda), TBL_ENTRY(0xedb),
- TBL_ENTRY(0xedc), TBL_ENTRY(0xedd), TBL_ENTRY(0xede), TBL_ENTRY(0xedf),
- TBL_ENTRY(0xee0), TBL_ENTRY(0xee1), TBL_ENTRY(0xee2), TBL_ENTRY(0xee3),
- TBL_ENTRY(0xee4), TBL_ENTRY(0xee5), TBL_ENTRY(0xee6), TBL_ENTRY(0xee7),
- TBL_ENTRY(0xee8), TBL_ENTRY(0xee9), TBL_ENTRY(0xeea), TBL_ENTRY(0xeeb),
- TBL_ENTRY(0xeec), TBL_ENTRY(0xeed), TBL_ENTRY(0xeee), TBL_ENTRY(0xeef),
- TBL_ENTRY(0xef0), TBL_ENTRY(0xef1), TBL_ENTRY(0xef2), TBL_ENTRY(0xef3),
- TBL_ENTRY(0xef4), TBL_ENTRY(0xef5), TBL_ENTRY(0xef6), TBL_ENTRY(0xef7),
- TBL_ENTRY(0xef8), TBL_ENTRY(0xef9), TBL_ENTRY(0xefa), TBL_ENTRY(0xefb),
- TBL_ENTRY(0xefc), TBL_ENTRY(0xefd), TBL_ENTRY(0xefe), TBL_ENTRY(0xeff),
- TBL_ENTRY(0xf00), TBL_ENTRY(0xf01), TBL_ENTRY(0xf02), TBL_ENTRY(0xf03),
- TBL_ENTRY(0xf04), TBL_ENTRY(0xf05), TBL_ENTRY(0xf06), TBL_ENTRY(0xf07),
- TBL_ENTRY(0xf08), TBL_ENTRY(0xf09), TBL_ENTRY(0xf0a), TBL_ENTRY(0xf0b),
- TBL_ENTRY(0xf0c), TBL_ENTRY(0xf0d), TBL_ENTRY(0xf0e), TBL_ENTRY(0xf0f),
- TBL_ENTRY(0xf10), TBL_ENTRY(0xf11), TBL_ENTRY(0xf12), TBL_ENTRY(0xf13),
- TBL_ENTRY(0xf14), TBL_ENTRY(0xf15), TBL_ENTRY(0xf16), TBL_ENTRY(0xf17),
- TBL_ENTRY(0xf18), TBL_ENTRY(0xf19), TBL_ENTRY(0xf1a), TBL_ENTRY(0xf1b),
- TBL_ENTRY(0xf1c), TBL_ENTRY(0xf1d), TBL_ENTRY(0xf1e), TBL_ENTRY(0xf1f),
- TBL_ENTRY(0xf20), TBL_ENTRY(0xf21), TBL_ENTRY(0xf22), TBL_ENTRY(0xf23),
- TBL_ENTRY(0xf24), TBL_ENTRY(0xf25), TBL_ENTRY(0xf26), TBL_ENTRY(0xf27),
- TBL_ENTRY(0xf28), TBL_ENTRY(0xf29), TBL_ENTRY(0xf2a), TBL_ENTRY(0xf2b),
- TBL_ENTRY(0xf2c), TBL_ENTRY(0xf2d), TBL_ENTRY(0xf2e), TBL_ENTRY(0xf2f),
- TBL_ENTRY(0xf30), TBL_ENTRY(0xf31), TBL_ENTRY(0xf32), TBL_ENTRY(0xf33),
- TBL_ENTRY(0xf34), TBL_ENTRY(0xf35), TBL_ENTRY(0xf36), TBL_ENTRY(0xf37),
- TBL_ENTRY(0xf38), TBL_ENTRY(0xf39), TBL_ENTRY(0xf3a), TBL_ENTRY(0xf3b),
- TBL_ENTRY(0xf3c), TBL_ENTRY(0xf3d), TBL_ENTRY(0xf3e), TBL_ENTRY(0xf3f),
- TBL_ENTRY(0xf40), TBL_ENTRY(0xf41), TBL_ENTRY(0xf42), TBL_ENTRY(0xf43),
- TBL_ENTRY(0xf44), TBL_ENTRY(0xf45), TBL_ENTRY(0xf46), TBL_ENTRY(0xf47),
- TBL_ENTRY(0xf48), TBL_ENTRY(0xf49), TBL_ENTRY(0xf4a), TBL_ENTRY(0xf4b),
- TBL_ENTRY(0xf4c), TBL_ENTRY(0xf4d), TBL_ENTRY(0xf4e), TBL_ENTRY(0xf4f),
- TBL_ENTRY(0xf50), TBL_ENTRY(0xf51), TBL_ENTRY(0xf52), TBL_ENTRY(0xf53),
- TBL_ENTRY(0xf54), TBL_ENTRY(0xf55), TBL_ENTRY(0xf56), TBL_ENTRY(0xf57),
- TBL_ENTRY(0xf58), TBL_ENTRY(0xf59), TBL_ENTRY(0xf5a), TBL_ENTRY(0xf5b),
- TBL_ENTRY(0xf5c), TBL_ENTRY(0xf5d), TBL_ENTRY(0xf5e), TBL_ENTRY(0xf5f),
- TBL_ENTRY(0xf60), TBL_ENTRY(0xf61), TBL_ENTRY(0xf62), TBL_ENTRY(0xf63),
- TBL_ENTRY(0xf64), TBL_ENTRY(0xf65), TBL_ENTRY(0xf66), TBL_ENTRY(0xf67),
- TBL_ENTRY(0xf68), TBL_ENTRY(0xf69), TBL_ENTRY(0xf6a), TBL_ENTRY(0xf6b),
- TBL_ENTRY(0xf6c), TBL_ENTRY(0xf6d), TBL_ENTRY(0xf6e), TBL_ENTRY(0xf6f),
- TBL_ENTRY(0xf70), TBL_ENTRY(0xf71), TBL_ENTRY(0xf72), TBL_ENTRY(0xf73),
- TBL_ENTRY(0xf74), TBL_ENTRY(0xf75), TBL_ENTRY(0xf76), TBL_ENTRY(0xf77),
- TBL_ENTRY(0xf78), TBL_ENTRY(0xf79), TBL_ENTRY(0xf7a), TBL_ENTRY(0xf7b),
- TBL_ENTRY(0xf7c), TBL_ENTRY(0xf7d), TBL_ENTRY(0xf7e), TBL_ENTRY(0xf7f),
- TBL_ENTRY(0xf80), TBL_ENTRY(0xf81), TBL_ENTRY(0xf82), TBL_ENTRY(0xf83),
- TBL_ENTRY(0xf84), TBL_ENTRY(0xf85), TBL_ENTRY(0xf86), TBL_ENTRY(0xf87),
- TBL_ENTRY(0xf88), TBL_ENTRY(0xf89), TBL_ENTRY(0xf8a), TBL_ENTRY(0xf8b),
- TBL_ENTRY(0xf8c), TBL_ENTRY(0xf8d), TBL_ENTRY(0xf8e), TBL_ENTRY(0xf8f),
- TBL_ENTRY(0xf90), TBL_ENTRY(0xf91), TBL_ENTRY(0xf92), TBL_ENTRY(0xf93),
- TBL_ENTRY(0xf94), TBL_ENTRY(0xf95), TBL_ENTRY(0xf96), TBL_ENTRY(0xf97),
- TBL_ENTRY(0xf98), TBL_ENTRY(0xf99), TBL_ENTRY(0xf9a), TBL_ENTRY(0xf9b),
- TBL_ENTRY(0xf9c), TBL_ENTRY(0xf9d), TBL_ENTRY(0xf9e), TBL_ENTRY(0xf9f),
- TBL_ENTRY(0xfa0), TBL_ENTRY(0xfa1), TBL_ENTRY(0xfa2), TBL_ENTRY(0xfa3),
- TBL_ENTRY(0xfa4), TBL_ENTRY(0xfa5), TBL_ENTRY(0xfa6), TBL_ENTRY(0xfa7),
- TBL_ENTRY(0xfa8), TBL_ENTRY(0xfa9), TBL_ENTRY(0xfaa), TBL_ENTRY(0xfab),
- TBL_ENTRY(0xfac), TBL_ENTRY(0xfad), TBL_ENTRY(0xfae), TBL_ENTRY(0xfaf),
- TBL_ENTRY(0xfb0), TBL_ENTRY(0xfb1), TBL_ENTRY(0xfb2), TBL_ENTRY(0xfb3),
- TBL_ENTRY(0xfb4), TBL_ENTRY(0xfb5), TBL_ENTRY(0xfb6), TBL_ENTRY(0xfb7),
- TBL_ENTRY(0xfb8), TBL_ENTRY(0xfb9), TBL_ENTRY(0xfba), TBL_ENTRY(0xfbb),
- TBL_ENTRY(0xfbc), TBL_ENTRY(0xfbd), TBL_ENTRY(0xfbe), TBL_ENTRY(0xfbf),
- TBL_ENTRY(0xfc0), TBL_ENTRY(0xfc1), TBL_ENTRY(0xfc2), TBL_ENTRY(0xfc3),
- TBL_ENTRY(0xfc4), TBL_ENTRY(0xfc5), TBL_ENTRY(0xfc6), TBL_ENTRY(0xfc7),
- TBL_ENTRY(0xfc8), TBL_ENTRY(0xfc9), TBL_ENTRY(0xfca), TBL_ENTRY(0xfcb),
- TBL_ENTRY(0xfcc), TBL_ENTRY(0xfcd), TBL_ENTRY(0xfce), TBL_ENTRY(0xfcf),
- TBL_ENTRY(0xfd0), TBL_ENTRY(0xfd1), TBL_ENTRY(0xfd2), TBL_ENTRY(0xfd3),
- TBL_ENTRY(0xfd4), TBL_ENTRY(0xfd5), TBL_ENTRY(0xfd6), TBL_ENTRY(0xfd7),
- TBL_ENTRY(0xfd8), TBL_ENTRY(0xfd9), TBL_ENTRY(0xfda), TBL_ENTRY(0xfdb),
- TBL_ENTRY(0xfdc), TBL_ENTRY(0xfdd), TBL_ENTRY(0xfde), TBL_ENTRY(0xfdf),
- TBL_ENTRY(0xfe0), TBL_ENTRY(0xfe1), TBL_ENTRY(0xfe2), TBL_ENTRY(0xfe3),
- TBL_ENTRY(0xfe4), TBL_ENTRY(0xfe5), TBL_ENTRY(0xfe6), TBL_ENTRY(0xfe7),
- TBL_ENTRY(0xfe8), TBL_ENTRY(0xfe9), TBL_ENTRY(0xfea), TBL_ENTRY(0xfeb),
- TBL_ENTRY(0xfec), TBL_ENTRY(0xfed), TBL_ENTRY(0xfee), TBL_ENTRY(0xfef),
- TBL_ENTRY(0xff0), TBL_ENTRY(0xff1), TBL_ENTRY(0xff2), TBL_ENTRY(0xff3),
- TBL_ENTRY(0xff4), TBL_ENTRY(0xff5), TBL_ENTRY(0xff6), TBL_ENTRY(0xff7),
- TBL_ENTRY(0xff8), TBL_ENTRY(0xff9), TBL_ENTRY(0xffa), TBL_ENTRY(0xffb),
- TBL_ENTRY(0xffc), TBL_ENTRY(0xffd), TBL_ENTRY(0xffe), TBL_ENTRY(0xfff),
-};
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
index 68b9d5f..b83582f 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
@@ -11,7 +11,7 @@
#undef DPLL_SSC_RATE_1PER
-void dpll_init(void)
+static void dpll_init(void)
{
u32 tmp;
@@ -42,7 +42,7 @@
writel(tmp, SC_DPLLCTRL2);
}
-void upll_init(void)
+static void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
@@ -82,7 +82,7 @@
writel(tmp, SC_UPLLCTRL);
}
-void vpll_init(void)
+static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
index b4dd799..2cc5df6 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
@@ -21,7 +21,7 @@
#endif
writel(tmp, SG_MEMCONF);
- /* Input ports must be enabled deasserting reset of cores */
+ /* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
index 8788916..bbc3dcb 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
@@ -9,7 +9,7 @@
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
-static inline void umc_start_ssif(void __iomem *ssif_base)
+static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
@@ -43,8 +43,8 @@
writel(0x00000001, ssif_base + UMC_DMDRST);
}
-void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
{
if (freq == 1333) {
writel(0x45990b11, dramcont + UMC_CMDCTLA);
@@ -119,7 +119,7 @@
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
-static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
index 2dcc089..1db90f8 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
@@ -11,7 +11,7 @@
#undef DPLL_SSC_RATE_1PER
-void dpll_init(void)
+static void dpll_init(void)
{
u32 tmp;
@@ -46,7 +46,7 @@
writel(tmp, SC_DPLLCTRL2);
}
-void stop_mpll(void)
+static void stop_mpll(void)
{
u32 tmp;
@@ -62,7 +62,7 @@
;
}
-void vpll_init(void)
+static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
index b4dd799..b7c4b10 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
@@ -21,8 +21,8 @@
#endif
writel(tmp, SG_MEMCONF);
- /* Input ports must be enabled deasserting reset of cores */
+ /* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
- tmp |= 0x1;
+ tmp |= 1 << 6;
writel(tmp, SG_IECTRL);
}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
index 1973ab0..2d1bde6 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
@@ -9,7 +9,7 @@
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
-static inline void umc_start_ssif(void __iomem *ssif_base)
+static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000001, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
@@ -52,8 +52,8 @@
writel(0x00000001, ssif_base + UMC_DMDRST);
}
-void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
{
writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
@@ -88,7 +88,7 @@
writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
}
-static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
index 4d87053..4b82700 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
@@ -9,7 +9,7 @@
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
-void dpll_init(void)
+static void dpll_init(void)
{
u32 tmp;
/*
@@ -54,7 +54,7 @@
writel(tmp, SC_DPLLCTRL2);
}
-void upll_init(void)
+static void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
@@ -94,7 +94,7 @@
writel(tmp, SC_UPLLCTRL);
}
-void vpll_init(void)
+static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
index 2e0f9ae..2fbc73a 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
@@ -9,7 +9,7 @@
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
-static inline void umc_start_ssif(void __iomem *ssif_base)
+static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
@@ -43,8 +43,8 @@
writel(0x00000001, ssif_base + UMC_DMDRST);
}
-void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
{
#ifdef CONFIG_DDR_STANDARD
writel(0x55990b11, dramcont + UMC_CMDCTLA);
@@ -99,7 +99,7 @@
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
-static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 651ca40..b69fd37 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -15,8 +15,6 @@
#include <asm/io.h>
#include <asm/secure.h>
-unsigned long gic_dist_addr;
-
static unsigned int read_id_pfr1(void)
{
unsigned int reg;
@@ -68,6 +66,12 @@
void __weak smp_kick_all_cpus(void)
{
+ unsigned long gic_dist_addr;
+
+ gic_dist_addr = get_gicd_base_address();
+ if (gic_dist_addr == -1)
+ return;
+
kick_secondary_cpus_gic(gic_dist_addr);
}
@@ -75,6 +79,7 @@
{
unsigned int reg;
unsigned itlinesnr, i;
+ unsigned long gic_dist_addr;
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
index 3fb876d..b80c357 100644
--- a/arch/arm/cpu/armv7/zynq/spl.c
+++ b/arch/arm/cpu/armv7/zynq/spl.c
@@ -20,9 +20,6 @@
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
- /* Set global data pointer. */
- gd = &gdata;
-
preloader_console_init();
arch_cpu_init();
board_init_r(NULL, 0);
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 4b3ee6e..9c6e824 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -94,7 +94,7 @@
b.gt loop_level
mov x0, #0
- msr csselr_el1, x0 /* resotre csselr_el1 */
+ msr csselr_el1, x0 /* restore csselr_el1 */
dsb sy
isb
mov lr, x15
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 8dd69b3..b94b56c 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -219,6 +219,12 @@
unsigned int resv4[2];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
+
+struct prm_device_inst {
+ unsigned int prm_rstctrl;
+ unsigned int prm_rsttime;
+ unsigned int prm_rstst;
+};
#else
/* Encapsulating core pll registers */
struct cm_wkuppll {
@@ -386,6 +392,11 @@
unsigned int cm_dll_ctrl;
};
+struct prm_device_inst {
+ unsigned int prm_rstctrl;
+ unsigned int prm_rstst;
+};
+
struct cm_dpll {
unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x04 */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index c67a080..d1aed58 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -39,6 +39,7 @@
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x44E10E0C
#define VTP1_CTRL_ADDR 0x48140E10
+#define PRM_DEVICE_INST 0x44E00F00
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x44E12000
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index efdecf4..29e3816 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -71,6 +71,7 @@
#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
#define USBPHYOCPSCP_MODULE_EN (1 << 1)
#define CM_DEVICE_INST 0x44df4100
+#define PRM_DEVICE_INST 0x44df4000
/* Control status register */
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 5e934da..7915518 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -97,8 +97,13 @@
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_FSL_ERRATUM_A008378
#else
#error SoC not defined
#endif
+#define FSL_IFC_COMPAT "fsl,ifc"
+#define FSL_QSPI_COMPAT "fsl,ls1-qspi"
+#define FSL_DSPI_COMPAT "fsl,vf610-dspi"
+
#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h
new file mode 100644
index 0000000..b704436
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_LS102XA_GPIO_H_
+#define __ASM_ARCH_LS102XA_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 697d4ca..f70d568 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -105,6 +105,8 @@
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
+#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
+#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
#define SCFG_QSPI_CLKSEL 0xc0100000
@@ -456,6 +458,8 @@
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
+#define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
index 132d58c..748b802 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -28,6 +28,12 @@
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x00000000
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
+
#define R8A7790_CUT_ES2X 2
#define IS_R8A7790_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index d2cbcd7..1d06b65 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -17,6 +17,11 @@
/* SH-I2C */
#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793.h b/arch/arm/include/asm/arch-rmobile/r8a7793.h
index 1abdeb7..3efc62a 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7793.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7793.h
@@ -18,6 +18,11 @@
/* SH-I2C */
#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h
index d7c9004..6d11fa4 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7794.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h
@@ -27,4 +27,9 @@
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x000001C0
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
#endif /* __ASM_ARCH_R8A7794_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index 23c4bba..d594cd7 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -82,6 +82,9 @@
#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000
#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
+
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
diff --git a/arch/arm/include/asm/arch-rmobile/sh_sdhi.h b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h
new file mode 100644
index 0000000..057bf3f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h
@@ -0,0 +1,168 @@
+/*
+ * drivers/mmc/sh-sdhi.h
+ *
+ * SD/MMC driver for Reneas rmobile ARM SoCs
+ *
+ * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2008-2009 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _SH_SDHI_H
+#define _SH_SDHI_H
+
+#define SDHI_CMD (0x0000 >> 1)
+#define SDHI_PORTSEL (0x0004 >> 1)
+#define SDHI_ARG0 (0x0008 >> 1)
+#define SDHI_ARG1 (0x000C >> 1)
+#define SDHI_STOP (0x0010 >> 1)
+#define SDHI_SECCNT (0x0014 >> 1)
+#define SDHI_RSP00 (0x0018 >> 1)
+#define SDHI_RSP01 (0x001C >> 1)
+#define SDHI_RSP02 (0x0020 >> 1)
+#define SDHI_RSP03 (0x0024 >> 1)
+#define SDHI_RSP04 (0x0028 >> 1)
+#define SDHI_RSP05 (0x002C >> 1)
+#define SDHI_RSP06 (0x0030 >> 1)
+#define SDHI_RSP07 (0x0034 >> 1)
+#define SDHI_INFO1 (0x0038 >> 1)
+#define SDHI_INFO2 (0x003C >> 1)
+#define SDHI_INFO1_MASK (0x0040 >> 1)
+#define SDHI_INFO2_MASK (0x0044 >> 1)
+#define SDHI_CLK_CTRL (0x0048 >> 1)
+#define SDHI_SIZE (0x004C >> 1)
+#define SDHI_OPTION (0x0050 >> 1)
+#define SDHI_ERR_STS1 (0x0058 >> 1)
+#define SDHI_ERR_STS2 (0x005C >> 1)
+#define SDHI_BUF0 (0x0060 >> 1)
+#define SDHI_SDIO_MODE (0x0068 >> 1)
+#define SDHI_SDIO_INFO1 (0x006C >> 1)
+#define SDHI_SDIO_INFO1_MASK (0x0070 >> 1)
+#define SDHI_CC_EXT_MODE (0x01B0 >> 1)
+#define SDHI_SOFT_RST (0x01C0 >> 1)
+#define SDHI_VERSION (0x01C4 >> 1)
+#define SDHI_HOST_MODE (0x01C8 >> 1)
+#define SDHI_SDIF_MODE (0x01CC >> 1)
+#define SDHI_EXT_SWAP (0x01E0 >> 1)
+#define SDHI_SD_DMACR (0x0324 >> 1)
+
+/* SDHI CMD VALUE */
+#define CMD_MASK 0x0000ffff
+#define SDHI_APP 0x0040
+#define SDHI_SD_APP_SEND_SCR 0x0073
+#define SDHI_SD_SWITCH 0x1C06
+
+/* SDHI_PORTSEL */
+#define USE_1PORT (1 << 8) /* 1 port */
+
+/* SDHI_ARG */
+#define ARG0_MASK 0x0000ffff
+#define ARG1_MASK 0x0000ffff
+
+/* SDHI_STOP */
+#define STOP_SEC_ENABLE (1 << 8)
+
+/* SDHI_INFO1 */
+#define INFO1_RESP_END (1 << 0)
+#define INFO1_ACCESS_END (1 << 2)
+#define INFO1_CARD_RE (1 << 3)
+#define INFO1_CARD_IN (1 << 4)
+#define INFO1_ISD0CD (1 << 5)
+#define INFO1_WRITE_PRO (1 << 7)
+#define INFO1_DATA3_CARD_RE (1 << 8)
+#define INFO1_DATA3_CARD_IN (1 << 9)
+#define INFO1_DATA3 (1 << 10)
+
+/* SDHI_INFO2 */
+#define INFO2_CMD_ERROR (1 << 0)
+#define INFO2_CRC_ERROR (1 << 1)
+#define INFO2_END_ERROR (1 << 2)
+#define INFO2_TIMEOUT (1 << 3)
+#define INFO2_BUF_ILL_WRITE (1 << 4)
+#define INFO2_BUF_ILL_READ (1 << 5)
+#define INFO2_RESP_TIMEOUT (1 << 6)
+#define INFO2_SDDAT0 (1 << 7)
+#define INFO2_BRE_ENABLE (1 << 8)
+#define INFO2_BWE_ENABLE (1 << 9)
+#define INFO2_CBUSY (1 << 14)
+#define INFO2_ILA (1 << 15)
+#define INFO2_ALL_ERR (0x807f)
+
+/* SDHI_INFO1_MASK */
+#define INFO1M_RESP_END (1 << 0)
+#define INFO1M_ACCESS_END (1 << 2)
+#define INFO1M_CARD_RE (1 << 3)
+#define INFO1M_CARD_IN (1 << 4)
+#define INFO1M_DATA3_CARD_RE (1 << 8)
+#define INFO1M_DATA3_CARD_IN (1 << 9)
+#define INFO1M_ALL (0xffff)
+#define INFO1M_SET (INFO1M_RESP_END | \
+ INFO1M_ACCESS_END | \
+ INFO1M_DATA3_CARD_RE | \
+ INFO1M_DATA3_CARD_IN)
+
+/* SDHI_INFO2_MASK */
+#define INFO2M_CMD_ERROR (1 << 0)
+#define INFO2M_CRC_ERROR (1 << 1)
+#define INFO2M_END_ERROR (1 << 2)
+#define INFO2M_TIMEOUT (1 << 3)
+#define INFO2M_BUF_ILL_WRITE (1 << 4)
+#define INFO2M_BUF_ILL_READ (1 << 5)
+#define INFO2M_RESP_TIMEOUT (1 << 6)
+#define INFO2M_BRE_ENABLE (1 << 8)
+#define INFO2M_BWE_ENABLE (1 << 9)
+#define INFO2M_ILA (1 << 15)
+#define INFO2M_ALL (0xffff)
+#define INFO2M_ALL_ERR (0x807f)
+
+/* SDHI_CLK_CTRL */
+#define CLK_ENABLE (1 << 8)
+
+/* SDHI_OPTION */
+#define OPT_BUS_WIDTH_1 (1 << 15) /* bus width = 1 bit */
+
+/* SDHI_ERR_STS1 */
+#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \
+ (1 << 8) | (1 << 5))
+#define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \
+ (1 << 1) | (1 << 0))
+
+/* SDHI_ERR_STS2 */
+#define ERR_STS2_RES_TIMEOUT (1 << 0)
+#define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1))
+#define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \
+ (1 << 3) | (1 << 2) | (1 << 1) | \
+ (1 << 0))
+
+/* SDHI_SDIO_MODE */
+#define SDIO_MODE_ON (1 << 0)
+#define SDIO_MODE_OFF (0 << 0)
+
+/* SDHI_SDIO_INFO1 */
+#define SDIO_INFO1_IOIRQ (1 << 0)
+#define SDIO_INFO1_EXPUB52 (1 << 14)
+#define SDIO_INFO1_EXWT (1 << 15)
+
+/* SDHI_SDIO_INFO1_MASK */
+#define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2))
+#define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \
+ (1 << 1) | (1 << 0))
+
+/* SDHI_EXT_SWAP */
+#define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */
+
+/* SDHI_SOFT_RST */
+#define SOFT_RST_ON (0 << 0)
+#define SOFT_RST_OFF (1 << 0)
+
+#define CLKDEV_SD_DATA 25000000 /* 25 MHz */
+#define CLKDEV_HS_DATA 50000000 /* 50 MHz */
+#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
+#define CLKDEV_INIT 400000 /* 100 - 400 KHz */
+
+/* For quirk */
+#define SH_SDHI_QUIRK_16BIT_BUF (1)
+int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
+
+#endif /* _SH_SDHI_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 64acff3..3e5d999 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -17,6 +17,8 @@
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
#include <asm/arch/clock_sun6i.h>
+#elif defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/clock_sun9i.h>
#else
#include <asm/arch/clock_sun4i.h>
#endif
@@ -24,11 +26,6 @@
#ifndef __ASSEMBLY__
int clock_init(void);
int clock_twi_onoff(int port, int state);
-void clock_set_pll1(unsigned int hz);
-void clock_set_pll3(unsigned int hz);
-void clock_set_pll5(unsigned int hz);
-unsigned int clock_get_pll5p(void);
-unsigned int clock_get_pll6(void);
void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
void clock_init_safe(void);
void clock_init_uart(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index eb88969..05fbad3 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -182,14 +182,17 @@
#define AHB_GATE_OFFSET_USB_EHCI1 3
#define AHB_GATE_OFFSET_USB_OHCI0 2
#define AHB_GATE_OFFSET_USB_EHCI0 1
-#define AHB_GATE_OFFSET_USB 0
+#define AHB_GATE_OFFSET_USB0 0
/* ahb clock gate bit offset (second register) */
#define AHB_GATE_OFFSET_GMAC 17
+#define AHB_GATE_OFFSET_DE_FE0 14
#define AHB_GATE_OFFSET_DE_BE0 12
#define AHB_GATE_OFFSET_HDMI 11
#define AHB_GATE_OFFSET_LCD1 5
#define AHB_GATE_OFFSET_LCD0 4
+#define AHB_GATE_OFFSET_TVE1 3
+#define AHB_GATE_OFFSET_TVE0 2
#define CCM_AHB_GATE_GPS (0x1 << 26)
#define CCM_AHB_GATE_SDRAM (0x1 << 14)
@@ -255,13 +258,19 @@
#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
#define CCM_MBUS_CTRL_GATE (0x1 << 31)
-#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
-#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
-#define CCM_MMC_CTRL_PLL5 (0x2 << 24)
+#define CCM_MMC_CTRL_M(x) ((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
+#define CCM_MMC_CTRL_N(x) ((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
+#define CCM_MMC_CTRL_PLL5 (0x2 << 24)
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
-#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
-
+#define CCM_DRAM_GATE_OFFSET_DE_FE1 24 /* Note the order of FE1 and */
+#define CCM_DRAM_GATE_OFFSET_DE_FE0 25 /* FE0 is swapped ! */
#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1 27
#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
@@ -279,6 +288,8 @@
/* Enable / disable both ch1 sclk1 and sclk2 at the same time */
#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15)
+#define CCM_LVDS_CTRL_RST (1 << 0)
+
#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
#define CCM_HDMI_CTRL_PLL3 (0 << 24)
@@ -295,10 +306,12 @@
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
#define CCM_USB_CTRL_PHYGATE (0x1 << 8)
-/* These 2 are sun6i only, define them as 0 on sun4i */
+/* These 3 are sun6i only, define them as 0 on sun4i */
+#define CCM_USB_CTRL_PHY0_CLK 0
#define CCM_USB_CTRL_PHY1_CLK 0
#define CCM_USB_CTRL_PHY2_CLK 0
@@ -311,4 +324,11 @@
#define CCM_DE_CTRL_RST (1 << 30)
#define CCM_DE_CTRL_GATE (1 << 31)
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
+unsigned int clock_get_pll5p(void);
+unsigned int clock_get_pll6(void);
+#endif
+
#endif /* _SUNXI_CLOCK_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 3599054..e101c54 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -173,7 +173,7 @@
#define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
#define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
-#define CCM_PLL1_CTRL_MAGIC (0x1 << 16)
+#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
@@ -185,6 +185,7 @@
#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
#define CCM_PLL5_CTRL_UPD (0x1 << 20)
+#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
@@ -203,6 +204,7 @@
#define AHB_GATE_OFFSET_USB_OHCI0 29
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
+#define AHB_GATE_OFFSET_USB0 24
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_MMC3 11
@@ -210,6 +212,7 @@
#define AHB_GATE_OFFSET_MMC1 9
#define AHB_GATE_OFFSET_MMC0 8
#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_SS 5
/* ahb_gate1 offsets */
#define AHB_GATE_OFFSET_DRC0 25
@@ -218,15 +221,20 @@
#define AHB_GATE_OFFSET_LCD1 5
#define AHB_GATE_OFFSET_LCD0 4
-#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
-#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
+#define CCM_MMC_CTRL_M(x) ((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
+#define CCM_MMC_CTRL_N(x) ((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
+#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
+#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
+#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
-#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
-
+#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
/* There is no global phy clk gate on sun6i, define as 0 */
#define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
@@ -250,6 +258,8 @@
#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24)
+/* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */
+#define CCM_LCD_CH0_CTRL_RST 0
#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
@@ -268,7 +278,13 @@
#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
#define CCM_HDMI_CTRL_GATE (0x1 << 31)
+#ifndef CONFIG_MACH_SUN8I
#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
+#else
+#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
+#endif
+
+#define CCM_PLL5_PATTERN 0xd1303333
/* ahb_reset0 offsets */
#define AHB_RESET_OFFSET_GMAC 17
@@ -278,8 +294,9 @@
#define AHB_RESET_OFFSET_MMC1 9
#define AHB_RESET_OFFSET_MMC0 8
#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
+#define AHB_RESET_OFFSET_SS 5
-/* ahb_reset0 offsets */
+/* ahb_reset1 offsets */
#define AHB_RESET_OFFSET_DRC0 25
#define AHB_RESET_OFFSET_DE_BE0 12
#define AHB_RESET_OFFSET_HDMI 11
@@ -303,4 +320,11 @@
#define CCM_DE_CTRL_PLL10 (5 << 24)
#define CCM_DE_CTRL_GATE (1 << 31)
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+unsigned int clock_get_pll6(void);
+#endif
+
#endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
new file mode 100644
index 0000000..c506b0a
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -0,0 +1,139 @@
+/*
+ * sun9i clock register definitions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN9I_H
+#define _SUNXI_CLOCK_SUN9I_H
+
+struct sunxi_ccm_reg {
+ u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */
+ u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */
+ u32 pll3_audio_cfg; /* 0x08 audio pll configuration */
+ u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */
+ u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */
+ u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */
+ u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */
+ u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */
+ u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */
+ u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */
+ u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */
+ u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */
+ u8 reserved1[0x20]; /* 0x30 */
+ u32 cpu_clk_source; /* 0x50 cpu clk source configuration */
+ u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */
+ u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */
+ u32 gtbus_cfg; /* 0x5c gtbus clock configuration */
+ u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */
+ u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */
+ u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */
+ u8 reserved2[0x04]; /* 0x6c */
+ u32 apb0_cfg; /* 0x70 apb0 clock configuration */
+ u32 apb1_cfg; /* 0x74 apb1 clock configuration */
+ u32 cci400_cfg; /* 0x78 cci400 clock configuration */
+ u8 reserved3[0x04]; /* 0x7c */
+ u32 ats_cfg; /* 0x80 ats clock configuration */
+ u32 trace_cfg; /* 0x84 trace clock configuration */
+ u8 reserved4[0xf8]; /* 0x88 */
+ u32 clk_output_a; /* 0x180 clk_output_a */
+ u32 clk_output_b; /* 0x184 clk_output_a */
+ u8 reserved5[0x278]; /* 0x188 */
+
+ u32 nand0_clk_cfg0; /* 0x400 nand0 clock configuration0 */
+ u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
+ u8 reserved6[0x08]; /* 0x408 */
+ u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */
+ u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */
+ u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */
+ u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */
+ u8 reserved7[0x08]; /* 0x420 */
+ u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
+ u32 ss_clk_cfg; /* 0x42c security system clock cfg */
+ u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */
+ u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */
+ u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */
+ u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */
+ u8 reserved8[0x50]; /* 0x440 */
+ u32 de_clk_cfg; /* 0x490 display engine clock configuration */
+ u8 reserved9[0x04]; /* 0x494 */
+ u32 mp_clk_cfg; /* 0x498 mp clock configuration */
+ u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */
+ u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */
+ u8 reserved10[0x1c]; /* 0x4a4 */
+ u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */
+ u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */
+ u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */
+ u32 fd_clk_cfg; /* 0x4cc FD module clock */
+ u32 ve_clk_cfg; /* 0x4d0 VE module clock */
+ u32 avs_clk_cfg; /* 0x4d4 AVS module clock */
+ u8 reserved11[0x18]; /* 0x4d8 */
+ u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */
+ u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */
+ u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */
+ u8 reserved12[0x10]; /* 0x4fc */
+ u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
+ u8 reserved13[0x70]; /* 0x510 */
+
+ u32 ahb_gate0; /* 0x580 AHB0 Gating Register */
+ u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
+ u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
+ u8 reserved14[0x04]; /* 0x58c */
+ u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */
+ u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */
+ u8 reserved15[0x08]; /* 0x598 */
+ u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */
+ u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */
+ u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */
+ u8 reserved16[0x04]; /* 0x5ac */
+ u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */
+ u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */
+};
+
+/* pll4_periph0_cfg */
+#define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */
+
+#define CCM_PLL4_CTRL_N_SHIFT 8
+#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT)
+#define CCM_PLL4_CTRL_P_SHIFT 16
+#define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT)
+#define CCM_PLL4_CTRL_M_SHIFT 18
+#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT)
+
+/* sd#_clk_cfg fields */
+#define CCM_MMC_CTRL_M(x) ((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
+#define CCM_MMC_CTRL_N(x) ((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
+#define CCM_MMC_CTRL_OSCM24 (0 << 24)
+#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24)
+#define CCM_MMC_CTRL_ENABLE (1 << 31)
+
+/* ahb_gate0 fields */
+/* On sun9i all sdc-s share their ahb gate, so ignore (x) */
+#define AHB_GATE_OFFSET_MMC(x) 8
+
+/* apb1_gate fields */
+#define APB1_GATE_UART_SHIFT 16
+#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
+#define APB1_GATE_TWI_SHIFT 0
+#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
+
+/* ahb_reset0_cfg fields */
+/* On sun9i all sdc-s share their ahb reset, so ignore (x) */
+#define AHB_RESET_OFFSET_MMC(x) 8
+
+/* apb1_reset_cfg fields */
+#define APB1_RESET_UART_SHIFT 16
+#define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT)
+#define APB1_RESET_TWI_SHIFT 0
+#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT)
+
+
+#ifndef __ASSEMBLY__
+unsigned int clock_get_pll4_periph0(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN9I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index 2c92b5c..73583ed 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -1,7 +1,5 @@
/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,139 +7,10 @@
#ifndef _SUNXI_CPU_H
#define _SUNXI_CPU_H
-#define SUNXI_SRAM_A1_BASE 0x00000000
-#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
-
-#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
-#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
-#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
-#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
-#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
-
-#define SUNXI_SRAMC_BASE 0x01c00000
-#define SUNXI_DRAMC_BASE 0x01c01000
-#define SUNXI_DMA_BASE 0x01c02000
-#define SUNXI_NFC_BASE 0x01c03000
-#define SUNXI_TS_BASE 0x01c04000
-#define SUNXI_SPI0_BASE 0x01c05000
-#define SUNXI_SPI1_BASE 0x01c06000
-#define SUNXI_MS_BASE 0x01c07000
-#define SUNXI_TVD_BASE 0x01c08000
-#define SUNXI_CSI0_BASE 0x01c09000
-#define SUNXI_TVE0_BASE 0x01c0a000
-#define SUNXI_EMAC_BASE 0x01c0b000
-#define SUNXI_LCD0_BASE 0x01c0C000
-#define SUNXI_LCD1_BASE 0x01c0d000
-#define SUNXI_VE_BASE 0x01c0e000
-#define SUNXI_MMC0_BASE 0x01c0f000
-#define SUNXI_MMC1_BASE 0x01c10000
-#define SUNXI_MMC2_BASE 0x01c11000
-#define SUNXI_MMC3_BASE 0x01c12000
-#ifndef CONFIG_MACH_SUN6I
-#define SUNXI_USB0_BASE 0x01c13000
-#define SUNXI_USB1_BASE 0x01c14000
-#endif
-#define SUNXI_SS_BASE 0x01c15000
-#define SUNXI_HDMI_BASE 0x01c16000
-#define SUNXI_SPI2_BASE 0x01c17000
-#define SUNXI_SATA_BASE 0x01c18000
-#ifndef CONFIG_MACH_SUN6I
-#define SUNXI_PATA_BASE 0x01c19000
-#define SUNXI_ACE_BASE 0x01c1a000
-#define SUNXI_TVE1_BASE 0x01c1b000
-#define SUNXI_USB2_BASE 0x01c1c000
+#if defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/cpu_sun9i.h>
#else
-#define SUNXI_USB0_BASE 0x01c19000
-#define SUNXI_USB1_BASE 0x01c1a000
-#define SUNXI_USB2_BASE 0x01c1b000
-#endif
-#define SUNXI_CSI1_BASE 0x01c1d000
-#define SUNXI_TZASC_BASE 0x01c1e000
-#define SUNXI_SPI3_BASE 0x01c1f000
-
-#define SUNXI_CCM_BASE 0x01c20000
-#define SUNXI_INTC_BASE 0x01c20400
-#define SUNXI_PIO_BASE 0x01c20800
-#define SUNXI_TIMER_BASE 0x01c20c00
-#define SUNXI_SPDIF_BASE 0x01c21000
-#define SUNXI_AC97_BASE 0x01c21400
-#define SUNXI_IR0_BASE 0x01c21800
-#define SUNXI_IR1_BASE 0x01c21c00
-
-#define SUNXI_IIS_BASE 0x01c22400
-#define SUNXI_LRADC_BASE 0x01c22800
-#define SUNXI_AD_DA_BASE 0x01c22c00
-#define SUNXI_KEYPAD_BASE 0x01c23000
-#define SUNXI_TZPC_BASE 0x01c23400
-#define SUNXI_SID_BASE 0x01c23800
-#define SUNXI_SJTAG_BASE 0x01c23c00
-
-#define SUNXI_TP_BASE 0x01c25000
-#define SUNXI_PMU_BASE 0x01c25400
-#define SUN7I_CPUCFG_BASE 0x01c25c00
-
-#define SUNXI_UART0_BASE 0x01c28000
-#define SUNXI_UART1_BASE 0x01c28400
-#define SUNXI_UART2_BASE 0x01c28800
-#define SUNXI_UART3_BASE 0x01c28c00
-#define SUNXI_UART4_BASE 0x01c29000
-#define SUNXI_UART5_BASE 0x01c29400
-#define SUNXI_UART6_BASE 0x01c29800
-#define SUNXI_UART7_BASE 0x01c29c00
-#define SUNXI_PS2_0_BASE 0x01c2a000
-#define SUNXI_PS2_1_BASE 0x01c2a400
-
-#define SUNXI_TWI0_BASE 0x01c2ac00
-#define SUNXI_TWI1_BASE 0x01c2b000
-#define SUNXI_TWI2_BASE 0x01c2b400
-
-#define SUNXI_CAN_BASE 0x01c2bc00
-
-#define SUNXI_SCR_BASE 0x01c2c400
-
-#ifndef CONFIG_MACH_SUN6I
-#define SUNXI_GPS_BASE 0x01c30000
-#define SUNXI_MALI400_BASE 0x01c40000
-#define SUNXI_GMAC_BASE 0x01c50000
-#else
-#define SUNXI_GMAC_BASE 0x01c30000
+#include <asm/arch/cpu_sun4i.h>
#endif
-#define SUNXI_DRAM_COM_BASE 0x01c62000
-#define SUNXI_DRAM_CTL0_BASE 0x01c63000
-#define SUNXI_DRAM_CTL1_BASE 0x01c64000
-#define SUNXI_DRAM_PHY0_BASE 0x01c65000
-#define SUNXI_DRAM_PHY1_BASE 0x01c66000
-
-/* module sram */
-#define SUNXI_SRAM_C_BASE 0x01d00000
-
-#define SUNXI_DE_FE0_BASE 0x01e00000
-#define SUNXI_DE_FE1_BASE 0x01e20000
-#define SUNXI_DE_BE0_BASE 0x01e60000
-#define SUNXI_DE_BE1_BASE 0x01e40000
-#define SUNXI_MP_BASE 0x01e80000
-#define SUNXI_AVG_BASE 0x01ea0000
-
-#define SUNXI_RTC_BASE 0x01f00000
-#define SUNXI_PRCM_BASE 0x01f01400
-#define SUN6I_CPUCFG_BASE 0x01f01c00
-#define SUNXI_R_UART_BASE 0x01f02800
-#define SUNXI_R_PIO_BASE 0x01f02c00
-#define SUNXI_P2WI_BASE 0x01f03400
-
-/* CoreSight Debug Module */
-#define SUNXI_CSDM_BASE 0x3f500000
-
-#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
-
-#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
-
-#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
-
-#ifndef __ASSEMBLY__
-void sunxi_board_init(void);
-void sunxi_reset(void);
-#endif /* __ASSEMBLY__ */
-
-#endif /* _CPU_H */
+#endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
new file mode 100644
index 0000000..dae6069
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN4I_H
+#define _SUNXI_CPU_SUN4I_H
+
+#define SUNXI_SRAM_A1_BASE 0x00000000
+#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
+
+#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
+#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
+#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
+#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
+#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
+
+#define SUNXI_SRAMC_BASE 0x01c00000
+#define SUNXI_DRAMC_BASE 0x01c01000
+#define SUNXI_DMA_BASE 0x01c02000
+#define SUNXI_NFC_BASE 0x01c03000
+#define SUNXI_TS_BASE 0x01c04000
+#define SUNXI_SPI0_BASE 0x01c05000
+#define SUNXI_SPI1_BASE 0x01c06000
+#define SUNXI_MS_BASE 0x01c07000
+#define SUNXI_TVD_BASE 0x01c08000
+#define SUNXI_CSI0_BASE 0x01c09000
+#define SUNXI_TVE0_BASE 0x01c0a000
+#define SUNXI_EMAC_BASE 0x01c0b000
+#define SUNXI_LCD0_BASE 0x01c0C000
+#define SUNXI_LCD1_BASE 0x01c0d000
+#define SUNXI_VE_BASE 0x01c0e000
+#define SUNXI_MMC0_BASE 0x01c0f000
+#define SUNXI_MMC1_BASE 0x01c10000
+#define SUNXI_MMC2_BASE 0x01c11000
+#define SUNXI_MMC3_BASE 0x01c12000
+#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#define SUNXI_USB0_BASE 0x01c13000
+#define SUNXI_USB1_BASE 0x01c14000
+#endif
+#define SUNXI_SS_BASE 0x01c15000
+#define SUNXI_HDMI_BASE 0x01c16000
+#define SUNXI_SPI2_BASE 0x01c17000
+#define SUNXI_SATA_BASE 0x01c18000
+#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#define SUNXI_PATA_BASE 0x01c19000
+#define SUNXI_ACE_BASE 0x01c1a000
+#define SUNXI_TVE1_BASE 0x01c1b000
+#define SUNXI_USB2_BASE 0x01c1c000
+#else
+#define SUNXI_USB0_BASE 0x01c19000
+#define SUNXI_USB1_BASE 0x01c1a000
+#define SUNXI_USB2_BASE 0x01c1b000
+#endif
+#define SUNXI_CSI1_BASE 0x01c1d000
+#define SUNXI_TZASC_BASE 0x01c1e000
+#define SUNXI_SPI3_BASE 0x01c1f000
+
+#define SUNXI_CCM_BASE 0x01c20000
+#define SUNXI_INTC_BASE 0x01c20400
+#define SUNXI_PIO_BASE 0x01c20800
+#define SUNXI_TIMER_BASE 0x01c20c00
+#define SUNXI_SPDIF_BASE 0x01c21000
+#define SUNXI_AC97_BASE 0x01c21400
+#define SUNXI_IR0_BASE 0x01c21800
+#define SUNXI_IR1_BASE 0x01c21c00
+
+#define SUNXI_IIS_BASE 0x01c22400
+#define SUNXI_LRADC_BASE 0x01c22800
+#define SUNXI_AD_DA_BASE 0x01c22c00
+#define SUNXI_KEYPAD_BASE 0x01c23000
+#define SUNXI_TZPC_BASE 0x01c23400
+#define SUNXI_SID_BASE 0x01c23800
+#define SUNXI_SJTAG_BASE 0x01c23c00
+
+#define SUNXI_TP_BASE 0x01c25000
+#define SUNXI_PMU_BASE 0x01c25400
+#define SUN7I_CPUCFG_BASE 0x01c25c00
+
+#define SUNXI_UART0_BASE 0x01c28000
+#define SUNXI_UART1_BASE 0x01c28400
+#define SUNXI_UART2_BASE 0x01c28800
+#define SUNXI_UART3_BASE 0x01c28c00
+#define SUNXI_UART4_BASE 0x01c29000
+#define SUNXI_UART5_BASE 0x01c29400
+#define SUNXI_UART6_BASE 0x01c29800
+#define SUNXI_UART7_BASE 0x01c29c00
+#define SUNXI_PS2_0_BASE 0x01c2a000
+#define SUNXI_PS2_1_BASE 0x01c2a400
+
+#define SUNXI_TWI0_BASE 0x01c2ac00
+#define SUNXI_TWI1_BASE 0x01c2b000
+#define SUNXI_TWI2_BASE 0x01c2b400
+
+#define SUNXI_CAN_BASE 0x01c2bc00
+
+#define SUNXI_SCR_BASE 0x01c2c400
+
+#ifndef CONFIG_MACH_SUN6I
+#define SUNXI_GPS_BASE 0x01c30000
+#define SUNXI_MALI400_BASE 0x01c40000
+#define SUNXI_GMAC_BASE 0x01c50000
+#else
+#define SUNXI_GMAC_BASE 0x01c30000
+#endif
+
+#define SUNXI_DRAM_COM_BASE 0x01c62000
+#define SUNXI_DRAM_CTL0_BASE 0x01c63000
+#define SUNXI_DRAM_CTL1_BASE 0x01c64000
+#define SUNXI_DRAM_PHY0_BASE 0x01c65000
+#define SUNXI_DRAM_PHY1_BASE 0x01c66000
+
+/* module sram */
+#define SUNXI_SRAM_C_BASE 0x01d00000
+
+#define SUNXI_DE_FE0_BASE 0x01e00000
+#define SUNXI_DE_FE1_BASE 0x01e20000
+#define SUNXI_DE_BE0_BASE 0x01e60000
+#define SUNXI_DE_BE1_BASE 0x01e40000
+#define SUNXI_MP_BASE 0x01e80000
+#define SUNXI_AVG_BASE 0x01ea0000
+
+#define SUNXI_RTC_BASE 0x01f00000
+#define SUNXI_PRCM_BASE 0x01f01400
+#define SUN6I_CPUCFG_BASE 0x01f01c00
+#define SUNXI_R_UART_BASE 0x01f02800
+#define SUNXI_R_PIO_BASE 0x01f02c00
+#define SUN6I_P2WI_BASE 0x01f03400
+#define SUNXI_RSB_BASE 0x01f03400
+
+/* CoreSight Debug Module */
+#define SUNXI_CSDM_BASE 0x3f500000
+
+#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
+
+#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
+
+#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
+
+/* SS bonding ids used for cpu identification */
+#define SUNXI_SS_BOND_ID_A31 4
+#define SUNXI_SS_BOND_ID_A31S 5
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_ss_bonding_id(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SUNXI_CPU_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
new file mode 100644
index 0000000..a2a7839
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Jerry Wang <wangflord@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN9I_H
+#define _SUNXI_CPU_SUN9I_H
+
+#define REGS_AHB0_BASE 0x01C00000
+#define REGS_AHB1_BASE 0x00800000
+#define REGS_AHB2_BASE 0x03000000
+#define REGS_APB0_BASE 0x06000000
+#define REGS_APB1_BASE 0x07000000
+#define REGS_RCPUS_BASE 0x08000000
+
+#define SUNXI_SRAM_D_BASE 0x08100000
+
+/* AHB0 Module */
+#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
+#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
+
+#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000)
+#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000)
+#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000)
+#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000)
+#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000)
+
+#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000)
+#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000)
+#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000)
+#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000)
+
+#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000)
+#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000)
+#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000)
+
+/* AHB1 Module */
+#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000)
+#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000)
+#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000)
+#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000)
+#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000)
+
+/* AHB2 Module */
+#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
+#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000)
+#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
+#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
+#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
+
+#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
+#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
+#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000)
+
+#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000)
+#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000)
+#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000)
+#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000)
+
+#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
+#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
+#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
+#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000)
+/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */
+#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100)
+#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000)
+
+/* APB0 Module */
+#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
+#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
+#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
+#define SUNXI_R_PIO_BASE (0x08002C00)
+#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
+#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
+#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
+
+/* APB1 Module */
+#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000)
+#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400)
+#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800)
+#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00)
+#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000)
+#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400)
+#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800)
+#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00)
+#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000)
+#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400)
+#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800)
+
+/* RCPUS Module */
+#define SUNXI_RPRCM_BASE (REGS_RCPUS_BASE + 0x1400)
+#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
+
+/* Misc. */
+#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */
+#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif
+
+#endif /* _SUNXI_CPU_SUN9I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h
index ddb71c1..5e94253 100644
--- a/arch/arm/include/asm/arch-sunxi/display.h
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -9,6 +9,107 @@
#ifndef _SUNXI_DISPLAY_H
#define _SUNXI_DISPLAY_H
+struct sunxi_de_fe_reg {
+ u32 enable; /* 0x000 */
+ u32 frame_ctrl; /* 0x004 */
+ u32 bypass; /* 0x008 */
+ u32 algorithm_sel; /* 0x00c */
+ u32 line_int_ctrl; /* 0x010 */
+ u8 res0[0x0c]; /* 0x014 */
+ u32 ch0_addr; /* 0x020 */
+ u32 ch1_addr; /* 0x024 */
+ u32 ch2_addr; /* 0x028 */
+ u32 field_sequence; /* 0x02c */
+ u32 ch0_offset; /* 0x030 */
+ u32 ch1_offset; /* 0x034 */
+ u32 ch2_offset; /* 0x038 */
+ u8 res1[0x04]; /* 0x03c */
+ u32 ch0_stride; /* 0x040 */
+ u32 ch1_stride; /* 0x044 */
+ u32 ch2_stride; /* 0x048 */
+ u32 input_fmt; /* 0x04c */
+ u32 ch3_addr; /* 0x050 */
+ u32 ch4_addr; /* 0x054 */
+ u32 ch5_addr; /* 0x058 */
+ u32 output_fmt; /* 0x05c */
+ u32 int_enable; /* 0x060 */
+ u32 int_status; /* 0x064 */
+ u32 status; /* 0x068 */
+ u8 res2[0x04]; /* 0x06c */
+ u32 csc_coef00; /* 0x070 */
+ u32 csc_coef01; /* 0x074 */
+ u32 csc_coef02; /* 0x078 */
+ u32 csc_coef03; /* 0x07c */
+ u32 csc_coef10; /* 0x080 */
+ u32 csc_coef11; /* 0x084 */
+ u32 csc_coef12; /* 0x088 */
+ u32 csc_coef13; /* 0x08c */
+ u32 csc_coef20; /* 0x090 */
+ u32 csc_coef21; /* 0x094 */
+ u32 csc_coef22; /* 0x098 */
+ u32 csc_coef23; /* 0x09c */
+ u32 deinterlace_ctrl; /* 0x0a0 */
+ u32 deinterlace_diag; /* 0x0a4 */
+ u32 deinterlace_tempdiff; /* 0x0a8 */
+ u32 deinterlace_sawtooth; /* 0x0ac */
+ u32 deinterlace_spatcomp; /* 0x0b0 */
+ u32 deinterlace_burstlen; /* 0x0b4 */
+ u32 deinterlace_preluma; /* 0x0b8 */
+ u32 deinterlace_tile_addr; /* 0x0bc */
+ u32 deinterlace_tile_stride; /* 0x0c0 */
+ u8 res3[0x0c]; /* 0x0c4 */
+ u32 wb_stride_enable; /* 0x0d0 */
+ u32 ch3_stride; /* 0x0d4 */
+ u32 ch4_stride; /* 0x0d8 */
+ u32 ch5_stride; /* 0x0dc */
+ u32 fe_3d_ctrl; /* 0x0e0 */
+ u32 fe_3d_ch0_addr; /* 0x0e4 */
+ u32 fe_3d_ch1_addr; /* 0x0e8 */
+ u32 fe_3d_ch2_addr; /* 0x0ec */
+ u32 fe_3d_ch0_offset; /* 0x0f0 */
+ u32 fe_3d_ch1_offset; /* 0x0f4 */
+ u32 fe_3d_ch2_offset; /* 0x0f8 */
+ u8 res4[0x04]; /* 0x0fc */
+ u32 ch0_insize; /* 0x100 */
+ u32 ch0_outsize; /* 0x104 */
+ u32 ch0_horzfact; /* 0x108 */
+ u32 ch0_vertfact; /* 0x10c */
+ u32 ch0_horzphase; /* 0x110 */
+ u32 ch0_vertphase0; /* 0x114 */
+ u32 ch0_vertphase1; /* 0x118 */
+ u8 res5[0x04]; /* 0x11c */
+ u32 ch0_horztapoffset0; /* 0x120 */
+ u32 ch0_horztapoffset1; /* 0x124 */
+ u32 ch0_verttapoffset; /* 0x128 */
+ u8 res6[0xd4]; /* 0x12c */
+ u32 ch1_insize; /* 0x200 */
+ u32 ch1_outsize; /* 0x204 */
+ u32 ch1_horzfact; /* 0x208 */
+ u32 ch1_vertfact; /* 0x20c */
+ u32 ch1_horzphase; /* 0x210 */
+ u32 ch1_vertphase0; /* 0x214 */
+ u32 ch1_vertphase1; /* 0x218 */
+ u8 res7[0x04]; /* 0x21c */
+ u32 ch1_horztapoffset0; /* 0x220 */
+ u32 ch1_horztapoffset1; /* 0x224 */
+ u32 ch1_verttapoffset; /* 0x228 */
+ u8 res8[0x1d4]; /* 0x22c */
+ u32 ch0_horzcoef0[32]; /* 0x400 */
+ u32 ch0_horzcoef1[32]; /* 0x480 */
+ u32 ch0_vertcoef[32]; /* 0x500 */
+ u8 res9[0x80]; /* 0x580 */
+ u32 ch1_horzcoef0[32]; /* 0x600 */
+ u32 ch1_horzcoef1[32]; /* 0x680 */
+ u32 ch1_vertcoef[32]; /* 0x700 */
+ u8 res10[0x280]; /* 0x780 */
+ u32 vpp_enable; /* 0xa00 */
+ u32 vpp_dcti; /* 0xa04 */
+ u32 vpp_lp1; /* 0xa08 */
+ u32 vpp_lp2; /* 0xa0c */
+ u32 vpp_wle; /* 0xa10 */
+ u32 vpp_ble; /* 0xa14 */
+};
+
struct sunxi_de_be_reg {
u8 res0[0x800]; /* 0x000 */
u32 mode; /* 0x800 */
@@ -57,14 +158,16 @@
u32 int0; /* 0x04 */
u32 int1; /* 0x08 */
u8 res0[0x04]; /* 0x0c */
- u32 frame_ctrl; /* 0x10 */
- u8 res1[0x2c]; /* 0x14 */
+ u32 tcon0_frm_ctrl; /* 0x10 */
+ u32 tcon0_frm_seed[6]; /* 0x14 */
+ u32 tcon0_frm_table[4]; /* 0x2c */
+ u8 res1[4]; /* 0x3c */
u32 tcon0_ctrl; /* 0x40 */
u32 tcon0_dclk; /* 0x44 */
- u32 tcon0_basic_timing0; /* 0x48 */
- u32 tcon0_basic_timing1; /* 0x4c */
- u32 tcon0_basic_timing2; /* 0x50 */
- u32 tcon0_basic_timing3; /* 0x54 */
+ u32 tcon0_timing_active; /* 0x48 */
+ u32 tcon0_timing_h; /* 0x4c */
+ u32 tcon0_timing_v; /* 0x50 */
+ u32 tcon0_timing_sync; /* 0x54 */
u32 tcon0_hv_intf; /* 0x58 */
u8 res2[0x04]; /* 0x5c */
u32 tcon0_cpu_intf; /* 0x60 */
@@ -89,6 +192,9 @@
u8 res3[0x44]; /* 0xac */
u32 tcon1_io_polarity; /* 0xf0 */
u32 tcon1_io_tristate; /* 0xf4 */
+ u8 res4[0x128]; /* 0xf8 */
+ u32 lvds_ana0; /* 0x220 */
+ u32 lvds_ana1; /* 0x224 */
};
struct sunxi_hdmi_reg {
@@ -102,14 +208,123 @@
u32 video_fp; /* 0x01c */
u32 video_spw; /* 0x020 */
u32 video_polarity; /* 0x024 */
- u8 res0[0x1d8]; /* 0x028 */
+ u8 res0[0x58]; /* 0x028 */
+ u8 avi_info_frame[0x14]; /* 0x080 */
+ u8 res1[0x4c]; /* 0x094 */
+ u32 qcp_packet0; /* 0x0e0 */
+ u32 qcp_packet1; /* 0x0e4 */
+ u8 res2[0x118]; /* 0x0e8 */
u32 pad_ctrl0; /* 0x200 */
u32 pad_ctrl1; /* 0x204 */
u32 pll_ctrl; /* 0x208 */
u32 pll_dbg0; /* 0x20c */
+ u32 pll_dbg1; /* 0x210 */
+ u32 hpd_cec; /* 0x214 */
+ u8 res3[0x28]; /* 0x218 */
+ u8 vendor_info_frame[0x14]; /* 0x240 */
+ u8 res4[0x9c]; /* 0x254 */
+ u32 pkt_ctrl0; /* 0x2f0 */
+ u32 pkt_ctrl1; /* 0x2f4 */
+ u8 res5[0x8]; /* 0x2f8 */
+ u32 unknown; /* 0x300 */
+ u8 res6[0xc]; /* 0x304 */
+ u32 audio_sample_count; /* 0x310 */
+ u8 res7[0xec]; /* 0x314 */
+ u32 audio_tx_fifo; /* 0x400 */
+ u8 res8[0xfc]; /* 0x404 */
+#ifndef CONFIG_MACH_SUN6I
+ u32 ddc_ctrl; /* 0x500 */
+ u32 ddc_addr; /* 0x504 */
+ u32 ddc_int_mask; /* 0x508 */
+ u32 ddc_int_status; /* 0x50c */
+ u32 ddc_fifo_ctrl; /* 0x510 */
+ u32 ddc_fifo_status; /* 0x514 */
+ u32 ddc_fifo_data; /* 0x518 */
+ u32 ddc_byte_count; /* 0x51c */
+ u32 ddc_cmnd; /* 0x520 */
+ u32 ddc_exreg; /* 0x524 */
+ u32 ddc_clock; /* 0x528 */
+ u8 res9[0x14]; /* 0x52c */
+ u32 ddc_line_ctrl; /* 0x540 */
+#else
+ u32 ddc_ctrl; /* 0x500 */
+ u32 ddc_exreg; /* 0x504 */
+ u32 ddc_cmnd; /* 0x508 */
+ u32 ddc_addr; /* 0x50c */
+ u32 ddc_int_mask; /* 0x510 */
+ u32 ddc_int_status; /* 0x514 */
+ u32 ddc_fifo_ctrl; /* 0x518 */
+ u32 ddc_fifo_status; /* 0x51c */
+ u32 ddc_clock; /* 0x520 */
+ u32 ddc_timeout; /* 0x524 */
+ u8 res9[0x18]; /* 0x528 */
+ u32 ddc_dbg; /* 0x540 */
+ u8 res10[0x3c]; /* 0x544 */
+ u32 ddc_fifo_data; /* 0x580 */
+#endif
};
/*
+ * This is based on the A10s User Manual, and the A10s only supports
+ * composite video and not vga like the A10 / A20 does, still other
+ * than the removed vga out capability the tvencoder seems to be the same.
+ * "unknown#" registers are registers which are used in the A10 kernel code,
+ * but not documented in the A10s User Manual.
+ */
+struct sunxi_tve_reg {
+ u32 gctrl; /* 0x000 */
+ u32 cfg0; /* 0x004 */
+ u32 dac_cfg0; /* 0x008 */
+ u32 filter; /* 0x00c */
+ u32 chroma_freq; /* 0x010 */
+ u32 porch_num; /* 0x014 */
+ u32 unknown0; /* 0x018 */
+ u32 line_num; /* 0x01c */
+ u32 blank_black_level; /* 0x020 */
+ u32 unknown1; /* 0x024, seems to be 1 byte per dac */
+ u8 res0[0x08]; /* 0x028 */
+ u32 auto_detect_en; /* 0x030 */
+ u32 auto_detect_int_status; /* 0x034 */
+ u32 auto_detect_status; /* 0x038 */
+ u32 auto_detect_debounce; /* 0x03c */
+ u32 csc_reg0; /* 0x040 */
+ u32 csc_reg1; /* 0x044 */
+ u32 csc_reg2; /* 0x048 */
+ u32 csc_reg3; /* 0x04c */
+ u8 res1[0xb0]; /* 0x050 */
+ u32 color_burst; /* 0x100 */
+ u32 vsync_num; /* 0x104 */
+ u32 notch_freq; /* 0x108 */
+ u32 cbr_level; /* 0x10c */
+ u32 burst_phase; /* 0x110 */
+ u32 burst_width; /* 0x114 */
+ u8 res2[0x04]; /* 0x118 */
+ u32 sync_vbi_level; /* 0x11c */
+ u32 white_level; /* 0x120 */
+ u32 active_num; /* 0x124 */
+ u32 chroma_bw_gain; /* 0x128 */
+ u32 notch_width; /* 0x12c */
+ u32 resync_num; /* 0x130 */
+ u32 slave_para; /* 0x134 */
+ u32 cfg1; /* 0x138 */
+ u32 cfg2; /* 0x13c */
+};
+
+/*
+ * DE-FE register constants.
+ */
+#define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0)
+#define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16)
+#define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16)
+#define SUNXI_DE_FE_ENABLE_EN (1 << 0)
+#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0)
+#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1)
+#define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16)
+#define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1)
+#define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151
+#define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002
+
+/*
* DE-BE register constants.
*/
#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0)
@@ -119,6 +334,7 @@
#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8)
#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5)
#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0)
+#define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002
#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
/*
@@ -126,17 +342,40 @@
*/
#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
+#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
+#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
+#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4))
+#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4))
+#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111
+#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000
+#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111
+#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555
+#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777
+#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
+#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31)
+#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0)
#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
+#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0)
+#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
+#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0)
+#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
+#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
+#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31)
+#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28)
#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16)
+#define SUNXI_LCDC_LVDS_ANA0 0x3f310000
+#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22)
+#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10)
+#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00)
/*
* HDMI register constants.
@@ -149,9 +388,12 @@
#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73
#define SUNXI_HDMI_HPD_DETECT (1 << 0)
#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31)
+#define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30)
#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0)
#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1)
#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16)
+#define SUNXI_HDMI_QCP_PACKET0 3
+#define SUNXI_HDMI_QCP_PACKET1 0
#ifdef CONFIG_MACH_SUN6I
#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f
@@ -182,6 +424,83 @@
#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21)
#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21)
+#define SUNXI_HDMI_PKT_CTRL0 0x00000f21
+#define SUNXI_HDMI_PKT_CTRL1 0x0000000f
+#define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0)
+#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4)
+#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6)
+#define SUNXI_HMDI_DDC_CTRL_START (1 << 27)
+#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31)
+#else
+#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0)
+/* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
+#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0
+#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0
+#define SUNXI_HMDI_DDC_CTRL_START (1 << 30)
+#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31)
+#endif
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0)
+#else
+#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0)
+#endif
+#define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8)
+#define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16)
+#define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24)
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15)
+#else
+#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31)
+#endif
+
+#define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6
+#define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_DDC_CLOCK 0x61
+#else
+/* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
+#define SUNXI_HDMI_DDC_CLOCK 0x0d
+#endif
+
+#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8)
+#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9)
+
+/*
+ * TVE register constants.
+ */
+#define SUNXI_TVE_GCTRL_ENABLE (1 << 0)
+/*
+ * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
+ * dac from tve1. When using tve1 the mux value must be written to both tve0's
+ * and tve1's gctrl reg.
+ */
+#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4))
+#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4))
+#define SUNXI_TVE_GCTRL_CFG0_VGA 0x20000000
+#define SUNXI_TVE_GCTRL_DAC_CFG0_VGA 0x403e1ac7
+#define SUNXI_TVE_GCTRL_UNKNOWN1_VGA 0x00000000
+#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0))
+#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16))
+#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0))
+#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8)
+#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8))
+#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0
+#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1
+#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3
+#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8)
+#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8))
+#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31)
+#define SUNXI_TVE_CSC_REG0 0x08440832
+#define SUNXI_TVE_CSC_REG1 0x3b6dace1
+#define SUNXI_TVE_CSC_REG2 0x0e1d13dc
+#define SUNXI_TVE_CSC_REG3 0x00108080
+
int sunxi_simplefb_setup(void *blob);
#endif /* _SUNXI_DISPLAY_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 9072e68..7ff43e6 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -12,15 +12,44 @@
#ifndef _SUNXI_DRAM_H
#define _SUNXI_DRAM_H
+#include <asm/io.h>
#include <linux/types.h>
/* dram regs definition */
#if defined(CONFIG_MACH_SUN6I)
#include <asm/arch/dram_sun6i.h>
+#elif defined(CONFIG_MACH_SUN8I)
+#include <asm/arch/dram_sun8i.h>
#else
#include <asm/arch/dram_sun4i.h>
#endif
unsigned long sunxi_dram_init(void);
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+static inline void mctl_await_completion(u32 *reg, u32 mask, u32 val)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ while ((readl(reg) & mask) != val) {
+ if (timer_get_us() > tmo)
+ panic("Timeout initialising DRAM\n");
+ }
+}
+
+/*
+ * Test if memory at offset offset matches memory at begin of DRAM
+ */
+static inline bool mctl_mem_matches(u32 offset)
+{
+ /* Try to write different values to RAM at two addresses */
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
+ /* Check if the same value is actually observed when reading back */
+ return readl(CONFIG_SYS_SDRAM_BASE) ==
+ readl(CONFIG_SYS_SDRAM_BASE + offset);
+}
+
#endif /* _SUNXI_DRAM_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
index 6c1ec5b..40c385a 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
@@ -76,7 +76,7 @@
u32 cas;
u32 zq;
u32 odt_en;
- u32 size;
+ u32 size; /* For compat with dram.c files from u-boot-sunxi, unused */
u32 tpr0;
u32 tpr1;
u32 tpr2;
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i.h
new file mode 100644
index 0000000..06adee2
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i.h
@@ -0,0 +1,266 @@
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * CPL <cplanxy@allwinnertech.com>
+ * Jerry Wang <wangflord@allwinnertech.com>
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_H
+#define _SUNXI_DRAM_SUN8I_H
+
+struct dram_para {
+ u32 clock;
+ u32 type;
+ u32 zq;
+ u32 odt_en;
+ u32 para1;
+ u32 para2;
+ u32 mr0;
+ u32 mr1;
+ u32 mr2;
+ u32 mr3;
+ u32 tpr0;
+ u32 tpr1;
+ u32 tpr2;
+ u32 tpr3;
+ u32 tpr4;
+ u32 tpr5;
+ u32 tpr6;
+ u32 tpr7;
+ u32 tpr8;
+ u32 tpr9;
+ u32 tpr10;
+ u32 tpr11;
+ u32 tpr12;
+ u32 tpr13;
+};
+
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x00 */
+ u32 ccr; /* 0x04 controller configuration register */
+ u32 dbgcr; /* 0x08 */
+ u8 res0[0x4]; /* 0x0c */
+ u32 mcr0_0; /* 0x10 */
+ u32 mcr1_0; /* 0x14 */
+ u32 mcr0_1; /* 0x18 */
+ u32 mcr1_1; /* 0x1c */
+ u32 mcr0_2; /* 0x20 */
+ u32 mcr1_2; /* 0x24 */
+ u32 mcr0_3; /* 0x28 */
+ u32 mcr1_3; /* 0x2c */
+ u32 mcr0_4; /* 0x30 */
+ u32 mcr1_4; /* 0x34 */
+ u32 mcr0_5; /* 0x38 */
+ u32 mcr1_5; /* 0x3c */
+ u32 mcr0_6; /* 0x40 */
+ u32 mcr1_6; /* 0x44 */
+ u32 mcr0_7; /* 0x48 */
+ u32 mcr1_7; /* 0x4c */
+ u32 mcr0_8; /* 0x50 */
+ u32 mcr1_8; /* 0x54 */
+ u32 mcr0_9; /* 0x58 */
+ u32 mcr1_9; /* 0x5c */
+ u32 mcr0_10; /* 0x60 */
+ u32 mcr1_10; /* 0x64 */
+ u32 mcr0_11; /* 0x68 */
+ u32 mcr1_11; /* 0x6c */
+ u32 mcr0_12; /* 0x70 */
+ u32 mcr1_12; /* 0x74 */
+ u32 mcr0_13; /* 0x78 */
+ u32 mcr1_13; /* 0x7c */
+ u32 mcr0_14; /* 0x80 */
+ u32 mcr1_14; /* 0x84 */
+ u32 mcr0_15; /* 0x88 */
+ u32 mcr1_15; /* 0x8c */
+ u32 bwcr; /* 0x90 */
+ u32 maer; /* 0x94 */
+ u8 res1[0x4]; /* 0x98 */
+ u32 mcgcr; /* 0x9c */
+ u32 bwctr; /* 0xa0 */
+ u8 res2[0x4]; /* 0xa4 */
+ u32 swonr; /* 0xa8 */
+ u32 swoffr; /* 0xac */
+};
+
+struct sunxi_mctl_ctl_reg {
+ u32 mstr; /* 0x00 */
+ u32 statr; /* 0x04 */
+ u8 res0[0x08]; /* 0x08 */
+ u32 mrctrl0; /* 0x10 */
+ u32 mrctrl1; /* 0x14 */
+ u32 mrstatr; /* 0x18 */
+ u8 res1[0x04]; /* 0x1c */
+ u32 derateen; /* 0x20 */
+ u32 deratenint; /* 0x24 */
+ u8 res2[0x08]; /* 0x28 */
+ u32 pwrctl; /* 0x30 */
+ u32 pwrtmg; /* 0x34 */
+ u8 res3[0x18]; /* 0x38 */
+ u32 rfshctl0; /* 0x50 */
+ u32 rfshctl1; /* 0x54 */
+ u8 res4[0x8]; /* 0x58 */
+ u32 rfshctl3; /* 0x60 */
+ u32 rfshtmg; /* 0x64 */
+ u8 res6[0x68]; /* 0x68 */
+ u32 init0; /* 0xd0 */
+ u32 init1; /* 0xd4 */
+ u32 init2; /* 0xd8 */
+ u32 init3; /* 0xdc */
+ u32 init4; /* 0xe0 */
+ u32 init5; /* 0xe4 */
+ u8 res7[0x0c]; /* 0xe8 */
+ u32 rankctl; /* 0xf4 */
+ u8 res8[0x08]; /* 0xf8 */
+ u32 dramtmg0; /* 0x100 */
+ u32 dramtmg1; /* 0x104 */
+ u32 dramtmg2; /* 0x108 */
+ u32 dramtmg3; /* 0x10c */
+ u32 dramtmg4; /* 0x110 */
+ u32 dramtmg5; /* 0x114 */
+ u32 dramtmg6; /* 0x118 */
+ u32 dramtmg7; /* 0x11c */
+ u32 dramtmg8; /* 0x120 */
+ u8 res9[0x5c]; /* 0x124 */
+ u32 zqctl0; /* 0x180 */
+ u32 zqctl1; /* 0x184 */
+ u32 zqctl2; /* 0x188 */
+ u32 zqstat; /* 0x18c */
+ u32 pitmg0; /* 0x190 */
+ u32 pitmg1; /* 0x194 */
+ u32 plpcfg0; /* 0x198 */
+ u8 res10[0x04]; /* 0x19c */
+ u32 upd0; /* 0x1a0 */
+ u32 upd1; /* 0x1a4 */
+ u32 upd2; /* 0x1a8 */
+ u32 upd3; /* 0x1ac */
+ u32 pimisc; /* 0x1b0 */
+ u8 res11[0x1c]; /* 0x1b4 */
+ u32 trainctl0; /* 0x1d0 */
+ u32 trainctl1; /* 0x1d4 */
+ u32 trainctl2; /* 0x1d8 */
+ u32 trainstat; /* 0x1dc */
+ u8 res12[0x60]; /* 0x1e0 */
+ u32 odtcfg; /* 0x240 */
+ u32 odtmap; /* 0x244 */
+ u8 res13[0x08]; /* 0x248 */
+ u32 sched; /* 0x250 */
+ u8 res14[0x04]; /* 0x254 */
+ u32 perfshpr0; /* 0x258 */
+ u32 perfshpr1; /* 0x25c */
+ u32 perflpr0; /* 0x260 */
+ u32 perflpr1; /* 0x264 */
+ u32 perfwr0; /* 0x268 */
+ u32 perfwr1; /* 0x26c */
+};
+
+struct sunxi_mctl_phy_reg {
+ u8 res0[0x04]; /* 0x00 */
+ u32 pir; /* 0x04 */
+ u32 pgcr0; /* 0x08 phy general configuration register */
+ u32 pgcr1; /* 0x0c phy general configuration register */
+ u32 pgsr0; /* 0x10 */
+ u32 pgsr1; /* 0x14 */
+ u32 dllgcr; /* 0x18 */
+ u32 ptr0; /* 0x1c */
+ u32 ptr1; /* 0x20 */
+ u32 ptr2; /* 0x24 */
+ u32 ptr3; /* 0x28 */
+ u32 ptr4; /* 0x2c */
+ u32 acmdlr; /* 0x30 */
+ u32 acbdlr; /* 0x34 */
+ u32 aciocr; /* 0x38 */
+ u32 dxccr; /* 0x3c DATX8 common configuration register */
+ u32 dsgcr; /* 0x40 dram system general config register */
+ u32 dcr; /* 0x44 */
+ u32 dtpr0; /* 0x48 dram timing parameters register 0 */
+ u32 dtpr1; /* 0x4c dram timing parameters register 1 */
+ u32 dtpr2; /* 0x50 dram timing parameters register 2 */
+ u32 mr0; /* 0x54 mode register 0 */
+ u32 mr1; /* 0x58 mode register 1 */
+ u32 mr2; /* 0x5c mode register 2 */
+ u32 mr3; /* 0x60 mode register 3 */
+ u32 odtcr; /* 0x64 */
+ u32 dtcr; /* 0x68 */
+ u32 dtar0; /* 0x6c data training address register 0 */
+ u32 dtar1; /* 0x70 data training address register 1 */
+ u32 dtar2; /* 0x74 data training address register 2 */
+ u32 dtar3; /* 0x78 data training address register 3 */
+ u32 dtdr0; /* 0x7c */
+ u32 dtdr1; /* 0x80 */
+ u32 dtedr0; /* 0x84 */
+ u32 dtedr1; /* 0x88 */
+ u32 pgcr2; /* 0x8c */
+ u8 res1[0x70]; /* 0x90 */
+ u32 bistrr; /* 0x100 */
+ u32 bistwcr; /* 0x104 */
+ u32 bistmskr0; /* 0x108 */
+ u32 bistmskr1; /* 0x10c */
+ u32 bistmskr2; /* 0x110 */
+ u32 bistlsr; /* 0x114 */
+ u32 bistar0; /* 0x118 */
+ u32 bistar1; /* 0x11c */
+ u32 bistar2; /* 0x120 */
+ u32 bistupdr; /* 0x124 */
+ u32 bistgsr; /* 0x128 */
+ u32 bistwer; /* 0x12c */
+ u32 bistber0; /* 0x130 */
+ u32 bistber1; /* 0x134 */
+ u32 bistber2; /* 0x138 */
+ u32 bistber3; /* 0x13c */
+ u32 bistwcsr; /* 0x140 */
+ u32 bistfwr0; /* 0x144 */
+ u32 bistfwr1; /* 0x148 */
+ u32 bistfwr2; /* 0x14c */
+ u8 res2[0x30]; /* 0x150 */
+ u32 zqcr0; /* 0x180 zq control register 0 */
+ u32 zqcr1; /* 0x184 zq control register 1 */
+ u32 zqsr0; /* 0x188 zq status register 0 */
+ u32 zqsr1; /* 0x18c zq status register 1 */
+ u32 zqcr2; /* 0x190 zq control register 2 */
+ u8 res3[0x2c]; /* 0x194 */
+ u32 dx0gcr; /* 0x1c0 */
+ u32 dx0gsr0; /* 0x1c4 */
+ u32 dx0gsr1; /* 0x1c8 */
+ u32 dx0bdlr0; /* 0x1cc */
+ u32 dx0bdlr1; /* 0x1d0 */
+ u32 dx0bdlr2; /* 0x1d4 */
+ u32 dx0bdlr3; /* 0x1d8 */
+ u32 dx0bdlr4; /* 0x1dc */
+ u32 dx0lcdlr0; /* 0x1e0 */
+ u32 dx0lcdlr1; /* 0x1e4 */
+ u32 dx0lcdlr2; /* 0x1e8 */
+ u32 dx0mdlr; /* 0x1ec */
+ u32 dx0gtr; /* 0x1f0 */
+ u32 dx0gsr2; /* 0x1f4 */
+ u8 res4[0x08]; /* 0x1f8 */
+ u32 dx1gcr; /* 0x200 */
+ u32 dx1gsr0; /* 0x204 */
+ u32 dx1gsr1; /* 0x208 */
+ u32 dx1bdlr0; /* 0x20c */
+ u32 dx1bdlr1; /* 0x210 */
+ u32 dx1bdlr2; /* 0x214 */
+ u32 dx1bdlr3; /* 0x218 */
+ u32 dx1bdlr4; /* 0x21c */
+ u32 dx1lcdlr0; /* 0x220 */
+ u32 dx1lcdlr1; /* 0x224 */
+ u32 dx1lcdlr2; /* 0x228 */
+ u32 dx1mdlr; /* 0x22c */
+ u32 dx1gtr; /* 0x230 */
+ u32 dx1gsr2; /* 0x234 */
+};
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_ROW_MASK (0xf << 4)
+#define MCTL_CR_ROW(x) (((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x) ((x) << 8)
+
+#endif /* _SUNXI_DRAM_SUN8I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 366c0dc..71cc879 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -114,6 +114,7 @@
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
SUNXI_GPIO_L_START = 352,
SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
+ SUNXI_GPIO_AXP0_START = 1024,
};
/* SUNXI GPIO number definitions */
@@ -129,6 +130,8 @@
#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
+#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
+
/* GPIO pin function config */
#define SUNXI_GPIO_INPUT 0
#define SUNXI_GPIO_OUTPUT 1
@@ -145,13 +148,11 @@
#define SUN5I_GPB19_UART0_TX 2
#define SUN5I_GPB20_UART0_RX 2
-#define SUN5I_GPG3_SDC1 2
-
-#define SUN5I_GPG3_UART1_TX 4
-#define SUN5I_GPG4_UART1_RX 4
-
#define SUNXI_GPC6_SDC2 3
+#define SUNXI_GPD0_LCD0 2
+#define SUNXI_GPD0_LVDS0 3
+
#define SUNXI_GPF0_SDC0 2
#define SUNXI_GPF2_SDC0 2
@@ -166,6 +167,11 @@
#define SUN4I_GPG0_SDC1 4
+#define SUN5I_GPG3_SDC1 2
+
+#define SUN5I_GPG3_UART1_TX 4
+#define SUN5I_GPG4_UART1_RX 4
+
#define SUN4I_GPH22_SDC1 5
#define SUN6I_GPH20_UART0_TX 2
@@ -173,9 +179,11 @@
#define SUN4I_GPI4_SDC3 2
-#define SUNXI_GPL0_R_P2WI_SCK 3
-#define SUNXI_GPL1_R_P2WI_SDA 3
+#define SUN6I_GPL0_R_P2WI_SCK 3
+#define SUN6I_GPL1_R_P2WI_SDA 3
+#define SUN8I_GPL0_R_RSB_SCK 2
+#define SUN8I_GPL1_R_RSB_SDA 2
#define SUN8I_GPL2_R_UART_TX 2
#define SUN8I_GPL3_R_UART_RX 2
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 537f145..74833b5 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,10 +43,11 @@
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res1[26];
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
+ defined(CONFIG_MACH_SUN9I)
u32 res2[64];
#endif
- u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */
+ u32 fifo; /* 0x100 / 0x200 FIFO access address */
};
#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
@@ -123,5 +124,8 @@
#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
+#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
+#define SUNXI_MMC_COMMON_RESET (1 << 18)
+
struct mmc *sunxi_mmc_init(int sdc_no);
#endif /* _SUNXI_MMC_H */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 88de1ff..82ed541 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -50,7 +50,8 @@
#define PRCM_APB0_GATE_PIO (0x1 << 0)
#define PRCM_APB0_GATE_IR (0x1 << 1)
#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
-#define PRCM_APB0_GATE_P2WI (0x1 << 3)
+#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */
+#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */
#define PRCM_APB0_GATE_UART (0x1 << 4)
#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
#define PRCM_APB0_GATE_I2C (0x1 << 6)
diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h
new file mode 100644
index 0000000..95a595a
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/rsb.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * lixiang <lixiang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SUNXI_RSB_H
+#define __SUNXI_RSB_H
+
+#include <common.h>
+#include <asm/io.h>
+
+struct sunxi_rsb_reg {
+ u32 ctrl; /* 0x00 */
+ u32 ccr; /* 0x04 */
+ u32 inte; /* 0x08 */
+ u32 stat; /* 0x0c */
+ u32 addr; /* 0x10 */
+ u8 res0[8]; /* 0x14 */
+ u32 data; /* 0x1c */
+ u8 res1[4]; /* 0x20 */
+ u32 lcr; /* 0x24 */
+ u32 dmcr; /* 0x28 */
+ u32 cmd; /* 0x2c */
+ u32 devaddr; /* 0x30 */
+};
+
+#define RSB_CTRL_SOFT_RST (1 << 0)
+#define RSB_CTRL_START_TRANS (1 << 7)
+
+#define RSB_STAT_TOVER_INT (1 << 0)
+#define RSB_STAT_TERR_INT (1 << 1)
+#define RSB_STAT_LBSY_INT (1 << 2)
+
+#define RSB_DMCR_DEVICE_MODE_START (1 << 31)
+
+#define RSB_CMD_BYTE_WRITE 0x4e
+#define RSB_CMD_BYTE_READ 0x8b
+#define RSB_CMD_SET_RTSADDR 0xe8
+
+#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16)
+#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0)
+
+void rsb_init(void);
+int rsb_set_device_mode(u32 device_mode_data);
+int rsb_set_device_address(u16 device_addr, u16 runtime_addr);
+int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
+int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h
new file mode 100644
index 0000000..cb538cd
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/usbc.h
@@ -0,0 +1,22 @@
+/*
+ * Sunxi usb-controller code shared between the ehci and musb controllers
+ *
+ * Copyright (C) 2014 Roman Byshko
+ *
+ * Roman Byshko <rbyshko@gmail.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+extern const struct musb_platform_ops sunxi_musb_ops;
+
+void *sunxi_usbc_get_io_base(int index);
+int sunxi_usbc_request_resources(int index);
+int sunxi_usbc_free_resources(int index);
+void sunxi_usbc_enable(int index);
+void sunxi_usbc_disable(int index);
+void sunxi_usbc_vbus_enable(int index);
+void sunxi_usbc_vbus_disable(int index);
diff --git a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
index 484559c..6b7d600 100644
--- a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
@@ -72,7 +72,7 @@
u32 gtr; /* General Timing Register */
u32 rsv[3]; /* Reserved */
} dx[9];
-} __packed;
+};
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h
index fa5e6ae..4ae67c8 100644
--- a/arch/arm/include/asm/arch-uniphier/sg-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h
@@ -25,22 +25,29 @@
/* Memory Configuration */
#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
-#define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0))
-#define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0))
-#define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0))
-#define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0))
-#define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
+#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
+#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
-#define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2))
-#define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2))
-#define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2))
-#define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2))
-#define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
+#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
+#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
+#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
+#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
+#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
+#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
+#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
+
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
/* Pin Control */
@@ -101,6 +108,7 @@
#else
#include <linux/types.h>
+#include <linux/sizes.h>
#include <asm/io.h>
static inline void sg_set_pinsel(int n, int value)
@@ -111,24 +119,24 @@
static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
{
- int size_mb = (size >> 20) / num;
+ int size_mb = size / num;
u32 ret;
switch (size_mb) {
- case 64:
- ret = SG_MEMCONF_CH0_SIZE_64MB;
+ case SZ_64M:
+ ret = SG_MEMCONF_CH0_SZ_64M;
break;
- case 128:
- ret = SG_MEMCONF_CH0_SIZE_128MB;
+ case SZ_128M:
+ ret = SG_MEMCONF_CH0_SZ_128M;
break;
- case 256:
- ret = SG_MEMCONF_CH0_SIZE_256MB;
+ case SZ_256M:
+ ret = SG_MEMCONF_CH0_SZ_256M;
break;
- case 512:
- ret = SG_MEMCONF_CH0_SIZE_512MB;
+ case SZ_512M:
+ ret = SG_MEMCONF_CH0_SZ_512M;
break;
- case 1024:
- ret = SG_MEMCONF_CH0_SIZE_1024MB;
+ case SZ_1G:
+ ret = SG_MEMCONF_CH0_SZ_1G;
break;
default:
BUG();
@@ -151,24 +159,24 @@
static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
{
- int size_mb = (size >> 20) / num;
+ int size_mb = size / num;
u32 ret;
switch (size_mb) {
- case 64:
- ret = SG_MEMCONF_CH1_SIZE_64MB;
+ case SZ_64M:
+ ret = SG_MEMCONF_CH1_SZ_64M;
break;
- case 128:
- ret = SG_MEMCONF_CH1_SIZE_128MB;
+ case SZ_128M:
+ ret = SG_MEMCONF_CH1_SZ_128M;
break;
- case 256:
- ret = SG_MEMCONF_CH1_SIZE_256MB;
+ case SZ_256M:
+ ret = SG_MEMCONF_CH1_SZ_256M;
break;
- case 512:
- ret = SG_MEMCONF_CH1_SIZE_512MB;
+ case SZ_512M:
+ ret = SG_MEMCONF_CH1_SZ_512M;
break;
- case 1024:
- ret = SG_MEMCONF_CH1_SIZE_1024MB;
+ case SZ_1G:
+ ret = SG_MEMCONF_CH1_SZ_1G;
break;
default:
BUG();
@@ -188,6 +196,43 @@
}
return ret;
}
+
+static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
+{
+ int size_mb = size / num;
+ u32 ret;
+
+ switch (size_mb) {
+ case SZ_64M:
+ ret = SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ ret = SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ ret = SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ ret = SG_MEMCONF_CH2_SZ_512M;
+ break;
+ default:
+ BUG();
+ break;
+ }
+
+ switch (num) {
+ case 1:
+ ret |= SG_MEMCONF_CH2_NUM_1;
+ break;
+ case 2:
+ ret |= SG_MEMCONF_CH2_NUM_2;
+ break;
+ default:
+ BUG();
+ break;
+ }
+ return ret;
+}
#endif /* __ASSEMBLY__ */
#endif /* ARCH_SG_REGS_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 89c47f3..9d50e24 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -20,7 +20,7 @@
extern unsigned int zynq_get_silicon_version(void);
/* Driver extern functions */
-extern int zynq_sdhci_init(u32 regbase);
+extern int zynq_sdhci_init(phys_addr_t regbase);
extern int zynq_sdhci_of_init(const void *blob);
extern void ps7_init(void);
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 2fe5776..342f045 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -650,8 +650,8 @@
u32 emif_rd_wr_exec_thresh;
u32 emif_cos_config;
u32 padding9[6];
- u32 emif_ddr_phy_status[21];
- u32 padding10[27];
+ u32 emif_ddr_phy_status[28];
+ u32 padding10[20];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
@@ -700,9 +700,36 @@
u32 emif_ddr_ext_phy_ctrl_23_shdw;
u32 emif_ddr_ext_phy_ctrl_24;
u32 emif_ddr_ext_phy_ctrl_24_shdw;
- u32 padding[22];
- u32 emif_ddr_fifo_misaligned_clear_1;
- u32 emif_ddr_fifo_misaligned_clear_2;
+ u32 emif_ddr_ext_phy_ctrl_25;
+ u32 emif_ddr_ext_phy_ctrl_25_shdw;
+ u32 emif_ddr_ext_phy_ctrl_26;
+ u32 emif_ddr_ext_phy_ctrl_26_shdw;
+ u32 emif_ddr_ext_phy_ctrl_27;
+ u32 emif_ddr_ext_phy_ctrl_27_shdw;
+ u32 emif_ddr_ext_phy_ctrl_28;
+ u32 emif_ddr_ext_phy_ctrl_28_shdw;
+ u32 emif_ddr_ext_phy_ctrl_29;
+ u32 emif_ddr_ext_phy_ctrl_29_shdw;
+ u32 emif_ddr_ext_phy_ctrl_30;
+ u32 emif_ddr_ext_phy_ctrl_30_shdw;
+ u32 emif_ddr_ext_phy_ctrl_31;
+ u32 emif_ddr_ext_phy_ctrl_31_shdw;
+ u32 emif_ddr_ext_phy_ctrl_32;
+ u32 emif_ddr_ext_phy_ctrl_32_shdw;
+ u32 emif_ddr_ext_phy_ctrl_33;
+ u32 emif_ddr_ext_phy_ctrl_33_shdw;
+ u32 emif_ddr_ext_phy_ctrl_34;
+ u32 emif_ddr_ext_phy_ctrl_34_shdw;
+ u32 emif_ddr_ext_phy_ctrl_35;
+ u32 emif_ddr_ext_phy_ctrl_35_shdw;
+ union {
+ u32 emif_ddr_ext_phy_ctrl_36;
+ u32 emif_ddr_fifo_misaligned_clear_1;
+ };
+ union {
+ u32 emif_ddr_ext_phy_ctrl_36_shdw;
+ u32 emif_ddr_fifo_misaligned_clear_2;
+ };
};
struct dmm_lisa_map_regs {
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index dfcc596..c41850a 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -15,6 +15,11 @@
/* Pointer to as well as the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * WARNING: This is going away very soon. Don't use it and don't submit
+ * pafches that rely on it. The global_data area is set up in crt0.S.
+ */
gd_t gdata __attribute__ ((section(".data")));
/*
@@ -28,7 +33,7 @@
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
- /* Set global data pointer. */
+ /* TODO: Remove settings of the global data pointer here */
gd = &gdata;
board_init_r(NULL, 0);
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 5374b4d..78c98ed 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -19,9 +19,6 @@
config TARGET_EB_CPU5282
bool "Support eb_cpu5282"
-config TARGET_TASREG
- bool "Support TASREG"
-
config TARGET_M5208EVBE
bool "Support M5208EVBE"
@@ -75,7 +72,6 @@
source "board/BuS/eb_cpu5282/Kconfig"
source "board/astro/mcf5373l/Kconfig"
source "board/cobra5272/Kconfig"
-source "board/esd/tasreg/Kconfig"
source "board/freescale/m5208evbe/Kconfig"
source "board/freescale/m52277evb/Kconfig"
source "board/freescale/m5235evb/Kconfig"
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 1757bbf..84c29e5 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -23,11 +23,15 @@
mts rmsr, r0 /* disable cache */
+ addi r8, r0, __end
+ mts rslr, r8
#if defined(CONFIG_SPL_BUILD)
addi r1, r0, CONFIG_SPL_STACK_ADDR
+ mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
#else
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
+ mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
/* Find-out if u-boot is running on BIG/LITTLE endian platform
@@ -130,7 +134,7 @@
/* enable instruction and data cache */
mfs r12, rmsr
- ori r12, r12, 0xa0
+ ori r12, r12, 0x1a0
mts rmsr, r12
clear_bss:
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4991da2..ef78929 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -29,6 +29,7 @@
select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SWAP_IO_SPACE
config TARGET_VCT
bool "Support vct"
@@ -116,6 +117,39 @@
endchoice
+menu "OS boot interface"
+
+config MIPS_BOOT_CMDLINE_LEGACY
+ bool "Hand over legacy command line to Linux kernel"
+ default y
+ help
+ Enable this option if you want U-Boot to hand over the Yamon-style
+ command line to the kernel. All bootargs will be prepared as argc/argv
+ compatible list. The argument count (argc) is stored in register $a0.
+ The address of the argument list (argv) is stored in register $a1.
+
+config MIPS_BOOT_ENV_LEGACY
+ bool "Hand over legacy environment to Linux kernel"
+ default y
+ help
+ Enable this option if you want U-Boot to hand over the Yamon-style
+ environment to the kernel. Information like memory size, initrd
+ address and size will be prepared as zero-terminated key/value list.
+ The address of the enviroment is stored in register $a2.
+
+config MIPS_BOOT_FDT
+ bool "Hand over a flattened device tree to Linux kernel (INCOMPLETE)"
+ default n
+ help
+ Enable this option if you want U-Boot to hand over a flattened
+ device tree to the kernel.
+
+ Note: the final hand over to the kernel is not yet implemented. After
+ the community agreed on the MIPS boot interface for device trees,
+ the corresponding code will be added.
+
+endmenu
+
config SUPPORTS_BIG_ENDIAN
bool
@@ -134,12 +168,23 @@
config SUPPORTS_CPU_MIPS64_R2
bool
+config CPU_MIPS32
+ bool
+ default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
+
+config CPU_MIPS64
+ bool
+ default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
+
config 32BIT
bool
config 64BIT
bool
+config SWAP_IO_SPACE
+ bool
+
endif
endmenu
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 1907b57..0a9e7e6 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -2,7 +2,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
-head-y := arch/mips/cpu/$(CPU)/start.o
+head-$(CONFIG_CPU_MIPS32) := arch/mips/cpu/mips32/start.o
+head-$(CONFIG_CPU_MIPS64) := arch/mips/cpu/mips64/start.o
-libs-y += arch/mips/cpu/$(CPU)/
+libs-$(CONFIG_CPU_MIPS32) += arch/mips/cpu/mips32/
+libs-$(CONFIG_CPU_MIPS64) += arch/mips/cpu/mips64/
libs-y += arch/mips/lib/
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 384ea26..36b92cc 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -15,6 +15,11 @@
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+#endif
+
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
@@ -135,9 +140,31 @@
#endif
/* Set up temporary stack */
- li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ li t0, -16
+ li t1, CONFIG_SYS_INIT_SP_ADDR
+ and sp, t1, t0 # force 16 byte alignment
+ sub sp, sp, GD_SIZE # reserve space for gd
+ and sp, sp, t0 # force 16 byte alignment
+ move k0, sp # save gd pointer
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ li t2, CONFIG_SYS_MALLOC_F_LEN
+ sub sp, sp, t2 # reserve space for early malloc
+ and sp, sp, t0 # force 16 byte alignment
+#endif
move fp, sp
+ /* Clear gd */
+ move t0, k0
+1:
+ sw zero, 0(t0)
+ blt t0, t1, 1b
+ addi t0, 4
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ addu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
+ sw sp, 0(t0)
+#endif
+
la t9, board_init_f
jr t9
move ra, zero
diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c
index 386f45a..553da5f 100644
--- a/arch/mips/cpu/mips32/time.c
+++ b/arch/mips/cpu/mips32/time.c
@@ -8,63 +8,12 @@
#include <common.h>
#include <asm/mipsregs.h>
-static unsigned long timestamp;
-
-/* how many counter cycles in a jiffy */
-#define CYCLES_PER_JIFFY \
- (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
-
-/*
- * timer without interrupts
- */
-
-int timer_init(void)
+unsigned long notrace timer_read_counter(void)
{
- /* Set up the timer for the first expiration. */
- write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-
- return 0;
+ return read_c0_count();
}
-ulong get_timer(ulong base)
+ulong notrace get_tbclk(void)
{
- unsigned int count;
- unsigned int expirelo = read_c0_compare();
-
- /* Check to see if we have missed any timestamps. */
- count = read_c0_count();
- while ((count - expirelo) < 0x7fffffff) {
- expirelo += CYCLES_PER_JIFFY;
- timestamp++;
- }
- write_c0_compare(expirelo);
-
- return timestamp - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned int tmo;
-
- tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
- while ((tmo - read_c0_count()) < 0x7fffffff)
- /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
+ return CONFIG_SYS_MIPS_TIMER_FREQ;
}
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 6ff714e..471bc1e 100644
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -15,6 +15,11 @@
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_SP_OFFSET)
+#endif
+
#ifdef CONFIG_SYS_LITTLE_ENDIAN
#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
@@ -129,9 +134,31 @@
#endif
/* Set up temporary stack */
- dli sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ dli t0, -16
+ dli t1, CONFIG_SYS_INIT_SP_ADDR
+ and sp, t1, t0 # force 16 byte alignment
+ dsub sp, sp, GD_SIZE # reserve space for gd
+ and sp, sp, t0 # force 16 byte alignment
+ move k0, sp # save gd pointer
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ dli t2, CONFIG_SYS_MALLOC_F_LEN
+ dsub sp, sp, t2 # reserve space for early malloc
+ and sp, sp, t0 # force 16 byte alignment
+#endif
move fp, sp
+ /* Clear gd */
+ move t0, k0
+1:
+ sw zero, 0(t0)
+ blt t0, t1, 1b
+ daddi t0, 4
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ daddu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
+ sw sp, 0(t0)
+#endif
+
dla t9, board_init_f
jr t9
move ra, zero
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
index 0497acf..553da5f 100644
--- a/arch/mips/cpu/mips64/time.c
+++ b/arch/mips/cpu/mips64/time.c
@@ -8,63 +8,12 @@
#include <common.h>
#include <asm/mipsregs.h>
-static unsigned long timestamp;
-
-/* how many counter cycles in a jiffy */
-#define CYCLES_PER_JIFFY \
- (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
-
-/*
- * timer without interrupts
- */
-
-int timer_init(void)
+unsigned long notrace timer_read_counter(void)
{
- /* Set up the timer for the first expiration. */
- write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-
- return 0;
+ return read_c0_count();
}
-ulong get_timer(ulong base)
+ulong notrace get_tbclk(void)
{
- unsigned int count;
- unsigned int expirelo = read_c0_compare();
-
- /* Check to see if we have missed any timestamps. */
- count = read_c0_count();
- while ((count - expirelo) < 0x7fffffff) {
- expirelo += CYCLES_PER_JIFFY;
- timestamp++;
- }
- write_c0_compare(expirelo);
-
- return timestamp - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned int tmo;
-
- tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
- while ((tmo - read_c0_count()) < 0x7fffffff)
- /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
+ return CONFIG_SYS_MIPS_TIMER_FREQ;
}
diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h
index 1c8a42b..3a891ba 100644
--- a/arch/mips/include/asm/config.h
+++ b/arch/mips/include/asm/config.h
@@ -7,8 +7,6 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index e0722d2..d9d8396 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <image.h>
+#include <fdt_support.h>
#include <asm/addrspace.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -20,6 +21,18 @@
#define mips_boot_malta 0
#endif
+#if defined(CONFIG_MIPS_BOOT_CMDLINE_LEGACY)
+#define mips_boot_cmdline_legacy 1
+#else
+#define mips_boot_cmdline_legacy 0
+#endif
+
+#if defined(CONFIG_MIPS_BOOT_ENV_LEGACY)
+#define mips_boot_env_legacy 1
+#else
+#define mips_boot_env_legacy 0
+#endif
+
static int linux_argc;
static char **linux_argv;
static char *linux_argp;
@@ -60,9 +73,39 @@
if (ret)
return ret;
+#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT)
+ if (images->ft_len) {
+ boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
+
+ ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
+ &images->ft_len);
+ if (ret)
+ return ret;
+ }
+#endif
+
return 0;
}
+static void boot_setup_fdt(bootm_headers_t *images)
+{
+#if defined(CONFIG_MIPS_BOOT_FDT) && defined(CONFIG_OF_LIBFDT)
+ u64 mem_start = 0;
+ u64 mem_size = gd->ram_size;
+
+ debug("## setup FDT\n");
+
+ fdt_chosen(images->ft_addr, 1);
+ fdt_fixup_memory_banks(images->ft_addr, &mem_start, &mem_size, 1);
+ fdt_fixup_ethernet(images->ft_addr);
+ fdt_initrd(images->ft_addr, images->initrd_start, images->initrd_end, 1);
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+ ft_board_setup(images->ft_addr, gd->bd);
+#endif
+#endif
+}
+
static void linux_cmdline_init(void)
{
linux_argc = 1;
@@ -92,7 +135,7 @@
debug(" arg %03d: %s\n", i, linux_argv[i]);
}
-static void boot_cmdline_linux(bootm_headers_t *images)
+static void linux_cmdline_legacy(bootm_headers_t *images)
{
const char *bootargs, *next, *quote;
@@ -130,8 +173,40 @@
bootargs = next;
}
+}
- linux_cmdline_dump();
+static void linux_cmdline_append(bootm_headers_t *images)
+{
+ char buf[24];
+ ulong mem, rd_start, rd_size;
+
+ /* append mem */
+ mem = gd->ram_size >> 20;
+ sprintf(buf, "mem=%luM", mem);
+ linux_cmdline_set(buf, strlen(buf));
+
+ /* append rd_start and rd_size */
+ rd_start = images->initrd_start;
+ rd_size = images->initrd_end - images->initrd_start;
+
+ if (rd_size) {
+ sprintf(buf, "rd_start=0x%08lX", rd_start);
+ linux_cmdline_set(buf, strlen(buf));
+ sprintf(buf, "rd_size=0x%lX", rd_size);
+ linux_cmdline_set(buf, strlen(buf));
+ }
+}
+
+static void boot_cmdline_linux(bootm_headers_t *images)
+{
+ if (mips_boot_cmdline_legacy && !images->ft_len) {
+ linux_cmdline_legacy(images);
+
+ if (!mips_boot_env_legacy)
+ linux_cmdline_append(images);
+
+ linux_cmdline_dump();
+ }
}
static void linux_env_init(void)
@@ -165,7 +240,7 @@
}
}
-static void boot_prep_linux(bootm_headers_t *images)
+static void linux_env_legacy(bootm_headers_t *images)
{
char env_buf[12];
const char *cp;
@@ -213,6 +288,15 @@
}
}
+static void boot_prep_linux(bootm_headers_t *images)
+{
+ if (mips_boot_env_legacy && !images->ft_len)
+ linux_env_legacy(images);
+
+ if (images->ft_len)
+ boot_setup_fdt(images);
+}
+
static void boot_jump_linux(bootm_headers_t *images)
{
typedef void __noreturn (*kernel_entry_t)(int, ulong, ulong, ulong);
@@ -226,8 +310,12 @@
if (mips_boot_malta)
linux_extra = gd->ram_size;
- /* we assume that the kernel is in place */
- printf("\nStarting kernel ...\n\n");
+#ifdef CONFIG_BOOTSTAGE_FDT
+ bootstage_fdt_add_report();
+#endif
+#ifdef CONFIG_BOOTSTAGE_REPORT
+ bootstage_report();
+#endif
kernel(linux_argc, (ulong)linux_argv, (ulong)linux_env, linux_extra);
}
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7a50301..8e5a3e2 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -7,9 +7,6 @@
choice
prompt "CPU select"
-config 74xx_7xx
- bool "74xx"
-
config MPC512X
bool "MPC512X"
@@ -39,7 +36,6 @@
endchoice
-source "arch/powerpc/cpu/74xx_7xx/Kconfig"
source "arch/powerpc/cpu/mpc512x/Kconfig"
source "arch/powerpc/cpu/mpc5xx/Kconfig"
source "arch/powerpc/cpu/mpc5xxx/Kconfig"
diff --git a/arch/powerpc/cpu/74xx_7xx/Kconfig b/arch/powerpc/cpu/74xx_7xx/Kconfig
deleted file mode 100644
index b2f1a59..0000000
--- a/arch/powerpc/cpu/74xx_7xx/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-menu "74xx_7xx CPU"
- depends on 74xx_7xx
-
-config SYS_CPU
- default "74xx_7xx"
-
-choice
- prompt "Target select"
-
-config TARGET_P3G4
- bool "Support P3G4"
-
-config TARGET_ZUMA
- bool "Support ZUMA"
-
-config TARGET_PPMC7XX
- bool "Support ppmc7xx"
-
-config TARGET_ELPPC
- bool "Support ELPPC"
-
-config TARGET_MPC7448HPC2
- bool "Support mpc7448hpc2"
-
-endchoice
-
-source "board/eltec/elppc/Kconfig"
-source "board/evb64260/Kconfig"
-source "board/freescale/mpc7448hpc2/Kconfig"
-source "board/ppmc7xx/Kconfig"
-
-endmenu
diff --git a/arch/powerpc/cpu/74xx_7xx/Makefile b/arch/powerpc/cpu/74xx_7xx/Makefile
deleted file mode 100644
index f31fe75..0000000
--- a/arch/powerpc/cpu/74xx_7xx/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cache.o kgdb.o io.o
-obj-y += traps.o cpu.o cpu_init.o speed.o interrupts.o
diff --git a/arch/powerpc/cpu/74xx_7xx/cache.S b/arch/powerpc/cpu/74xx_7xx/cache.S
deleted file mode 100644
index 66c7298..0000000
--- a/arch/powerpc/cpu/74xx_7xx/cache.S
+++ /dev/null
@@ -1,404 +0,0 @@
-#include <config.h>
-#include <74xx_7xx.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#ifndef CACHE_LINE_SIZE
-# define CACHE_LINE_SIZE L1_CACHE_BYTES
-#endif
-
-#if CACHE_LINE_SIZE == 128
-#define LG_CACHE_LINE_SIZE 7
-#elif CACHE_LINE_SIZE == 32
-#define LG_CACHE_LINE_SIZE 5
-#elif CACHE_LINE_SIZE == 16
-#define LG_CACHE_LINE_SIZE 4
-#elif CACHE_LINE_SIZE == 8
-#define LG_CACHE_LINE_SIZE 3
-#else
-# error "Invalid cache line size!"
-#endif
-
-/*
- * Invalidate L1 instruction cache.
- */
-_GLOBAL(invalidate_l1_instruction_cache)
- mfspr r3,PVR
- rlwinm r3,r3,16,16,31
- cmpi 0,r3,1
- beqlr /* for 601, do nothing */
- /* 603/604 processor - use invalidate-all bit in HID0 */
- mfspr r3,HID0
- ori r3,r3,HID0_ICFI
- mtspr HID0,r3
- isync
- blr
-
-/*
- * Invalidate L1 data cache.
- */
-_GLOBAL(invalidate_l1_data_cache)
- mfspr r3,HID0
- ori r3,r3,HID0_DCFI
- mtspr HID0,r3
- isync
- blr
-
-/*
- * Flush data cache.
- */
-_GLOBAL(flush_dcache)
- lis r3,0
- lis r5,CACHE_LINE_SIZE
-flush:
- cmp 0,1,r3,r5
- bge done
- lwz r5,0(r3)
- lis r5,CACHE_LINE_SIZE
- addi r3,r3,0x4
- b flush
-done:
- blr
-/*
- * Write any modified data cache blocks out to memory
- * and invalidate the corresponding instruction cache blocks.
- * This is a no-op on the 601.
- *
- * flush_icache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(flush_icache_range)
- mfspr r5,PVR
- rlwinm r5,r5,16,16,31
- cmpi 0,r5,1
- beqlr /* for 601, do nothing */
- li r5,CACHE_LINE_SIZE-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,LG_CACHE_LINE_SIZE
- beqlr
- mtctr r4
- mr r6,r3
-1: dcbst 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- mtctr r4
-2: icbi 0,r6
- addi r6,r6,CACHE_LINE_SIZE
- bdnz 2b
- sync /* additional sync needed on g4 */
- isync
- blr
-/*
- * Write any modified data cache blocks out to memory.
- * Does not invalidate the corresponding cache lines (especially for
- * any corresponding instruction cache).
- *
- * clean_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(clean_dcache_range)
- li r5,CACHE_LINE_SIZE-1
- andc r3,r3,r5 /* align r3 down to cache line */
- subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
- add r4,r4,r5 /* r4 += cache_line_size-1 */
- srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
- beqlr /* if r4 == 0 return */
- mtctr r4 /* ctr = r4 */
-
- sync
-1: dcbst 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- blr
-
-/*
- * Write any modified data cache blocks out to memory
- * and invalidate the corresponding instruction cache blocks.
- *
- * flush_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(flush_dcache_range)
- li r5,CACHE_LINE_SIZE-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,LG_CACHE_LINE_SIZE
- beqlr
- mtctr r4
-
- sync
-1: dcbf 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync /* wait for dcbf's to get to ram */
- blr
-
-/*
- * Like above, but invalidate the D-cache. This is used by the 8xx
- * to invalidate the cache so the PPC core doesn't get stale data
- * from the CPM (no cache snooping here :-).
- *
- * invalidate_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(invalidate_dcache_range)
- li r5,CACHE_LINE_SIZE-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,LG_CACHE_LINE_SIZE
- beqlr
- mtctr r4
-
- sync
-1: dcbi 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync /* wait for dcbi's to get to ram */
- blr
-
-/*
- * Flush a particular page from the data cache to RAM.
- * Note: this is necessary because the instruction cache does *not*
- * snoop from the data cache.
- * This is a no-op on the 601 which has a unified cache.
- *
- * void __flush_page_to_ram(void *page)
- */
-_GLOBAL(__flush_page_to_ram)
- mfspr r5,PVR
- rlwinm r5,r5,16,16,31
- cmpi 0,r5,1
- beqlr /* for 601, do nothing */
- rlwinm r3,r3,0,0,19 /* Get page base address */
- li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
- mtctr r4
- mr r6,r3
-0: dcbst 0,r3 /* Write line to ram */
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 0b
- sync
- mtctr r4
-1: icbi 0,r6
- addi r6,r6,CACHE_LINE_SIZE
- bdnz 1b
- sync
- isync
- blr
-
-/*
- * Flush a particular page from the instruction cache.
- * Note: this is necessary because the instruction cache does *not*
- * snoop from the data cache.
- * This is a no-op on the 601 which has a unified cache.
- *
- * void __flush_icache_page(void *page)
- */
-_GLOBAL(__flush_icache_page)
- mfspr r5,PVR
- rlwinm r5,r5,16,16,31
- cmpi 0,r5,1
- beqlr /* for 601, do nothing */
- li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
- mtctr r4
-1: icbi 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync
- isync
- blr
-
-/*
- * Clear a page using the dcbz instruction, which doesn't cause any
- * memory traffic (except to write out any cache lines which get
- * displaced). This only works on cacheable memory.
- */
-_GLOBAL(clear_page)
- li r0,4096/CACHE_LINE_SIZE
- mtctr r0
-1: dcbz 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- blr
-
-/*
- * Enable L1 Instruction cache
- */
-_GLOBAL(icache_enable)
- mfspr r3, HID0
- li r5, HID0_ICFI|HID0_ILOCK
- andc r3, r3, r5
- ori r3, r3, HID0_ICE
- ori r5, r3, HID0_ICFI
- mtspr HID0, r5
- mtspr HID0, r3
- isync
- blr
-
-/*
- * Disable L1 Instruction cache
- */
-_GLOBAL(icache_disable)
- mflr r4
- bl invalidate_l1_instruction_cache /* uses r3 */
- sync
- mtlr r4
- mfspr r3, HID0
- li r5, 0
- ori r5, r5, HID0_ICE
- andc r3, r3, r5
- mtspr HID0, r3
- isync
- blr
-
-/*
- * Is instruction cache enabled?
- */
-_GLOBAL(icache_status)
- mfspr r3, HID0
- andi. r3, r3, HID0_ICE
- blr
-
-
-_GLOBAL(l1dcache_enable)
- mfspr r3, HID0
- li r5, HID0_DCFI|HID0_DLOCK
- andc r3, r3, r5
- mtspr HID0, r3 /* no invalidate, unlock */
- ori r3, r3, HID0_DCE
- ori r5, r3, HID0_DCFI
- mtspr HID0, r5 /* enable + invalidate */
- mtspr HID0, r3 /* enable */
- sync
- blr
-
-/*
- * Enable data cache(s) - L1 and optionally L2
- * Calls l2cache_enable. LR saved in r5
- */
-_GLOBAL(dcache_enable)
- mfspr r3, HID0
- li r5, HID0_DCFI|HID0_DLOCK
- andc r3, r3, r5
- mtspr HID0, r3 /* no invalidate, unlock */
- ori r3, r3, HID0_DCE
- ori r5, r3, HID0_DCFI
- mtspr HID0, r5 /* enable + invalidate */
- mtspr HID0, r3 /* enable */
- sync
-#ifdef CONFIG_SYS_L2
- mflr r5
- bl l2cache_enable /* uses r3 and r4 */
- sync
- mtlr r5
-#endif
- blr
-
-
-/*
- * Disable data cache(s) - L1 and optionally L2
- * Calls flush_dcache and l2cache_disable_no_flush.
- * LR saved in r4
- */
-_GLOBAL(dcache_disable)
- mflr r4 /* save link register */
- bl flush_dcache /* uses r3 and r5 */
- sync
- mfspr r3, HID0
- li r5, HID0_DCFI|HID0_DLOCK
- andc r3, r3, r5
- mtspr HID0, r3 /* no invalidate, unlock */
- li r5, HID0_DCE|HID0_DCFI
- andc r3, r3, r5 /* no enable, no invalidate */
- mtspr HID0, r3
- sync
-#ifdef CONFIG_SYS_L2
- bl l2cache_disable_no_flush /* uses r3 */
-#endif
- mtlr r4 /* restore link register */
- blr
-
-/*
- * Is data cache enabled?
- */
-_GLOBAL(dcache_status)
- mfspr r3, HID0
- andi. r3, r3, HID0_DCE
- blr
-
-/*
- * Invalidate L2 cache using L2I and polling L2IP or L2I
- */
-_GLOBAL(l2cache_invalidate)
- sync
- mfspr r3, l2cr
- oris r3, r3, L2CR_L2I@h
- sync
- mtspr l2cr, r3
- sync
- mfspr r3, PVR
- sync
- rlwinm r3, r3, 16,16,31
- cmpli 0,r3,0x8000 /* 7451, 7441 */
- beq 0,inv_7450
- cmpli 0,r3,0x8001 /* 7455, 7445 */
- beq 0,inv_7450
- cmpli 0,r3,0x8002 /* 7457, 7447 */
- beq 0,inv_7450
- cmpli 0,r3,0x8003 /* 7447A */
- beq 0,inv_7450
- cmpli 0,r3,0x8004 /* 7448 */
- beq 0,inv_7450
-invl2:
- mfspr r3, l2cr
- andi. r3, r3, L2CR_L2IP
- bne invl2
- /* turn off the global invalidate bit */
- mfspr r3, l2cr
- rlwinm r3, r3, 0, 11, 9
- sync
- mtspr l2cr, r3
- sync
- blr
-inv_7450:
- mfspr r3, l2cr
- andis. r3, r3, L2CR_L2I@h
- bne inv_7450
- blr
-
-/*
- * Enable L2 cache
- * Calls l2cache_invalidate. LR is saved in r4
- */
-_GLOBAL(l2cache_enable)
- mflr r4 /* save link register */
- bl l2cache_invalidate /* uses r3 */
- sync
- lis r3, L2_ENABLE@h
- ori r3, r3, L2_ENABLE@l
- mtspr l2cr, r3
- isync
- mtlr r4 /* restore link register */
- blr
-
-/*
- * Disable L2 cache
- * Calls flush_dcache. LR is saved in r4
- */
-_GLOBAL(l2cache_disable)
- mflr r4 /* save link register */
- bl flush_dcache /* uses r3 and r5 */
- sync
- mtlr r4 /* restore link register */
-l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
- lis r3, L2_INIT@h
- ori r3, r3, L2_INIT@l
- mtspr l2cr, r3
- isync
- blr
diff --git a/arch/powerpc/cpu/74xx_7xx/config.mk b/arch/powerpc/cpu/74xx_7xx/config.mk
deleted file mode 100644
index 4cd1a26..0000000
--- a/arch/powerpc/cpu/74xx_7xx/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mstring
diff --git a/arch/powerpc/cpu/74xx_7xx/cpu.c b/arch/powerpc/cpu/74xx_7xx/cpu.c
deleted file mode 100644
index 6cd54bf..0000000
--- a/arch/powerpc/cpu/74xx_7xx/cpu.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * cpu.c
- *
- * CPU specific code
- *
- * written or collected and sometimes rewritten by
- * Magnus Damm <damm@bitsmart.com>
- *
- * minor modifications by
- * Wolfgang Denk <wd@denx.de>
- *
- * more modifications by
- * Josh Huber <huber@mclx.com>
- * added support for the 74xx series of cpus
- * added support for the 7xx series of cpus
- * made the code a little less hard-coded, and more auto-detectish
- */
-
-#include <common.h>
-#include <command.h>
-#include <74xx_7xx.h>
-#include <asm/cache.h>
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-cpu_t
-get_cpu_type(void)
-{
- uint pvr = get_pvr();
- cpu_t type;
-
- type = CPU_UNKNOWN;
-
- switch (PVR_VER(pvr)) {
- case 0x000c:
- type = CPU_7400;
- break;
- case 0x0008:
- type = CPU_750;
-
- if (((pvr >> 8) & 0xff) == 0x01) {
- type = CPU_750CX; /* old CX (80100 and 8010x?)*/
- } else if (((pvr >> 8) & 0xff) == 0x22) {
- type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */
- } else if (((pvr >> 8) & 0xff) == 0x33) {
- type = CPU_750CX; /* CXe (83311) */
- } else if (((pvr >> 12) & 0xF) == 0x3) {
- type = CPU_755;
- }
- break;
-
- case 0x7000:
- type = CPU_750FX;
- break;
-
- case 0x7002:
- type = CPU_750GX;
- break;
-
- case 0x800C:
- type = CPU_7410;
- break;
-
- case 0x8000:
- type = CPU_7450;
- break;
-
- case 0x8001:
- type = CPU_7455;
- break;
-
- case 0x8002:
- type = CPU_7457;
- break;
-
- case 0x8003:
- type = CPU_7447A;
- break;
-
- case 0x8004:
- type = CPU_7448;
- break;
-
- default:
- break;
- }
-
- return type;
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if !defined(CONFIG_BAB7xx)
-int checkcpu (void)
-{
- uint type = get_cpu_type();
- uint pvr = get_pvr();
- ulong clock = gd->cpu_clk;
- char buf[32];
- char *str;
-
- puts ("CPU: ");
-
- switch (type) {
- case CPU_750CX:
- printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"",
- (pvr>>8) & 0xf,
- pvr & 0xf);
- goto PR_CLK;
-
- case CPU_750:
- str = "750";
- break;
-
- case CPU_750FX:
- str = "750FX";
- break;
-
- case CPU_750GX:
- str = "750GX";
- break;
-
- case CPU_755:
- str = "755";
- break;
-
- case CPU_7400:
- str = "MPC7400";
- break;
-
- case CPU_7410:
- str = "MPC7410";
- break;
-
- case CPU_7447A:
- str = "MPC7447A";
- break;
-
- case CPU_7448:
- str = "MPC7448";
- break;
-
- case CPU_7450:
- str = "MPC7450";
- break;
-
- case CPU_7455:
- str = "MPC7455";
- break;
-
- case CPU_7457:
- str = "MPC7457";
- break;
-
- default:
- printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
- return -1;
- }
-
- printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF);
-PR_CLK:
- printf (" @ %s MHz\n", strmhz(buf, clock));
-
- return (0);
-}
-#endif
-/* these two functions are unimplemented currently [josh] */
-
-/* -------------------------------------------------------------------- */
-/* L1 i-cache */
-
-int
-checkicache(void)
-{
- return 0; /* XXX */
-}
-
-/* -------------------------------------------------------------------- */
-/* L1 d-cache */
-
-int
-checkdcache(void)
-{
- return 0; /* XXX */
-}
-
-/* -------------------------------------------------------------------- */
-
-static inline void
-soft_restart(unsigned long addr)
-{
- /* SRR0 has system reset vector, SRR1 has default MSR value */
- /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
-
- __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
- __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
- __asm__ __volatile__ ("mtspr 27, 4");
- __asm__ __volatile__ ("rfi");
-
- while(1); /* not reached */
-}
-
-
-#if !defined(CONFIG_BAB7xx) && \
- !defined(CONFIG_ELPPC) && \
- !defined(CONFIG_PPMC7XX)
-/* no generic way to do board reset. simply call soft_reset. */
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr;
- /* flush and disable I/D cache */
- __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
- __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
- __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
- __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("mtspr 1008, 4");
- __asm__ __volatile__ ("isync");
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("mtspr 1008, 5");
- __asm__ __volatile__ ("isync");
- __asm__ __volatile__ ("sync");
-
-#ifdef CONFIG_SYS_RESET_ADDRESS
- addr = CONFIG_SYS_RESET_ADDRESS;
-#else
- /*
- * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
- * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
- * address. Better pick an address known to be invalid on your
- * system and assign it to CONFIG_SYS_RESET_ADDRESS.
- */
- addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
-#endif
- soft_restart(addr);
-
- /* not reached */
- while(1)
- ;
-
- return 1;
-}
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
- */
-#ifndef CONFIG_SYS_BUS_CLK
-#define CONFIG_SYS_BUS_CLK gd->bus_clk
-#endif
-
-unsigned long get_tbclk(void)
-{
- return CONFIG_SYS_BUS_CLK / 4;
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_WATCHDOG)
-#if !defined(CONFIG_BAB7xx)
-void
-watchdog_reset(void)
-{
-
-}
-#endif /* !CONFIG_BAB7xx */
-#endif /* CONFIG_WATCHDOG */
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_OF_LIBFDT
-void ft_cpu_setup(void *blob, bd_t *bd)
-{
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", bd->bi_busfreq / 4, 1);
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "clock-frequency", bd->bi_intfreq, 1);
-
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-
- fdt_fixup_ethernet(blob);
-}
-#endif
-/* ------------------------------------------------------------------------- */
diff --git a/arch/powerpc/cpu/74xx_7xx/cpu_init.c b/arch/powerpc/cpu/74xx_7xx/cpu_init.c
deleted file mode 100644
index a6a8788..0000000
--- a/arch/powerpc/cpu/74xx_7xx/cpu_init.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * cpu_init.c - low level cpu init
- *
- * there's really nothing going on here yet. future work area?
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-
-/*
- * Breath some life into the CPU...
- *
- * there's basically nothing to do here since the memory controller
- * isn't on the CPU in this case.
- */
-void
-cpu_init_f (void)
-{
- switch (get_cpu_type()) {
- case CPU_7450:
- case CPU_7455:
- case CPU_7457:
- case CPU_7447A:
- case CPU_7448:
- /* enable the timebase bit in HID0 */
- set_hid0(get_hid0() | 0x4000000);
- break;
- default:
- /* do nothing */
- break;
- }
-}
-
-/*
- * initialize higher level parts of CPU like timers
- */
-int cpu_init_r (void)
-{
- return (0);
-}
diff --git a/arch/powerpc/cpu/74xx_7xx/interrupts.c b/arch/powerpc/cpu/74xx_7xx/interrupts.c
deleted file mode 100644
index a906243..0000000
--- a/arch/powerpc/cpu/74xx_7xx/interrupts.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * interrupts.c - just enough support for the decrementer/timer
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <mpc8xx_irq.h>
-#include <asm/processor.h>
-#include <commproc.h>
-#include <command.h>
-
-int interrupt_init_cpu (unsigned *decrementer_count)
-{
- debug("interrupt_init: GT main cause reg: %08x:%08x\n",
- GTREGREAD(LOW_INTERRUPT_CAUSE_REGISTER),
- GTREGREAD(HIGH_INTERRUPT_CAUSE_REGISTER));
- debug("interrupt_init: ethernet cause regs: %08x %08x %08x\n",
- GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER),
- GTREGREAD(ETHERNET1_INTERRUPT_CAUSE_REGISTER),
- GTREGREAD(ETHERNET2_INTERRUPT_CAUSE_REGISTER));
- debug("interrupt_init: ethernet mask regs: %08x %08x %08x\n",
- GTREGREAD(ETHERNET0_INTERRUPT_MASK_REGISTER),
- GTREGREAD(ETHERNET1_INTERRUPT_MASK_REGISTER),
- GTREGREAD(ETHERNET2_INTERRUPT_MASK_REGISTER));
- debug("interrupt_init: setting decrementer_count\n");
-
- *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
-
- return (0);
-}
-
-/****************************************************************************/
-
-/*
- * Handle external interrupts
- */
-void
-external_interrupt(struct pt_regs *regs)
-{
- puts("external_interrupt (oops!)\n");
-}
-
-volatile ulong timestamp = 0;
-
-/*
- * timer_interrupt - gets called when the decrementer overflows,
- * with interrupts disabled.
- * Trivial implementation - no need to be really accurate.
- */
-void
-timer_interrupt_cpu (struct pt_regs *regs)
-{
- /* nothing to do here */
- return;
-}
-
-/****************************************************************************/
-
-/*
- * Install and free a interrupt handler.
- */
-
-void
-irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
-{
-
-}
-
-void
-irq_free_handler(int vec)
-{
-
-}
-
-/****************************************************************************/
-
-void
-do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
-{
- puts("IRQ related functions are unimplemented currently.\n");
-}
diff --git a/arch/powerpc/cpu/74xx_7xx/io.S b/arch/powerpc/cpu/74xx_7xx/io.S
deleted file mode 100644
index 3b4b08a..0000000
--- a/arch/powerpc/cpu/74xx_7xx/io.S
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
- * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- * Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- * Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <ppc_asm.tmpl>
-
-/* ------------------------------------------------------------------------------- */
-/* Function: in8 */
-/* Description: Input 8 bits */
-/* ------------------------------------------------------------------------------- */
- .globl in8
-in8:
- lbz r3,0(r3)
- sync
- blr
-
-/* ------------------------------------------------------------------------------- */
-/* Function: in16 */
-/* Description: Input 16 bits */
-/* ------------------------------------------------------------------------------- */
- .globl in16
-in16:
- lhz r3,0(r3)
- sync
- blr
-
-/* ------------------------------------------------------------------------------- */
-/* Function: in16r */
-/* Description: Input 16 bits and byte reverse */
-/* ------------------------------------------------------------------------------- */
- .globl in16r
-in16r:
- lhbrx r3,0,r3
- sync
- blr
-
-/* ------------------------------------------------------------------------------- */
-/* Function: in32 */
-/* Description: Input 32 bits */
-/* ------------------------------------------------------------------------------- */
- .globl in32
-in32:
- lwz 3,0(3)
- sync
- blr
-
-/* ------------------------------------------------------------------------------- */
-/* Function: in32r */
-/* Description: Input 32 bits and byte reverse */
-/* ------------------------------------------------------------------------------- */
- .globl in32r
-in32r:
- lwbrx r3,0,r3
- sync
- blr
-
-/* ------------------------------------------------------------------------------- */
-/* Function: out8 */
-/* Description: Output 8 bits */
-/* ------------------------------------------------------------------------------- */
- .globl out8
-out8:
- stb r4,0(r3)
- sync
- blr
-
-/* ------------------------------------------------------------------------------- */
-/* Function: out16 */
-/* Description: Output 16 bits */
-/* ------------------------------------------------------------------------------- */
- .globl out16
-out16:
- sth r4,0(r3)
- sync
- blr
-
-/* ------------------------------------------------------------------------------- */
-/* Function: out16r */
-/* Description: Byte reverse and output 16 bits */
-/* ------------------------------------------------------------------------------- */
- .globl out16r
-out16r:
- sthbrx r4,0,r3
- sync
- blr
-
-/* ------------------------------------------------------------------------------- */
-/* Function: out32 */
-/* Description: Output 32 bits */
-/* ------------------------------------------------------------------------------- */
- .globl out32
-out32:
- stw r4,0(r3)
- sync
- blr
-
-/* ------------------------------------------------------------------------------- */
-/* Function: out32r */
-/* Description: Byte reverse and output 32 bits */
-/* ------------------------------------------------------------------------------- */
- .globl out32r
-out32r:
- stwbrx r4,0,r3
- sync
- blr
diff --git a/arch/powerpc/cpu/74xx_7xx/kgdb.S b/arch/powerpc/cpu/74xx_7xx/kgdb.S
deleted file mode 100644
index 42b3a76..0000000
--- a/arch/powerpc/cpu/74xx_7xx/kgdb.S
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <command.h>
-#include <74xx_7xx.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#if defined(CONFIG_CMD_KGDB)
-
- /*
- * cache flushing routines for kgdb
- */
-
- .globl kgdb_flush_cache_all
-kgdb_flush_cache_all:
- lis r3,0
- addis r4,r0,0x0040
-kgdb_flush_loop:
- lwz r5,0(r3)
- addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
- cmp 0,0,r3,r4
- bne kgdb_flush_loop
- SYNC
- mfspr r3,1008
- ori r3,r3,0x8800
- mtspr 1008,r3
- sync
- blr
-
- .globl kgdb_flush_cache_range
-kgdb_flush_cache_range:
- li r5,CONFIG_SYS_CACHELINE_SIZE-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
- beqlr
- mtctr r4
- mr r6,r3
-1: dcbst 0,r3
- addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- mtctr r4
-2: icbi 0,r6
- addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
- bdnz 2b
- SYNC
- blr
-
-#endif
diff --git a/arch/powerpc/cpu/74xx_7xx/speed.c b/arch/powerpc/cpu/74xx_7xx/speed.c
deleted file mode 100644
index 5ffa41c..0000000
--- a/arch/powerpc/cpu/74xx_7xx/speed.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern unsigned long get_board_bus_clk (void);
-
-static const int hid1_multipliers_x_10[] = {
- 25, /* 0000 - 2.5x */
- 75, /* 0001 - 7.5x */
- 70, /* 0010 - 7x */
- 10, /* 0011 - bypass */
- 20, /* 0100 - 2x */
- 65, /* 0101 - 6.5x */
- 100, /* 0110 - 10x */
- 45, /* 0111 - 4.5x */
- 30, /* 1000 - 3x */
- 55, /* 1001 - 5.5x */
- 40, /* 1010 - 4x */
- 50, /* 1011 - 5x */
- 80, /* 1100 - 8x */
- 60, /* 1101 - 6x */
- 35, /* 1110 - 3.5x */
- 0 /* 1111 - off */
-};
-
-/* PLL_CFG[0:4] table for cpu 7448/7447A/7455/7457 */
-static const int hid1_74xx_multipliers_x_10[] = {
- 115, /* 00000 - 11.5x */
- 170, /* 00001 - 17x */
- 75, /* 00010 - 7.5x */
- 150, /* 00011 - 15x */
- 70, /* 00100 - 7x */
- 180, /* 00101 - 18x */
- 10, /* 00110 - bypass */
- 200, /* 00111 - 20x */
- 20, /* 01000 - 2x */
- 210, /* 01001 - 21x */
- 65, /* 01010 - 6.5x */
- 130, /* 01011 - 13x */
- 85, /* 01100 - 8.5x */
- 240, /* 01101 - 24x */
- 95, /* 01110 - 9.5x */
- 90, /* 01111 - 9x */
- 30, /* 10000 - 3x */
- 105, /* 10001 - 10.5x */
- 55, /* 10010 - 5.5x */
- 110, /* 10011 - 11x */
- 40, /* 10100 - 4x */
- 100, /* 10101 - 10x */
- 50, /* 10110 - 5x */
- 120, /* 10111 - 12x */
- 80, /* 11000 - 8x */
- 140, /* 11001 - 14x */
- 60, /* 11010 - 6x */
- 160, /* 11011 - 16x */
- 135, /* 11100 - 13.5x */
- 280, /* 11101 - 28x */
- 0, /* 11110 - off */
- 125 /* 11111 - 12.5x */
-};
-
-static const int hid1_fx_multipliers_x_10[] = {
- 00, /* 0000 - off */
- 00, /* 0001 - off */
- 10, /* 0010 - bypass */
- 10, /* 0011 - bypass */
- 20, /* 0100 - 2x */
- 25, /* 0101 - 2.5x */
- 30, /* 0110 - 3x */
- 35, /* 0111 - 3.5x */
- 40, /* 1000 - 4x */
- 45, /* 1001 - 4.5x */
- 50, /* 1010 - 5x */
- 55, /* 1011 - 5.5x */
- 60, /* 1100 - 6x */
- 65, /* 1101 - 6.5x */
- 70, /* 1110 - 7x */
- 75, /* 1111 - 7.5 */
- 80, /* 10000 - 8x */
- 85, /* 10001 - 8.5x */
- 90, /* 10010 - 9x */
- 95, /* 10011 - 9.5x */
- 100, /* 10100 - 10x */
- 110, /* 10101 - 11x */
- 120, /* 10110 - 12x */
-};
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Measure CPU clock speed (core clock GCLK1, GCLK2)
- *
- * (Approx. GCLK frequency in Hz)
- */
-
-int get_clocks (void)
-{
- ulong clock = 0;
-
-#ifdef CONFIG_SYS_BUS_CLK
- gd->bus_clk = CONFIG_SYS_BUS_CLK; /* bus clock is a fixed frequency */
-#else
- gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
-#endif
-
- /* calculate the clock frequency based upon the CPU type */
- switch (get_cpu_type()) {
- case CPU_7447A:
- case CPU_7448:
- case CPU_7455:
- case CPU_7457:
- /*
- * Make sure division is done before multiplication to prevent 32-bit
- * arithmetic overflows which will cause a negative number
- */
- clock = (gd->bus_clk / 10) *
- hid1_74xx_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
- break;
-
- case CPU_750GX:
- case CPU_750FX:
- clock = (gd->bus_clk / 10) *
- hid1_fx_multipliers_x_10[get_hid1 () >> 27];
- break;
-
- case CPU_7450:
- case CPU_740:
- case CPU_740P:
- case CPU_745:
- case CPU_750CX:
- case CPU_750:
- case CPU_750P:
- case CPU_755:
- case CPU_7400:
- case CPU_7410:
- /*
- * Make sure division is done before multiplication to prevent 32-bit
- * arithmetic overflows which will cause a negative number
- */
- clock = (gd->bus_clk / 10) *
- hid1_multipliers_x_10[get_hid1 () >> 28];
- break;
-
- case CPU_UNKNOWN:
- printf ("get_gclk_freq(): unknown CPU type\n");
- clock = 0;
- return (1);
- }
-
- gd->cpu_clk = clock;
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S
deleted file mode 100644
index 8393781..0000000
--- a/arch/powerpc/cpu/74xx_7xx/start.S
+++ /dev/null
@@ -1,829 +0,0 @@
-/*
- * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
- * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
- * Copyright (C) 2001 Josh Huber <huber@mclx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* U-Boot - Startup Code for PowerPC based Embedded Boards
- *
- *
- * The processor starts at 0xfff00100 and the code is executed
- * from flash. The code is organized to be at an other address
- * in memory, but as long we don't jump around before relocating.
- * board_init lies at a quite high address and when the cpu has
- * jumped there, everything is ok.
- */
-#include <asm-offsets.h>
-#include <config.h>
-#include <74xx_7xx.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/u-boot.h>
-
-/* We don't want the MMU yet.
-*/
-#undef MSR_KERNEL
-/* Machine Check and Recoverable Interr. */
-#define MSR_KERNEL ( MSR_ME | MSR_RI )
-
-/*
- * Set up GOT: Global Offset Table
- *
- * Use r12 to access the GOT
- */
- START_GOT
- GOT_ENTRY(_GOT2_TABLE_)
- GOT_ENTRY(_FIXUP_TABLE_)
-
- GOT_ENTRY(_start)
- GOT_ENTRY(_start_of_vectors)
- GOT_ENTRY(_end_of_vectors)
- GOT_ENTRY(transfer_to_handler)
-
- GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end)
- GOT_ENTRY(__bss_start)
- END_GOT
-
-/*
- * r3 - 1st arg to board_init(): IMMP pointer
- * r4 - 2nd arg to board_init(): boot flag
- */
- .text
- .long 0x27051956 /* U-Boot Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
-
- . = EXC_OFF_SYS_RESET
- .globl _start
-_start:
- b boot_cold
-
- /* the boot code is located below the exception table */
-
- .globl _start_of_vectors
-_start_of_vectors:
-
-/* Machine check */
- STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
-
-/* Data Storage exception. "Never" generated on the 860. */
- STD_EXCEPTION(0x300, DataStorage, UnknownException)
-
-/* Instruction Storage exception. "Never" generated on the 860. */
- STD_EXCEPTION(0x400, InstStorage, UnknownException)
-
-/* External Interrupt exception. */
- STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
-
-/* Alignment exception. */
- . = 0x600
-Alignment:
- EXCEPTION_PROLOG(SRR0, SRR1)
- mfspr r4,DAR
- stw r4,_DAR(r21)
- mfspr r5,DSISR
- stw r5,_DSISR(r21)
- addi r3,r1,STACK_FRAME_OVERHEAD
- EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-
-/* Program check exception */
- . = 0x700
-ProgramCheck:
- EXCEPTION_PROLOG(SRR0, SRR1)
- addi r3,r1,STACK_FRAME_OVERHEAD
- EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
- MSR_KERNEL, COPY_EE)
-
- /* No FPU on MPC8xx. This exception is not supposed to happen.
- */
- STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
-
- /* I guess we could implement decrementer, and may have
- * to someday for timekeeping.
- */
- STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
- STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
- STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
- STD_EXCEPTION(0xc00, SystemCall, UnknownException)
- STD_EXCEPTION(0xd00, SingleStep, UnknownException)
-
- STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
- STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
-
- /*
- * On the MPC8xx, this is a software emulation interrupt. It
- * occurs for all unimplemented and illegal instructions.
- */
- STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
-
- STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
- STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
- STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
- STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
-
- STD_EXCEPTION(0x1500, Reserved5, UnknownException)
- STD_EXCEPTION(0x1600, Reserved6, UnknownException)
- STD_EXCEPTION(0x1700, Reserved7, UnknownException)
- STD_EXCEPTION(0x1800, Reserved8, UnknownException)
- STD_EXCEPTION(0x1900, Reserved9, UnknownException)
- STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
- STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
-
- STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
- STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
- STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
- STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
-
- .globl _end_of_vectors
-_end_of_vectors:
-
- . = 0x2000
-
-boot_cold:
- /* disable everything */
- li r0, 0
- mtspr HID0, r0
- sync
- mtmsr 0
- bl invalidate_bats
- sync
-
-#ifdef CONFIG_SYS_L2
- /* init the L2 cache */
- addis r3, r0, L2_INIT@h
- ori r3, r3, L2_INIT@l
- sync
- mtspr l2cr, r3
-#endif
-#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
- .long 0x7e00066c
- /*
- * dssall instruction, gas doesn't have it yet
- * ...for altivec, data stream stop all this probably
- * isn't needed unless we warm (software) reboot U-Boot
- */
-#endif
-
-#ifdef CONFIG_SYS_L2
- /* invalidate the L2 cache */
- bl l2cache_invalidate
- sync
-#endif
-#ifdef CONFIG_SYS_BOARD_ASM_INIT
- /* do early init */
- bl board_asm_init
-#endif
-
- /*
- * Calculate absolute address in FLASH and jump there
- *------------------------------------------------------*/
- lis r3, CONFIG_SYS_MONITOR_BASE@h
- ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
- addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
- mtlr r3
- blr
-
-in_flash:
- /* let the C-code set up the rest */
- /* */
- /* Be careful to keep code relocatable ! */
- /*------------------------------------------------------*/
-
- /* perform low-level init */
- /* sdram init, galileo init, etc */
- /* r3: NHR bit from HID0 */
-
- /* setup the bats */
- bl setup_bats
- sync
-
- /*
- * Cache must be enabled here for stack-in-cache trick.
- * This means we need to enable the BATS.
- * This means:
- * 1) for the EVB, original gt regs need to be mapped
- * 2) need to have an IBAT for the 0xf region,
- * we are running there!
- * Cache should be turned on after BATs, since by default
- * everything is write-through.
- * The init-mem BAT can be reused after reloc. The old
- * gt-regs BAT can be reused after board_init_f calls
- * board_early_init_f (EVB only).
- */
-#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
- /* enable address translation */
- bl enable_addr_trans
- sync
-
- /* enable and invalidate the data cache */
- bl l1dcache_enable
- sync
-#endif
-#ifdef CONFIG_SYS_INIT_RAM_LOCK
- bl lock_ram_in_cache
- sync
-#endif
-
- /* set up the stack pointer in our newly created
- * cache-ram (r1) */
- lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
- ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
-
- li r0, 0 /* Make room for stack frame header and */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
-
- GET_GOT /* initialize GOT access */
-
- /* run low-level CPU init code (from Flash) */
- bl cpu_init_f
- sync
-
- /* run 1st part of board init code (from Flash) */
- bl board_init_f
- sync
-
- /* NOTREACHED - board_init_f() does not return */
-
- .globl invalidate_bats
-invalidate_bats:
- /* invalidate BATs */
- mtspr IBAT0U, r0
- mtspr IBAT1U, r0
- mtspr IBAT2U, r0
- mtspr IBAT3U, r0
-#ifdef CONFIG_HIGH_BATS
- mtspr IBAT4U, r0
- mtspr IBAT5U, r0
- mtspr IBAT6U, r0
- mtspr IBAT7U, r0
-#endif
- isync
- mtspr DBAT0U, r0
- mtspr DBAT1U, r0
- mtspr DBAT2U, r0
- mtspr DBAT3U, r0
-#ifdef CONFIG_HIGH_BATS
- mtspr DBAT4U, r0
- mtspr DBAT5U, r0
- mtspr DBAT6U, r0
- mtspr DBAT7U, r0
-#endif
- isync
- sync
- blr
-
- /* setup_bats - set them up to some initial state */
- .globl setup_bats
-setup_bats:
- addis r0, r0, 0x0000
-
- /* IBAT 0 */
- addis r4, r0, CONFIG_SYS_IBAT0L@h
- ori r4, r4, CONFIG_SYS_IBAT0L@l
- addis r3, r0, CONFIG_SYS_IBAT0U@h
- ori r3, r3, CONFIG_SYS_IBAT0U@l
- mtspr IBAT0L, r4
- mtspr IBAT0U, r3
- isync
-
- /* DBAT 0 */
- addis r4, r0, CONFIG_SYS_DBAT0L@h
- ori r4, r4, CONFIG_SYS_DBAT0L@l
- addis r3, r0, CONFIG_SYS_DBAT0U@h
- ori r3, r3, CONFIG_SYS_DBAT0U@l
- mtspr DBAT0L, r4
- mtspr DBAT0U, r3
- isync
-
- /* IBAT 1 */
- addis r4, r0, CONFIG_SYS_IBAT1L@h
- ori r4, r4, CONFIG_SYS_IBAT1L@l
- addis r3, r0, CONFIG_SYS_IBAT1U@h
- ori r3, r3, CONFIG_SYS_IBAT1U@l
- mtspr IBAT1L, r4
- mtspr IBAT1U, r3
- isync
-
- /* DBAT 1 */
- addis r4, r0, CONFIG_SYS_DBAT1L@h
- ori r4, r4, CONFIG_SYS_DBAT1L@l
- addis r3, r0, CONFIG_SYS_DBAT1U@h
- ori r3, r3, CONFIG_SYS_DBAT1U@l
- mtspr DBAT1L, r4
- mtspr DBAT1U, r3
- isync
-
- /* IBAT 2 */
- addis r4, r0, CONFIG_SYS_IBAT2L@h
- ori r4, r4, CONFIG_SYS_IBAT2L@l
- addis r3, r0, CONFIG_SYS_IBAT2U@h
- ori r3, r3, CONFIG_SYS_IBAT2U@l
- mtspr IBAT2L, r4
- mtspr IBAT2U, r3
- isync
-
- /* DBAT 2 */
- addis r4, r0, CONFIG_SYS_DBAT2L@h
- ori r4, r4, CONFIG_SYS_DBAT2L@l
- addis r3, r0, CONFIG_SYS_DBAT2U@h
- ori r3, r3, CONFIG_SYS_DBAT2U@l
- mtspr DBAT2L, r4
- mtspr DBAT2U, r3
- isync
-
- /* IBAT 3 */
- addis r4, r0, CONFIG_SYS_IBAT3L@h
- ori r4, r4, CONFIG_SYS_IBAT3L@l
- addis r3, r0, CONFIG_SYS_IBAT3U@h
- ori r3, r3, CONFIG_SYS_IBAT3U@l
- mtspr IBAT3L, r4
- mtspr IBAT3U, r3
- isync
-
- /* DBAT 3 */
- addis r4, r0, CONFIG_SYS_DBAT3L@h
- ori r4, r4, CONFIG_SYS_DBAT3L@l
- addis r3, r0, CONFIG_SYS_DBAT3U@h
- ori r3, r3, CONFIG_SYS_DBAT3U@l
- mtspr DBAT3L, r4
- mtspr DBAT3U, r3
- isync
-
-#ifdef CONFIG_HIGH_BATS
- /* IBAT 4 */
- addis r4, r0, CONFIG_SYS_IBAT4L@h
- ori r4, r4, CONFIG_SYS_IBAT4L@l
- addis r3, r0, CONFIG_SYS_IBAT4U@h
- ori r3, r3, CONFIG_SYS_IBAT4U@l
- mtspr IBAT4L, r4
- mtspr IBAT4U, r3
- isync
-
- /* DBAT 4 */
- addis r4, r0, CONFIG_SYS_DBAT4L@h
- ori r4, r4, CONFIG_SYS_DBAT4L@l
- addis r3, r0, CONFIG_SYS_DBAT4U@h
- ori r3, r3, CONFIG_SYS_DBAT4U@l
- mtspr DBAT4L, r4
- mtspr DBAT4U, r3
- isync
-
- /* IBAT 5 */
- addis r4, r0, CONFIG_SYS_IBAT5L@h
- ori r4, r4, CONFIG_SYS_IBAT5L@l
- addis r3, r0, CONFIG_SYS_IBAT5U@h
- ori r3, r3, CONFIG_SYS_IBAT5U@l
- mtspr IBAT5L, r4
- mtspr IBAT5U, r3
- isync
-
- /* DBAT 5 */
- addis r4, r0, CONFIG_SYS_DBAT5L@h
- ori r4, r4, CONFIG_SYS_DBAT5L@l
- addis r3, r0, CONFIG_SYS_DBAT5U@h
- ori r3, r3, CONFIG_SYS_DBAT5U@l
- mtspr DBAT5L, r4
- mtspr DBAT5U, r3
- isync
-
- /* IBAT 6 */
- addis r4, r0, CONFIG_SYS_IBAT6L@h
- ori r4, r4, CONFIG_SYS_IBAT6L@l
- addis r3, r0, CONFIG_SYS_IBAT6U@h
- ori r3, r3, CONFIG_SYS_IBAT6U@l
- mtspr IBAT6L, r4
- mtspr IBAT6U, r3
- isync
-
- /* DBAT 6 */
- addis r4, r0, CONFIG_SYS_DBAT6L@h
- ori r4, r4, CONFIG_SYS_DBAT6L@l
- addis r3, r0, CONFIG_SYS_DBAT6U@h
- ori r3, r3, CONFIG_SYS_DBAT6U@l
- mtspr DBAT6L, r4
- mtspr DBAT6U, r3
- isync
-
- /* IBAT 7 */
- addis r4, r0, CONFIG_SYS_IBAT7L@h
- ori r4, r4, CONFIG_SYS_IBAT7L@l
- addis r3, r0, CONFIG_SYS_IBAT7U@h
- ori r3, r3, CONFIG_SYS_IBAT7U@l
- mtspr IBAT7L, r4
- mtspr IBAT7U, r3
- isync
-
- /* DBAT 7 */
- addis r4, r0, CONFIG_SYS_DBAT7L@h
- ori r4, r4, CONFIG_SYS_DBAT7L@l
- addis r3, r0, CONFIG_SYS_DBAT7U@h
- ori r3, r3, CONFIG_SYS_DBAT7U@l
- mtspr DBAT7L, r4
- mtspr DBAT7U, r3
- isync
-#endif
-
- /* bats are done, now invalidate the TLBs */
-
- addis r3, 0, 0x0000
- addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
-
- isync
-
-tlblp:
- tlbie r3
- sync
- addi r3, r3, 0x1000
- cmp 0, 0, r3, r5
- blt tlblp
-
- blr
-
- .globl enable_addr_trans
-enable_addr_trans:
- /* enable address translation */
- mfmsr r5
- ori r5, r5, (MSR_IR | MSR_DR)
- mtmsr r5
- isync
- blr
-
- .globl disable_addr_trans
-disable_addr_trans:
- /* disable address translation */
- mflr r4
- mfmsr r3
- andi. r0, r3, (MSR_IR | MSR_DR)
- beqlr
- andc r3, r3, r0
- mtspr SRR0, r4
- mtspr SRR1, r3
- rfi
-
-/*
- * This code finishes saving the registers to the exception frame
- * and jumps to the appropriate handler for the exception.
- * Register r21 is pointer into trap frame, r1 has new stack pointer.
- */
- .globl transfer_to_handler
-transfer_to_handler:
- stw r22,_NIP(r21)
- lis r22,MSR_POW@h
- andc r23,r23,r22
- stw r23,_MSR(r21)
- SAVE_GPR(7, r21)
- SAVE_4GPRS(8, r21)
- SAVE_8GPRS(12, r21)
- SAVE_8GPRS(24, r21)
- mflr r23
- andi. r24,r23,0x3f00 /* get vector offset */
- stw r24,TRAP(r21)
- li r22,0
- stw r22,RESULT(r21)
- mtspr SPRG2,r22 /* r1 is now kernel sp */
- lwz r24,0(r23) /* virtual address of handler */
- lwz r23,4(r23) /* where to go when done */
- mtspr SRR0,r24
- mtspr SRR1,r20
- mtlr r23
- SYNC
- rfi /* jump to handler, enable MMU */
-
-int_return:
- mfmsr r28 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r28,r28,r4
- SYNC /* Some chip revs need this... */
- mtmsr r28
- SYNC
- lwz r2,_CTR(r1)
- lwz r0,_LINK(r1)
- mtctr r2
- mtlr r0
- lwz r2,_XER(r1)
- lwz r0,_CCR(r1)
- mtspr XER,r2
- mtcrf 0xFF,r0
- REST_10GPRS(3, r1)
- REST_10GPRS(13, r1)
- REST_8GPRS(23, r1)
- REST_GPR(31, r1)
- lwz r2,_NIP(r1) /* Restore environment */
- lwz r0,_MSR(r1)
- mtspr SRR0,r2
- mtspr SRR1,r0
- lwz r0,GPR0(r1)
- lwz r2,GPR2(r1)
- lwz r1,GPR1(r1)
- SYNC
- rfi
-
- .globl dc_read
-dc_read:
- blr
-
- .globl get_pvr
-get_pvr:
- mfspr r3, PVR
- blr
-
-/*-----------------------------------------------------------------------*/
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
- */
- .globl relocate_code
-relocate_code:
- mr r1, r3 /* Set new stack pointer */
- mr r9, r4 /* Save copy of Global Data pointer */
- mr r10, r5 /* Save copy of Destination Address */
-
- GET_GOT
- mr r3, r5 /* Destination Address */
- lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
- lwz r5, GOT(__init_end)
- sub r5, r5, r4
- li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
-
- /*
- * Fix GOT pointer:
- *
- * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
- *
- * Offset:
- */
- sub r15, r10, r4
-
- /* First our own GOT */
- add r12, r12, r15
- /* then the one used by the C code */
- add r30, r30, r15
-
- /*
- * Now relocate code
- */
-#ifdef CONFIG_ECC
- bl board_relocate_rom
- sync
- mr r3, r10 /* Destination Address */
- lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
- lwz r5, GOT(__init_end)
- sub r5, r5, r4
- li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
-#else
- cmplw cr1,r3,r4
- addi r0,r5,3
- srwi. r0,r0,2
- beq cr1,4f /* In place copy is not necessary */
- beq 7f /* Protect against 0 count */
- mtctr r0
- bge cr1,2f
-
- la r8,-4(r4)
- la r7,-4(r3)
-1: lwzu r0,4(r8)
- stwu r0,4(r7)
- bdnz 1b
- b 4f
-
-2: slwi r0,r0,2
- add r8,r4,r0
- add r7,r3,r0
-3: lwzu r0,-4(r8)
- stwu r0,-4(r7)
- bdnz 3b
-#endif
-/*
- * Now flush the cache: note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line.
- */
-4: cmpwi r6,0
- add r5,r3,r5
- beq 7f /* Always flush prefetch queue in any case */
- subi r0,r6,1
- andc r3,r3,r0
- mr r4,r3
-5: dcbst 0,r4
- add r4,r4,r6
- cmplw r4,r5
- blt 5b
- sync /* Wait for all dcbst to complete on bus */
- mr r4,r3
-6: icbi 0,r4
- add r4,r4,r6
- cmplw r4,r5
- blt 6b
-7: sync /* Wait for all icbi to complete on bus */
- isync
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
- addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
- mtlr r0
- blr
-
-in_ram:
-#ifdef CONFIG_ECC
- bl board_init_ecc
-#endif
- /*
- * Relocation Function, r12 point to got2+0x8000
- *
- * Adjust got2 pointers, no need to check for 0, this code
- * already puts a few entries in the table.
- */
- li r0,__got2_entries@sectoff@l
- la r3,GOT(_GOT2_TABLE_)
- lwz r11,GOT(_GOT2_TABLE_)
- mtctr r0
- sub r11,r3,r11
- addi r3,r3,-4
-1: lwzu r0,4(r3)
- cmpwi r0,0
- beq- 2f
- add r0,r0,r11
- stw r0,0(r3)
-2: bdnz 1b
-
- /*
- * Now adjust the fixups and the pointers to the fixups
- * in case we need to move ourselves again.
- */
- li r0,__fixup_entries@sectoff@l
- lwz r3,GOT(_FIXUP_TABLE_)
- cmpwi r0,0
- mtctr r0
- addi r3,r3,-4
- beq 4f
-3: lwzu r4,4(r3)
- lwzux r0,r4,r11
- cmpwi r0,0
- add r0,r0,r11
- stw r4,0(r3)
- beq- 5f
- stw r0,0(r4)
-5: bdnz 3b
-4:
-/* clear_bss: */
- /*
- * Now clear BSS segment
- */
- lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end)
-
- cmplw 0, r3, r4
- beq 6f
-
- li r0, 0
-5:
- stw r0, 0(r3)
- addi r3, r3, 4
- cmplw 0, r3, r4
- bne 5b
-6:
- mr r3, r10 /* Destination Address */
-#if defined(CONFIG_PPMC7XX)
- mr r4, r9 /* Use RAM copy of the global data */
-#endif
- bl after_reloc
-
- /* not reached - end relocate_code */
-/*-----------------------------------------------------------------------*/
-
- /*
- * Copy exception vector code to low memory
- *
- * r3: dest_addr
- * r7: source address, r8: end address, r9: target address
- */
- .globl trap_init
-trap_init:
- mflr r4 /* save link register */
- GET_GOT
- lwz r7, GOT(_start)
- lwz r8, GOT(_end_of_vectors)
-
- li r9, 0x100 /* reset vector always at 0x100 */
-
- cmplw 0, r7, r8
- bgelr /* return if r7>=r8 - just in case */
-1:
- lwz r0, 0(r7)
- stw r0, 0(r9)
- addi r7, r7, 4
- addi r9, r9, 4
- cmplw 0, r7, r8
- bne 1b
-
- /*
- * relocate `hdlr' and `int_return' entries
- */
- li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
- li r8, Alignment - _start + EXC_OFF_SYS_RESET
-2:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 2b
-
- li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
- bl trap_reloc
-
- li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
- bl trap_reloc
-
- li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
- li r8, SystemCall - _start + EXC_OFF_SYS_RESET
-3:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 3b
-
- li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
- li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
-4:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 4b
-
- /* enable execptions from RAM vectors */
- mfmsr r7
- li r8,MSR_IP
- andc r7,r7,r8
- mtmsr r7
-
- mtlr r4 /* restore link register */
- blr
-
-#ifdef CONFIG_SYS_INIT_RAM_LOCK
-lock_ram_in_cache:
- /* Allocate Initial RAM in data cache.
- */
- lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
- (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r4
-1:
- dcbz r0, r3
- addi r3, r3, 32
- bdnz 1b
-
- /* Lock the data cache */
- mfspr r0, HID0
- ori r0, r0, 0x1000
- sync
- mtspr HID0, r0
- sync
- blr
-
-.globl unlock_ram_in_cache
-unlock_ram_in_cache:
- /* invalidate the INIT_RAM section */
- lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
- (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r4
-1: icbi r0, r3
- addi r3, r3, 32
- bdnz 1b
- sync /* Wait for all icbi to complete on bus */
- isync
-
- /* Unlock the data cache and invalidate it */
- mfspr r0, HID0
- li r3,0x1000
- andc r0,r0,r3
- li r3,0x0400
- or r0,r0,r3
- sync
- mtspr HID0, r0
- sync
- blr
-#endif
diff --git a/arch/powerpc/cpu/74xx_7xx/traps.c b/arch/powerpc/cpu/74xx_7xx/traps.c
deleted file mode 100644
index 111c86c..0000000
--- a/arch/powerpc/cpu/74xx_7xx/traps.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * linux/arch/powerpc/kernel/traps.c
- *
- * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
- *
- * Modified by Cort Dougan (cort@cs.nmt.edu)
- * and Paul Mackerras (paulus@cs.anu.edu.au)
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This file handles the architecture-dependent parts of hardware exceptions
- */
-
-#include <common.h>
-#include <command.h>
-#include <kgdb.h>
-#include <asm/processor.h>
-
-/* Returns 0 if exception not found and fixup otherwise. */
-extern unsigned long search_exception_table(unsigned long);
-
-/* THIS NEEDS CHANGING to use the board info structure.
-*/
-#define END_OF_MEM 0x02000000
-
-/*
- * Trap & Exception support
- */
-
-static void print_backtrace(unsigned long *sp)
-{
- int cnt = 0;
- unsigned long i;
-
- printf("Call backtrace: ");
- while (sp) {
- if ((uint)sp > END_OF_MEM)
- break;
-
- i = sp[1];
- if (cnt++ % 7 == 0)
- printf("\n");
- printf("%08lX ", i);
- if (cnt > 32) break;
- sp = (unsigned long *)*sp;
- }
- printf("\n");
-}
-
-void show_regs(struct pt_regs *regs)
-{
- int i;
-
- printf("NIP: %08lX XER: %08lX LR: %08lX REGS:"
- " %p TRAP: %04lx DAR: %08lX\n",
- regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
- printf("MSR: %08lx EE: %01x PR: %01x FP:"
- " %01x ME: %01x IR/DR: %01x%01x\n",
- regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
- regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
- regs->msr&MSR_IR ? 1 : 0,
- regs->msr&MSR_DR ? 1 : 0);
-
- printf("\n");
- for (i = 0; i < 32; i++) {
- if ((i % 8) == 0)
- {
- printf("GPR%02d: ", i);
- }
-
- printf("%08lX ", regs->gpr[i]);
- if ((i % 8) == 7)
- {
- printf("\n");
- }
- }
-}
-
-
-static void _exception(int signr, struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
-}
-
-void MachineCheckException(struct pt_regs *regs)
-{
- unsigned long fixup;
-
- /* Probing PCI using config cycles cause this exception
- * when a device is not present. Catch it and return to
- * the PCI exception handler.
- */
- if ((fixup = search_exception_table(regs->nip)) != 0) {
- regs->nip = fixup;
- return;
- }
-
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return;
-#endif
-
- printf("Machine check in kernel mode.\n");
- printf("Caused by (from msr): ");
- printf("regs %p ",regs);
- switch( regs->msr & 0x000F0000) {
- case (0x80000000>>12):
- printf("Machine check signal - probably due to mm fault\n"
- "with mmu off\n");
- break;
- case (0x80000000>>13):
- printf("Transfer error ack signal\n");
- break;
- case (0x80000000>>14):
- printf("Data parity signal\n");
- break;
- case (0x80000000>>15):
- printf("Address parity signal\n");
- break;
- default:
- printf("Unknown values in msr\n");
- }
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("machine check");
-}
-
-void AlignmentException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return;
-#endif
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Alignment Exception");
-}
-
-void ProgramCheckException(struct pt_regs *regs)
-{
- unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
- int i, j;
-
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return;
-#endif
- show_regs(regs);
-
- p = (unsigned char *) ((unsigned long)p & 0xFFFFFFE0);
- p -= 32;
- for (i = 0; i < 256; i+=16) {
- printf("%08x: ", (unsigned int)p+i);
- for (j = 0; j < 16; j++) {
- printf("%02x ", p[i+j]);
- }
- printf("\n");
- }
-
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Program Check Exception");
-}
-
-void SoftEmuException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return;
-#endif
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Software Emulation Exception");
-}
-
-void UnknownException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- return;
-#endif
- printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
- regs->nip, regs->msr, regs->trap);
- _exception(0, regs);
-}
-
-/* Probe an address by reading. If not present, return -1, otherwise
- * return 0.
- */
-int addr_probe(uint *addr)
-{
-#if 0
- int retval;
-
- __asm__ __volatile__( \
- "1: lwz %0,0(%1)\n" \
- " eieio\n" \
- " li %0,0\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3: li %0,-1\n" \
- " b 2b\n" \
- ".section __ex_table,\"a\"\n" \
- " .align 2\n" \
- " .long 1b,3b\n" \
- ".text" \
- : "=r" (retval) : "r"(addr));
-
- return (retval);
-#endif
- return 0;
-}
diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds
deleted file mode 100644
index c099849..0000000
--- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2010 Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index e2e9cb7..9da00da 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -26,9 +26,6 @@
config TARGET_GALAXY5200
bool "Support galaxy5200"
-config TARGET_ICECUBE
- bool "Support IceCube"
-
config TARGET_INKA4X0
bool "Support inka4x0"
@@ -44,24 +41,9 @@
config TARGET_MUNICES
bool "Support munices"
-config TARGET_PM520
- bool "Support PM520"
-
-config TARGET_TOTAL5200
- bool "Support Total5200"
-
config TARGET_V38B
bool "Support v38b"
-config TARGET_CPCI5200
- bool "Support cpci5200"
-
-config TARGET_MECP5200
- bool "Support mecp5200"
-
-config TARGET_PF5200
- bool "Support pf5200"
-
config TARGET_O2D
bool "Support O2D"
@@ -105,11 +87,7 @@
source "board/bc3450/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
-source "board/esd/cpci5200/Kconfig"
-source "board/esd/mecp5200/Kconfig"
-source "board/esd/pf5200/Kconfig"
source "board/galaxy5200/Kconfig"
-source "board/icecube/Kconfig"
source "board/ifm/o2dnt2/Kconfig"
source "board/inka4x0/Kconfig"
source "board/intercontrol/digsy_mtc/Kconfig"
@@ -118,8 +96,6 @@
source "board/motionpro/Kconfig"
source "board/munices/Kconfig"
source "board/phytec/pcm030/Kconfig"
-source "board/pm520/Kconfig"
-source "board/total5200/Kconfig"
source "board/tqc/tqm5200/Kconfig"
source "board/v38b/Kconfig"
diff --git a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
index a89d5fd..70b7e6e 100644
--- a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
+++ b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
@@ -33,21 +33,7 @@
*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
eieio();
udelay(10);
-#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
- if (dev & 0x00ff0000) {
- u32 val;
- val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
- udelay(10);
- val = val << 16;
- val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
- *value = val;
- } else {
- *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
- }
- udelay(10);
-#else
*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
-#endif
eieio();
*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
udelay(10);
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 69a600c..4d6cb09 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -41,12 +41,6 @@
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
-config TARGET_MPC8360EMDS
- bool "Support MPC8360EMDS"
-
-config TARGET_MPC8360ERDK
- bool "Support MPC8360ERDK"
-
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
@@ -81,8 +75,6 @@
source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc8349itx/Kconfig"
-source "board/freescale/mpc8360emds/Kconfig"
-source "board/freescale/mpc8360erdk/Kconfig"
source "board/freescale/mpc837xemds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7501eb4..adb5bd3 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -85,11 +85,6 @@
config TARGET_P1023RDB
bool "Support P1023RDB"
-config TARGET_P1_P2_RDB
- bool "Support P1_P2_RDB"
- select SUPPORT_SPL
- select SUPPORT_TPL
-
config TARGET_P1_P2_RDB_PC
bool "Support p1_p2_rdb_pc"
select SUPPORT_SPL
@@ -98,12 +93,6 @@
config TARGET_P1_TWR
bool "Support p1_twr"
-config TARGET_P2020COME
- bool "Support P2020COME"
-
-config TARGET_P2020DS
- bool "Support P2020DS"
-
config TARGET_P2041RDB
bool "Support P2041RDB"
@@ -184,11 +173,8 @@
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
-source "board/freescale/p1_p2_rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p1_twr/Kconfig"
-source "board/freescale/p2020come/Kconfig"
-source "board/freescale/p2020ds/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xqds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 598f7bd..fd7f5fa 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -57,7 +57,7 @@
SET_USB_LIODN(1, "fsl-usb2-dr", 553),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 85d32fc..4cf8853 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -424,7 +424,6 @@
ulong cpu_init_f(void)
{
- ulong flag = 0;
extern void m8560_cpm_reset (void);
#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
@@ -499,18 +498,11 @@
in_be32(&gur->dcsrcr);
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-#ifdef CONFIG_DEEP_SLEEP
- /* disable the console if boot from deep sleep */
- if (in_be32(&gur->scrtsr[0]) & (1 << 3))
- flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
-#endif
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
- return flag;
+ return 0;
}
/* Implement a dummy function for those platforms w/o SERDES */
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 5cfae47..acb1353 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -15,16 +15,16 @@
#include "fsl_corenet2_serdes.h"
#ifdef CONFIG_SYS_FSL_SRDS_1
-static u64 serdes1_prtcl_map;
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
-static u64 serdes2_prtcl_map;
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
-static u64 serdes3_prtcl_map;
+static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
-static u64 serdes4_prtcl_map;
+static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef DEBUG
@@ -78,24 +78,30 @@
[INTERLAKEN] = "INTERLAKEN",
[QSGMII_SW1_A] = "QSGMII_SW1_A",
[QSGMII_SW1_B] = "QSGMII_SW1_B",
+ [SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
+ [SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
+ [SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
+ [SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
+ [SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
+ [SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
};
#endif
int is_serdes_configured(enum srds_prtcl device)
{
- u64 ret = 0;
+ int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
- ret |= (1ULL << device) & serdes1_prtcl_map;
+ ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
- ret |= (1ULL << device) & serdes2_prtcl_map;
+ ret |= serdes2_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
- ret |= (1ULL << device) & serdes3_prtcl_map;
+ ret |= serdes3_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
- ret |= (1ULL << device) & serdes4_prtcl_map;
+ ret |= serdes4_prtcl_map[device];
#endif
return !!ret;
@@ -171,12 +177,14 @@
#define BCAP_OVD_MASK 0x10000000
#define BYP_CAL_MASK 0x02000000
-u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+ u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
+
+ memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
struct ccsr_sfp_regs __iomem *sfp_regs =
(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
@@ -312,38 +320,43 @@
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
- serdes_prtcl_map |= (1ULL << lane_prtcl);
+ if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+ debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+ else
+ serdes_prtcl_map[lane_prtcl] = 1;
}
-
- return serdes_prtcl_map;
}
void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
- serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+ serdes_init(FSL_SRDS_1,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
+ serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
- serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+ serdes_init(FSL_SRDS_2,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
+ serdes2_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
- serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
- FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
- FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
+ serdes_init(FSL_SRDS_3,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
+ serdes3_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
- serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
- FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
- FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
+ serdes_init(FSL_SRDS_4,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
+ serdes4_prtcl_map);
#endif
}
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
index 7dc8385..2ba314a 100644
--- a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
@@ -11,6 +11,7 @@
static u8 serdes_cfg_tbl[][4] = {
+ [0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
@@ -20,6 +21,7 @@
[0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
+ [0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
index d86bb27..d5dccd5 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -33,10 +33,10 @@
PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
- [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
- PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
- [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
- PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
+ [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+ PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
+ [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+ PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
diff --git a/arch/powerpc/cpu/mpc8xx/u-boot.lds b/arch/powerpc/cpu/mpc8xx/u-boot.lds
deleted file mode 100644
index 0eb2fba..0000000
--- a/arch/powerpc/cpu/mpc8xx/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 2d28eb2..c92589f 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -15,6 +15,7 @@
#include <netdev.h>
#include <asm/cache.h>
#include <asm/io.h>
+#include <vsc9953.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -271,5 +272,9 @@
#ifdef CONFIG_FMAN_ENET
fm_standard_init(bis);
#endif
+
+#ifdef CONFIG_VSC9953
+ vsc9953_init(bis);
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 1c63f93..9cc1676 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -73,176 +73,6 @@
}
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
-/*
- * update crypto node properties to a specified revision of the SEC
- * called with sec_rev == 0 if not on an E processor
- */
-#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
-void fdt_fixup_crypto_node(void *blob, int sec_rev)
-{
- static const struct sec_rev_prop {
- u32 sec_rev;
- u32 num_channels;
- u32 channel_fifo_len;
- u32 exec_units_mask;
- u32 descriptor_types_mask;
- } sec_rev_prop_list [] = {
- { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
- { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
- { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
- { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
- { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
- { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
- { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
- };
- static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
- sizeof("fsl,secX.Y")];
- int crypto_node, sec_idx, err;
- char *p;
- u32 val;
-
- /* locate crypto node based on lowest common compatible */
- crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
- if (crypto_node == -FDT_ERR_NOTFOUND)
- return;
-
- /* delete it if not on an E-processor */
- if (crypto_node > 0 && !sec_rev) {
- fdt_del_node(blob, crypto_node);
- return;
- }
-
- /* else we got called for possible uprev */
- for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
- if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
- break;
-
- if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
- puts("warning: unknown SEC revision number\n");
- return;
- }
-
- val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
- err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-
- val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
- err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-
- val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
- err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-
- val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
- err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-
- val = 0;
- while (sec_idx >= 0) {
- p = compat_strlist + val;
- val += sprintf(p, "fsl,sec%d.%d",
- (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
- sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
- sec_idx--;
- }
- err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val);
- if (err < 0)
- printf("WARNING: could not set crypto property: %s\n",
- fdt_strerror(err));
-}
-#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
-static u8 caam_get_era(void)
-{
- static const struct {
- u16 ip_id;
- u8 maj_rev;
- u8 era;
- } caam_eras[] = {
- {0x0A10, 1, 1},
- {0x0A10, 2, 2},
- {0x0A12, 1, 3},
- {0x0A14, 1, 3},
- {0x0A14, 2, 4},
- {0x0A16, 1, 4},
- {0x0A10, 3, 4},
- {0x0A11, 1, 4},
- {0x0A18, 1, 4},
- {0x0A11, 2, 5},
- {0x0A12, 2, 5},
- {0x0A13, 1, 5},
- {0x0A1C, 1, 5}
- };
-
- ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
- u32 secvid_ms = sec_in32(&sec->secvid_ms);
- u32 ccbvid = sec_in32(&sec->ccbvid);
- u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
- SEC_SECVID_MS_IPID_SHIFT;
- u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
- SEC_SECVID_MS_MAJ_REV_SHIFT;
- u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT;
-
- int i;
-
- if (era) /* This is '0' prior to CAAM ERA-6 */
- return era;
-
- for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
- if (caam_eras[i].ip_id == ip_id &&
- caam_eras[i].maj_rev == maj_rev)
- return caam_eras[i].era;
-
- return 0;
-}
-
-static void fdt_fixup_crypto_era(void *blob, u32 era)
-{
- int err;
- int crypto_node;
-
- crypto_node = fdt_path_offset(blob, "crypto");
- if (crypto_node < 0) {
- printf("WARNING: Missing crypto node\n");
- return;
- }
-
- err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
- sizeof(era));
- if (err < 0) {
- printf("ERROR: could not set fsl,sec-era property: %s\n",
- fdt_strerror(err));
- }
-}
-
-void fdt_fixup_crypto_node(void *blob, int sec_rev)
-{
- u8 era;
-
- if (!sec_rev) {
- fdt_del_node_and_alias(blob, "crypto");
- return;
- }
-
- /* Add SEC ERA information in compatible */
- era = caam_get_era();
- if (era) {
- fdt_fixup_crypto_era(blob, era);
- } else {
- printf("WARNING: Unable to get ERA for CAAM rev: %d\n",
- sec_rev);
- }
-}
-#endif
-
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
return fdt_setprop_string(blob, offset, "phy-connection-type",
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
index 33dc725..b26ec2a 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c
@@ -63,10 +63,6 @@
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
-#if defined(CONFIG_PMC405)
-ushort pmc405_pci_subsys_deviceid(void);
-#endif
-
/*#define DEBUG*/
/*
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 8f88601..5db5e34 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -13,9 +13,6 @@
config TARGET_CSB472
bool "Support csb472"
-config TARGET_G2000
- bool "Support G2000"
-
config TARGET_JSE
bool "Support JSE"
@@ -104,84 +101,24 @@
config TARGET_V5FX30TEVAL
bool "Support v5fx30teval"
-config TARGET_CATCENTER
- bool "Support CATcenter"
-
-config TARGET_PPCHAMELEONEVB
- bool "Support PPChameleonEVB"
-
-config TARGET_APC405
- bool "Support APC405"
-
-config TARGET_AR405
- bool "Support AR405"
-
-config TARGET_ASH405
- bool "Support ASH405"
-
-config TARGET_CMS700
- bool "Support CMS700"
-
config TARGET_CPCI2DP
bool "Support CPCI2DP"
-config TARGET_CPCI405
- bool "Support CPCI405"
-
config TARGET_CPCI4052
bool "Support CPCI4052"
-config TARGET_CPCI405AB
- bool "Support CPCI405AB"
-
-config TARGET_CPCI405DT
- bool "Support CPCI405DT"
-
-config TARGET_CPCIISER4
- bool "Support CPCIISER4"
-
-config TARGET_DP405
- bool "Support DP405"
-
-config TARGET_DU405
- bool "Support DU405"
-
-config TARGET_DU440
- bool "Support DU440"
-
-config TARGET_HH405
- bool "Support HH405"
-
-config TARGET_HUB405
- bool "Support HUB405"
-
-config TARGET_OCRTC
- bool "Support OCRTC"
-
-config TARGET_PCI405
- bool "Support PCI405"
-
config TARGET_PLU405
bool "Support PLU405"
-config TARGET_PMC405
- bool "Support PMC405"
-
config TARGET_PMC405DE
bool "Support PMC405DE"
config TARGET_PMC440
bool "Support PMC440"
-config TARGET_VOH405
- bool "Support VOH405"
-
config TARGET_VOM405
bool "Support VOM405"
-config TARGET_WUH405
- bool "Support WUH405"
-
config TARGET_DLVISION_10G
bool "Support dlvision-10g"
@@ -256,29 +193,12 @@
source "board/avnet/v5fx30teval/Kconfig"
source "board/csb272/Kconfig"
source "board/csb472/Kconfig"
-source "board/dave/PPChameleonEVB/Kconfig"
-source "board/esd/apc405/Kconfig"
-source "board/esd/ar405/Kconfig"
-source "board/esd/ash405/Kconfig"
-source "board/esd/cms700/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
-source "board/esd/cpciiser4/Kconfig"
-source "board/esd/dp405/Kconfig"
-source "board/esd/du405/Kconfig"
-source "board/esd/du440/Kconfig"
-source "board/esd/hh405/Kconfig"
-source "board/esd/hub405/Kconfig"
-source "board/esd/ocrtc/Kconfig"
-source "board/esd/pci405/Kconfig"
source "board/esd/plu405/Kconfig"
-source "board/esd/pmc405/Kconfig"
source "board/esd/pmc405de/Kconfig"
source "board/esd/pmc440/Kconfig"
-source "board/esd/voh405/Kconfig"
source "board/esd/vom405/Kconfig"
-source "board/esd/wuh405/Kconfig"
-source "board/g2000/Kconfig"
source "board/gdsys/405ep/Kconfig"
source "board/gdsys/405ex/Kconfig"
source "board/gdsys/dlvision/Kconfig"
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
new file mode 100644
index 0000000..8beed30
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+#endif
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 423a6fb..65496d0 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -75,6 +75,7 @@
* SEC (crypto unit) major compatible version determination
*/
#if defined(CONFIG_MPC83xx)
+#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 14c6fc3..b4c0c99 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -12,6 +12,8 @@
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
#elif defined(CONFIG_BSC9132QDS)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
+#elif defined(CONFIG_C29XPCIE)
+#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
#else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 8e0e190..45e248e 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -87,6 +87,13 @@
SGMII_2500_FM2_DTSEC6,
SGMII_2500_FM2_DTSEC9,
SGMII_2500_FM2_DTSEC10,
+ SGMII_SW1_MAC1,
+ SGMII_SW1_MAC2,
+ SGMII_SW1_MAC3,
+ SGMII_SW1_MAC4,
+ SGMII_SW1_MAC5,
+ SGMII_SW1_MAC6,
+ SERDES_PRCTL_COUNT /* Keep this item the last one */
};
enum srds {
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 4430477..c57d9c0 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -100,9 +100,6 @@
#if defined(CONFIG_4xx)
u32 uart_clk;
#endif /* CONFIG_4xx */
-#if defined(CONFIG_SYS_GT_6426x)
- unsigned int mirror_hack[16];
-#endif
#ifdef CONFIG_SYS_FPGA_COUNT
unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
#endif
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index e6d5355..91645d3 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -346,13 +346,6 @@
#ifdef CONFIG_PRAM
ulong reg;
#endif
-#ifdef CONFIG_DEEP_SLEEP
- const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
- u32 start_addr;
- typedef void (*func_t)(void);
- func_t kernel_resume;
-#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -372,20 +365,6 @@
if ((*init_fnc_ptr) () != 0)
hang();
-#ifdef CONFIG_DEEP_SLEEP
- /* Jump to kernel in deep sleep case */
- if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
- l2cache_init();
-#if defined(CONFIG_RAMBOOT_PBL)
- disable_cpc_sram();
-#endif
- enable_cpc();
- start_addr = in_be32(&scfg->sparecr[1]);
- kernel_resume = (func_t)start_addr;
- kernel_resume();
- }
-#endif
-
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index ebf72b3..90e828a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -47,13 +47,10 @@
hex
default 0x100000
-config RAMTOP
- hex
- default 0x200000
-
config XIP_ROM_SIZE
hex
- default 0x10000
+ depends on X86_RESET_VECTOR
+ default ROM_SIZE
config CPU_ADDR_BITS
int
@@ -70,6 +67,15 @@
config SMM_TSEG_SIZE
hex
+config X86_RESET_VECTOR
+ bool
+ default n
+
+config SYS_X86_START16
+ hex
+ depends on X86_RESET_VECTOR
+ default 0xfffff800
+
config BOARD_ROMSIZE_KB_512
bool
config BOARD_ROMSIZE_KB_1024
@@ -85,6 +91,7 @@
choice
prompt "ROM chip size"
+ depends on X86_RESET_VECTOR
default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
@@ -317,6 +324,28 @@
endmenu
+config TSC_CALIBRATION_BYPASS
+ bool "Bypass Time-Stamp Counter (TSC) calibration"
+ default n
+ help
+ By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
+ running frequency via Model-Specific Register (MSR) and Programmable
+ Interval Timer (PIT). If the calibration does not work on your board,
+ select this option and provide a hardcoded TSC running frequency with
+ CONFIG_TSC_FREQ_IN_MHZ below.
+
+ Normally this option should be turned on in a simulation environment
+ like qemu.
+
+config TSC_FREQ_IN_MHZ
+ int "Time-Stamp Counter (TSC) running frequency in MHz"
+ depends on TSC_CALIBRATION_BYPASS
+ default 1000
+ help
+ The running frequency in MHz of Time-Stamp Counter (TSC).
+
+source "arch/x86/cpu/coreboot/Kconfig"
+
source "arch/x86/cpu/ivybridge/Kconfig"
source "arch/x86/cpu/queensbay/Kconfig"
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 5033d2b..62e43c0 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -17,5 +17,6 @@
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-y += lapic.o
+obj-y += mtrr.o
obj-$(CONFIG_PCI) += pci.o
obj-y += turbo.o
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
new file mode 100644
index 0000000..e0e3c64
--- /dev/null
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_COREBOOT
+
+config SYS_COREBOOT
+ bool
+ default y
+
+config CBMEM_CONSOLE
+ bool
+ default y
+
+config VIDEO_COREBOOT
+ bool
+ default y
+
+endif
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index cfacc05..6d06d5a 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -15,6 +15,7 @@
#include <asm/cache.h>
#include <asm/cpu.h>
#include <asm/io.h>
+#include <asm/mtrr.h>
#include <asm/arch/tables.h>
#include <asm/arch/sysinfo.h>
#include <asm/arch/timestamp.h>
@@ -64,11 +65,6 @@
return pci_eth_init(bis);
}
-#define MTRR_TYPE_WP 5
-#define MTRRcap_MSR 0xfe
-#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
-#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-
void board_final_cleanup(void)
{
/* Un-cache the ROM so the kernel has one
@@ -77,15 +73,17 @@
* Coreboot should have assigned this to the
* top available variable MTRR.
*/
- u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
- u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
+ u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
+ u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
/* Make sure this MTRR is the correct Write-Protected type */
- if (top_type == MTRR_TYPE_WP) {
- disable_caches();
- wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
- wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
- enable_caches();
+ if (top_type == MTRR_TYPE_WRPROT) {
+ struct mtrr_state state;
+
+ mtrr_open(&state);
+ wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
+ wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
+ mtrr_close(&state);
}
/* Issue SMI to Coreboot to lock down ME and registers */
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 6a3dd93..c9983f1 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -13,6 +13,8 @@
#include <pci.h>
#include <asm/pci.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
{
@@ -35,7 +37,31 @@
hose->first_busno = 0;
hose->last_busno = 0;
- pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
PCI_REGION_MEM);
- hose->region_count = 1;
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_PREF_BUS,
+ CONFIG_PCI_PREF_PHYS,
+ CONFIG_PCI_PREF_SIZE,
+ PCI_REGION_PREFETCH);
+
+ pci_set_region(hose->regions + 3,
+ 0,
+ 0,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ hose->region_count = 4;
}
diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c
index bd3558a..0edee6b 100644
--- a/arch/x86/cpu/coreboot/timestamp.c
+++ b/arch/x86/cpu/coreboot/timestamp.c
@@ -3,18 +3,7 @@
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -38,9 +27,27 @@
void timestamp_init(void)
{
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+ uint64_t base_time;
+#endif
+
ts_table = lib_sysinfo.tstamp_table;
#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(ts_table->base_time);
+ /*
+ * If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
+ * of base_time in coreboot's timestamp table as our timer base,
+ * otherwise TSC counter value will be used.
+ *
+ * Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
+ * the value of base_time in the timestamp table is still zero, so
+ * we must exclude this case too (this is currently seen on booting
+ * coreboot in qemu)
+ */
+ if (ts_table && ts_table->base_time)
+ base_time = ts_table->base_time;
+ else
+ base_time = rdtsc();
+ timer_set_base(base_time);
#endif
timestamp_add_now(TS_U_BOOT_INITTED);
}
diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S
index dca68e4..9441666 100644
--- a/arch/x86/cpu/ivybridge/car.S
+++ b/arch/x86/cpu/ivybridge/car.S
@@ -12,9 +12,11 @@
*/
#include <common.h>
+#include <asm/msr-index.h>
#include <asm/mtrr.h>
#include <asm/post.h>
#include <asm/processor-flags.h>
+#include <asm/arch/microcode.h>
#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
@@ -45,6 +47,14 @@
movl $0xFEE00300, %esi
movl %eax, (%esi)
+ /* TODO: Load microcode later - the 'no eviction' mode breaks this */
+ movl $MSR_IA32_UCODE_WRITE, %ecx
+ xorl %edx, %edx
+ movl $_dt_ucode_base_size, %eax
+ movl (%eax), %eax
+ addl $UCODE_HEADER_LEN, %eax
+ wrmsr
+
post_code(POST_CAR_SIPI)
/* Zero out all fixed range and variable range MTRRs */
movl $mtrr_table, %esi
@@ -61,7 +71,7 @@
post_code(POST_CAR_MTRR)
/* Configure the default memory type to uncacheable */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(~0x00000cff), %eax
wrmsr
@@ -76,16 +86,16 @@
post_code(POST_CAR_BASE_ADDRESS)
/* Set Cache-as-RAM mask */
movl $(MTRR_PHYS_MASK_MSR(0)), %ecx
- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
post_code(POST_CAR_MASK)
/* Enable MTRR */
- movl $MTRRdefType_MSR, %ecx
+ movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- orl $MTRRdefTypeEn, %eax
+ orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0) */
@@ -130,7 +140,7 @@
movl $MTRR_PHYS_MASK_MSR(1), %ecx
movl $CPU_PHYSMASK_HI, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
post_code(POST_CAR_ROM_CACHE)
@@ -141,7 +151,7 @@
xorl %edx, %edx
wrmsr
movl $MTRR_PHYS_MASK_MSR(2), %ecx
- movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+ movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif
@@ -163,6 +173,52 @@
/* return */
jmp car_init_ret
+.globl car_uninit
+car_uninit:
+ /* Disable cache */
+ movl %cr0, %eax
+ orl $X86_CR0_CD, %eax
+ movl %eax, %cr0
+
+ /* Disable MTRRs */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ andl $(~MTRR_DEF_TYPE_EN), %eax
+ wrmsr
+
+ /* Disable the no-eviction run state */
+ movl NOEVICTMOD_MSR, %ecx
+ rdmsr
+ andl $~2, %eax
+ wrmsr
+
+ invd
+
+ /* Disable the no-eviction mode */
+ rdmsr
+ andl $~1, %eax
+ wrmsr
+
+#ifdef CONFIG_CACHE_MRC_BIN
+ /* Clear the MTRR that was used to cache MRC */
+ xorl %eax, %eax
+ xorl %edx, %edx
+ movl $MTRR_PHYS_BASE_MSR(2), %ecx
+ wrmsr
+ movl $MTRR_PHYS_MASK_MSR(2), %ecx
+ wrmsr
+#endif
+
+ /* Enable MTRRs */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ orl $MTRR_DEF_TYPE_EN, %eax
+ wrmsr
+
+ invd
+
+ ret
+
mtrr_table:
/* Fixed MTRRs */
.word 0x250, 0x258, 0x259
@@ -176,3 +232,9 @@
.word 0x20C, 0x20D, 0x20E, 0x20F
.word 0x210, 0x211, 0x212, 0x213
mtrr_table_end:
+
+ .align 4
+_dt_ucode_base_size:
+ /* These next two fields are filled in by ifdtool */
+ .long 0 /* microcode base */
+ .long 0 /* microcode size */
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 969b07b..e925310 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -49,27 +49,6 @@
pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
}
-static void set_var_mtrr(
- unsigned reg, unsigned base, unsigned size, unsigned type)
-
-{
- /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
- /* FIXME: It only support 4G less range */
- wrmsr(MTRRphysBase_MSR(reg), base | type, 0);
- wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid,
- (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1);
-}
-
-static void enable_rom_caching(void)
-{
- disable_caches();
- set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT);
- enable_caches();
-
- /* Enable Variable MTRRs */
- wrmsr(MTRRdefType_MSR, 0x800, 0);
-}
-
static int set_flex_ratio_to_tdp_nominal(void)
{
msr_t flex_ratio, msr;
@@ -165,10 +144,6 @@
/* This is already done in start.S, but let's do it in C */
enable_port80_on_lpc(hose, PCH_LPC_DEV);
- /* already done in car.S */
- if (false)
- enable_rom_caching();
-
set_spi_speed();
/*
@@ -288,7 +263,7 @@
enable_lapic();
ret = microcode_update_intel();
- if (ret && ret != -ENOENT && ret != -EEXIST)
+ if (ret)
return ret;
/* Enable upper 128bytes of CMOS */
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 3d7f740..6cf9654 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -12,9 +12,11 @@
#include <fdtdec.h>
#include <pci_rom.h>
#include <asm/io.h>
+#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
+#include <linux/kconfig.h>
struct gt_powermeter {
u16 reg;
@@ -730,7 +732,11 @@
int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
const void *blob, int node)
{
+#ifdef CONFIG_VIDEO
+ ulong start;
+#endif
void *gtt_bar;
+ ulong base;
u32 reg32;
int ret;
@@ -739,14 +745,22 @@
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
+ /* Use write-combining for the graphics memory, 256MB */
+ base = pci_read_bar32(hose, dev, 2);
+ mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
+ mtrr_commit(true);
+
gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
debug("GT bar %p\n", gtt_bar);
ret = gma_pm_init_pre_vbios(gtt_bar);
if (ret)
return ret;
+#ifdef CONFIG_VIDEO
+ start = get_timer(0);
ret = pci_run_vga_bios(dev, int15_handler, false);
-
+ debug("BIOS ran in %lums\n", get_timer(start));
+#endif
/* Post VBIOS init */
ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
if (ret)
diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c b/arch/x86/cpu/ivybridge/microcode_intel.c
index 0817751..2440a97 100644
--- a/arch/x86/cpu/ivybridge/microcode_intel.c
+++ b/arch/x86/cpu/ivybridge/microcode_intel.c
@@ -13,7 +13,9 @@
#include <libfdt.h>
#include <asm/cpu.h>
#include <asm/msr.h>
+#include <asm/msr-index.h>
#include <asm/processor.h>
+#include <asm/arch/microcode.h>
/**
* struct microcode_update - standard microcode header from Intel
@@ -40,8 +42,8 @@
update->data = fdt_getprop(blob, node, "data", &update->size);
if (!update->data)
return -EINVAL;
- update->data += 48;
- update->size -= 48;
+ update->data += UCODE_HEADER_LEN;
+ update->size -= UCODE_HEADER_LEN;
update->header_version = fdtdec_get_int(blob, node,
"intel,header-version", 0);
@@ -71,15 +73,16 @@
asm volatile (
"xorl %%eax, %%eax\n"
"xorl %%edx, %%edx\n"
- "movl $0x8b, %%ecx\n"
+ "movl %2, %%ecx\n"
"wrmsr\n"
"movl $0x01, %%eax\n"
"cpuid\n"
- "movl $0x8b, %%ecx\n"
+ "movl %2, %%ecx\n"
"rdmsr\n"
: /* outputs */
"=a" (low), "=d" (high)
: /* inputs */
+ "i" (MSR_IA32_UCODE_REV)
: /* clobbers */
"ebx", "ecx"
);
@@ -94,9 +97,9 @@
struct cpuid_result result;
uint32_t low, high;
- wrmsr(0x8b, 0, 0);
+ wrmsr(MSR_IA32_UCODE_REV, 0, 0);
result = cpuid(1);
- rdmsr(0x8b, low, cpu->update_revision);
+ rdmsr(MSR_IA32_UCODE_REV, low, cpu->update_revision);
x86_model = (result.eax >> 4) & 0x0f;
x86_family = (result.eax >> 8) & 0x0f;
cpu->processor_signature = result.eax;
@@ -120,6 +123,7 @@
int count;
int node;
int ret;
+ int rev;
microcode_read_cpu(&cpu);
node = 0;
@@ -147,12 +151,16 @@
skipped++;
continue;
}
- ret = microcode_read_rev();
- wrmsr(0x79, (ulong)update.data, 0);
+ wrmsr(MSR_IA32_UCODE_WRITE, (ulong)update.data, 0);
+ rev = microcode_read_rev();
debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
- microcode_read_rev(), update.date_code & 0xffff,
+ rev, update.date_code & 0xffff,
(update.date_code >> 24) & 0xff,
(update.date_code >> 16) & 0xff);
+ if (update.update_revision != rev) {
+ printf("Microcode update failed\n");
+ return -EFAULT;
+ }
count++;
} while (1);
}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index b95e781..9504735 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -17,6 +17,7 @@
#include <asm/processor.h>
#include <asm/gpio.h>
#include <asm/global_data.h>
+#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/arch/me.h>
#include <asm/arch/pei_data.h>
@@ -430,6 +431,15 @@
add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
add_memory_area(info, 1ULL << 32, touud);
+
+ /* Add MTRRs for memory */
+ mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
+ mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20);
+ mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20);
+ mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20);
+ mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20),
+ 32 << 20);
+
/*
* If >= 4GB installed then memory from TOLUD to 4GB
* is remapped above TOM, TOUUD will account for both
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
new file mode 100644
index 0000000..d5a825d
--- /dev/null
+++ b/arch/x86/cpu/mtrr.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Memory Type Range Regsters - these are used to tell the CPU whether
+ * memory is cacheable and if so the cache write mode to use.
+ *
+ * These can speed up booting. See the mtrr command.
+ *
+ * Reference: Intel Architecture Software Developer's Manual, Volume 3:
+ * System Programming
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+
+/* Prepare to adjust MTRRs */
+void mtrr_open(struct mtrr_state *state)
+{
+ state->enable_cache = dcache_status();
+
+ if (state->enable_cache)
+ disable_caches();
+ state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
+ wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
+}
+
+/* Clean up after adjusting MTRRs, and enable them */
+void mtrr_close(struct mtrr_state *state)
+{
+ wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
+ if (state->enable_cache)
+ enable_caches();
+}
+
+int mtrr_commit(bool do_caches)
+{
+ struct mtrr_request *req = gd->arch.mtrr_req;
+ struct mtrr_state state;
+ uint64_t mask;
+ int i;
+
+ mtrr_open(&state);
+ for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) {
+ mask = ~(req->size - 1);
+ mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
+ wrmsrl(MTRR_PHYS_BASE_MSR(i), req->start | req->type);
+ wrmsrl(MTRR_PHYS_MASK_MSR(i), mask | MTRR_PHYS_MASK_VALID);
+ }
+
+ /* Clear the ones that are unused */
+ for (; i < MTRR_COUNT; i++)
+ wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
+ mtrr_close(&state);
+
+ return 0;
+}
+
+int mtrr_add_request(int type, uint64_t start, uint64_t size)
+{
+ struct mtrr_request *req;
+ uint64_t mask;
+
+ if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
+ return -ENOSPC;
+ req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
+ req->type = type;
+ req->start = start;
+ req->size = size;
+ debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
+ req->type, req->start, req->size);
+ mask = ~(req->size - 1);
+ mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
+ mask |= MTRR_PHYS_MASK_VALID;
+ debug(" %016llx %016llx\n", req->start | req->type, mask);
+
+ return 0;
+}
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index f3492c3..ab1aaaa 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -15,6 +15,8 @@
#include <pci.h>
#include <asm/pci.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static struct pci_controller x86_hose;
int pci_early_init_hose(struct pci_controller **hosep)
@@ -27,7 +29,8 @@
board_pci_setup_hose(hose);
pci_setup_type1(hose);
- gd->arch.hose = hose;
+ hose->last_busno = pci_hose_scan(hose);
+ gd->hose = hose;
*hosep = hose;
return 0;
@@ -48,7 +51,7 @@
struct pci_controller *hose = &x86_hose;
/* Stop using the early hose */
- gd->arch.hose = NULL;
+ gd->hose = NULL;
board_pci_setup_hose(hose);
pci_setup_type1(hose);
@@ -61,8 +64,8 @@
static struct pci_controller *get_hose(void)
{
- if (gd->arch.hose)
- return gd->arch.hose;
+ if (gd->hose)
+ return gd->hose;
return pci_bus_to_hose(0);
}
diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c
index ef1916b..aed3e2b 100644
--- a/arch/x86/cpu/queensbay/fsp_support.c
+++ b/arch/x86/cpu/queensbay/fsp_support.c
@@ -231,26 +231,28 @@
u32 fsp_get_usable_lowmem_top(const void *hob_list)
{
- union hob_pointers hob;
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
phys_addr_t phys_start;
u32 top;
/* Get the HOB list for processing */
- hob.raw = (void *)hob_list;
+ hdr = hob_list;
/* * Collect memory ranges */
top = FSP_LOWMEM_BASE;
- while (!end_of_hob(hob)) {
- if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
- if (hob.res_desc->type == RES_SYS_MEM) {
- phys_start = hob.res_desc->phys_start;
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type == RES_SYS_MEM) {
+ phys_start = res_desc->phys_start;
/* Need memory above 1MB to be collected here */
if (phys_start >= FSP_LOWMEM_BASE &&
phys_start < (phys_addr_t)FSP_HIGHMEM_BASE)
- top += (u32)(hob.res_desc->len);
+ top += (u32)(res_desc->len);
}
}
- hob.raw = get_next_hob(hob);
+ hdr = get_next_hob(hdr);
}
return top;
@@ -258,25 +260,27 @@
u64 fsp_get_usable_highmem_top(const void *hob_list)
{
- union hob_pointers hob;
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
phys_addr_t phys_start;
u64 top;
/* Get the HOB list for processing */
- hob.raw = (void *)hob_list;
+ hdr = hob_list;
/* Collect memory ranges */
top = FSP_HIGHMEM_BASE;
- while (!end_of_hob(hob)) {
- if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
- if (hob.res_desc->type == RES_SYS_MEM) {
- phys_start = hob.res_desc->phys_start;
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type == RES_SYS_MEM) {
+ phys_start = res_desc->phys_start;
/* Need memory above 1MB to be collected here */
if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE)
- top += (u32)(hob.res_desc->len);
+ top += (u32)(res_desc->len);
}
}
- hob.raw = get_next_hob(hob);
+ hdr = get_next_hob(hdr);
}
return top;
@@ -285,24 +289,26 @@
u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
struct efi_guid *guid)
{
- union hob_pointers hob;
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
/* Get the HOB list for processing */
- hob.raw = (void *)hob_list;
+ hdr = hob_list;
/* Collect memory ranges */
- while (!end_of_hob(hob)) {
- if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
- if (hob.res_desc->type == RES_MEM_RESERVED) {
- if (compare_guid(&hob.res_desc->owner, guid)) {
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type == RES_MEM_RESERVED) {
+ if (compare_guid(&res_desc->owner, guid)) {
if (len)
- *len = (u32)(hob.res_desc->len);
+ *len = (u32)(res_desc->len);
- return (u64)(hob.res_desc->phys_start);
+ return (u64)(res_desc->phys_start);
}
}
}
- hob.raw = get_next_hob(hob);
+ hdr = get_next_hob(hdr);
}
return 0;
@@ -336,44 +342,45 @@
return base;
}
-void *fsp_get_next_hob(u16 type, const void *hob_list)
+const struct hob_header *fsp_get_next_hob(uint type, const void *hob_list)
{
- union hob_pointers hob;
+ const struct hob_header *hdr;
- assert(hob_list != NULL);
-
- hob.raw = (u8 *)hob_list;
+ hdr = hob_list;
/* Parse the HOB list until end of list or matching type is found */
- while (!end_of_hob(hob)) {
- if (get_hob_type(hob) == type)
- return hob.raw;
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == type)
+ return hdr;
- hob.raw = get_next_hob(hob);
+ hdr = get_next_hob(hdr);
}
return NULL;
}
-void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list)
+const struct hob_header *fsp_get_next_guid_hob(const struct efi_guid *guid,
+ const void *hob_list)
{
- union hob_pointers hob;
+ const struct hob_header *hdr;
+ struct hob_guid *guid_hob;
- hob.raw = (u8 *)hob_list;
- while ((hob.raw = fsp_get_next_hob(HOB_TYPE_GUID_EXT,
- hob.raw)) != NULL) {
- if (compare_guid(guid, &hob.guid->name))
+ hdr = hob_list;
+ while ((hdr = fsp_get_next_hob(HOB_TYPE_GUID_EXT,
+ hdr)) != NULL) {
+ guid_hob = (struct hob_guid *)hdr;
+ if (compare_guid(guid, &(guid_hob->name)))
break;
- hob.raw = get_next_hob(hob);
+ hdr = get_next_hob(hdr);
}
- return hob.raw;
+ return hdr;
}
void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
struct efi_guid *guid)
{
- u8 *guid_hob;
+ const struct hob_header *guid_hob;
guid_hob = fsp_get_next_guid_hob(guid, hob_list);
if (guid_hob == NULL) {
diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/cpu/queensbay/tnc_dram.c
index 8e97c9b..df79a39 100644
--- a/arch/x86/cpu/queensbay/tnc_dram.c
+++ b/arch/x86/cpu/queensbay/tnc_dram.c
@@ -14,17 +14,19 @@
int dram_init(void)
{
phys_size_t ram_size = 0;
- union hob_pointers hob;
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
- hob.raw = gd->arch.hob_list;
- while (!end_of_hob(hob)) {
- if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
- if (hob.res_desc->type == RES_SYS_MEM ||
- hob.res_desc->type == RES_MEM_RESERVED) {
- ram_size += hob.res_desc->len;
+ hdr = gd->arch.hob_list;
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type == RES_SYS_MEM ||
+ res_desc->type == RES_MEM_RESERVED) {
+ ram_size += res_desc->len;
}
}
- hob.raw = get_next_hob(hob);
+ hdr = get_next_hob(hdr);
}
gd->ram_size = ram_size;
@@ -55,22 +57,23 @@
unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
{
unsigned num_entries = 0;
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
- union hob_pointers hob;
+ hdr = gd->arch.hob_list;
- hob.raw = gd->arch.hob_list;
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ entries[num_entries].addr = res_desc->phys_start;
+ entries[num_entries].size = res_desc->len;
- while (!end_of_hob(hob)) {
- if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
- entries[num_entries].addr = hob.res_desc->phys_start;
- entries[num_entries].size = hob.res_desc->len;
-
- if (hob.res_desc->type == RES_SYS_MEM)
+ if (res_desc->type == RES_SYS_MEM)
entries[num_entries].type = E820_RAM;
- else if (hob.res_desc->type == RES_MEM_RESERVED)
+ else if (res_desc->type == RES_MEM_RESERVED)
entries[num_entries].type = E820_RESERVED;
}
- hob.raw = get_next_hob(hob);
+ hdr = get_next_hob(hdr);
num_entries++;
}
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 125782c..f51f112 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -205,6 +205,14 @@
/* Setup global descriptor table so gd->xyz works */
call setup_gdt
+ /* Set if we need to disable CAR */
+.weak car_uninit
+ movl $car_uninit, %eax
+ cmpl $0, %eax
+ jz 1f
+
+ call car_uninit
+1:
/* Re-enter U-Boot by calling board_init_f_r */
call board_init_f_r
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 3b5d6da..97ed884 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,6 +1,4 @@
-dtb-y += link.dtb \
- chromebook_link.dtb \
- alex.dtb \
+dtb-y += chromebook_link.dtb \
crownbay.dtb
targets += $(dtb-y)
diff --git a/arch/x86/dts/alex.dts b/arch/x86/dts/alex.dts
deleted file mode 100644
index 2f13544..0000000
--- a/arch/x86/dts/alex.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-/dts-v1/;
-
-/include/ "coreboot.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "Google Alex";
- compatible = "google,alex", "intel,atom-pineview";
-
- config {
- silent_console = <0>;
- };
-
- gpio: gpio {};
-
- serial {
- reg = <0x3f8 8>;
- clock-frequency = <115200>;
- };
-
- chosen { };
- memory { device_type = "memory"; reg = <0 0>; };
-};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
deleted file mode 120000
index 6f8c5cd..0000000
--- a/arch/x86/dts/chromebook_link.dts
+++ /dev/null
@@ -1 +0,0 @@
-link.dts
\ No newline at end of file
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
new file mode 100644
index 0000000..9490b16
--- /dev/null
+++ b/arch/x86/dts/chromebook_link.dts
@@ -0,0 +1,216 @@
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+ model = "Google Link";
+ compatible = "google,link", "intel,celeron-ivybridge";
+
+ config {
+ silent_console = <0>;
+ };
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x10>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x30 0x10>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x10>;
+ bank-name = "C";
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ spd {
+ compatible = "memory-spd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ elpida_4Gb_1600_x16 {
+ reg = <0>;
+ data = [92 10 0b 03 04 19 02 02
+ 03 52 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 81
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 42 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 02 fe 00
+ 11 52 00 00 00 07 7f 37
+ 45 42 4a 32 30 55 47 36
+ 45 42 55 30 2d 47 4e 2d
+ 46 20 30 20 02 fe 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ samsung_4Gb_1600_1.35v_x16 {
+ reg = <1>;
+ data = [92 11 0b 03 04 19 02 02
+ 03 11 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ f0 0a 3c 3c 01 40 83 01
+ 00 80 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 ce 01
+ 00 00 00 00 00 00 6a 04
+ 4d 34 37 31 42 35 36 37
+ 34 42 48 30 2d 59 4b 30
+ 20 20 00 00 80 ce 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ micron_4Gb_1600_1.35v_x16 {
+ reg = <2>;
+ data = [92 11 0b 03 04 19 02 02
+ 03 11 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 05
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 01 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 2c 00
+ 00 00 00 00 00 00 ad 75
+ 34 4b 54 46 32 35 36 36
+ 34 48 5a 2d 31 47 36 45
+ 31 20 45 31 80 2c 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff];
+ };
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich9";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "winbond,w25q64", "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ };
+ };
+
+ pci {
+ sata {
+ compatible = "intel,pantherpoint-ahci";
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+ };
+
+ gma {
+ compatible = "intel,gma";
+ intel,dp_hotplug = <0 0 0x06>;
+ intel,panel-port-select = <1>;
+ intel,panel-power-cycle-delay = <6>;
+ intel,panel-power-up-delay = <2000>;
+ intel,panel-power-down-delay = <500>;
+ intel,panel-power-backlight-on-delay = <2000>;
+ intel,panel-power-backlight-off-delay = <2000>;
+ intel,cpu-backlight = <0x00000200>;
+ intel,pch-backlight = <0x04000000>;
+ };
+
+ lpc {
+ compatible = "intel,lpc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+ intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+ 0x80 0x80 0x80 0x80>;
+ intel,gpi-routing = <0 0 0 0 0 0 0 2
+ 1 0 0 0 0 0 0 0>;
+ /* Enable EC SMI source */
+ intel,alt-gp-smi-enable = <0x0100>;
+
+ cros-ec@200 {
+ compatible = "google,cros-ec";
+ reg = <0x204 1 0x200 1 0x880 0x80>;
+
+ /* Describes the flash memory within the EC */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ flash@8000000 {
+ reg = <0x08000000 0x20000>;
+ erase-value = <0xff>;
+ };
+ };
+ };
+ };
+
+ microcode {
+ update@0 {
+#include "microcode/m12306a9_0000001b.dtsi"
+ };
+ };
+
+};
diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi
deleted file mode 100644
index 65a93ac..0000000
--- a/arch/x86/dts/coreboot.dtsi
+++ /dev/null
@@ -1,17 +0,0 @@
-/include/ "skeleton.dtsi"
-
-/ {
- chosen {
- stdout-path = "/serial";
- };
-
- serial {
- compatible = "x86-uart";
- reg = <0x3f8 0x10>;
- reg-shift = <0>;
- io-mapped = <1>;
- multiplier = <1>;
- baudrate = <115200>;
- status = "disabled";
- };
-};
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 3f43f3c..e81054e 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -6,11 +6,10 @@
/dts-v1/;
-/include/ "coreboot.dtsi"
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
/ {
- #address-cells = <1>;
- #size-cells = <1>;
model = "Intel Crown Bay";
compatible = "intel,crownbay", "intel,queensbay";
@@ -32,14 +31,18 @@
bank-name = "B";
};
- serial {
- reg = <0x3f8 8>;
- clock-frequency = <115200>;
+ chosen {
+ /*
+ * By default the legacy superio serial port is used as the
+ * U-Boot serial console. If we want to use UART from Topcliff
+ * PCH as the console, change this property to &pciuart#.
+ *
+ * For example, stdout-path = &pciuart0 will use the first
+ * UART on Topcliff PCH.
+ */
+ stdout-path = "/serial";
};
- chosen { };
- memory { device_type = "memory"; reg = <0 0>; };
-
spi {
#address-cells = <1>;
#size-cells = <0>;
@@ -57,4 +60,77 @@
};
};
+ pci {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "intel,pci";
+ device_type = "pci";
+
+ pcie@17,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "intel,pci";
+ device_type = "pci";
+
+ topcliff@0,0 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "intel,pci";
+ device_type = "pci";
+
+ pciuart0: uart@a,1 {
+ compatible = "pci8086,8811.00",
+ "pci8086,8811",
+ "pciclass,070002",
+ "pciclass,0700",
+ "x86-uart";
+ reg = <0x00025100 0x0 0x0 0x0 0x0
+ 0x01025110 0x0 0x0 0x0 0x0>;
+ reg-shift = <0>;
+ clock-frequency = <1843200>;
+ current-speed = <115200>;
+ };
+
+ pciuart1: uart@a,2 {
+ compatible = "pci8086,8812.00",
+ "pci8086,8812",
+ "pciclass,070002",
+ "pciclass,0700",
+ "x86-uart";
+ reg = <0x00025200 0x0 0x0 0x0 0x0
+ 0x01025210 0x0 0x0 0x0 0x0>;
+ reg-shift = <0>;
+ clock-frequency = <1843200>;
+ current-speed = <115200>;
+ };
+
+ pciuart2: uart@a,3 {
+ compatible = "pci8086,8813.00",
+ "pci8086,8813",
+ "pciclass,070002",
+ "pciclass,0700",
+ "x86-uart";
+ reg = <0x00025300 0x0 0x0 0x0 0x0
+ 0x01025310 0x0 0x0 0x0 0x0>;
+ reg-shift = <0>;
+ clock-frequency = <1843200>;
+ current-speed = <115200>;
+ };
+
+ pciuart3: uart@a,4 {
+ compatible = "pci8086,8814.00",
+ "pci8086,8814",
+ "pciclass,070002",
+ "pciclass,0700",
+ "x86-uart";
+ reg = <0x00025400 0x0 0x0 0x0 0x0
+ 0x01025410 0x0 0x0 0x0 0x0>;
+ reg-shift = <0>;
+ clock-frequency = <1843200>;
+ current-speed = <115200>;
+ };
+ };
+ };
+ };
+
};
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
deleted file mode 100644
index a739080..0000000
--- a/arch/x86/dts/link.dts
+++ /dev/null
@@ -1,224 +0,0 @@
-/dts-v1/;
-
-/include/ "coreboot.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "Google Link";
- compatible = "google,link", "intel,celeron-ivybridge";
-
- config {
- silent_console = <0>;
- };
-
- gpioa {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0 0x10>;
- bank-name = "A";
- };
-
- gpiob {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x30 0x10>;
- bank-name = "B";
- };
-
- gpioc {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x40 0x10>;
- bank-name = "C";
- };
-
- serial {
- reg = <0x3f8 8>;
- clock-frequency = <115200>;
- };
-
- chosen { };
- memory { device_type = "memory"; reg = <0 0>; };
-
- spd {
- compatible = "memory-spd";
- #address-cells = <1>;
- #size-cells = <0>;
- elpida_4Gb_1600_x16 {
- reg = <0>;
- data = [92 10 0b 03 04 19 02 02
- 03 52 01 08 0a 00 fe 00
- 69 78 69 3c 69 11 18 81
- 20 08 3c 3c 01 40 83 81
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 0f 11 42 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 02 fe 00
- 11 52 00 00 00 07 7f 37
- 45 42 4a 32 30 55 47 36
- 45 42 55 30 2d 47 4e 2d
- 46 20 30 20 02 fe 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00];
- };
- samsung_4Gb_1600_1.35v_x16 {
- reg = <1>;
- data = [92 11 0b 03 04 19 02 02
- 03 11 01 08 0a 00 fe 00
- 69 78 69 3c 69 11 18 81
- f0 0a 3c 3c 01 40 83 01
- 00 80 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 0f 11 02 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 80 ce 01
- 00 00 00 00 00 00 6a 04
- 4d 34 37 31 42 35 36 37
- 34 42 48 30 2d 59 4b 30
- 20 20 00 00 80 ce 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00];
- };
- micron_4Gb_1600_1.35v_x16 {
- reg = <2>;
- data = [92 11 0b 03 04 19 02 02
- 03 11 01 08 0a 00 fe 00
- 69 78 69 3c 69 11 18 81
- 20 08 3c 3c 01 40 83 05
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 0f 01 02 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 80 2c 00
- 00 00 00 00 00 00 ad 75
- 34 4b 54 46 32 35 36 36
- 34 48 5a 2d 31 47 36 45
- 31 20 45 31 80 2c 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- 00 00 00 00 00 00 00 00
- ff ff ff ff ff ff ff ff
- ff ff ff ff ff ff ff ff
- ff ff ff ff ff ff ff ff
- ff ff ff ff ff ff ff ff
- ff ff ff ff ff ff ff ff
- ff ff ff ff ff ff ff ff
- ff ff ff ff ff ff ff ff
- ff ff ff ff ff ff ff ff
- ff ff ff ff ff ff ff ff
- ff ff ff ff ff ff ff ff];
- };
- };
-
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich9";
- spi-flash@0 {
- reg = <0>;
- compatible = "winbond,w25q64", "spi-flash";
- memory-map = <0xff800000 0x00800000>;
- };
- };
-
- pci {
- sata {
- compatible = "intel,pantherpoint-ahci";
- intel,sata-mode = "ahci";
- intel,sata-port-map = <1>;
- intel,sata-port0-gen3-tx = <0x00880a7f>;
- };
-
- gma {
- compatible = "intel,gma";
- intel,dp_hotplug = <0 0 0x06>;
- intel,panel-port-select = <1>;
- intel,panel-power-cycle-delay = <6>;
- intel,panel-power-up-delay = <2000>;
- intel,panel-power-down-delay = <500>;
- intel,panel-power-backlight-on-delay = <2000>;
- intel,panel-power-backlight-off-delay = <2000>;
- intel,cpu-backlight = <0x00000200>;
- intel,pch-backlight = <0x04000000>;
- };
-
- lpc {
- compatible = "intel,lpc";
- #address-cells = <1>;
- #size-cells = <1>;
- gen-dec = <0x800 0xfc 0x900 0xfc>;
- intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
- intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
- 0x80 0x80 0x80 0x80>;
- intel,gpi-routing = <0 0 0 0 0 0 0 2
- 1 0 0 0 0 0 0 0>;
- /* Enable EC SMI source */
- intel,alt-gp-smi-enable = <0x0100>;
-
- cros-ec@200 {
- compatible = "google,cros-ec";
- reg = <0x204 1 0x200 1 0x880 0x80>;
-
- /* Describes the flash memory within the EC */
- #address-cells = <1>;
- #size-cells = <1>;
- flash@8000000 {
- reg = <0x08000000 0x20000>;
- erase-value = <0xff>;
- };
- };
- };
- };
-
- microcode {
- update@0 {
-#include "microcode/m12206a7_00000029.dtsi"
- };
- update@1 {
-#include "microcode/m12306a9_0000001b.dtsi"
- };
- };
-
-};
diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
new file mode 100644
index 0000000..9b097f4
--- /dev/null
+++ b/arch/x86/dts/serial.dtsi
@@ -0,0 +1,9 @@
+/ {
+ serial {
+ compatible = "x86-uart";
+ reg = <0x3f8 8>;
+ reg-shift = <0>;
+ clock-frequency = <1843200>;
+ current-speed = <115200>;
+ };
+};
diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/arch-ivybridge/microcode.h
index bc9b87c..b868283 100644
--- a/arch/x86/include/asm/arch-ivybridge/microcode.h
+++ b/arch/x86/include/asm/arch-ivybridge/microcode.h
@@ -7,6 +7,11 @@
#ifndef __ASM_ARCH_MICROCODE_H
#define __ASM_ARCH_MICROCODE_H
+/* Length of the public header on Intel microcode blobs */
+#define UCODE_HEADER_LEN 0x30
+
+#ifndef __ASSEMBLY__
+
/**
* microcode_update_intel() - Apply microcode updates
*
@@ -16,5 +21,6 @@
* not updates were found, -EINVAL if an update was invalid
*/
int microcode_update_intel(void);
+#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
index 380b64e..6cca7f5 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
@@ -182,58 +182,19 @@
/* GUID specific data goes here */
};
-/* Union of all the possible HOB Types */
-union hob_pointers {
- struct hob_header *hdr;
- struct hob_mem_alloc *mem_alloc;
- struct hob_res_desc *res_desc;
- struct hob_guid *guid;
- u8 *raw;
-};
-
-/**
- * get_hob_type() - return the type of a HOB
- *
- * This macro returns the type field from the HOB header for the
- * HOB specified by hob.
- *
- * @hob: A pointer to a HOB.
- *
- * @return: HOB type.
- */
-static inline u16 get_hob_type(union hob_pointers hob)
-{
- return hob.hdr->type;
-}
-
-/**
- * get_hob_length() - return the length, in bytes, of a HOB
- *
- * This macro returns the len field from the HOB header for the
- * HOB specified by hob.
- *
- * @hob: A pointer to a HOB.
- *
- * @return: HOB length.
- */
-static inline u16 get_hob_length(union hob_pointers hob)
-{
- return hob.hdr->len;
-}
-
/**
* get_next_hob() - return a pointer to the next HOB in the HOB list
*
* This macro returns a pointer to HOB that follows the HOB specified by hob
* in the HOB List.
*
- * @hob: A pointer to a HOB.
+ * @hdr: A pointer to a HOB.
*
* @return: A pointer to the next HOB in the HOB list.
*/
-static inline void *get_next_hob(union hob_pointers hob)
+static inline const struct hob_header *get_next_hob(const struct hob_header *hdr)
{
- return (void *)(*(u8 **)&(hob) + get_hob_length(hob));
+ return (const struct hob_header *)((u32)hdr + hdr->len);
}
/**
@@ -243,14 +204,14 @@
* HOB list. If hob is last HOB in the HOB list, then true is returned.
* Otherwise, false is returned.
*
- * @hob: A pointer to a HOB.
+ * @hdr: A pointer to a HOB.
*
- * @retval true: The HOB specified by hob is the last HOB in the HOB list.
- * @retval false: The HOB specified by hob is not the last HOB in the HOB list.
+ * @retval true: The HOB specified by hdr is the last HOB in the HOB list.
+ * @retval false: The HOB specified by hdr is not the last HOB in the HOB list.
*/
-static inline bool end_of_hob(union hob_pointers hob)
+static inline bool end_of_hob(const struct hob_header *hdr)
{
- return get_hob_type(hob) == HOB_TYPE_EOH;
+ return hdr->type == HOB_TYPE_EOH;
}
/**
@@ -260,13 +221,13 @@
* This macro returns a pointer to the data buffer in a HOB specified by hob.
* hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
*
- * @hob: A pointer to a HOB.
+ * @hdr: A pointer to a HOB.
*
* @return: A pointer to the data buffer in a HOB.
*/
-static inline void *get_guid_hob_data(u8 *hob)
+static inline void *get_guid_hob_data(const struct hob_header *hdr)
{
- return (void *)(hob + sizeof(struct hob_guid));
+ return (void *)((u32)hdr + sizeof(struct hob_guid));
}
/**
@@ -276,14 +237,13 @@
* This macro returns the size, in bytes, of the data buffer in a HOB
* specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
*
- * @hob: A pointer to a HOB.
+ * @hdr: A pointer to a HOB.
*
* @return: The size of the data buffer.
*/
-static inline u16 get_guid_hob_data_size(u8 *hob)
+static inline u16 get_guid_hob_data_size(const struct hob_header *hdr)
{
- union hob_pointers hob_p = *(union hob_pointers *)hob;
- return get_hob_length(hob_p) - sizeof(struct hob_guid);
+ return hdr->len - sizeof(struct hob_guid);
}
/* FSP specific GUID HOB definitions */
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
index 3ae1b66..ebdbd03 100644
--- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
@@ -145,7 +145,7 @@
*
* @retval: A HOB object with matching type; Otherwise NULL.
*/
-void *fsp_get_next_hob(u16 type, const void *hob_list);
+const struct hob_header *fsp_get_next_hob(uint type, const void *hob_list);
/**
* Returns the next instance of the matched GUID HOB from the starting HOB.
@@ -155,7 +155,8 @@
*
* @retval: A HOB object with matching GUID; Otherwise NULL.
*/
-void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list);
+const struct hob_header *fsp_get_next_guid_hob(const struct efi_guid *guid,
+ const void *hob_list);
/**
* This function retrieves a GUID HOB data buffer and size.
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 03d491a..24e3052 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -29,6 +29,19 @@
struct memory_area area[CONFIG_NR_DRAM_BANKS];
};
+#define MAX_MTRR_REQUESTS 8
+
+/**
+ * A request for a memory region to be set up in a particular way. These
+ * requests are processed before board_init_r() is called. They are generally
+ * optional and can be ignored with some performance impact.
+ */
+struct mtrr_request {
+ int type; /* MTRR_TYPE_... */
+ uint64_t start;
+ uint64_t size;
+};
+
/* Architecture-specific global data */
struct arch_global_data {
struct global_data *gd_addr; /* Location of Global Data */
@@ -43,13 +56,14 @@
uint32_t tsc_mhz; /* TSC frequency in MHz */
void *new_fdt; /* Relocated FDT */
uint32_t bist; /* Built-in self test value */
- struct pci_controller *hose; /* PCI hose for early use */
enum pei_boot_mode_t pei_boot_mode;
const struct pch_gpio_map *gpio_map; /* board GPIO map */
struct memory_info meminfo; /* Memory information */
#ifdef CONFIG_HAVE_FSP
void *hob_list; /* FSP HOB list */
#endif
+ struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
+ int mtrr_req_count;
};
#endif
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 5f05a48..3c11740 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -9,99 +9,86 @@
#ifndef _ASM_MTRR_H
#define _ASM_MTRR_H
-/* These are the region types */
-#define MTRR_TYPE_UNCACHEABLE 0
-#define MTRR_TYPE_WRCOMB 1
-/*#define MTRR_TYPE_ 2*/
-/*#define MTRR_TYPE_ 3*/
-#define MTRR_TYPE_WRTHROUGH 4
-#define MTRR_TYPE_WRPROT 5
-#define MTRR_TYPE_WRBACK 6
-#define MTRR_NUM_TYPES 7
+/* MTRR region types */
+#define MTRR_TYPE_UNCACHEABLE 0
+#define MTRR_TYPE_WRCOMB 1
+#define MTRR_TYPE_WRTHROUGH 4
+#define MTRR_TYPE_WRPROT 5
+#define MTRR_TYPE_WRBACK 6
-#define MTRRcap_MSR 0x0fe
-#define MTRRdefType_MSR 0x2ff
+#define MTRR_TYPE_COUNT 7
-#define MTRRdefTypeEn (1 << 11)
-#define MTRRdefTypeFixEn (1 << 10)
+#define MTRR_CAP_MSR 0x0fe
+#define MTRR_DEF_TYPE_MSR 0x2ff
-#define SMRRphysBase_MSR 0x1f2
-#define SMRRphysMask_MSR 0x1f3
+#define MTRR_DEF_TYPE_EN (1 << 11)
+#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
-#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
-#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
+#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
-#define MTRRphysMaskValid (1 << 11)
+#define MTRR_PHYS_MASK_VALID (1 << 11)
-#define NUM_FIXED_RANGES 88
-#define RANGES_PER_FIXED_MTRR 8
-#define MTRRfix64K_00000_MSR 0x250
-#define MTRRfix16K_80000_MSR 0x258
-#define MTRRfix16K_A0000_MSR 0x259
-#define MTRRfix4K_C0000_MSR 0x268
-#define MTRRfix4K_C8000_MSR 0x269
-#define MTRRfix4K_D0000_MSR 0x26a
-#define MTRRfix4K_D8000_MSR 0x26b
-#define MTRRfix4K_E0000_MSR 0x26c
-#define MTRRfix4K_E8000_MSR 0x26d
-#define MTRRfix4K_F0000_MSR 0x26e
-#define MTRRfix4K_F8000_MSR 0x26f
+#define MTRR_BASE_TYPE_MASK 0x7
+
+/* Number of MTRRs supported */
+#define MTRR_COUNT 8
#if !defined(__ASSEMBLER__)
-/*
- * The MTRR code has some side effects that the callers should be aware for.
- * 1. The call sequence matters. x86_setup_mtrrs() calls
- * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent
- * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers
- * want to call the components of x86_setup_mtrrs() because of other
- * rquirements the ordering should still preserved.
- * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because
- * of the nature of the global MTRR enable flag. Therefore, all direct
- * or indirect callers of enable_fixed_mtrr() should ensure that the
- * variable MTRR MSRs do not contain bad ranges.
- * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling
- * the caching of the ROM. However, it is set to uncacheable (UC). It
- * is the responsiblity of the caller to enable it by calling
- * x86_mtrr_enable_rom_caching().
+/**
+ * Information about the previous MTRR state, set up by mtrr_open()
+ *
+ * @deftype: Previous value of MTRR_DEF_TYPE_MSR
+ * @enable_cache: true if cache was enabled
*/
-void x86_setup_mtrrs(void);
-/*
- * x86_setup_var_mtrrs() parameters:
- * address_bits - number of physical address bits supported by cpu
- * above4gb - 2 means dynamically detect number of variable MTRRs available.
- * non-zero means handle memory ranges above 4GiB.
- * 0 means ignore memory ranges above 4GiB
+struct mtrr_state {
+ uint64_t deftype;
+ bool enable_cache;
+};
+
+/**
+ * mtrr_open() - Prepare to adjust MTRRs
+ *
+ * Use mtrr_open() passing in a structure - this function will init it. Then
+ * when done, pass the same structure to mtrr_close() to re-enable MTRRs and
+ * possibly the cache.
+ *
+ * @state: Empty structure to pass in to hold settings
*/
-void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
-void enable_fixed_mtrr(void);
-void x86_setup_fixed_mtrrs(void);
-/* Set up fixed MTRRs but do not enable them. */
-void x86_setup_fixed_mtrrs_no_enable(void);
-int x86_mtrr_check(void);
-/* ROM caching can be used after variable MTRRs are set up. Beware that
- * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on
- * one's IO hole size and WRCOMB resources. Be sure to check the console
- * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that
- * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the
- * rom caching will be disabled if all threads run the MTRR code. Therefore,
- * one needs to call x86_mtrr_enable_rom_caching() after all threads of the
- * same core have run the MTRR code. */
-#if CONFIG_CACHE_ROM
-void x86_mtrr_enable_rom_caching(void);
-void x86_mtrr_disable_rom_caching(void);
-/* Return the variable range MTRR index of the ROM cache. */
-long x86_mtrr_rom_cache_var_index(void);
-#else
-static inline void x86_mtrr_enable_rom_caching(void) {}
-static inline void x86_mtrr_disable_rom_caching(void) {}
-static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
-#endif /* CONFIG_CACHE_ROM */
+void mtrr_open(struct mtrr_state *state);
-#endif
+/**
+ * mtrr_open() - Clean up after adjusting MTRRs, and enable them
+ *
+ * This uses the structure containing information returned from mtrr_open().
+ *
+ * @state: Structure from mtrr_open()
+ */
+/* */
+void mtrr_close(struct mtrr_state *state);
-#if !defined(CONFIG_RAMTOP)
-# error "CONFIG_RAMTOP not defined"
+/**
+ * mtrr_add_request() - Add a new MTRR request
+ *
+ * This adds a request for a memory region to be set up in a particular way.
+ *
+ * @type: Requested type (MTRR_TYPE_)
+ * @start: Start address
+ * @size: Size
+ */
+int mtrr_add_request(int type, uint64_t start, uint64_t size);
+
+/**
+ * mtrr_commit() - set up the MTRR registers based on current requests
+ *
+ * This sets up MTRRs for the available DRAM and the requests received so far.
+ * It must be called with caches disabled.
+ *
+ * @do_caches: true if caches are currently on
+ */
+int mtrr_commit(bool do_caches);
+
#endif
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
@@ -114,8 +101,4 @@
#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
-#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
-# error "CONFIG_RAMTOP must be a power of 2"
-#endif
-
#endif
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index ac1a808..c30dd4c 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -29,7 +29,7 @@
* pci_early_init_hose() - Set up PCI host before relocation
*
* This allocates memory for, sets up and returns the PCI hose. It can be
- * called before relocation. The hose will be stored in gd->arch.hose for
+ * called before relocation. The hose will be stored in gd->hose for
* later use, but will become invalid one DRAM is available.
*/
int pci_early_init_hose(struct pci_controller **hosep);
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 73262d7..32d7b98 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -14,6 +14,7 @@
obj-y += gcc.o
obj-y += init_helpers.o
obj-y += interrupts.o
+obj-y += cmd_mtrr.o
obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
obj-$(CONFIG_PCI) += pci_type1.o
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index d1f8933..1d75cfc 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -207,12 +207,14 @@
static u8 vbe_set_mode(struct vbe_mode_info *mi)
{
- debug("VBE: Setting VESA mode %#04x\n", mi->video_mode);
+ int video_mode = mi->video_mode;
+
+ debug("VBE: Setting VESA mode %#04x\n", video_mode);
/* request linear framebuffer mode */
- mi->video_mode |= (1 << 14);
- /* request clearing of framebuffer */
- mi->video_mode &= ~(1 << 15);
- realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode,
+ video_mode |= (1 << 14);
+ /* don't clear the framebuffer, we do that later */
+ video_mode |= (1 << 15);
+ realmode_interrupt(0x10, VESA_SET_MODE, video_mode,
0x0000, 0x0000, 0x0000, 0x0000);
return 0;
@@ -236,6 +238,7 @@
return;
}
+ mode_info->video_mode &= 0x3ff;
vbe_set_mode(mode_info);
}
@@ -262,7 +265,6 @@
/* Make sure the code is placed. */
setup_realmode_code();
- disable_caches();
debug("Calling Option ROM at %lx, pci device %#x...", addr, num_dev);
/* Option ROM entry point is at OPROM start + 3 */
diff --git a/arch/x86/lib/cmd_hob.c b/arch/x86/lib/cmd_hob.c
index b552fe6..a0ef037 100644
--- a/arch/x86/lib/cmd_hob.c
+++ b/arch/x86/lib/cmd_hob.c
@@ -28,20 +28,20 @@
int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- union hob_pointers hob;
- u16 type;
+ const struct hob_header *hdr;
+ uint type;
char *desc;
int i = 0;
- hob.raw = (u8 *)gd->arch.hob_list;
+ hdr = gd->arch.hob_list;
- printf("HOB list address: 0x%08x\n\n", (unsigned int)hob.raw);
+ printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr);
printf("No. | Address | Type | Length in Bytes\n");
printf("----|----------|---------------------|----------------\n");
- while (!end_of_hob(hob)) {
- printf("%-3d | %08x | ", i, (unsigned int)hob.raw);
- type = get_hob_type(hob);
+ while (!end_of_hob(hdr)) {
+ printf("%-3d | %08x | ", i, (unsigned int)hdr);
+ type = hdr->type;
if (type == HOB_TYPE_UNUSED)
desc = "*Unused*";
else if (type == HOB_TYPE_EOH)
@@ -50,8 +50,8 @@
desc = hob_type[type];
else
desc = "*Invalid Type*";
- printf("%-19s | %-15d\n", desc, get_hob_length(hob));
- hob.raw = get_next_hob(hob);
+ printf("%-19s | %-15d\n", desc, hdr->len);
+ hdr = get_next_hob(hdr);
i++;
}
diff --git a/arch/x86/lib/cmd_mtrr.c b/arch/x86/lib/cmd_mtrr.c
new file mode 100644
index 0000000..7e0506b
--- /dev/null
+++ b/arch/x86/lib/cmd_mtrr.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+
+static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
+ "Uncacheable",
+ "Combine",
+ "2",
+ "3",
+ "Through",
+ "Protect",
+ "Back",
+};
+
+static int do_mtrr_list(void)
+{
+ int i;
+
+ printf("Reg Valid Write-type %-16s %-16s %-16s\n", "Base ||",
+ "Mask ||", "Size ||");
+ for (i = 0; i < MTRR_COUNT; i++) {
+ const char *type = "Invalid";
+ uint64_t base, mask, size;
+ bool valid;
+
+ base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
+ mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
+ size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
+ size |= (1 << 12) - 1;
+ size += 1;
+ valid = mask & MTRR_PHYS_MASK_VALID;
+ type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
+ printf("%d %-5s %-12s %016llx %016llx %016llx\n", i,
+ valid ? "Y" : "N", type, base, mask, size);
+ }
+
+ return 0;
+}
+
+static int do_mtrr_set(uint reg, int argc, char * const argv[])
+{
+ const char *typename = argv[0];
+ struct mtrr_state state;
+ uint32_t start, size;
+ uint64_t base, mask;
+ int i, type = -1;
+ bool valid;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ for (i = 0; i < MTRR_TYPE_COUNT; i++) {
+ if (*typename == *mtrr_type_name[i])
+ type = i;
+ }
+ if (type == -1) {
+ printf("Invalid type name %s\n", typename);
+ return CMD_RET_USAGE;
+ }
+ start = simple_strtoul(argv[1], NULL, 16);
+ size = simple_strtoul(argv[2], NULL, 16);
+
+ base = start | type;
+ valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID;
+ mask = ~((uint64_t)size - 1);
+ mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
+ if (valid)
+ mask |= MTRR_PHYS_MASK_VALID;
+
+ printf("base=%llx, mask=%llx\n", base, mask);
+ mtrr_open(&state);
+ wrmsrl(MTRR_PHYS_BASE_MSR(reg), base);
+ wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
+ mtrr_close(&state);
+
+ return 0;
+}
+
+static int mtrr_set_valid(int reg, bool valid)
+{
+ struct mtrr_state state;
+ uint64_t mask;
+
+ mtrr_open(&state);
+ mask = native_read_msr(MTRR_PHYS_MASK_MSR(reg));
+ if (valid)
+ mask |= MTRR_PHYS_MASK_VALID;
+ else
+ mask &= ~MTRR_PHYS_MASK_VALID;
+ wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);
+ mtrr_close(&state);
+
+ return 0;
+}
+
+static int do_mtrr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *cmd;
+ uint reg;
+
+ cmd = argv[1];
+ if (argc < 2 || *cmd == 'l')
+ return do_mtrr_list();
+ argc -= 2;
+ argv += 2;
+ if (argc <= 0)
+ return CMD_RET_USAGE;
+ reg = simple_strtoul(argv[0], NULL, 16);
+ if (reg >= MTRR_COUNT) {
+ printf("Invalid register number\n");
+ return CMD_RET_USAGE;
+ }
+ if (*cmd == 'e')
+ return mtrr_set_valid(reg, true);
+ else if (*cmd == 'd')
+ return mtrr_set_valid(reg, false);
+ else if (*cmd == 's')
+ return do_mtrr_set(reg, argc - 1, argv + 1);
+ else
+ return CMD_RET_USAGE;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ mtrr, 6, 1, do_mtrr,
+ "Use x86 memory type range registers (32-bit only)",
+ "[list] - list current registers\n"
+ "set <reg> <type> <start> <size> - set a register\n"
+ "\t<type> is Uncacheable, Combine, Through, Protect, Back\n"
+ "disable <reg> - disable a register\n"
+ "ensable <reg> - enable a register"
+);
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index be4eb12..fc211d9 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fdtdec.h>
#include <spi.h>
+#include <asm/mtrr.h>
#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -66,6 +67,13 @@
int init_cache_f_r(void)
{
+#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP)
+ int ret;
+
+ ret = mtrr_commit(false);
+ if (ret)
+ return ret;
+#endif
/* Initialise the CPU cache(s) */
return init_cache();
}
diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index fb9afed..7f5ba2c 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -78,7 +78,7 @@
*
* Returns the calibration value or 0 if MSR calibration failed.
*/
-static unsigned long try_msr_calibrate_tsc(void)
+static unsigned long __maybe_unused try_msr_calibrate_tsc(void)
{
u32 lo, hi, ratio, freq_id, freq;
unsigned long res;
@@ -199,7 +199,7 @@
#define MAX_QUICK_PIT_MS 50
#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
-static unsigned long quick_pit_calibrate(void)
+static unsigned long __maybe_unused quick_pit_calibrate(void)
{
int i;
u64 tsc, delta;
@@ -306,6 +306,9 @@
if (gd->arch.tsc_mhz)
return gd->arch.tsc_mhz;
+#ifdef CONFIG_TSC_CALIBRATION_BYPASS
+ fast_calibrate = CONFIG_TSC_FREQ_IN_MHZ;
+#else
fast_calibrate = try_msr_calibrate_tsc();
if (!fast_calibrate) {
@@ -313,6 +316,7 @@
if (!fast_calibrate)
panic("TSC frequency is ZERO");
}
+#endif
gd->arch.tsc_mhz = fast_calibrate;
return fast_calibrate;
diff --git a/board/Seagate/nas220/Kconfig b/board/Seagate/nas220/Kconfig
new file mode 100644
index 0000000..0fa529c
--- /dev/null
+++ b/board/Seagate/nas220/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NAS220
+
+config SYS_BOARD
+ default "nas220"
+
+config SYS_VENDOR
+ default "Seagate"
+
+config SYS_CONFIG_NAME
+ default "nas220"
+
+endif
diff --git a/board/Seagate/nas220/MAINTAINERS b/board/Seagate/nas220/MAINTAINERS
new file mode 100644
index 0000000..f2df7ea
--- /dev/null
+++ b/board/Seagate/nas220/MAINTAINERS
@@ -0,0 +1,6 @@
+NAS220 BOARD
+M: Evgeni Dobrev <evgeni@studio-punkt.com>
+S: Maintained
+F: board/Seagate/nas220/
+F: include/configs/nas220.h
+F: configs/nas220_defconfig
diff --git a/board/Seagate/nas220/Makefile b/board/Seagate/nas220/Makefile
new file mode 100644
index 0000000..9de73e6
--- /dev/null
+++ b/board/Seagate/nas220/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nas220.o
diff --git a/board/Seagate/nas220/kwbimage.cfg b/board/Seagate/nas220/kwbimage.cfg
new file mode 100644
index 0000000..dbbfb9c
--- /dev/null
+++ b/board/Seagate/nas220/kwbimage.cfg
@@ -0,0 +1,151 @@
+#
+# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0200
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000819 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+
+DATA 0xFFD01410 0x0000000d # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000632 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 0
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+DATA 0xffd01620 0x00465000
+
+# End of Header extension
+DATA 0x0 0x0
+
diff --git a/board/Seagate/nas220/nas220.c b/board/Seagate/nas220/nas220.c
new file mode 100644
index 0000000..d9a0627
--- /dev/null
+++ b/board/Seagate/nas220/nas220.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ */
+ mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
+ NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_SPI_SCn,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_SATA0_ACTn,
+ MPP16_SATA1_ACTn,
+ MPP17_SATA0_PRESENTn,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_NAS220;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+ printf("Err..%s could not read PHY dev address\n", __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
index 6fe937b..5b4b76f 100644
--- a/board/compulab/cm_fx6/spl.c
+++ b/board/compulab/cm_fx6/spl.c
@@ -313,7 +313,6 @@
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- gd = &gdata;
/*
* We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
* initializes DMA very early (before all board code), so the only
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index 6ca6ced..981de1f 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -9,7 +9,32 @@
config SYS_SOC
default "coreboot"
+comment "coreboot-specific options"
+
config SYS_CONFIG_NAME
- default "coreboot"
+ string "Board configuration file"
+ default "chromebook_link"
+ help
+ This option selects the board configuration file in include/configs/
+ directory to be used to build U-Boot for coreboot.
+
+config DEFAULT_DEVICE_TREE
+ string "Board Device Tree Source (dts) file"
+ default "chromebook_link"
+ help
+ This option selects the board Device Tree Source (dts) file in
+ arch/x86/dts/ directory to be used to build U-Boot for coreboot.
+
+config SYS_CAR_ADDR
+ hex "Board specific Cache-As-RAM (CAR) address"
+ default 0x19200000
+ help
+ This option specifies the board specific Cache-As-RAM (CAR) address.
+
+config SYS_CAR_SIZE
+ hex "Board specific Cache-As-RAM (CAR) size"
+ default 0x4000
+ help
+ This option specifies the board specific Cache-As-RAM (CAR) size.
endif
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
index 6ce66f5..2736aa0 100644
--- a/board/coreboot/coreboot/MAINTAINERS
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -2,5 +2,5 @@
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/coreboot/coreboot/
-F: include/configs/coreboot.h
+F: include/configs/chromebook_link.h
F: configs/coreboot-x86_defconfig
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
index 154faf6..e076ea6 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -10,8 +10,10 @@
int arch_early_init_r(void)
{
+#ifdef CONFIG_CROS_EC
if (cros_ec_board_init())
return -1;
+#endif
return 0;
}
diff --git a/board/dave/PPChameleonEVB/Kconfig b/board/dave/PPChameleonEVB/Kconfig
deleted file mode 100644
index bfe0011..0000000
--- a/board/dave/PPChameleonEVB/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_CATCENTER
-
-config SYS_BOARD
- default "PPChameleonEVB"
-
-config SYS_VENDOR
- default "dave"
-
-config SYS_CONFIG_NAME
- default "CATcenter"
-
-endif
-
-if TARGET_PPCHAMELEONEVB
-
-config SYS_BOARD
- default "PPChameleonEVB"
-
-config SYS_VENDOR
- default "dave"
-
-config SYS_CONFIG_NAME
- default "PPChameleonEVB"
-
-endif
diff --git a/board/dave/PPChameleonEVB/MAINTAINERS b/board/dave/PPChameleonEVB/MAINTAINERS
deleted file mode 100644
index d43c6d0..0000000
--- a/board/dave/PPChameleonEVB/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-PPCHAMELEONEVB BOARD
-#M: -
-S: Maintained
-F: board/dave/PPChameleonEVB/
-F: include/configs/CATcenter.h
-F: configs/CATcenter_defconfig
-F: configs/CATcenter_25_defconfig
-F: configs/CATcenter_33_defconfig
-
-PPCHAMELEONEVB BOARD
-M: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-S: Maintained
-F: include/configs/PPChameleonEVB.h
-F: configs/PPChameleonEVB_defconfig
-F: configs/PPChameleonEVB_BA_25_defconfig
-F: configs/PPChameleonEVB_BA_33_defconfig
-F: configs/PPChameleonEVB_HI_25_defconfig
-F: configs/PPChameleonEVB_HI_33_defconfig
-F: configs/PPChameleonEVB_ME_25_defconfig
-F: configs/PPChameleonEVB_ME_33_defconfig
diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile
deleted file mode 100644
index 31edc4a..0000000
--- a/board/dave/PPChameleonEVB/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = PPChameleonEVB.o flash.o nand.o
diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
deleted file mode 100644
index c9ab50e..0000000
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * (C) Copyright 2003
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-int board_early_init_f (void)
-{
- out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */
- out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0)
- * IRQ 26 (EXT IRQ 1)
- * IRQ 27 (EXT IRQ 2)
- * IRQ 28 (EXT IRQ 3)
- * IRQ 29 (EXT IRQ 4)
- * IRQ 30 (EXT IRQ 5)
- * IRQ 31 (EXT IRQ 6)
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
-#if 1 /* test-only */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-#else
- mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
-#endif
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-extern flash_info_t flash_info[]; /* info for FLASH chips */
-
-int misc_init_r (void)
-{
- /* adjust flash start and size as well as the offset */
- gd->bd->bi_flashstart = 0 - flash_info[0].size;
- gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
-#if 0
- volatile unsigned short *fpga_mode =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
- volatile unsigned char *duart0_mcr =
- (unsigned char *)((ulong)DUART0_BA + 4);
- volatile unsigned char *duart1_mcr =
- (unsigned char *)((ulong)DUART1_BA + 4);
-
- bd_t *bd = gd->bd;
- char * tmp; /* Temporary char pointer */
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
- unsigned long CPC0_CR0Reg;
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-#endif
-
-#if 0
- /*
- * Enable power on PS/2 interface
- */
- *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- *duart0_mcr = 0x08;
- *duart1_mcr = 0x08;
-#endif
- return (0);
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming PPChameleonEVB");
- } else {
- puts(str);
- }
-
- putc ('\n');
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_CFB_CONSOLE
-# ifdef CONFIG_CONSOLE_EXTRA_INFO
-# include <video_fb.h>
-extern GraphicDevice smi;
-
-void video_get_info_str (int line_number, char *info)
-{
- uint pvr = get_pvr ();
-
- /* init video info strings for graphic console */
- switch (line_number) {
- case 1:
- switch (pvr) {
- case PVR_405EP_RB:
- sprintf (info, " AMCC PowerPC 405EP Rev. B");
- break;
- default:
- sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
- break;
- }
- return;
- case 2:
- sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
- return;
- case 3:
- sprintf (info, " %s", smi.modeIdent);
- return;
- }
-
- /* no more info lines */
- *info = 0;
- return;
-}
-# endif /* CONFIG_CONSOLE_EXTRA_INFO */
-#endif /* CONFIG_CFB_CONSOLE */
diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c
deleted file mode 100644
index 771151b..0000000
--- a/board/dave/PPChameleonEVB/flash.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-#ifdef __DEBUG_START_FROM_SRAM__
- return CONFIG_SYS_DUMMY_FLASH_SIZE;
-#else
- unsigned long size;
- int i;
- uint pbcr;
- unsigned long base;
- int size_val = 0;
-
- debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
- debug("[%s, %d] flash_info = 0x%p ...\n", __func__, __LINE__,
- flash_info);
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
- size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-
- /* Setup offsets */
- flash_get_offsets (-size, &flash_info[0]);
- debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base = -size;
- switch (size) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
- debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
- flash_info[0].size = size;
-
- return (size);
-#endif
-}
diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c
deleted file mode 100644
index a191a0c..0000000
--- a/board/dave/PPChameleonEVB/nand.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
- */
-static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- ulong base = (ulong) this->IO_ADDR_W;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- MACRO_NAND_CTL_SETCLE((unsigned long)base);
- else
- MACRO_NAND_CTL_CLRCLE((unsigned long)base);
- if ( ctrl & NAND_ALE )
- MACRO_NAND_CTL_CLRCLE((unsigned long)base);
- else
- MACRO_NAND_CTL_CLRALE((unsigned long)base);
- if ( ctrl & NAND_NCE )
- MACRO_NAND_ENABLE_CE((unsigned long)base);
- else
- MACRO_NAND_DISABLE_CE((unsigned long)base);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-
-/*
- * read device ready pin
- * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
- */
-static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
-{
- struct nand_chip *this = mtdinfo->priv;
- ulong rb_gpio_pin;
-
- /* use the base addr to find out which chip are we dealing with */
- switch((ulong) this->IO_ADDR_W) {
- case CONFIG_SYS_NAND0_BASE:
- rb_gpio_pin = CONFIG_SYS_NAND0_RDY;
- break;
- case CONFIG_SYS_NAND1_BASE:
- rb_gpio_pin = CONFIG_SYS_NAND1_RDY;
- break;
- default: /* this should never happen */
- return 0;
- break;
- }
-
- if (in32(GPIO0_IR) & rb_gpio_pin)
- return 1;
- return 0;
-}
-
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - cmd_ctrl: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
- * only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- * read regs (tR)
- * - options: various chip options. They can partly be set to inform
- * nand_scan about special functionality. See the defines for further
- * explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-
- nand->cmd_ctrl = ppchameleonevb_hwcontrol;
- nand->dev_ready = ppchameleonevb_device_ready;
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->chip_delay = NAND_BIG_DELAY_US;
- nand->options = NAND_SAMSUNG_LP_OPTIONS;
- return 0;
-}
-#endif
diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds
deleted file mode 100644
index 94b7076..0000000
--- a/board/dave/PPChameleonEVB/u-boot.lds
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "config.h"
-
-#ifndef RESET_VECTOR_ADDRESS
-#define RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-OUTPUT_ARCH(powerpc)
-
-PHDRS
-{
- text PT_LOAD;
- bss PT_LOAD;
-}
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- *(.text*)
- } :text
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- } :text
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
- . = 0xFFFF8000;
- .ppcenv :
- {
- common/env_embedded.o(.ppcenv);
- }
-
- .resetvec RESET_VECTOR_ADDRESS :
- {
- KEEP(*(.resetvec))
- } :text = 0xffff
-
- . = RESET_VECTOR_ADDRESS + 0x4;
-
- /*
- * Make sure that the bss segment isn't linked at 0x0, otherwise its
- * address won't be updated during relocation fixups. Note that
- * this is a temporary fix. Code to dynamically the fixup the bss
- * location will be added in the future. When the bss relocation
- * fixup code is present this workaround should be removed.
- */
-#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
- . |= 0x10;
-#endif
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- } :bss
-
- . = ALIGN(4);
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/eltec/elppc/Kconfig b/board/eltec/elppc/Kconfig
deleted file mode 100644
index d4003e5..0000000
--- a/board/eltec/elppc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ELPPC
-
-config SYS_BOARD
- default "elppc"
-
-config SYS_VENDOR
- default "eltec"
-
-config SYS_CONFIG_NAME
- default "ELPPC"
-
-endif
diff --git a/board/eltec/elppc/MAINTAINERS b/board/eltec/elppc/MAINTAINERS
deleted file mode 100644
index e3b35f1..0000000
--- a/board/eltec/elppc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ELPPC BOARD
-#M: -
-S: Maintained
-F: board/eltec/elppc/
-F: include/configs/ELPPC.h
-F: configs/ELPPC_defconfig
diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile
deleted file mode 100644
index 791f2fb..0000000
--- a/board/eltec/elppc/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = elppc.o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o
-obj-y += asm_init.o
diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S
deleted file mode 100644
index 10fdfa2..0000000
--- a/board/eltec/elppc/asm_init.S
+++ /dev/null
@@ -1,862 +0,0 @@
-/*
- * (C) Copyright 2001 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * ELTEC ELPPC RAM initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <version.h>
-#include <mpc106.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-.globl board_asm_init
-board_asm_init:
-
-/*
- * setup pointer to message block
- */
- mflr r13 /* save away link register */
- bl get_lnk_reg /* r3=addr of next instruction */
- subi r4, r3, 8 /* r4=board_asm_init addr */
- addi r29, r4, (MessageBlock-board_asm_init)
-
-/*
- * dcache_disable
- */
- mfspr r3, HID0
- li r4, HID0_DCE
- andc r3, r3, r4
- mr r2, r3
- ori r3, r3, HID0_DCI
- sync
- mtspr HID0, r3
- mtspr HID0, r2
- isync
- sync
-/*
- * icache_disable
- */
- mfspr r3, HID0
- li r4, 0
- ori r4, r4, HID0_ICE
- andc r3, r3, r4
- sync
- mtspr HID0, r3
-/*
- * invalidate caches
- */
- ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE)
- or r4, r4, r3
- isync
- mtspr HID0, r4
- andc r4, r4, r3
- isync
- mtspr HID0, r4
- isync
-/*
- * icache_enable
- */
- mfspr r3, HID0
- ori r3, r3, (HID0_ICE | HID0_ICFI)
- sync
- mtspr HID0, r3
-
-
-/*
- * setup memory controller
- */
- lis r1, MPC106_REG_ADDR@h
- ori r1, r1, MPC106_REG_ADDR@l
- lis r2, MPC106_REG_DATA@h
- ori r2, r2, MPC106_REG_DATA@l
-
- /* Configure PICR1 */
- lis r3, MPC106_REG@h
- ori r3, r3, PCI_PICR1
- stwbrx r3, 0, r1
- addis r3, r0, 0xFF14
- ori r3, r3, 0x1CC8
- eieio
- stwbrx r3, 0, r2
-
- /* Configure PICR2 */
- lis r3, MPC106_REG@h
- ori r3, r3, PCI_PICR2
- stwbrx r3, 0, r1
- addis r3, r0, 0x0000
- ori r3, r3, 0x0000
- eieio
- stwbrx r3, 0, r2
-
- /* Configure EUMBAR */
- lis r3, MPC106_REG@h
- ori r3, r3, 0x0078 /* offest of EUMBAR in PCI config space */
- stwbrx r3, 0, r1
- lis r3, MPC107_EUMB_ADDR@h
- eieio
- stwbrx r3, 0, r2
-
- /* Configure Address Map B Option Reg */
- lis r3, MPC106_REG@h
- ori r3, r3, 0x00e0 /* offest of AMBOR in PCI config space */
- stwbrx r3, 0, r1
- lis r3, 0
- eieio
- stwbrx r3, 0, r2
-
- /* Configure I2C Controller */
- lis r14, MPC107_I2C_ADDR@h /* base of I2C controller */
- ori r14, r14, MPC107_I2C_ADDR@l
- lis r3, 0x2b10 /* I2C clock = 100MHz/1024 */
- stw r3, 4(r14)
- li r3, 0 /* clear arbitration */
- eieio
- stw r3, 12(r14)
-
- /* Configure MCCR1 */
- lis r3, MPC106_REG@h
- ori r3, r3, MPC106_MCCR1
- stwbrx r3, 0, r1
- addis r3, r0, 0x0660 /* don't set MEMGO now ! */
- ori r3, r3, 0x0000
- eieio
- stwbrx r3, 0, r2
-
- /* Configure MCCR2 */
- lis r3, MPC106_REG@h
- ori r3, r3, MPC106_MCCR2
- stwbrx r3, 0, r1
- addis r3, r0, 0x0400
- ori r3, r3, 0x1800
- eieio
- stwbrx r3, 0, r2
-
-
- /* Configure MCCR3 */
- lis r3, MPC106_REG@h
- ori r3, r3, MPC106_MCCR3
- stwbrx r3, 0, r1
- addis r3, r0, 0x0230
- ori r3, r3, 0x0000
- eieio
- stwbrx r3, 0, r2
-
- /* Configure MCCR4 */
- lis r3, MPC106_REG@h
- ori r3, r3, MPC106_MCCR4
- stwbrx r3, 0, r1
- addis r3, r0, 0x2532
- ori r3, r3, 0x2220
- eieio
- stwbrx r3, 0, r2
-
-/*
- * configure memory interface (MICRs)
- */
- addis r3, r0, 0x8000 /* ADDR_80 */
- ori r3, r3, 0x0080 /* SMEMADD1 */
- stwbrx r3, 0, r1
- addis r3, r0, 0xFFFF
- ori r3, r3, 0x4000
- eieio
- stwbrx r3, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_84 */
- ori r3, r3, 0x0084 /* SMEMADD2 */
- stwbrx r3, 0, r1
- addis r3, r0, 0xFFFF
- ori r3, r3, 0xFFFF
- eieio
- stwbrx r3, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_88 */
- ori r3, r3, 0x0088 /* EXTSMEM1 */
- stwbrx r3, 0, r1
- addis r3, r0, 0x0303
- ori r3, r3, 0x0000
- eieio
- stwbrx r3, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_8C */
- ori r3, r3, 0x008c /* EXTSMEM2 */
- stwbrx r3, 0, r1
- addis r3, r0, 0x0303
- ori r3, r3, 0x0303
- eieio
- stwbrx r3, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_90 */
- ori r3, r3, 0x0090 /* EMEMADD1 */
- stwbrx r3, 0, r1
- addis r3, r0, 0xFFFF
- ori r3, r3, 0x7F3F
- eieio
- stwbrx r3, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_94 */
- ori r3, r3, 0x0094 /* EMEMADD2 */
- stwbrx r3, 0, r1
- addis r3, r0, 0xFFFF
- ori r3, r3, 0xFFFF
- eieio
- stwbrx r3, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_98 */
- ori r3, r3, 0x0098 /* EXTEMEM1 */
- stwbrx r3, 0, r1
- addis r3, r0, 0x0303
- ori r3, r3, 0x0000
- eieio
- stwbrx r3, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_9C */
- ori r3, r3, 0x009c /* EXTEMEM2 */
- stwbrx r3, 0, r1
- addis r3, r0, 0x0303
- ori r3, r3, 0x0303
- eieio
- stwbrx r3, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_A0 */
- ori r3, r3, 0x00a0 /* MEMBNKEN */
- stwbrx r3, 0, r1
- addis r3, r0, 0x0000
- ori r3, r3, 0x0003
- eieio
- stwbrx r3, 0, r2
-
-/*
- * must wait at least 100us after HRESET to issue a MEMGO
- */
- lis r0, 1
- mtctr r0
-memStartWait:
- bdnz memStartWait
-
-/*
- * enable RAM Operations through MCCR1 (MEMGO)
- */
- lis r3, 0x8000
- ori r3, r3, 0x00f0
- stwbrx r3, r0, r1
- sync
- lwbrx r3, 0, r2
- lis r0, 0x0008
- or r3, r0, r3
- stwbrx r3, 0, r2
- sync
-
-/*
- * set LEDs first time
- */
- li r3, 0x1
- lis r30, CONFIG_SYS_USR_LED_BASE@h
- stb r3, 2(r30)
- sync
-
-/*
- * init COM1 for polled output
- */
- lis r8, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
- ori r8, r8, CONFIG_SYS_NS16550_COM1@l
- li r9, 0x00
- stb r9, 1(r8) /* int disabled */
- eieio
- li r9, 0x00
- stb r9, 4(r8) /* modem ctrl */
- eieio
- li r9, 0x80
- stb r9, 3(r8) /* link ctrl */
- eieio
- li r9, (CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE)
- stb r9, 0(r8) /* baud rate (LSB)*/
- eieio
- li r9, ((CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8)
- stb r9, 1(r8) /* baud rate (MSB) */
- eieio
- li r9, 0x07
- stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */
- eieio
- li r9, 0x0b
- stb r9, 4(r8) /* enable the receiver and transmitter (modem ctrl) */
- eieio
-waitEmpty:
- lbz r9, 5(r8) /* transmit empty */
- andi. r9, r9, 0x40
- beq waitEmpty
- li r9, 0x47
- stb r9, 3(r8) /* send break, 8 data bits, 2 stop bit, no parity */
- eieio
-
- lis r0, 0x0001
- mtctr r0
-waitCOM1:
- lwz r0, 5(r8) /* load from port for delay */
- bdnz waitCOM1
-
-waitEmpty1:
- lbz r9, 5(r8) /* transmit empty */
- andi. r9, r9, 0x40
- beq waitEmpty1
- li r9, 0x07
- stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */
- eieio
-
-/*
- * intro message from message block
- */
- addi r3, r29, (MnewLine-MessageBlock)
- bl Printf
- addi r3, r29, (MinitLogo-MessageBlock)
- bl Printf
-
-/*
- * memory cofiguration using SPD information stored on the SODIMMs
- */
- addi r3, r29, (Mspd01-MessageBlock)
- bl Printf
-
- li r17, 0
-
- li r3, 0x0002 /* get RAM type from spd for bank0/1 */
- bl spdRead
-
- cmpi 0, 0, r3, -1 /* error ? */
- bne noSpdError
-
- addi r3, r29, (Mfail-MessageBlock)
- bl Printf
-
- li r6, 0xe /* error codes in r6 and r7 */
- li r7, 0x0
- b toggleError /* fail - loop forever */
-
-noSpdError:
- mr r15, r3 /* save r3 */
-
- addi r3, r29, (Mok-MessageBlock)
- bl Printf
-
- cmpli 0, 0, r15, 0x0004 /* SDRAM ? */
- beq isSDRAM
-
- addi r3, r29, (MramTyp-MessageBlock)
- bl Printf
-
- li r6, 0xd /* error codes in r6 and r7 */
- li r7, 0x0
- b toggleError /* fail - loop forever */
-
-isSDRAM:
- li r3, 0x0012 /* get supported CAS latencies from byte 18 */
- bl spdRead
- mr r15, r3
- li r3, 0x09
- andi. r0, r15, 0x04
- bne maxCLis3
- li r3, 0x17
-maxCLis3:
- andi. r0, r15, 0x02
- bne CL2
-
- addi r3, r29, (MramTyp-MessageBlock)
- bl Printf
-
- li r6, 0xc /* error codes in r6 and r7 */
- li r7, 0x0
- b toggleError /* fail - loop forever */
-CL2:
- bl spdRead
- cmpli 0, 0, r3, 0xa1 /* cycle time must be 10ns max. */
- blt speedOk
-
- addi r3, r29, (MramTyp-MessageBlock)
- bl Printf
-
- li r6, 0xb /* error codes in r6 and r7 */
- li r7, 0x0
- b toggleError /* fail - loop forever */
-speedOk:
- lis r20, 0x06e8 /* preset MCR1 value */
-
- li r3, 0x0011 /* get number of internal banks from spd for bank0/1 */
- bl spdRead
-
- cmpli 0, 0, r3, 0x02
- beq SD_2B
- cmpli 0, 0, r3, 0x04
- beq SD_4B
-memConfErr:
- addi r3, r29, (MramConfErr-MessageBlock)
- bl Printf
-
- li r6, 0xa /* error codes in r6 and r7 */
- li r7, 0x0
- b toggleError /* fail - loop forever */
-
-SD_2B:
- li r3, 0x0003 /* get number of row bits from spd for bank0/1 */
- bl spdRead
- cmpli 0, 0, r3, 0x0b
- beq row11x2
- cmpli 0, 0, r3, 0x0c
- beq row12x2or13x2
- cmpli 0, 0, r3, 0x0d
- beq row12x2or13x2
- b memConfErr
-SD_4B:
- li r3, 0x0003 /* get number of row bits from spd for bank0/1 */
- bl spdRead
- cmpli 0, 0, r3, 0x0b
- beq row11x4or12x4
- cmpli 0, 0, r3, 0x0c
- beq row11x4or12x4
- cmpli 0, 0, r3, 0x0d
- beq row13x4
- b memConfErr
-row12x2or13x2:
- ori r20, r20, 0x05
- b row11x4or12x4
-row13x4:
- ori r20, r20, 0x0a
- b row11x4or12x4
-row11x2:
- ori r20, r20, 0x0f
-row11x4or12x4:
- /* get the size of bank 0-1 */
-
- li r3, 0x001f /* get bank size from spd for bank0/1 */
- bl spdRead
-
- rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte (128 MB max.) */
-
- li r3, 0x0005 /* get number of banks from spd for bank0/1 */
- bl spdRead
-
- cmpi 0, 0, r3, 2 /* 2 banks ? */
- bne SDRAMnobank1
-
- mr r17, r16
-
-SDRAMnobank1:
- li r3, 0x000c /* get refresh from spd for bank0/1 */
- bl spdRead
- andi. r3, r3, 0x007f /* mask selfrefresh bit */
- li r4, 0x1800 /* refesh cycle 1536 clocks left shifted 2 */
- cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */
- beq writeRefresh
-
- li r4, 0x0c00 /* refesh cycle 768 clocks left shifted 2 */
- cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */
- beq writeRefresh
-
- li r4, 0x3000 /* refesh cycle 3072 clocks left shifted 2 */
- cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */
- beq writeRefresh
-
- li r4, 0x6000 /* refesh cycle 6144 clocks left shifted 2 */
- cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */
- beq writeRefresh
-
- li r4, 0
- ori r4, r4, 0xc000 /* refesh cycle 8224 clocks left shifted 2 */
- cmpli 0, 0, r3, 0x0005 /* 125 us ? */
- beq writeRefresh
-
- b memConfErr
-
-writeRefresh:
- lis r21, 0x0400 /* preset MCCR2 value */
- or r21, r21, r4
-
- /* Overwrite MCCR1 */
- lis r3, MPC106_REG@h
- ori r3, r3, MPC106_MCCR1
- stwbrx r3, 0, r1
- eieio
- stwbrx r20, 0, r2
-
- /* Overwrite MCCR2 */
- lis r3, MPC106_REG@h
- ori r3, r3, MPC106_MCCR2
- stwbrx r3, 0, r1
- eieio
- stwbrx r21, 0, r2
-
- /* set the memory boundary registers for bank 0-3 */
- li r20, 0
- lis r23, 0x0303
- lis r24, 0x0303
- subi r21, r16, 1 /* calculate end address bank0 */
- li r22, 1
-
- cmpi 0, 0, r17, 0 /* bank1 present ? */
- beq nobank1
-
- andi. r3, r16, 0x00ff /* calculate start address of bank1 */
- andi. r4, r16, 0x0300
- rlwinm r3, r3, 8, 16, 23
- or r20, r20, r3
- or r23, r23, r4
-
- add r16, r16, r17 /* add to total memory size */
-
- subi r3, r16, 1 /* calculate end address of bank1 */
- andi. r4, r3, 0x0300
- andi. r3, r3, 0x00ff
- rlwinm r3, r3, 8, 16, 23
- or r21, r21, r3
- or r24, r24, r4
-
- ori r22, r22, 2 /* enable bank1 */
- b bankOk
-nobank1:
- ori r23, r23, 0x0300 /* set bank1 start to unused area */
- ori r24, r24, 0x0300 /* set bank1 end to unused area */
-bankOk:
- addi r3, r29, (Mactivate-MessageBlock)
- bl Printf
- mr r3, r16
- bl OutDec
- addi r3, r29, (Mact0123e-MessageBlock)
- bl Printf
-
-/*
- * overwrite MSAR1, MEAR1, EMSAR1, and EMEAR1
- */
- addis r3, r0, 0x8000 /* ADDR_80 */
- ori r3, r3, 0x0080 /* MSAR1 */
- stwbrx r3, 0, r1
- eieio
- stwbrx r20, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_88 */
- ori r3, r3, 0x0088 /* EMSAR1 */
- stwbrx r3, 0, r1
- eieio
- stwbrx r23, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_90 */
- ori r3, r3, 0x0090 /* MEAR1 */
- stwbrx r3, 0, r1
- eieio
- stwbrx r21, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_98 */
- ori r3, r3, 0x0098 /* EMEAR1 */
- stwbrx r3, 0, r1
- eieio
- stwbrx r24, 0, r2
-
- addis r3, r0, 0x8000 /* ADDR_A0 */
- ori r3, r3, 0x00a0 /* MBER */
- stwbrx r3, 0, r1
- eieio
- stwbrx r22, 0, r2
-
-/*
- * delay to let SDRAM go through several initialization/refresh cycles
- */
- lis r3, 3
- mtctr r3
-memStartWait_1:
- bdnz memStartWait_1
- eieio
-
-/*
- * set LEDs end
- */
- li r3, 0xf
- lis r30, CONFIG_SYS_USR_LED_BASE@h
- stb r3, 2(r30)
- sync
-
- mtlr r13
- blr /* EXIT board_asm_init ... */
-
-/*----------------------------------------------------------------------------*/
-/*
- * print a message to COM1 in polling mode (r10=COM1 port, r3=(char*)string)
- */
-
-Printf:
- lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
- ori r10, r10, CONFIG_SYS_NS16550_COM1@l
-WaitChr:
- lbz r0, 5(r10) /* read link status */
- eieio
- andi. r0, r0, 0x40 /* mask transmitter empty bit */
- beq cr0, WaitChr /* wait till empty */
- lbzx r0, r0, r3 /* get char */
- stb r0, 0(r10) /* write to transmit reg */
- eieio
- addi r3, r3, 1 /* next char */
- lbzx r0, r0, r3 /* get char */
- cmpwi cr1, r0, 0 /* end of string ? */
- bne cr1, WaitChr
- blr
-
-/*
- * print a char to COM1 in polling mode (r10=COM1 port, r3=char)
- */
-OutChr:
- lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
- ori r10, r10, CONFIG_SYS_NS16550_COM1@l
-OutChr1:
- lbz r0, 5(r10) /* read link status */
- eieio
- andi. r0, r0, 0x40 /* mask transmitter empty bit */
- beq cr0, OutChr1 /* wait till empty */
- stb r3, 0(r10) /* write to transmit reg */
- eieio
- blr
-
-/*
- * print 8/4/2 digits hex value to COM1 in polling mode (r10=COM1 port, r3=val)
- */
-OutHex2:
- li r9, 4 /* shift reg for 2 digits */
- b OHstart
-OutHex4:
- li r9, 12 /* shift reg for 4 digits */
- b OHstart
-OutHex:
- li r9, 28 /* shift reg for 8 digits */
-OHstart:
- lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
- ori r10, r10, CONFIG_SYS_NS16550_COM1@l
-OutDig:
- lbz r0, 0(r29) /* slow down dummy read */
- lbz r0, 5(r10) /* read link status */
- eieio
- andi. r0, r0, 0x40 /* mask transmitter empty bit */
- beq cr0, OutDig
- sraw r0, r3, r9
- clrlwi r0, r0, 28
- cmpwi cr1, r0, 9
- ble cr1, digIsNum
- addic r0, r0, 55
- b nextDig
-digIsNum:
- addic r0, r0, 48
-nextDig:
- stb r0, 0(r10) /* write to transmit reg */
- eieio
- addic. r9, r9, -4
- bge OutDig
- blr
-
-/*
- * print 3 digits hdec value to COM1 in polling mode
- * (r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch)
- */
-OutDec:
- li r6, 10
- divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */
- mullw r10, r0, r6
- subf r9, r10, r3
- mr r3, r0
- divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */
- mullw r10, r0, r6
- subf r8, r10, r3
- mr r3, r0
- divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */
- mullw r10, r0, r6
- subf r7, r10, r3
- lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
- ori r10, r10, CONFIG_SYS_NS16550_COM1@l
- or. r7, r7, r7
- bne noblank1
- li r3, 0x20
- b OutDec4
-noblank1:
- addi r3, r7, 48 /* convert to ASCII */
-OutDec4:
- lbz r0, 0(r29) /* slow down dummy read */
- lbz r0, 5(r10) /* read link status */
- eieio
- andi. r0, r0, 0x40 /* mask transmitter empty bit */
- beq cr0, OutDec4
- stb r3, 0(r10) /* x00 to transmit */
- eieio
- or. r7, r7, r8
- beq OutDec5
- addi r3, r8, 48 /* convert to ASCII */
-OutDec5:
- lbz r0, 0(r29) /* slow down dummy read */
- lbz r0, 5(r10) /* read link status */
- eieio
- andi. r0, r0, 0x40 /* mask transmitter empty bit */
- beq cr0, OutDec5
- stb r3, 0(r10) /* x0 to transmit */
- eieio
- addi r3, r9, 48 /* convert to ASCII */
-OutDec6:
- lbz r0, 0(r29) /* slow down dummy read */
- lbz r0, 5(r10) /* read link status */
- eieio
- andi. r0, r0, 0x40 /* mask transmitter empty bit */
- beq cr0, OutDec6
- stb r3, 0(r10) /* x to transmit */
- eieio
- blr
-
-/*
- * hang endless loop
- */
-toggleError: /* fail type in r6, r7=0xff, toggle LEDs */
- stb r7, 2(r30) /* r7 to LED */
- li r0, 0
- lis r9, 127
- ori r9, r9, 65535
-toggleError1:
- addic r0, r0, 1
- cmpw cr1, r0, r9
- ble cr1, toggleError1
- stb r6, 2(r30) /* r6 to LED */
- li r0, 0
- lis r9, 127
- ori r9, r9, 65535
-toggleError2:
- addic r0, r0, 1
- cmpw cr1, r0, r9
- ble cr1, toggleError2
- b toggleError
-
-/*
- * routines to read from ram spd
- */
-spdWaitIdle:
- lis r0, 0x1 /* timeout for about 100us */
- mtctr r0
-iSpd:
- lbz r10, 12(r14)
- andi. r10, r10, 0x20 /* mask and test MBB */
- beq idle
- bdnz iSpd
- orc. r10, r0, r0 /* return -1 to caller */
-idle:
- bclr 20, 0 /* return to caller */
-
-waitSpd:
- lis r0, 0x10 /* timeout for about 1.5ms */
- mtctr r0
-wSpd:
- lbz r10, 12(r14)
- andi. r10, r10, 0x82
- cmpli 0, 0, r10, 0x82 /* test MCF and MIF set */
- beq wend
- bdnz wSpd
- orc. r10, r0, r0 /* return -1 to caller */
- bclr 20, 0 /* return to caller */
-
-wend:
- li r10, 0
- stb r10, 12(r14) /* clear status */
- bclr 20, 0 /* return to caller */
-
-/*
- * spdread
- * in: r3 adr to read
- * out: r3 val or -1 for error
- * uses r10, assumes that r14 points to I2C controller
- */
-spdRead:
- mfspr r25, 8 /* save link register */
-
- bl spdWaitIdle
- bne spdErr
-
- li r10, 0x80 /* start with MEN */
- stb r10, 8(r14)
- eieio
-
- li r10, 0xb0 /* start as master */
- stb r10, 8(r14)
- eieio
-
- li r10, 0xa0 /* write device 0xA0 */
- stb r10, 16(r14)
- eieio
- bl waitSpd
- bne spdErr
-
- lbz r10, 12(r14) /* test ACK */
- andi. r10, r10, 0x01
- bne gotNoAck
-
- stb r3, 16(r14) /* data address */
- eieio
- bl waitSpd
- bne spdErr
-
-
- li r10, 0xb4 /* switch to read - restart */
- stb r10, 8(r14)
- eieio
-
- li r10, 0xa1 /* read device 0xA0 */
- stb r10, 16(r14)
- eieio
- bl waitSpd
- bne spdErr
-
- li r10, 0xa8 /* no ACK */
- stb r10, 8(r14)
- eieio
-
- lbz r10, 16(r14) /* trigger read next byte */
- eieio
- bl waitSpd
- bne spdErr
-
- li r10, 0x88 /* generate STOP condition */
- stb r10, 8(r14)
- eieio
-
- lbz r3, 16(r14) /* return read byte */
-
- mtspr 8, r25 /* restore link register */
- blr
-
-gotNoAck:
- li r10, 0x80 /* generate STOP condition */
- stb r10, 8(r14)
- eieio
-spdErr:
- orc r3, r0, r0 /* return -1 */
- mtspr 8, r25 /* restore link register */
- blr
-
-get_lnk_reg:
- mflr r3 /* return link reg */
- blr
-
-MessageBlock:
-
-MinitLogo:
- .ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012"
- .ascii "\015\012Initialising RAM\015\012\000"
-Mspd01:
- .ascii " Reading SPD of SODIMM ...... \000"
-MramTyp:
- .ascii "\015\012\SDRAM with CL=2 at 100 MHz required!\015\012\000"
-MramConfErr:
- .ascii "\015\012\Unsupported SODIMM Configuration!\015\012\000"
-Mactivate:
- .ascii " Activating \000"
-Mact0123e:
- .ascii " MByte.\015\012\000"
-Mok:
- .ascii "OK \015\012\000"
-Mfail:
- .ascii "FAILED \015\012\000"
-MnewLine:
- .ascii "\015\012\000"
- .align 4
diff --git a/board/eltec/elppc/eepro100_srom.c b/board/eltec/elppc/eepro100_srom.c
deleted file mode 100644
index 05ba9c4..0000000
--- a/board/eltec/elppc/eepro100_srom.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Local network srom writing for first time run
- */
-
-/* includes */
-#include <common.h>
-#include <pci.h>
-#include <net.h>
-#include "srom.h"
-
-extern int eepro100_write_eeprom (struct eth_device *dev,
- int location, int addr_len,
- unsigned short data);
-
-/*----------------------------------------------------------------------------*/
-
-unsigned short eepro100_srom_checksum (unsigned short *sromdata)
-{
- unsigned short sum = 0;
- unsigned int i;
-
- for (i = 0; i < (EE_SIZE - 1); i++) {
- sum += sromdata[i];
- }
- return (EE_CHECKSUM - sum);
-}
-
-/*----------------------------------------------------------------------------*/
-
-int eepro100_srom_store (unsigned short *source)
-{
- int count;
- struct eth_device onboard_dev;
-
- /* get onboard network iobase */
- pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0,
- (unsigned int *) &onboard_dev.iobase);
- onboard_dev.iobase &= ~0xf;
-
- source[63] = eepro100_srom_checksum (source);
-
- for (count = 0; count < EE_SIZE; count++) {
- if (eepro100_write_eeprom ((struct eth_device *) &onboard_dev,
- count, EE_ADDR_BITS,
- SROM_SHORT (source)) == -1) {
- return -1;
- }
- source++;
- }
- return 0;
-}
-
-/*----------------------------------------------------------------------------*/
-
-#ifdef EEPRO100_SROM_CHECK
-
-extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
-
-void eepro100_srom_load (unsigned short *destination)
-{
- int count;
- struct eth_device onboard_dev;
-
-#ifdef DEBUG
- int lr = 0;
-
- printf ("eepro100_srom_download:\n");
-#endif
-
- /* get onboard network iobase */
- pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0,
- &onboard_dev.iobase);
- onboard_dev.iobase &= ~0xf;
-
- memset (destination, 0x65, 128);
-
- for (count = 0; count < 0x40; count++) {
- *destination++ = read_eeprom ((struct eth_device *) &onboard_dev,
- count, EE_ADDR_BITS);
-#ifdef DEBUG
- printf ("%04x ", *(destination - 1));
- if (lr++ == 7) {
- printf ("\n");
- lr = 0;
- }
-#endif
- }
-}
-#endif /* EEPRO100_SROM_CHECK */
-
-/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c
deleted file mode 100644
index ac814b8..0000000
--- a/board/eltec/elppc/elppc.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <mpc106.h>
-#include <video_fb.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-int checkboard (void)
-{
- puts ("Board: ELTEC PowerPC\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int checkflash (void)
-{
- /* TODO */
- printf ("Test not implemented !\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static unsigned int mpc106_read_cfg_dword (unsigned int reg)
-{
- unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
-
- out32r (MPC106_REG_ADDR, reg_addr);
-
- return (in32r (MPC106_REG_DATA | (reg & 0x3)));
-}
-
-/* ------------------------------------------------------------------------- */
-
-long int dram_size (int board_type)
-{
- /*
- * No actual initialisation to do - done when setting up
- * PICRs MCCRs ME/SARs etc in asm_init.S.
- */
-
- register unsigned long i, msar1, mear1, memSize;
-
-#if defined(CONFIG_SYS_MEMTEST)
- register unsigned long reg;
-
- printf ("Testing DRAM\n");
-
- /* write each mem addr with it's address */
- for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
- *reg = reg;
-
- for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
- if (*reg != reg)
- return -1;
- }
-#endif
-
- /*
- * Since MPC107 memory controller chip has already been set to
- * control all memory, just read and interpret its memory boundery register.
- */
- memSize = 0;
- msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
- mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
- i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
-
- do {
- if (i & 0x01) /* is bank enabled ? */
- memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
- msar1 >>= 8;
- mear1 >>= 8;
- i >>= 1;
- } while (i);
-
- return (memSize * 0x100000);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- return dram_size (board_type);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * The BAB 911 can be reset by writing bit 0 of the Processor Initialization
- * Register PI in the MPC 107 (at offset 0x41090 of the Embedded Utilities
- * Memory Block).
- */
-int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- out8 (MPC107_EUMB_PI, 1);
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_WATCHDOG)
-
-/*
- * Since the 7xx CPUs don't have an internal watchdog, this function is
- * board specific.
- */
-void watchdog_reset (void)
-{
-}
-#endif /* CONFIG_WATCHDOG */
-
-/* ------------------------------------------------------------------------- */
-
-void after_reloc (ulong dest_addr)
-{
- /*
- * Jump to the main U-Boot board init code
- */
- board_init_r ((gd_t *)gd, dest_addr);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-extern GraphicDevice smi;
-
-void video_get_info_str (int line_number, char *info)
-{
- /* init video info strings for graphic console */
- switch (line_number) {
- case 1:
- sprintf (info, " MPC7xx V%d.%d at %d / %d MHz",
- (get_pvr () >> 8) & 0xFF, get_pvr () & 0xFF, 400, 100);
- return;
- case 2:
- sprintf (info, " ELTEC ELPPC with %ld MB DRAM and %ld MB FLASH",
- dram_size (0) / 0x100000, flash_init () / 0x100000);
- return;
- case 3:
- sprintf (info, " %s", smi.modeIdent);
- return;
- }
-
- /* no more info lines */
- *info = 0;
- return;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c
deleted file mode 100644
index 2b41685..0000000
--- a/board/eltec/elppc/flash.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC).
- * fixed monitor protection part
- *
- * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage
- * of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use
- * any other.
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*flash command address offsets*/
-
-#define ADDR0 (0x555)
-#define ADDR1 (0x2AA)
-#define ADDR3 (0x001)
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*----------------------------------------------------------------------------*/
-
-unsigned long flash_init (void)
-{
- unsigned long size1, size2;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* initialise 1st flash */
- size1 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN)
- {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size1, size1<<20);
- }
-
- /* initialise 2nd flash */
- size2 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (flash_info[1].flash_id == FLASH_UNKNOWN)
- {
- printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
- size2, size2<<20);
- }
-
- /* monitor protection ON by default */
- if (size1 == 512*1024)
- {
- (void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE0_PRELIM,
- FLASH_BASE0_PRELIM+monitor_flash_len-1,
- &flash_info[0]);
- }
- if (size2 == 512*1024)
- {
- (void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE1_PRELIM,
- FLASH_BASE1_PRELIM+monitor_flash_len-1,
- &flash_info[1]);
- }
- if (size2 == 4*1024*1024)
- {
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
- &flash_info[1]);
- }
-
- return (size1 + size2);
-}
-
-/*----------------------------------------------------------------------------*/
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- flash_init();
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case AMD_ID_F040B:
- printf ("AM29F040B (4 Mbit)\n");
- break;
- case AMD_ID_F016D:
- printf ("AM29F016D (16 Mbit)\n");
- break;
- case AMD_ID_F032B:
- printf ("AM29F032B (32 Mbit)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size >= (1 << 20)) {
- printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
- } else {
- printf (" Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count);
- }
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
-
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++) {
- if (*flash++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
-
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
- }
- printf ("\n");
-}
-
-/*----------------------------------------------------------------------------*/
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong vendor, devid;
- ulong base = (ulong)addr;
- volatile unsigned char *caddr = (unsigned char *)addr;
-
-#ifdef DEBUG
- printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr);
-#endif
-
- /* Write auto select command: read Manufacturer ID */
- caddr[0] = 0xF0; /* reset bank */
- udelay(10);
-
- eieio();
- caddr[0x555] = 0xAA;
- udelay(10);
- caddr[0x2AA] = 0x55;
- udelay(10);
- caddr[0x555] = 0x90;
-
- udelay(10);
-
- vendor = caddr[0];
- devid = caddr[1];
-
-#ifdef DEBUG
- printf("Manufacturer: 0x%lx\n", vendor);
-#endif
-
- vendor &= 0xff;
- devid &= 0xff;
-
- /* We accept only two AMD types */
- switch (vendor) {
- case (FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- switch (devid) {
- case (FLASH_WORD_SIZE)AMD_ID_F040B:
- info->flash_id |= AMD_ID_F040B;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_F016D:
- info->flash_id |= AMD_ID_F016D;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE)AMD_ID_F032B:
- info->flash_id |= AMD_ID_F032B;
- info->sector_count = 64;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
-#ifdef DEBUG
- printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size);
-#endif
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* sector base address */
- info->start[i] = base + i * (info->size / info->sector_count);
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- caddr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = caddr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (volatile unsigned char *)info->start[0];
- caddr[0] = 0xF0; /* reset bank */
- }
-
- return (info->size);
-}
-
-/*----------------------------------------------------------------------------*/
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- int rc = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (FLASH_WORD_SIZE *)(info->start[sect]);
- if (info->flash_id & FLASH_MAN_SST) {
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
- addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
- udelay(30000); /* wait 30 ms */
- }
- else
- addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
- while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return rc;
-}
-
-/*----------------------------------------------------------------------------*/
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*----------------------------------------------------------------------------*/
-/* Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
- ulong start;
- int flag;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *)dest) &
- (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
- {
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c
deleted file mode 100644
index 2acf800..0000000
--- a/board/eltec/elppc/misc.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* includes */
-#include <common.h>
-#include <cli.h>
-#include <linux/ctype.h>
-#include <pci.h>
-#include <net.h>
-#include "srom.h"
-
-/* imports */
-extern int l2_cache_enable (int l2control);
-extern int eepro100_write_eeprom (struct eth_device *dev, int location,
- int addr_len, unsigned short data);
-extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
-
-/*----------------------------------------------------------------------------*/
-/*
- * read/write to nvram is only byte access
- */
-void *nvram_read (void *dest, const long src, size_t count)
-{
- uchar *d = (uchar *) dest;
- uchar *s = (uchar *) (CONFIG_ENV_MAP_ADRS + src);
-
- while (count--)
- *d++ = *s++;
-
- return dest;
-}
-
-void nvram_write (long dest, const void *src, size_t count)
-{
- uchar *d = (uchar *) (CONFIG_ENV_MAP_ADRS + dest);
- uchar *s = (uchar *) src;
-
- while (count--)
- *d++ = *s++;
-}
-
-/*----------------------------------------------------------------------------*/
-/*
- * handle sroms on ELPPC
- * fix ether address
- * set serial console as default
- */
-int misc_init_r (void)
-{
- revinfo eerev;
- u_char *ptr;
- u_int i, l, initSrom, copyNv;
- char buf[256];
- char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
- 0, 0, 0, 0, 10, 11, 12, 13, 14, 15
- };
-
- /* Clock setting for MPC107 i2c */
- mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
-
- /* Reset the EPIC */
- out32r (MPC107_EUMB_GCR, 0xa0000000);
- while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */
- out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */
- while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */
-
- /*
- * Check/Remake revision info
- */
- initSrom = 0;
- copyNv = 0;
-
- /* read out current revision srom contens */
- mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo),
- SECOND_DEVICE, FIRST_BLOCK);
-
- /* read out current nvram shadow image */
- nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
-
- if (strcmp (eerev.magic, "ELTEC") != 0) {
- /* srom is not initialized -> create a default revision info */
- for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo);
- i++)
- *ptr++ = 0x00;
- strcpy (eerev.magic, "ELTEC");
- eerev.revrev[0] = 1;
- eerev.revrev[1] = 0;
- eerev.size = 0x00E0;
- eerev.category[0] = 0x01;
-
- /* node id from dead e128 as default */
- eerev.etheraddr[0] = 0x00;
- eerev.etheraddr[1] = 0x00;
- eerev.etheraddr[2] = 0x5B;
- eerev.etheraddr[3] = 0x00;
- eerev.etheraddr[4] = 0x2E;
- eerev.etheraddr[5] = 0x4D;
-
- /* cache config word for ELPPC */
- memset(&eerev.res[0], 0, 4);
-
- initSrom = 1; /* force dialog */
- copyNv = 1; /* copy to nvram */
- }
-
- if ((copyNv == 0)
- && (el_srom_checksum ((u_char *) & eerev, CONFIG_SYS_SROM_SIZE) !=
- el_srom_checksum ((u_char *) buf, CONFIG_SYS_SROM_SIZE))) {
- printf ("Invalid revision info copy in nvram !\n");
- printf ("Press key:\n <c> to copy current revision info to nvram.\n");
- printf (" <r> to reenter revision info.\n");
- printf ("=> ");
- if (0 != cli_readline(NULL)) {
- switch ((char) toupper (console_buffer[0])) {
- case 'C':
- copyNv = 1;
- break;
- case 'R':
- copyNv = 1;
- initSrom = 1;
- break;
- }
- }
- }
-
- if (initSrom) {
- memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */
- printf ("Enter revision number (0-9): %c ",
- eerev.revision[0][0]);
- if (0 != cli_readline(NULL)) {
- eerev.revision[0][0] =
- (char) toupper (console_buffer[0]);
- memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
- }
-
- printf ("Enter revision character (A-Z): %c ",
- eerev.revision[0][1]);
- if (1 == cli_readline(NULL)) {
- eerev.revision[0][1] =
- (char) toupper (console_buffer[0]);
- }
-
- printf ("Enter board name (V-XXXX-XXXX): %s ",
- (char *) &eerev.board);
- if (11 == cli_readline(NULL)) {
- for (i = 0; i < 11; i++)
- eerev.board[i] =
- (char) toupper (console_buffer[i]);
- eerev.board[11] = '\0';
- }
-
- printf ("Enter serial number: %s ", (char *) &eerev.serial);
- if (6 == cli_readline(NULL)) {
- for (i = 0; i < 6; i++)
- eerev.serial[i] = console_buffer[i];
- eerev.serial[6] = '\0';
- }
-
- printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
- if (12 == cli_readline(NULL)) {
- for (i = 0; i < 12; i += 2)
- eerev.etheraddr[i >> 1] =
- (char) (16 *
- hex[toupper
- (console_buffer[i]) -
- '0'] +
- hex[toupper
- (console_buffer[i + 1]) -
- '0']);
- }
-
- l = strlen ((char *) &eerev.text);
- printf ("Add to text section (max 64 chr): %s ",
- (char *) &eerev.text);
- if (0 != cli_readline(NULL)) {
- for (i = l; i < 63; i++)
- eerev.text[i] = console_buffer[i - l];
- eerev.text[63] = '\0';
- }
-
- /* prepare network eeprom */
- memset (buf, 0, 128);
-
- buf[0] = eerev.etheraddr[1];
- buf[1] = eerev.etheraddr[0];
- buf[2] = eerev.etheraddr[3];
- buf[3] = eerev.etheraddr[2];
- buf[4] = eerev.etheraddr[5];
- buf[5] = eerev.etheraddr[4];
-
- buf[20] = 0x48;
- buf[21] = 0xB2;
-
- buf[22] = 0x00;
- buf[23] = 0x04;
-
- buf[24] = 0x14;
- buf[25] = 0x33;
-
- printf ("\nSRom: Writing i82559 info ........ ");
- if (eepro100_srom_store ((unsigned short *) buf) == -1)
- printf ("FAILED\n");
- else
- printf ("OK\n");
-
- /* update CRC */
- eerev.crc =
- el_srom_checksum ((u_char *) eerev.board, eerev.size);
-
- /* write new values */
- printf ("\nSRom: Writing revision info ...... ");
- if (mpc107_srom_store
- ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev,
- sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
- printf ("FAILED\n\n");
- else
- printf ("OK\n\n");
-
- /* write new values as shadow image to nvram */
- nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
- CONFIG_SYS_SROM_SIZE);
-
- }
-
- /*if (initSrom) */
- /* copy current values as shadow image to nvram */
- if (initSrom == 0 && copyNv == 1)
- nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
- CONFIG_SYS_SROM_SIZE);
-
- /* update environment */
- sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
- eerev.etheraddr[0], eerev.etheraddr[1],
- eerev.etheraddr[2], eerev.etheraddr[3],
- eerev.etheraddr[4], eerev.etheraddr[5]);
- setenv ("ethaddr", buf);
-
- /* print actual board identification */
- printf ("Ident: %s Ser %s Rev %c%c\n",
- eerev.board, (char *) &eerev.serial,
- eerev.revision[0][0], eerev.revision[0][1]);
-
- return (0);
-}
-
-/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/mpc107_i2c.c b/board/eltec/elppc/mpc107_i2c.c
deleted file mode 100644
index 4f95703..0000000
--- a/board/eltec/elppc/mpc107_i2c.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* includes */
-#include <common.h>
-#include "srom.h"
-
-/* locals */
-static unsigned long mpc107_eumb_addr = 0;
-
-/*----------------------------------------------------------------------------*/
-
-/*
- * calculate checksum for ELTEC revision srom
- */
-unsigned long el_srom_checksum (ptr, size)
-register unsigned char *ptr;
-unsigned long size;
-{
- u_long f, accu = 0;
- u_int i;
- u_char byte;
-
- for (; size; size--)
- {
- byte = *ptr++;
- for (i = 8; i; i--)
- {
- f = ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0;
- accu >>= 1; accu ^= f;
- byte >>= 1;
- }
- }
- return(accu);
-}
-
-/*----------------------------------------------------------------------------*/
-
-static int mpc107_i2c_wait ( unsigned long timeout )
-{
- unsigned long x;
-
- while (((x = in32r(MPC107_I2CSR)) & 0x82) != 0x82)
- {
- if (!timeout--)
- return -1;
- }
-
- if (x & 0x10)
- {
- return -1;
- }
- out32r(MPC107_I2CSR, 0);
-
- return 0;
-}
-
-/*----------------------------------------------------------------------------*/
-
-static int mpc107_i2c_wait_idle ( unsigned long timeout )
-{
- while (in32r(MPC107_I2CSR) & 0x20)
- {
- if (!timeout--)
- return -1;
- }
- return 0;
-}
-
-
-/*----------------------------------------------------------------------------*/
-
-int mpc107_i2c_read_byte (
- unsigned char device,
- unsigned char block,
- unsigned char offset )
-{
- unsigned long timeout = MPC107_I2C_TIMEOUT;
- int data;
-
- if (!mpc107_eumb_addr)
- return -6;
-
- mpc107_i2c_wait_idle (timeout);
-
- /* Start with MEN */
- out32r(MPC107_I2CCR, 0x80);
-
- /* Start as master */
- out32r(MPC107_I2CCR, 0xB0);
- out32r(MPC107_I2CDR, (0xA0 | device | block));
-
- if (mpc107_i2c_wait(timeout) < 0)
- {
- printf("mpc107_i2c_read Error 1\n");
- return -2;
- }
-
- if (in32r(MPC107_I2CSR)&0x1)
- {
- /* Generate STOP condition; device busy or not existing */
- out32r(MPC107_I2CCR, 0x80);
- return -1;
- }
-
- /* Data address */
- out32r(MPC107_I2CDR, offset);
-
- if (mpc107_i2c_wait(timeout) < 0)
- {
- printf("mpc107_i2c_read Error 2\n");
- return -3;
- }
-
- /* Switch to read - restart */
- out32r(MPC107_I2CCR, 0xB4);
- out32r(MPC107_I2CDR, (0xA1 | device | block));
-
- if (mpc107_i2c_wait(timeout) < 0)
- {
- printf("mpc107_i2c_read Error 3\n");
- return -4;
- }
-
- out32r(MPC107_I2CCR, 0xA8); /* no ACK */
- in32r(MPC107_I2CDR);
-
- if (mpc107_i2c_wait(timeout) < 0)
- {
- printf("mpc107_i2c_read Error 4\n");
- return -5;
- }
- /* Generate STOP condition */
- out32r(MPC107_I2CCR, 0x88);
-
- /* read */
- data = in32r(MPC107_I2CDR);
-
- return (data);
-}
-
-/*----------------------------------------------------------------------------*/
-
-int mpc107_i2c_write_byte (
- unsigned char device,
- unsigned char block,
- unsigned char offset,
- unsigned char val )
-{
-
- unsigned long timeout = MPC107_I2C_TIMEOUT;
-
- if (!mpc107_eumb_addr)
- return -6;
-
- mpc107_i2c_wait_idle(timeout);
-
- /* Start with MEN */
- out32r(MPC107_I2CCR, 0x80);
-
- /* Start as master */
- out32r(MPC107_I2CCR, 0xB0);
- out32r(MPC107_I2CDR, (0xA0 | device | block));
-
- if (mpc107_i2c_wait(timeout) < 0)
- {
- printf("mpc107_i2c_write Error 1\n");
- return -1;
- }
-
- /* Data address */
- out32r(MPC107_I2CDR, offset);
-
- if (mpc107_i2c_wait(timeout) < 0)
- {
- printf("mpc107_i2c_write Error 2\n");
- return -1;
- }
-
- /* Write */
- out32r(MPC107_I2CDR, val);
- if (mpc107_i2c_wait(timeout) < 0)
- {
- printf("mpc107_i2c_write Error 3\n");
- return -1;
- }
-
- /* Generate Stop Condition */
- out32r(MPC107_I2CCR, 0x80);
-
- /* Return ACK or no ACK */
- return (in32r(MPC107_I2CSR) & 0x01);
-}
-
-/*----------------------------------------------------------------------------*/
-
-int mpc107_srom_load (
- unsigned char addr,
- unsigned char *pBuf,
- int cnt,
- unsigned char device,
- unsigned char block )
-{
- register int i;
- int val;
- int timeout;
-
- for (i = 0; i < cnt; i++)
- {
- timeout=100;
- do
- {
- val = mpc107_i2c_read_byte (device, block, addr);
- if (val < -1)
- {
- printf("i2c_read_error %d at dev %x block %x addr %x\n",
- val, device, block, addr);
- return -1;
- }
- else if (timeout==0)
- {
- printf ("i2c_read_error: timeout at dev %x block %x addr %x\n",
- device, block, addr);
- return -1;
- }
- timeout--;
- } while (val == -1); /* if no ack: try again! */
-
- *pBuf++ = (unsigned char)val;
- addr++;
-
- if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */
- {
- if (block == FIRST_BLOCK)
- block = SECOND_BLOCK;
- else
- {
- printf ("ic2_read_error: read beyond 2. block !\n");
- return -1;
- }
- }
- }
- udelay(100000);
- return (cnt);
-}
-
-/*----------------------------------------------------------------------------*/
-
-int mpc107_srom_store (
- unsigned char addr,
- unsigned char *pBuf,
- int cnt,
- unsigned char device,
- unsigned char block )
-{
- register int i;
-
- for (i = 0; i < cnt; i++)
- {
- while (mpc107_i2c_write_byte (device,block,addr,*pBuf) == 1);
- addr++;
- pBuf++;
-
- if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */
- {
- if (block == FIRST_BLOCK)
- block = SECOND_BLOCK;
- else
- {
- printf ("ic2_write_error: write beyond 2. block !\n");
- return -1;
- }
- }
- }
- udelay(100000);
- return(cnt);
-}
-
-/*----------------------------------------------------------------------------*/
-
-int mpc107_i2c_init ( unsigned long eumb_addr, unsigned long divider )
-{
- unsigned long x;
-
- if (eumb_addr)
- mpc107_eumb_addr = eumb_addr;
- else
- return -1;
-
- /* Set I2C clock */
- x = in32r(MPC107_I2CFDR) & 0xffffff00;
- out32r(MPC107_I2CFDR, (x | divider));
-
- /* Clear arbitration */
- out32r(MPC107_I2CSR, 0);
-
- return mpc107_eumb_addr;
-}
-
-/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c
deleted file mode 100644
index d81a41a..0000000
--- a/board/eltec/elppc/pci.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * PCI initialisation for the MPC10x.
- */
-
-#include <common.h>
-#include <pci.h>
-#include <mpc106.h>
-
-#ifdef CONFIG_PCI
-
-struct pci_controller local_hose;
-
-void pci_init_board(void)
-{
- struct pci_controller* hose = (struct pci_controller *)&local_hose;
- u16 reg16;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI_MEM_BUS,
- CONFIG_SYS_PCI_MEM_PHYS,
- CONFIG_SYS_PCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* ISA/PCI memory space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_ISA_MEM_BUS,
- CONFIG_SYS_ISA_MEM_PHYS,
- CONFIG_SYS_ISA_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + 3,
- CONFIG_SYS_PCI_IO_BUS,
- CONFIG_SYS_PCI_IO_PHYS,
- CONFIG_SYS_PCI_IO_SIZE,
- PCI_REGION_IO);
-
- /* ISA/PCI I/O space */
- pci_set_region(hose->regions + 4,
- CONFIG_SYS_ISA_IO_BUS,
- CONFIG_SYS_ISA_IO_PHYS,
- CONFIG_SYS_ISA_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 5;
-
- pci_setup_indirect(hose,
- MPC106_REG_ADDR,
- MPC106_REG_DATA);
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-
- /* Initialises the MPC10x PCI Configuration regs. */
- pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
- /* Clear non-reserved bits in status register */
- pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
-}
-
-#endif /* CONFIG_PCI */
diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h
deleted file mode 100644
index 662daf8..0000000
--- a/board/eltec/elppc/srom.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* common srom defs */
-#define FIRST_DEVICE 0x00
-#define SECOND_DEVICE 0x04
-#define FIRST_BLOCK 0x00
-#define SECOND_BLOCK 0x02
-#define BLOCK_SIZE 0x100
-#define ERROR (-1)
-
-#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100
-#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100
-
-#define CPU_TYPE_740 0x08
-#define CPU_TYPE_750 0x08
-#define CPU_TYPE ((get_pvr()>>16)&0xffff)
-
-#define ABS(x) ((x<0)?-x:x)
-#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
-
-/* bab7xx ELTEC srom */
-#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220)
-#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221)
-
-/* srom at mpc107 */
-#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */
-#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */
-#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */
-#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */
-#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */
-#define MPC107_I2C_TIMEOUT 10000000
-
-/* i82559 */
-#define EE_ADDR_BITS 6
-#define EE_SIZE 0x40 /* 0x40 words */
-#define EE_CHECKSUM 0xBABA
-
-/* dc21143 */
-#define DEC_SROM_SIZE 128
-
-
-/*
- * structure of revision srom
- */
-typedef struct {
- char magic[8]; /* 000 - Magic number */
- char revrev[2]; /* 008 - Revision of structure */
- unsigned short size; /* 00A - Size of CRC area */
- unsigned long crc; /* 00C - CRC */
- char board[16]; /* 010 - Board Revision information */
- char option[4][16]; /* 020 - Option Revision information */
- char serial[8]; /* 060 - Board serial number */
- char etheraddr[6]; /* 068 - Ethernet node addresse */
- char reserved[2]; /* 06E - Reserved */
- char revision[7][2]; /* 070 - Revision codes */
- char category[2]; /* 07E - Category codes */
- char text[64]; /* 080 - Text field */
- char res[64]; /* 0C0 - Reserved */
-} revinfo;
-
-unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size);
-int el_srom_load (unsigned char addr, unsigned char *buf, int cnt,
- unsigned char device, unsigned char block);
-int el_srom_store (unsigned char addr, unsigned char *buf, int cnt,
- unsigned char device, unsigned char block);
-
-int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider);
-int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset);
-int mpc107_i2c_write_byte (unsigned char device, unsigned char block,
- unsigned char offset, unsigned char val);
-int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt,
- unsigned char device, unsigned char block);
-int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt,
- unsigned char device, unsigned char block);
-
-int dc_srom_load (unsigned short *dest);
-int dc_srom_store (unsigned short *src);
-
-unsigned short eepro100_srom_checksum (unsigned short *sromdata);
-void eepro100_srom_load (unsigned short *destination);
-int eepro100_srom_store (unsigned short *source);
diff --git a/board/esd/apc405/Kconfig b/board/esd/apc405/Kconfig
deleted file mode 100644
index 6b03460..0000000
--- a/board/esd/apc405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_APC405
-
-config SYS_BOARD
- default "apc405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "APC405"
-
-endif
diff --git a/board/esd/apc405/MAINTAINERS b/board/esd/apc405/MAINTAINERS
deleted file mode 100644
index 7f2a33f..0000000
--- a/board/esd/apc405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-APC405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/apc405/
-F: include/configs/APC405.h
-F: configs/APC405_defconfig
diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile
deleted file mode 100644
index ada8bfd..0000000
--- a/board/esd/apc405/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = apc405.o \
- ../common/misc.o \
- ../common/auto_update.o
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
deleted file mode 100644
index 5cc1d0d..0000000
--- a/board/esd/apc405/apc405.c
+++ /dev/null
@@ -1,461 +0,0 @@
-/*
- * (C) Copyright 2005-2008
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <flash.h>
-#include <mtd/cfi_flash.h>
-#include <asm/4xx_pci.h>
-#include <pci.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef FPGA_DEBUG
-
-extern void lxt971_no_sleep(void);
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-#ifdef CONFIG_LCD_USED
-/* logo bitmap data - gzip compressed and generated by bin2c */
-unsigned char logo_bmp[] =
-{
-#include "logo_640_480_24bpp.c"
-};
-
-/*
- * include common lcd code (for esd boards)
- */
-#include "../common/lcd.c"
-#include "../common/s1d13505_640_480_16bpp.h"
-#include "../common/s1d13806_640_480_16bpp.h"
-#endif /* CONFIG_LCD_USED */
-
-/*
- * include common auto-update code (for esd boards)
- */
-#include "../common/auto_update.h"
-
-au_image_t au_image[] = {
- {"preinst.img", 0, -1, AU_SCRIPT},
- {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
- {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
- {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
- {"work.img", 0xfe500000, 0x01400000, AU_NOR},
- {"data.img", 0xff900000, 0x00580000, AU_NOR},
- {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
- {"postinst.img", 0, 0, AU_SCRIPT},
-};
-
-int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
-int board_revision(void)
-{
- unsigned long CPC0_CR0Reg;
- unsigned long value;
-
- /*
- * Get version of APC405 board from GPIO's
- */
-
- /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
- out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
-
- /* wait some time before reading input */
- udelay(1000);
-
- /* get config bits */
- value = in_be32((void*)GPIO0_IR) & 0x001c0000;
- /*
- * Restore GPIO settings
- */
- mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
- switch (value) {
- case 0x001c0000:
- /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
- return 2;
- case 0x000c0000:
- /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
- return 3;
- case 0x00180000:
- /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
- return 6;
- case 0x00140000:
- /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
- return 8;
- default:
- /* should not be reached! */
- return 0;
- }
-}
-
-int board_early_init_f (void)
-{
- /*
- * First pull fpga-prg pin low, to disable fpga logic
- */
- out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
- out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
- out_be32((void*)GPIO0_OR, 0); /* pull prg low */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks
- */
- mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- /*
- * New boards have a single 32MB flash connected to CS0
- * instead of two 16MB flashes on CS0+1.
- */
- if (board_revision() >= 8) {
- /* disable CS1 */
- mtebc(PB1AP, 0);
- mtebc(PB1CR, 0);
-
- /* resize CS0 to 32MB */
- mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
- mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
- }
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- if (gd->board_type >= 8)
- cfi_flash_num_flash_banks = 1;
-
- return 0;
-}
-
-#define FUJI_BASE 0xf0100200
-#define LCDBL_PWM 0xa0
-#define LCDBL_PWMMIN 0xa4
-#define LCDBL_PWMMAX 0xa8
-
-int misc_init_r(void)
-{
- u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
- u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
- u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
- u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
- unsigned long CPC0_CR0Reg;
- char *str;
- uchar *logo_addr;
- ulong logo_size;
- ushort minb, maxb;
- int result;
-
- /*
- * Setup GPIO pins (CS6+CS7 as GPIO)
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf("GUNZIP ERROR - must RESET board to recover\n");
- do_reset(NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: "
- "INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: "
- "INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: "
- "DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len + 3;
- }
- putc('\n');
- /* delayed reboot */
- for (i = 20; i > 0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index = 0; index < 1000; index++)
- udelay(1000);
- }
- putc('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- /* restore gpio/cs settings */
- mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index + 1]));
- index += len + 3;
- }
- putc('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-
- /*
- * Write board revision in FPGA
- */
- out_be16(fpga_ctrl2,
- (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
-
- /*
- * Enable power on PS/2 interface (with reset)
- */
- out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
- for (i=0;i<100;i++)
- udelay(1000);
- udelay(1000);
- out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- out_8(duart0_mcr, 0x08);
- out_8(duart1_mcr, 0x08);
-
- /*
- * Init lcd interface and display logo
- */
- str = getenv("splashimage");
- if (str) {
- logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
- logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
- } else {
- logo_addr = logo_bmp;
- logo_size = sizeof(logo_bmp);
- }
-
- if (gd->board_type >= 6) {
- result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
- (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13505_640_480_16bpp,
- sizeof(regs_13505_640_480_16bpp) /
- sizeof(regs_13505_640_480_16bpp[0]),
- logo_addr, logo_size);
- if (result && str) {
- /* retry with internal image */
- logo_addr = logo_bmp;
- logo_size = sizeof(logo_bmp);
- lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
- (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13505_640_480_16bpp,
- sizeof(regs_13505_640_480_16bpp) /
- sizeof(regs_13505_640_480_16bpp[0]),
- logo_addr, logo_size);
- }
- } else {
- result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
- (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13806_640_480_16bpp,
- sizeof(regs_13806_640_480_16bpp) /
- sizeof(regs_13806_640_480_16bpp[0]),
- logo_addr, logo_size);
- if (result && str) {
- /* retry with internal image */
- logo_addr = logo_bmp;
- logo_size = sizeof(logo_bmp);
- lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
- (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13806_640_480_16bpp,
- sizeof(regs_13806_640_480_16bpp) /
- sizeof(regs_13806_640_480_16bpp[0]),
- logo_addr, logo_size);
- }
- }
-
- /*
- * Reset microcontroller and setup backlight PWM controller
- */
- out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
- for (i=0;i<10;i++)
- udelay(1000);
- out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
-
- minb = 0;
- maxb = 0xff;
- str = getenv("lcdbl");
- if (str) {
- minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
- if (str && (*str=',')) {
- str++;
- maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
- } else
- minb = 0;
-
- out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
- out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
-
- printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
- }
- out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
-
- /*
- * fix environment for field updated units
- */
- if (getenv("altbootcmd") == NULL) {
- setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
- setenv("usbargs", CONFIG_SYS_USB_ARGS);
- setenv("bootcmd", CONFIG_BOOTCOMMAND);
- setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
- setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
- setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
- saveenv();
- }
-
- return (0);
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming APC405");
- } else {
- puts(str);
- }
-
- gd->board_type = board_revision();
- printf(", Rev. 1.%ld\n", gd->board_type);
-
- return 0;
-}
-
-#ifdef CONFIG_IDE_RESET
-void ide_set_reset(int on)
-{
- u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
-
- /*
- * Assert or deassert CompactFlash Reset Pin
- */
- if (on) {
- out_be16(fpga_mode,
- in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
- } else {
- out_be16(fpga_mode,
- in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
- }
-}
-#endif /* CONFIG_IDE_RESET */
-
-void reset_phy(void)
-{
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-}
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int board_usb_init(int index, enum usb_init_type init)
-{
- return 0;
-}
-
-int usb_board_stop(void)
-{
- unsigned short tmp;
- int i;
-
- /*
- * reset PCI bus
- * This is required to make some very old Linux OHCI driver
- * work after U-Boot has used the OHCI controller.
- */
- pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
- pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
-
- for (i = 0; i < 100; i++)
- udelay(1000);
-
- pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return usb_board_stop();
-}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
diff --git a/board/esd/apc405/fpgadata.c b/board/esd/apc405/fpgadata.c
deleted file mode 100644
index b68668c..0000000
--- a/board/esd/apc405/fpgadata.c
+++ /dev/null
@@ -1,4008 +0,0 @@
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diff --git a/board/esd/apc405/logo_640_480_24bpp.c b/board/esd/apc405/logo_640_480_24bpp.c
deleted file mode 100644
index a218032..0000000
--- a/board/esd/apc405/logo_640_480_24bpp.c
+++ /dev/null
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-0xb1, 0xff, 0x36, 0x90, 0x33, 0x16, 0x8e, 0xd3,
-0x76, 0x91, 0xd8, 0x7f, 0x1b, 0x2c, 0xa0, 0x58,
-0xa5, 0x1d, 0xf6, 0x13, 0xb7, 0x5c, 0x5b, 0x4f,
-0xb1, 0xef, 0xf7, 0x4c, 0x1c, 0x21, 0xb5, 0x33,
-0xe6, 0xfa, 0xc9, 0xa1, 0x74, 0xf1, 0xd0, 0x23,
-0xd3, 0x85, 0xf7, 0xbf, 0xf2, 0xfe, 0x1f, 0xe4,
-0x26, 0xfe, 0xc1, 0xe9, 0x6d, 0xb1, 0x15, 0x75,
-0x17, 0x9b, 0x6f, 0xff, 0x29, 0xfd, 0xb7, 0x9e,
-0xab, 0x73, 0x7e, 0x21, 0x49, 0x15, 0x6e, 0x7d,
-0x6a, 0x64, 0xb8, 0xd7, 0x9c, 0xa3, 0x7f, 0xa0,
-0x35, 0x72, 0x4a, 0x24, 0x8e, 0x0f, 0x35, 0x24,
-0xac, 0x6c, 0x3f, 0x38, 0xfe, 0x71, 0x2b, 0x3a,
-0xb5, 0x38, 0x67, 0xa3, 0xe1, 0xc6, 0x33, 0x15,
-0x8e, 0xfb, 0xbe, 0xec, 0x7f, 0xba, 0xbb, 0x32,
-0x0a, 0xd8, 0x96, 0xf4, 0xf8, 0xb7, 0xb6, 0x9e,
-0x18, 0x7e, 0x9e, 0x32, 0xdd, 0xa2, 0x07, 0x5f,
-0x45, 0x7b, 0x7e, 0xec, 0xc0, 0x40, 0x45, 0x97,
-0x49, 0xc0, 0xad, 0xb3, 0x26, 0x2a, 0xa6, 0x64,
-0x10, 0xdc, 0xbb, 0xeb, 0xd8, 0x7b, 0x0d, 0x99,
-0x7d, 0xf4, 0x7f, 0x33, 0xb1, 0x4d, 0x25, 0x38,
-0xbc, 0xab, 0x7f, 0xbe, 0xfe, 0x6b, 0x8d, 0x6b,
-0xcb, 0x64, 0xad, 0xff, 0x32, 0xfa, 0x4f, 0xa3,
-0x17, 0x2e, 0x28, 0x35, 0x38, 0x77, 0xfa, 0xe8,
-0x33, 0xfd, 0x55, 0x5d, 0xa2, 0xba, 0x78, 0x43,
-0x16, 0xf9, 0xb7, 0x58, 0x6d, 0x60, 0xdf, 0x5b,
-0x33, 0xbf, 0x17, 0x5a, 0xed, 0x75, 0xf8, 0xd9,
-0xc8, 0xd1, 0xf5, 0x24, 0xc4, 0xff, 0xc7, 0xc3,
-0x13, 0xbe, 0x51, 0x31, 0x79, 0x97, 0x65, 0xc4,
-0xc2, 0x43, 0x7e, 0xea, 0x96, 0x6b, 0x6c, 0x1d,
-0x97, 0xa7, 0xe5, 0xcf, 0x24, 0x4b, 0x0a, 0xb1,
-0x38, 0x33, 0x76, 0x60, 0x30, 0xfa, 0x39, 0x8a,
-0xe8, 0x59, 0xbc, 0xb8, 0xb0, 0x58, 0xb5, 0x7f,
-0x68, 0xe4, 0xf4, 0x5c, 0x5d, 0xc8, 0x4e, 0xbf,
-0x6d, 0x78, 0xdf, 0x79, 0x66, 0xdb, 0xc0, 0xb6,
-0x6d, 0xd1, 0xb6, 0xc1, 0x8f, 0xc1, 0x94, 0xfd,
-0x77, 0x7a, 0xdb, 0x7a, 0x62, 0xc8, 0x59, 0x90,
-0xa0, 0x23, 0x91, 0xed, 0x96, 0x92, 0xb0, 0x96,
-0x10, 0x37, 0x17, 0x66, 0x4e, 0xbf, 0x35, 0xf2,
-0xea, 0x91, 0x91, 0x23, 0xaf, 0xbe, 0xf2, 0xfa,
-0xc9, 0x73, 0x17, 0xaf, 0xdf, 0x16, 0x2d, 0x3d,
-0x2d, 0x55, 0xb4, 0xca, 0xd9, 0x21, 0x4f, 0xdc,
-0x45, 0xae, 0x7e, 0xec, 0x3f, 0xfd, 0x2e, 0xa6,
-0xee, 0xa2, 0x80, 0xf4, 0xc7, 0xc0, 0x8f, 0x8f,
-0xf9, 0x8a, 0xbe, 0xb1, 0x63, 0x3d, 0xc5, 0xf4,
-0x72, 0xc1, 0x93, 0x08, 0xda, 0xfe, 0x50, 0xa5,
-0xd4, 0xbc, 0x7d, 0xfd, 0xe2, 0xb9, 0x93, 0x47,
-0x47, 0x74, 0x29, 0x1d, 0x79, 0xf5, 0x57, 0xef,
-0xfe, 0x76, 0xe1, 0xc6, 0xb2, 0x68, 0xe9, 0x39,
-0x3f, 0xb1, 0x29, 0xc7, 0xbc, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x4f, 0xc5,
-0xff, 0x02, 0x04, 0xc4, 0x15, 0x0c, 0x36, 0xb4,
-0x04, 0x00,
diff --git a/board/esd/ar405/Kconfig b/board/esd/ar405/Kconfig
deleted file mode 100644
index 4ad9d51..0000000
--- a/board/esd/ar405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_AR405
-
-config SYS_BOARD
- default "ar405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "AR405"
-
-endif
diff --git a/board/esd/ar405/MAINTAINERS b/board/esd/ar405/MAINTAINERS
deleted file mode 100644
index be74ff7..0000000
--- a/board/esd/ar405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-AR405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/ar405/
-F: include/configs/AR405.h
-F: configs/AR405_defconfig
diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile
deleted file mode 100644
index dd54f54..0000000
--- a/board/esd/ar405/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = ar405.o flash.o ../common/misc.o
diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c
deleted file mode 100644
index d33aba4..0000000
--- a/board/esd/ar405/ar405.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include "ar405.h"
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-/* ------------------------------------------------------------------------- */
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* fpga configuration data - generated by bin2cc */
-const unsigned char fpgadata[] = {
-#include "fpgadata.c"
-};
-
-const unsigned char fpgadata_xl30[] = {
-#include "fpgadata_xl30.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-int board_early_init_f (void)
-{
- int index, len, i;
- int status;
-
-#ifdef FPGA_DEBUG
- /* set up serial port with default baudrate */
- (void) get_clocks ();
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init ();
- console_init_f ();
-#endif
-
- /*
- * Boot onboard FPGA
- */
- /* first try 40er image */
- gd->board_type = 40;
- status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
- if (status != 0) {
- /* try xl30er image */
- gd->board_type = 30;
- status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
- if (status != 0) {
- /* booting FPGA failed */
-#ifndef FPGA_DEBUG
- /* set up serial port with default baudrate */
- (void) get_clocks ();
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init ();
- console_init_f ();
-#endif
- printf ("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf ("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpgadata[index];
- printf ("FPGA: %s\n", &(fpgadata[index + 1]));
- index += len + 3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i = 20; i > 0; i--) {
- printf ("Rebooting in %2d seconds \r", i);
- for (index = 0; index < 1000; index++)
- udelay (1000);
- }
- putc ('\n');
- do_reset (NULL, 0, 0, NULL);
- }
- }
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- int index;
- int len;
- char str[64];
- int i = getenv_f("serial#", str, sizeof (str));
- const unsigned char *fpga;
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming AR405");
- } else {
- puts(str);
- }
-
- puts ("\nFPGA: ");
-
- /* display infos on fpgaimage */
- if (gd->board_type == 30) {
- fpga = fpgadata_xl30;
- } else {
- fpga = fpgadata;
- }
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpga[index];
- printf ("%s ", &(fpga[index + 1]));
- index += len + 3;
- }
-
- putc ('\n');
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
- return 0;
-}
-
-
-#if 1 /* test-only: some internal test routines... */
-#define DIGEN ((void *)0xf03000b4) /* u8 */
-#define DIGOUT ((void *)0xf03000b0) /* u16 */
-#define DIGIN ((void *)0xf03000a0) /* u16 */
-
-/*
- * Some test routines
- */
-int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
- int k;
- int start;
- int end;
-
- if (argc != 3) {
- puts("Usage: digtest n_start n_end (digtest 0 7)\n");
- return 0;
- }
-
- start = simple_strtol (argv[1], NULL, 10);
- end = simple_strtol (argv[2], NULL, 10);
-
- /*
- * Enable digital outputs
- */
- out_8(DIGEN, 0x08);
-
- printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
- start, end);
-
- /*
- * Set outputs one by one
- */
- for (;;) {
- for (i=start; i<=end; i++) {
- out_be16(DIGOUT, 0x0001 << i);
- for (k=0; k<200; k++)
- udelay(1000);
-
- if (in_be16(DIGIN) != (0x0001 << i)) {
- printf("ERROR: OUT=0x%04X, IN=0x%04X\n",
- 0x0001 << i, in_be16(DIGIN));
- return 0;
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
- }
- }
-
- return 0;
-}
-U_BOOT_CMD(
- digtest, 3, 1, do_digtest,
- "Test digital in-/output",
- ""
-);
-
-#define ERROR_DELTA 256
-
-struct io {
- short val;
- short dummy;
-};
-
-int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- short val;
- int i;
- int volt;
- struct io *out;
- struct io *in;
-
- out = (struct io *)0xf0300090;
- in = (struct io *)0xf0300000;
-
- i = simple_strtol (argv[1], NULL, 10);
-
- volt = 0;
- printf("Setting Channel %d to %dV...\n", i, volt);
- out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
- udelay(10000);
- val = in_be16((void *)&(in[i*2].val));
- printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
- if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
- (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
- printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
- ((volt * 0x7fff) / 40) + ERROR_DELTA);
- return -1;
- }
- val = in_be16((void *)&(in[i*2+1].val));
- printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
- if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
- (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
- printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
- ((volt * 0x7fff) / 40) + ERROR_DELTA);
- return -1;
- }
-
- volt = 5;
- printf("Setting Channel %d to %dV...\n", i, volt);
- out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
- udelay(10000);
- val = in_be16((void *)&(in[i*2].val));
- printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
- if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
- (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
- printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
- ((volt * 0x7fff) / 40) + ERROR_DELTA);
- return -1;
- }
- val = in_be16((void *)&(in[i*2+1].val));
- printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
- if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
- (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
- printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
- ((volt * 0x7fff) / 40) + ERROR_DELTA);
- return -1;
- }
-
- volt = 10;
- printf("Setting Channel %d to %dV...\n", i, volt);
- out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
- udelay(10000);
- val = in_be16((void *)&(in[i*2].val));
- printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
- if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
- (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
- printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
- ((volt * 0x7fff) / 40) + ERROR_DELTA);
- return -1;
- }
- val = in_be16((void *)&(in[i*2+1].val));
- printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
- if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
- (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
- printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
- ((volt * 0x7fff) / 40) + ERROR_DELTA);
- return -1;
- }
-
- printf("Channel %d OK!\n", i);
-
- return 0;
-}
-U_BOOT_CMD(
- anatest, 2, 1, do_anatest,
- "Test analog in-/output",
- ""
-);
-
-
-int counter = 0;
-
-void cyclicInt(void *ptr)
-{
- out_be16((void *)0xf03000e8, 0x0800); /* ack int */
- counter++;
-}
-
-
-int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong *incin;
- int i;
-
- incin = (ulong *)0xf0300040;
-
- /*
- * Clear inc counter
- */
- out_be32((void *)&incin[0], 0);
- out_be32((void *)&incin[1], 0);
- out_be32((void *)&incin[2], 0);
- out_be32((void *)&incin[3], 0);
-
- incin = (ulong *)0xf0300050;
-
- /*
- * Inc a little
- */
- for (i=0; i<10000; i++) {
- switch (i & 0x03) {
- case 0:
- out_8(DIGEN, 0x02);
- break;
- case 1:
- out_8(DIGEN, 0x03);
- break;
- case 2:
- out_8(DIGEN, 0x01);
- break;
- case 3:
- out_8(DIGEN, 0x00);
- break;
- }
- udelay(10);
- }
-
- printf("Inc 0 = %d\n", in_be32((void *)&incin[0]));
- printf("Inc 1 = %d\n", in_be32((void *)&incin[1]));
- printf("Inc 2 = %d\n", in_be32((void *)&incin[2]));
- printf("Inc 3 = %d\n", in_be32((void *)&incin[3]));
-
- out_be16((void *)0xf03000e0, 0x0c80-1); /* set counter */
- out_be16((void *)0xf03000ec,
- in_be16((void *)0xf03000ec) | 0x0800); /* enable int */
- irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
- printf("counter=%d\n", counter);
-
- return 0;
-}
-U_BOOT_CMD(
- inctest, 3, 1, do_inctest,
- "Test incremental encoder inputs",
- ""
-);
-#endif
diff --git a/board/esd/ar405/ar405.h b/board/esd/ar405/ar405.h
deleted file mode 100644
index 75e7950..0000000
--- a/board/esd/ar405/ar405.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/ar405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/ar405/fpgadata.c b/board/esd/ar405/fpgadata.c
deleted file mode 100644
index 055ab6b..0000000
--- a/board/esd/ar405/fpgadata.c
+++ /dev/null
@@ -1,5500 +0,0 @@
-0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
-0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d,
-0x70, 0x70, 0x63, 0x5f, 0x61, 0x72, 0x30, 0x31,
-0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b,
-0x73, 0x34, 0x30, 0x78, 0x6c, 0x70, 0x71, 0x32,
-0x34, 0x30, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30,
-0x30, 0x31, 0x2f, 0x30, 0x32, 0x2f, 0x31, 0x34,
-0x00, 0x64, 0x00, 0x09, 0x31, 0x35, 0x3a, 0x34,
-0x30, 0x3a, 0x30, 0x34, 0x00, 0x65, 0xe2, 0x01,
-0x00, 0x00, 0xab, 0x8e, 0xff, 0x30, 0xe5, 0xe5,
-0xe8, 0xe5, 0x03, 0xe8, 0x04, 0x01, 0x02, 0x11,
-0x09, 0x09, 0x01, 0x07, 0x02, 0x04, 0x04, 0x06,
-0x09, 0x07, 0x04, 0x04, 0x04, 0x04, 0x03, 0x07,
-0x02, 0x04, 0x09, 0x04, 0x04, 0x0b, 0x09, 0x09,
-0x03, 0x07, 0x02, 0x09, 0x04, 0x04, 0x04, 0x04,
-0x0e, 0x04, 0x04, 0x09, 0x03, 0x07, 0x02, 0x04,
-0x03, 0x03, 0x03, 0x07, 0xe5, 0x01, 0x0d, 0x02,
-0x02, 0x03, 0x02, 0x02, 0x03, 0x02, 0x02, 0x03,
-0x19, 0x03, 0x02, 0x02, 0x03, 0x02, 0x08, 0x09,
-0x07, 0x13, 0x03, 0x11, 0x02, 0x06, 0x03, 0x05,
-0x03, 0x05, 0x11, 0x1d, 0x1f, 0x13, 0x10, 0x01,
-0x01, 0xe3, 0x4c, 0xe5, 0x01, 0x0a, 0x04, 0x01,
-0xe5, 0x05, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x05,
-0x09, 0x04, 0x04, 0x02, 0x06, 0x01, 0xe5, 0x05,
-0x01, 0x02, 0x04, 0x04, 0x04, 0x09, 0x09, 0x09,
-0x09, 0x04, 0x06, 0x01, 0x07, 0x09, 0x04, 0x04,
-0x09, 0x06, 0x02, 0x09, 0x09, 0x04, 0x01, 0xe7,
-0x03, 0x04, 0x07, 0xe6, 0x08, 0x09, 0x09, 0x0e,
-0x01, 0xe6, 0x13, 0x09, 0x09, 0x09, 0x03, 0x05,
-0x03, 0x05, 0x09, 0x09, 0x09, 0x09, 0xe5, 0x07,
-0x03, 0x05, 0xe5, 0x07, 0xe5, 0x01, 0x05, 0x0b,
-0xe5, 0x07, 0xe5, 0x07, 0x09, 0x03, 0x05, 0xe6,
-0xe5, 0x04, 0xe5, 0x01, 0x05, 0xe5, 0x01, 0x05,
-0xe5, 0xe6, 0x04, 0x03, 0x05, 0xe5, 0xe6, 0x04,
-0xe5, 0x07, 0x03, 0x05, 0xe5, 0x07, 0x0b, 0x01,
-0x0e, 0x05, 0x03, 0x05, 0x03, 0x05, 0x1d, 0x03,
-0x05, 0x03, 0x44, 0xe5, 0xe5, 0x2e, 0x1c, 0x01,
-0x13, 0x32, 0x01, 0xe3, 0x4d, 0xe5, 0x0f, 0x09,
-0x09, 0x27, 0x09, 0x42, 0x04, 0x4a, 0x44, 0x01,
-0x01, 0x01, 0x12, 0x09, 0x09, 0x01, 0x06, 0x01,
-0x12, 0x09, 0x0a, 0x09, 0x11, 0x21, 0x13, 0x11,
-0x15, 0x1d, 0x1b, 0x0c, 0x0d, 0x03, 0x03, 0x01,
-0x31, 0x31, 0x47, 0x81, 0xe5, 0xe5, 0xe5, 0x77,
-0x3e, 0xe5, 0x19, 0xe5, 0x1b, 0x3b, 0xe5, 0xe5,
-0x5a, 0x3d, 0x1f, 0x74, 0xe6, 0xe5, 0x28, 0x5b,
-0x09, 0xe5, 0x0a, 0x08, 0xe5, 0x08, 0x1d, 0x11,
-0xe6, 0x37, 0x12, 0x01, 0x01, 0x09, 0x06, 0x09,
-0x09, 0x09, 0xe5, 0x07, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x01, 0x03, 0x03, 0x03, 0x05,
-0x05, 0x05, 0x09, 0x09, 0x09, 0x09, 0x09, 0xe5,
-0x07, 0x09, 0x09, 0x09, 0x05, 0x03, 0x09, 0x09,
-0x09, 0x10, 0xe5, 0x0f, 0x09, 0x09, 0x04, 0x04,
-0x09, 0x09, 0x05, 0x03, 0x05, 0x03, 0x01, 0x07,
-0x09, 0x09, 0x09, 0x09, 0x07, 0x01, 0x07, 0xe5,
-0x01, 0x07, 0x01, 0x06, 0x02, 0x09, 0x05, 0x03,
-0x06, 0x02, 0x09, 0x05, 0x01, 0x01, 0x01, 0x07,
-0x05, 0x03, 0x09, 0x09, 0x09, 0x04, 0x04, 0x0e,
-0x01, 0xe5, 0x02, 0x09, 0xe5, 0x07, 0xe5, 0x01,
-0x05, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x03, 0x03, 0xe5, 0x01,
-0x01, 0x03, 0xe5, 0x01, 0x05, 0xe5, 0x07, 0xe5,
-0xe5, 0x05, 0x09, 0x09, 0x01, 0x02, 0x06, 0x04,
-0x04, 0x09, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
-0x09, 0xe5, 0x07, 0x09, 0xe5, 0x02, 0x04, 0xe5,
-0x01, 0x05, 0x09, 0x09, 0xe5, 0x07, 0xe5, 0x04,
-0x0b, 0x01, 0x10, 0x09, 0x09, 0x09, 0x09, 0x05,
-0x03, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x06,
-0x02, 0x06, 0x02, 0x06, 0xe6, 0x01, 0x06, 0x02,
-0x06, 0x02, 0x09, 0x09, 0x03, 0x02, 0x02, 0x09,
-0x06, 0x02, 0x09, 0x09, 0x06, 0x02, 0x06, 0x02,
-0x09, 0x09, 0x0d, 0x02, 0xe5, 0x02, 0x01, 0xe5,
-0x05, 0xe5, 0x07, 0xe5, 0x04, 0x02, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x03, 0x03, 0xe5,
-0x03, 0x03, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x02, 0x04, 0xe5, 0x03, 0x03, 0x05, 0x03,
-0x0b, 0x04, 0xe5, 0x02, 0x06, 0x02, 0x09, 0xe5,
-0x07, 0xe5, 0x01, 0x05, 0x05, 0x03, 0xe5, 0x03,
-0x03, 0x05, 0x03, 0xe5, 0x07, 0xe5, 0x07, 0x09,
-0x09, 0xe5, 0x07, 0xe5, 0x07, 0x02, 0x03, 0xe5,
-0xe6, 0x08, 0x05, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x0b, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0f, 0x01,
-0xe5, 0x05, 0x06, 0x09, 0x07, 0xe6, 0x08, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x05, 0x03,
-0x0a, 0x09, 0x08, 0x01, 0x03, 0x06, 0x08, 0x09,
-0x09, 0x0a, 0x08, 0x0a, 0x07, 0xe5, 0x08, 0x0a,
-0x09, 0x08, 0x09, 0x11, 0xe5, 0xe5, 0x01, 0x0a,
-0x02, 0x04, 0x01, 0x02, 0x06, 0x02, 0x06, 0x02,
-0x06, 0x02, 0x01, 0x04, 0x02, 0x03, 0x02, 0x02,
-0x06, 0x02, 0x05, 0xe5, 0x01, 0x05, 0xe5, 0x01,
-0x06, 0x02, 0x06, 0x02, 0x06, 0x02, 0x06, 0x02,
-0x08, 0x02, 0x05, 0xe5, 0x01, 0x06, 0x02, 0x05,
-0xe5, 0x01, 0x04, 0x01, 0x02, 0x06, 0x02, 0x06,
-0x02, 0x06, 0x02, 0x01, 0x04, 0x02, 0x06, 0x02,
-0x06, 0x02, 0x05, 0xe5, 0x01, 0x06, 0x02, 0x06,
-0x02, 0x08, 0x04, 0xe5, 0xe6, 0x02, 0x11, 0x04,
-0xe6, 0x24, 0x09, 0xe5, 0x2f, 0x06, 0xe5, 0xe5,
-0x05, 0x0e, 0x06, 0xe5, 0x10, 0x17, 0x09, 0x06,
-0x02, 0x45, 0x03, 0x02, 0xe5, 0x15, 0x0f, 0x13,
-0x27, 0x1e, 0x05, 0x02, 0x01, 0x01, 0x05, 0x08,
-0x3c, 0x06, 0x01, 0x45, 0x04, 0xe8, 0x11, 0x01,
-0xe5, 0x07, 0x15, 0x13, 0x23, 0x22, 0xe5, 0x04,
-0x01, 0x06, 0x2e, 0x13, 0x1d, 0x2d, 0xe5, 0xe6,
-0x18, 0x02, 0x0c, 0x17, 0x09, 0x31, 0x0d, 0xe5,
-0x0c, 0x31, 0xe7, 0x58, 0x04, 0xe5, 0xe6, 0x0f,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x01, 0x02,
-0xe5, 0x02, 0x09, 0x09, 0x05, 0x03, 0x05, 0x03,
-0xe5, 0x07, 0x09, 0x0b, 0x09, 0x09, 0x09, 0x01,
-0x03, 0x03, 0x07, 0x01, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x0f, 0xe6, 0x13, 0x1d,
-0x03, 0x01, 0x1a, 0x13, 0xe5, 0xe5, 0x0f, 0x01,
-0xe5, 0x07, 0xe5, 0x05, 0x01, 0xe5, 0x06, 0xe6,
-0xe5, 0x05, 0x02, 0x06, 0x01, 0xe5, 0x09, 0x12,
-0x09, 0x10, 0x0a, 0x01, 0x08, 0xe5, 0x0f, 0x01,
-0xe5, 0x17, 0xe5, 0xe5, 0x50, 0x01, 0x07, 0x09,
-0x01, 0x14, 0x05, 0x01, 0x08, 0x0a, 0x0a, 0x02,
-0x09, 0x0d, 0x0b, 0x14, 0x4e, 0xe5, 0x01, 0x3c,
-0x0b, 0x12, 0x34, 0x0b, 0x06, 0x01, 0x0e, 0x18,
-0x04, 0x04, 0x04, 0x0f, 0x27, 0x19, 0x02, 0xe5,
-0x05, 0x67, 0x09, 0x3d, 0x33, 0x07, 0x1d, 0x17,
-0x05, 0xe5, 0xe6, 0x05, 0x15, 0x5b, 0x35, 0x81,
-0xe6, 0x34, 0x01, 0x07, 0x1d, 0xe6, 0x06, 0x01,
-0x0b, 0x05, 0x01, 0x0b, 0x0b, 0x2d, 0x01, 0x07,
-0x0b, 0x05, 0x03, 0x11, 0xe6, 0x1a, 0x01, 0x03,
-0x17, 0xe5, 0x1a, 0x1c, 0x09, 0x24, 0x01, 0x11,
-0x01, 0x0e, 0x07, 0x15, 0x1b, 0x09, 0x03, 0x21,
-0x1c, 0x01, 0x18, 0x01, 0x01, 0x35, 0x20, 0x01,
-0x04, 0x01, 0x13, 0x0d, 0x0b, 0x12, 0x10, 0x02,
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-0x06, 0x2a, 0x0c, 0x02, 0x1a, 0x0a, 0x08, 0x13,
-0x09, 0x10, 0xe5, 0xe5, 0x0b, 0x03, 0xe5, 0x0e,
-0x07, 0x1e, 0x03, 0x01, 0x12, 0x0f, 0x02, 0x01,
-0x02, 0x17, 0x02, 0x01, 0x02, 0x11, 0x0d, 0x13,
-0xe5, 0x01, 0x27, 0xe5, 0x33, 0x07, 0x0d, 0x3b,
-0x02, 0x0b, 0x09, 0x0e, 0x03, 0x1c, 0x35, 0x01,
-0xe6, 0x64, 0x09, 0x2a, 0x03, 0x06, 0x01, 0x03,
-0x07, 0x02, 0x2b, 0x05, 0x20, 0xe6, 0x24, 0xe5,
-0xe5, 0x06, 0x43, 0x0e, 0x37, 0x01, 0x28, 0x23,
-0x27, 0x0c, 0x15, 0xe5, 0xe6, 0x68, 0x0c, 0x03,
-0x02, 0x13, 0x05, 0x02, 0x14, 0x01, 0x0b, 0x03,
-0x07, 0x08, 0x06, 0x16, 0x06, 0x36, 0xe5, 0xe6,
-0x60, 0x07, 0x13, 0x02, 0x10, 0x0d, 0x11, 0x02,
-0x20, 0x10, 0x01, 0x0c, 0x01, 0x02, 0x34, 0xe7,
-0x09, 0x06, 0x58, 0x10, 0x01, 0x11, 0x01, 0x1f,
-0x04, 0x08, 0x17, 0x18, 0x04, 0x2c, 0x0b, 0x03,
-0xe6, 0x6e, 0x37, 0x0f, 0x02, 0x03, 0xe5, 0xe5,
-0x04, 0xe5, 0x06, 0x01, 0xe5, 0x03, 0xe5, 0xe6,
-0x05, 0x08, 0xe6, 0x03, 0x05, 0xe5, 0x07, 0xe5,
-0x05, 0x1e, 0xe7, 0xe6, 0x01, 0x01, 0x6c, 0x13,
-0xe5, 0x21, 0xe5, 0x0d, 0x04, 0x04, 0x04, 0x01,
-0x01, 0x07, 0xe5, 0xe5, 0x04, 0xe5, 0x0f, 0x05,
-0xe6, 0x03, 0xe5, 0x06, 0xe5, 0x21, 0x01, 0x06,
-0x04, 0x6c, 0x10, 0xe5, 0x16, 0x06, 0x01, 0xe5,
-0xe5, 0x0b, 0x04, 0x06, 0xe5, 0x10, 0xe5, 0x05,
-0xe5, 0x07, 0x0c, 0xe5, 0x18, 0x1b, 0x05, 0x01,
-0xe5, 0x01, 0x57, 0x16, 0x10, 0x13, 0xe5, 0x04,
-0x07, 0x01, 0x04, 0xe5, 0xe5, 0x08, 0x06, 0x12,
-0xe5, 0x1c, 0x38, 0x03, 0xe5, 0xe5, 0x5a, 0x27,
-0x03, 0x22, 0x06, 0xe5, 0x04, 0xe5, 0x06, 0x01,
-0x0e, 0x07, 0x02, 0x02, 0x05, 0x0c, 0x01, 0x01,
-0x02, 0xe5, 0x01, 0x05, 0x09, 0x1f, 0xe5, 0xe6,
-0x01, 0x5e, 0x13, 0x0f, 0x03, 0x04, 0x10, 0x01,
-0x02, 0x04, 0x08, 0x02, 0x01, 0xe6, 0x02, 0x05,
-0x03, 0x0f, 0x02, 0x02, 0x02, 0x14, 0x01, 0x02,
-0x01, 0x01, 0x2c, 0x02, 0x01, 0x01, 0xe5, 0x5b,
-0x01, 0x2d, 0x0d, 0x09, 0x01, 0x03, 0xe5, 0x03,
-0x04, 0x01, 0xe5, 0x05, 0x01, 0x11, 0x02, 0x0e,
-0x0b, 0x01, 0x02, 0x0b, 0x09, 0xe5, 0xe5, 0xe5,
-0x19, 0xe5, 0x02, 0x5d, 0x01, 0x3a, 0x02, 0x07,
-0x01, 0x01, 0xe5, 0xe5, 0x01, 0x02, 0x06, 0x17,
-0xe8, 0xe5, 0x01, 0x0a, 0xe5, 0x0d, 0x0e, 0x09,
-0x1f, 0xe5, 0xe6, 0x6c, 0xe5, 0x25, 0x12, 0x04,
-0x04, 0x02, 0x09, 0x10, 0x09, 0x09, 0x1d, 0x09,
-0x21, 0xe8, 0x63, 0x09, 0x09, 0x09, 0x09, 0x0b,
-0x0f, 0xe5, 0x0d, 0x07, 0xe6, 0x06, 0x05, 0xe5,
-0x0b, 0xe5, 0x03, 0xe5, 0x15, 0x05, 0xe5, 0x07,
-0xe5, 0x1f, 0x02, 0xe6, 0x0d, 0x09, 0x09, 0x09,
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diff --git a/board/esd/ar405/fpgadata_xl30.c b/board/esd/ar405/fpgadata_xl30.c
deleted file mode 100644
index 42a9206..0000000
--- a/board/esd/ar405/fpgadata_xl30.c
+++ /dev/null
@@ -1,4872 +0,0 @@
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-0xe6, 0x05, 0x02, 0x05, 0xe5, 0xe6, 0x05, 0x01,
-0xe5, 0x05, 0x01, 0xe5, 0x05, 0x02, 0xe5, 0x08,
-0x0b, 0x02, 0x02, 0x02, 0xe5, 0x01, 0x06, 0x05,
-0x01, 0xe6, 0x07, 0xe5, 0x01, 0x06, 0x05, 0x01,
-0xe6, 0x03, 0xe5, 0xe7, 0x03, 0xe5, 0x01, 0xe5,
-0x04, 0x02, 0x24, 0xe5, 0x4a, 0x13, 0x06, 0x07,
-0x02, 0x06, 0x1a, 0xe5, 0x0c, 0x09, 0x02, 0x01,
-0xe5, 0x0b, 0xe5, 0x08, 0x0e, 0x03, 0x05, 0x22,
-0xe5, 0x01, 0x15, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe6, 0x06, 0xe5,
-0x07, 0xe6, 0xe5, 0x02, 0x01, 0xe5, 0x07, 0xe5,
-0x02, 0x04, 0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x02, 0x04, 0xe5, 0x07, 0xe5,
-0x01, 0x05, 0xe5, 0x07, 0xe6, 0x06, 0xe5, 0x07,
-0xe6, 0x06, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x06,
-0xe5, 0xe6, 0x20, 0x01, 0x07, 0x01, 0x0a, 0xe5,
-0x04, 0x01, 0x09, 0x07, 0x01, 0xe6, 0x06, 0xe6,
-0xe5, 0xe5, 0xe5, 0xe6, 0x07, 0xe5, 0x08, 0xe5,
-0x09, 0xe5, 0x04, 0x02, 0x06, 0x02, 0x06, 0x01,
-0xe5, 0x05, 0x01, 0xe5, 0x08, 0x06, 0x01, 0x07,
-0x01, 0x07, 0x01, 0xe5, 0x07, 0x22, 0xe5, 0xe6,
-0x20, 0x01, 0x07, 0x01, 0x11, 0x01, 0x07, 0x09,
-0x01, 0x07, 0x01, 0x07, 0x01, 0xe5, 0x1a, 0x16,
-0x07, 0x01, 0xe5, 0x19, 0x01, 0x07, 0x01, 0x07,
-0x02, 0x06, 0x24, 0xe6, 0xe6, 0x49, 0x13, 0x05,
-0x0e, 0x08, 0x16, 0x09, 0x13, 0x09, 0x1c, 0x09,
-0x23, 0xe7, 0x02, 0x34, 0x10, 0x0c, 0x06, 0x01,
-0xe5, 0x08, 0x08, 0x02, 0x06, 0x02, 0x0b, 0x06,
-0x02, 0x09, 0x09, 0x09, 0x06, 0x02, 0x09, 0x04,
-0x04, 0x09, 0x04, 0x26, 0x01, 0x6c, 0x04, 0x01,
-0xe5, 0x0c, 0x03, 0x0a, 0x3b, 0x01, 0xe5, 0x02,
-0x0a, 0x26, 0x02, 0xe5, 0x01, 0xe5, 0x0c, 0x01,
-0x01, 0x05, 0x01, 0x01, 0x05, 0x01, 0x01, 0x05,
-0x01, 0x02, 0x04, 0x01, 0x02, 0x04, 0x01, 0x07,
-0x01, 0xe6, 0x04, 0x01, 0x01, 0x05, 0x01, 0x01,
-0x05, 0x01, 0x02, 0x01, 0x02, 0x01, 0x01, 0x05,
-0x01, 0x09, 0x01, 0x01, 0x05, 0x01, 0xe5, 0xe5,
-0x03, 0x01, 0x01, 0x05, 0x01, 0x02, 0x04, 0xe6,
-0x01, 0x04, 0x01, 0x01, 0x05, 0xe6, 0x02, 0x03,
-0x01, 0x02, 0x04, 0xe6, 0xe5, 0x04, 0x01, 0x06,
-0xe5, 0xe5, 0x06, 0x01, 0x02, 0x07, 0x02, 0xe5,
-0x0b, 0x11, 0x32, 0x03, 0x04, 0x08, 0x0f, 0xe5,
-0x13, 0xe5, 0x06, 0xe5, 0x08, 0xe5, 0x07, 0xe5,
-0x01, 0x05, 0x09, 0xe5, 0x0e, 0x08, 0x03, 0xe5,
-0x2c, 0xe7, 0x07, 0x25, 0x18, 0x09, 0x09, 0x06,
-0x02, 0x0a, 0x01, 0x06, 0x0c, 0x01, 0x09, 0x05,
-0x02, 0x08, 0x04, 0x06, 0x08, 0x03, 0xe5, 0x12,
-0x04, 0x0c, 0x1f, 0xe6, 0xe6, 0xe5, 0x52, 0x0d,
-0x01, 0x09, 0x12, 0x01, 0x18, 0x01, 0x07, 0x05,
-0x0c, 0x1d, 0x0b, 0x21, 0x01, 0x01, 0xe5, 0x24,
-0x0d, 0x21, 0x0f, 0x09, 0xe5, 0x02, 0x04, 0xe5,
-0x04, 0x03, 0x0a, 0xe5, 0xe5, 0x02, 0x03, 0x01,
-0x02, 0x02, 0x04, 0x06, 0x01, 0xe5, 0x51, 0x01,
-0xe7, 0x1e, 0x05, 0x35, 0x08, 0x0f, 0x08, 0x05,
-0x01, 0xe5, 0x05, 0x06, 0x09, 0x0f, 0xe5, 0xe5,
-0x19, 0x06, 0x27, 0x0b, 0x01, 0xe6, 0x07, 0x04,
-0xe5, 0xe5, 0x10, 0x09, 0x09, 0x2b, 0x09, 0x09,
-0x01, 0x0a, 0xe5, 0x04, 0x05, 0x09, 0x10, 0x01,
-0x02, 0x0a, 0x09, 0x03, 0x01, 0x02, 0x09, 0x13,
-0x17, 0x01, 0x02, 0x0a, 0x02, 0x13, 0x09, 0xe7,
-0x05, 0xe5, 0xe5, 0x08, 0x06, 0x01, 0xe5, 0x08,
-0x03, 0x0f, 0x03, 0x05, 0x09, 0xe5, 0x04, 0x0e,
-0x16, 0x0d, 0x01, 0x0f, 0x14, 0xe5, 0x01, 0x06,
-0x0d, 0x0c, 0x03, 0x02, 0x0c, 0x13, 0xe5, 0x11,
-0x1a, 0x1d, 0x12, 0x01, 0x08, 0xe5, 0x04, 0xe6,
-0x19, 0x1d, 0x05, 0x03, 0x05, 0x02, 0x07, 0x02,
-0x17, 0x02, 0xe5, 0x11, 0x12, 0x18, 0x09, 0x04,
-0x0c, 0x06, 0x14, 0x0e, 0x06, 0x08, 0x03, 0x14,
-0x04, 0x03, 0x0a, 0x04, 0x1c, 0x03, 0x12, 0x0a,
-0x01, 0x01, 0x46, 0x1b, 0x02, 0x0f, 0x03, 0x06,
-0x03, 0xe6, 0x1b, 0x05, 0xe5, 0x13, 0x0c, 0x3d,
-0xe5, 0x0f, 0x02, 0x04, 0x02, 0x01, 0x02, 0x01,
-0x04, 0xe5, 0x02, 0x09, 0x04, 0x04, 0x03, 0x05,
-0x01, 0x02, 0x04, 0x09, 0x01, 0x02, 0x04, 0x2b,
-0x16, 0x04, 0x09, 0x0d, 0x01, 0x03, 0x04, 0x02,
-0x01, 0x13, 0x01, 0x07, 0x09, 0x06, 0x01, 0x04,
-0x0c, 0x01, 0x03, 0x01, 0x09, 0x08, 0x07, 0x01,
-0xe5, 0xe5, 0xe5, 0x03, 0xe5, 0x0c, 0x05, 0x09,
-0x08, 0xe6, 0xe5, 0x13, 0x13, 0x08, 0x0a, 0x07,
-0x06, 0x02, 0x07, 0x01, 0x09, 0x09, 0x07, 0x01,
-0x09, 0x02, 0x06, 0x02, 0x0e, 0xe5, 0x16, 0x0a,
-0x0e, 0x05, 0x09, 0x03, 0x03, 0x09, 0x01, 0x01,
-0xe5, 0x03, 0xe5, 0x09, 0x06, 0x1f, 0x1e, 0xe5,
-0x07, 0xe5, 0x11, 0xe5, 0x04, 0x04, 0x01, 0x0f,
-0xe5, 0x07, 0x01, 0x0b, 0x03, 0xe5, 0xe5, 0x0b,
-0x02, 0xe5, 0x08, 0x09, 0x09, 0x09, 0x04, 0xe5,
-0x02, 0x09, 0x09, 0x05, 0x02, 0xe5, 0xe5, 0x01,
-0xe5, 0x01, 0xe5, 0xe5, 0x03, 0xe7, 0x07, 0xe5,
-0x03, 0x05, 0xe5, 0x05, 0xe7, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x08, 0x04, 0xe5, 0x02, 0x04,
-0x04, 0x08, 0xe5, 0x03, 0x04, 0x08, 0xe5, 0x07,
-0xe5, 0x0c, 0x02, 0xe5, 0x17, 0x14, 0x05, 0x0a,
-0x09, 0x01, 0x0a, 0x08, 0x01, 0x08, 0xe5, 0x01,
-0x01, 0x02, 0x01, 0x09, 0x02, 0x07, 0xe5, 0x06,
-0x01, 0x09, 0x08, 0xe5, 0x08, 0x0e, 0x18, 0x09,
-0x09, 0x09, 0x0e, 0x02, 0x03, 0x0b, 0x06, 0x02,
-0x06, 0x0c, 0x06, 0x0c, 0x0e, 0x01, 0x02, 0x02,
-0x06, 0x03, 0x05, 0x03, 0x05, 0x06, 0x02, 0x04,
-0x01, 0x04, 0x03, 0x02, 0x02, 0x09, 0x09, 0x03,
-0x03, 0x01, 0x07, 0x01, 0x07, 0x07, 0x01, 0x01,
-0x09, 0xe5, 0x11, 0x09, 0x0f, 0x02, 0x08, 0xe5,
-0x1c, 0x08, 0x13, 0x09, 0x03, 0x09, 0x0d, 0x0b,
-0x09, 0x0b, 0x17, 0x03, 0x0b, 0x09, 0xe5, 0x07,
-0x27, 0x12, 0x02, 0xe6, 0xe5, 0x0e, 0x01, 0x0c,
-0x04, 0x04, 0x05, 0x05, 0x02, 0x13, 0x0a, 0x03,
-0x18, 0x09, 0x0b, 0xe5, 0x04, 0x02, 0x09, 0x01,
-0x07, 0x07, 0x01, 0x07, 0x08, 0xe5, 0xe5, 0x02,
-0x01, 0x01, 0x01, 0x04, 0x0e, 0x09, 0x09, 0x0f,
-0x01, 0xe5, 0x0b, 0xe6, 0x07, 0xe5, 0x05, 0x01,
-0xe5, 0x02, 0x04, 0xe5, 0x07, 0xe5, 0x04, 0x02,
-0xe5, 0x04, 0x02, 0xe5, 0x04, 0x02, 0xe5, 0x07,
-0xe6, 0x06, 0xe6, 0x06, 0xe5, 0x07, 0xe5, 0x08,
-0xe6, 0x07, 0xe5, 0x07, 0xe5, 0x06, 0xe6, 0x07,
-0x13, 0x03, 0x03, 0x0b, 0xe5, 0x01, 0x05, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x0e, 0x01, 0xe6, 0x02,
-0x09, 0x01, 0x07, 0x05, 0x03, 0x01, 0x07, 0x07,
-0x01, 0x01, 0x07, 0x08, 0xe5, 0xe5, 0x06, 0x09,
-0x04, 0x04, 0x09, 0x09, 0x0a, 0xe5, 0x02, 0x05,
-0x09, 0x05, 0x03, 0x12, 0x0c, 0x04, 0x05, 0x06,
-0x08, 0xe5, 0x08, 0x09, 0x0b, 0x06, 0x01, 0x0e,
-0xe5, 0x07, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
-0x07, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
-0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
-0x09, 0x09, 0x09, 0xe5, 0x07, 0x02, 0x06, 0xe5,
-0xe5, 0x05, 0xe5, 0xe5, 0x0b, 0x02, 0xe5, 0x0d,
-0x02, 0x06, 0x01, 0x07, 0x09, 0x01, 0x02, 0x04,
-0x09, 0x01, 0x07, 0x09, 0x01, 0x07, 0x03, 0x05,
-0x05, 0x03, 0x02, 0x06, 0x0b, 0x04, 0x04, 0x09,
-0x1f, 0x07, 0x13, 0x09, 0x09, 0x09, 0x02, 0x10,
-0x12, 0x44, 0x02, 0x04, 0xe5, 0x04, 0x02, 0xe5,
-0x18, 0x25, 0x01, 0x01, 0x21, 0x2f, 0x05, 0x01,
-0x01, 0x0e, 0x09, 0x02, 0x06, 0x02, 0x06, 0x09,
-0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x04, 0x09,
-0x09, 0x09, 0x01, 0xe5, 0x05, 0x05, 0x03, 0x02,
-0x05, 0x02, 0x09, 0x02, 0xe5, 0x04, 0x04, 0x03,
-0xe5, 0x07, 0x03, 0x05, 0xe5, 0x08, 0x05, 0x02,
-0xe5, 0x02, 0x03, 0x01, 0x04, 0x04, 0x09, 0x09,
-0x09, 0x06, 0xe5, 0xe5, 0x06, 0x18, 0x09, 0x09,
-0x1d, 0x0f, 0x13, 0x03, 0x0a, 0x0a, 0x04, 0x10,
-0x09, 0x06, 0xe5, 0xe5, 0x4a, 0xe5, 0x01, 0x07,
-0x08, 0xe5, 0x07, 0x09, 0x09, 0x03, 0x05, 0x09,
-0x09, 0xe5, 0x07, 0x09, 0x09, 0x09, 0x05, 0x03,
-0x06, 0xe5, 0x02, 0x09, 0x09, 0x09, 0xe5, 0x07,
-0x07, 0x01, 0x01, 0x07, 0x01, 0x07, 0x05, 0x03,
-0x01, 0x07, 0x09, 0x09, 0x0e, 0x01, 0xe5, 0x03,
-0x61, 0x11, 0x01, 0x07, 0x0b, 0x09, 0x09, 0x03,
-0x05, 0x02, 0xe5, 0x05, 0x15, 0x3b, 0xe5, 0x14,
-0x13, 0x13, 0x09, 0x14, 0x09, 0x0d, 0x09, 0x06,
-0x04, 0x09, 0x04, 0xe5, 0x02, 0x04, 0x04, 0x18,
-0x13, 0x09, 0x27, 0xe5, 0xe5, 0x09, 0x17, 0x06,
-0x02, 0x4f, 0x4f, 0x09, 0x2b, 0x05, 0xe6, 0x0a,
-0x3b, 0x27, 0x5b, 0x3c, 0xe6, 0x3c, 0x5b, 0x1e,
-0x26, 0x27, 0xe5, 0xe5, 0x03, 0x10, 0x31, 0x2a,
-0x05, 0x03, 0x05, 0x02, 0x02, 0x05, 0x03, 0x05,
-0x03, 0x05, 0xe5, 0x01, 0x05, 0x14, 0x13, 0x29,
-0x06, 0xe5, 0xe6, 0x46, 0x27, 0x15, 0x46, 0x33,
-0x05, 0xe5, 0x01, 0x04, 0x57, 0xa9, 0x03, 0x14,
-0x09, 0x09, 0x09, 0x09, 0x09, 0xe6, 0x06, 0x09,
-0xe6, 0x06, 0x09, 0xe6, 0x06, 0x09, 0x0b, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0xe6, 0x06, 0x09,
-0x09, 0x09, 0x09, 0x0a, 0x02, 0x05, 0x09, 0x08,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x05, 0x01, 0xe5, 0x07, 0xe5, 0x05, 0x01,
-0xe5, 0x07, 0xe5, 0x05, 0x02, 0x09, 0x07, 0x03,
-0x09, 0x09, 0x09, 0x09, 0x04, 0x03, 0xe5, 0x07,
-0xe5, 0x05, 0x01, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x08, 0x09, 0x10, 0xe6, 0x15, 0x05, 0x03, 0x05,
-0x03, 0x05, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05,
-0x03, 0x05, 0x03, 0x09, 0x05, 0x03, 0x04, 0x09,
-0x05, 0x05, 0x09, 0x09, 0x09, 0x14, 0x03, 0x09,
-0x05, 0x03, 0x09, 0x27, 0x01, 0x0d, 0x03, 0x03,
-0x05, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05, 0x03,
-0x09, 0x05, 0x03, 0x09, 0x05, 0x03, 0x09, 0x01,
-0x04, 0x04, 0x04, 0x06, 0x04, 0x04, 0x04, 0x04,
-0x04, 0x04, 0x04, 0x06, 0x0b, 0x03, 0x09, 0x09,
-0x09, 0x09, 0x03, 0x05, 0x03, 0x0d, 0x02, 0x01,
-0x0b, 0x06, 0x01, 0x02, 0x01, 0x04, 0x02, 0x01,
-0x04, 0x02, 0x01, 0x04, 0x02, 0x01, 0x04, 0x02,
-0x01, 0x01, 0x05, 0x01, 0x04, 0x02, 0x01, 0x01,
-0x05, 0x01, 0x02, 0x01, 0x02, 0x01, 0x01, 0xe5,
-0x06, 0x02, 0x02, 0x03, 0x02, 0x02, 0x05, 0x02,
-0x02, 0x03, 0x02, 0x02, 0x03, 0x02, 0x02, 0x03,
-0x02, 0x02, 0x02, 0x04, 0x02, 0x01, 0x04, 0x02,
-0x01, 0x01, 0xe5, 0x03, 0x01, 0x01, 0x02, 0x04,
-0x02, 0x01, 0x02, 0x01, 0x01, 0x02, 0x04, 0x04,
-0x04, 0x06, 0x02, 0x02, 0xe6, 0xe5, 0xe5, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
diff --git a/board/esd/ash405/Kconfig b/board/esd/ash405/Kconfig
deleted file mode 100644
index 02c7c14..0000000
--- a/board/esd/ash405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ASH405
-
-config SYS_BOARD
- default "ash405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "ASH405"
-
-endif
diff --git a/board/esd/ash405/MAINTAINERS b/board/esd/ash405/MAINTAINERS
deleted file mode 100644
index a9dae90..0000000
--- a/board/esd/ash405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ASH405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/ash405/
-F: include/configs/ASH405.h
-F: configs/ASH405_defconfig
diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile
deleted file mode 100644
index aab8de4..0000000
--- a/board/esd/ash405/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = ash405.o flash.o \
- ../common/misc.o \
- ../common/esd405ep_nand.o \
diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
deleted file mode 100644
index 4460a19..0000000
--- a/board/esd/ash405/ash405.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-
-/* ------------------------------------------------------------------------- */
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-extern void lxt971_no_sleep(void);
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-
- /*
- * Reset external DUARTs
- */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
- udelay(10); /* wait 10us */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
- udelay(1000); /* wait 1ms */
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- out_8((void *)(DUART0_BA + 4), 0x08);
- out_8((void *)(DUART1_BA + 4), 0x08);
- out_8((void *)(DUART2_BA + 4), 0x08);
- out_8((void *)(DUART3_BA + 4), 0x08);
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming ASH405");
- } else {
- puts(str);
- }
-
- putc ('\n');
-
- return 0;
-}
-
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/ash405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/ash405/fpgadata.c b/board/esd/ash405/fpgadata.c
deleted file mode 100644
index 6e29053..0000000
--- a/board/esd/ash405/fpgadata.c
+++ /dev/null
@@ -1,4983 +0,0 @@
-0x1f, 0x8b, 0x08, 0x08, 0x5c, 0xa1, 0x5d, 0x3f,
-0x00, 0x03, 0x61, 0x73, 0x68, 0x34, 0x30, 0x35,
-0x5f, 0x31, 0x5f, 0x30, 0x32, 0x2e, 0x62, 0x69,
-0x74, 0x00, 0xec, 0xfd, 0x0f, 0x78, 0x1c, 0xe5,
-0x91, 0x2f, 0x0a, 0x57, 0xbf, 0xdd, 0x92, 0x5f,
-0x4d, 0x8f, 0x34, 0xad, 0x91, 0x4c, 0x14, 0x30,
-0xa6, 0x35, 0x92, 0xcd, 0x58, 0x19, 0xc9, 0xe3,
-0x91, 0x90, 0x85, 0x10, 0xa3, 0xb6, 0x24, 0x58,
-0x45, 0x36, 0x58, 0x71, 0xd8, 0x2c, 0x67, 0x97,
-0x93, 0x1d, 0x88, 0x93, 0xe3, 0xdd, 0x75, 0x72,
-0x1c, 0x36, 0x37, 0xc7, 0x21, 0x6c, 0xf2, 0x6a,
-0x24, 0xe3, 0xb1, 0x65, 0xe3, 0xc1, 0x38, 0xc1,
-0x04, 0x92, 0x3b, 0xfe, 0x43, 0x10, 0xe0, 0x24,
-0x63, 0xd9, 0x60, 0x19, 0x1b, 0x68, 0x09, 0x41,
-0xc6, 0xb6, 0xb0, 0x15, 0xc7, 0x9b, 0x35, 0xc4,
-0x0b, 0x63, 0x50, 0x88, 0x30, 0x82, 0xc8, 0xe0,
-0x24, 0xb2, 0x2d, 0xec, 0x5b, 0xd5, 0x23, 0xcd,
-0xf4, 0x38, 0x7b, 0xf6, 0xec, 0xde, 0xf3, 0xdc,
-0xef, 0xdb, 0xef, 0xbb, 0xab, 0x73, 0x9e, 0x67,
-0x2b, 0xdd, 0xed, 0xa6, 0xfb, 0x9d, 0xb7, 0xab,
-0x7e, 0x55, 0xf5, 0xab, 0x2a, 0xc8, 0x73, 0x8d,
-0xa7, 0xfe, 0x1f, 0x80, 0x74, 0x37, 0x68, 0x77,
-0xff, 0xfd, 0x8a, 0x1a, 0xff, 0x0d, 0x7f, 0xbd,
-0xe0, 0xaf, 0xfd, 0x81, 0xaa, 0xaf, 0x7d, 0x69,
-0x39, 0xdc, 0x03, 0x6a, 0xe0, 0xef, 0x6f, 0xf0,
-0x7f, 0xf9, 0x1b, 0x5f, 0x5f, 0x50, 0x53, 0x03,
-0x5f, 0xc2, 0xff, 0xe5, 0xf7, 0x57, 0xcf, 0xf7,
-0xdf, 0x88, 0xff, 0x1f, 0x96, 0x43, 0xde, 0x82,
-0x05, 0xf5, 0x35, 0xb5, 0xf5, 0xfe, 0x1a, 0xf8,
-0x32, 0x48, 0xd5, 0x3b, 0x2f, 0xe3, 0xdf, 0xd3,
-0x8f, 0xfe, 0xf9, 0x57, 0xfc, 0x20, 0x24, 0x00,
-0x98, 0xe1, 0x97, 0x42, 0xf4, 0x7f, 0x55, 0xbf,
-0xa4, 0x4b, 0x20, 0x1a, 0x2b, 0xfd, 0x60, 0xd2,
-0xff, 0x86, 0xa9, 0xf3, 0x79, 0x7e, 0xd0, 0xed,
-0xff, 0x5b, 0xf2, 0x83, 0x01, 0xed, 0x60, 0x6c,
-0x00, 0xb7, 0x1f, 0xfe, 0xd7, 0x7f, 0x86, 0x22,
-0xa6, 0xc5, 0x7f, 0xe7, 0xf5, 0x97, 0x0f, 0x8b,
-0xff, 0xe9, 0x55, 0x99, 0xbf, 0xc6, 0x8f, 0x62,
-0xd3, 0x22, 0xfb, 0x37, 0xdc, 0x5f, 0x32, 0x20,
-0x7d, 0xff, 0x37, 0xfe, 0x4d, 0xf7, 0xff, 0xc3,
-0xf4, 0xfd, 0xff, 0xbd, 0xd7, 0x83, 0xfb, 0xdf,
-0x70, 0x39, 0x80, 0x92, 0x7e, 0x1e, 0x37, 0x38,
-0x80, 0x09, 0x88, 0x81, 0xf7, 0x5f, 0x11, 0x1a,
-0x07, 0xa7, 0xff, 0x61, 0x7f, 0xce, 0x09, 0x71,
-0x4c, 0x34, 0x24, 0x67, 0xac, 0x92, 0x67, 0x19,
-0x93, 0x7c, 0x61, 0xd2, 0x15, 0xed, 0x3c, 0x17,
-0x3b, 0x2a, 0x1a, 0x93, 0xae, 0x44, 0xd9, 0x4a,
-0x76, 0xac, 0xa3, 0x5a, 0x5f, 0x3a, 0x51, 0x34,
-0xae, 0xad, 0x9a, 0xba, 0xde, 0x2c, 0xf9, 0x2d,
-0x74, 0x8b, 0x82, 0x10, 0x8f, 0xb3, 0xca, 0x48,
-0x1f, 0x38, 0x92, 0x05, 0x1b, 0xd8, 0x6f, 0xf4,
-0xf5, 0xa2, 0x2a, 0xa9, 0xf6, 0xc1, 0x8b, 0x7c,
-0x9d, 0xa8, 0x30, 0xd4, 0x3e, 0x96, 0x54, 0xf4,
-0xa9, 0xeb, 0x13, 0xd0, 0x65, 0x74, 0x82, 0xcf,
-0x7c, 0xcc, 0x9f, 0x9b, 0xaf, 0x3c, 0x9f, 0x17,
-0x33, 0x55, 0x0d, 0x06, 0x79, 0x58, 0xf2, 0xa1,
-0x90, 0xeb, 0x84, 0x67, 0x84, 0x6e, 0xa8, 0xfe,
-0xa6, 0xc3, 0xd2, 0xf4, 0xf5, 0x66, 0xce, 0x8f,
-0xa1, 0x1b, 0xaa, 0x42, 0x25, 0xc2, 0xb1, 0x12,
-0xfa, 0xc2, 0x1e, 0xd3, 0xb1, 0x81, 0x7d, 0x85,
-0x45, 0xb4, 0xaa, 0x41, 0x75, 0x6b, 0x93, 0x0f,
-0x9e, 0xd1, 0x2b, 0x5a, 0xd5, 0x38, 0x9b, 0x50,
-0xa6, 0x9f, 0x67, 0xd1, 0xcc, 0x77, 0xc3, 0x47,
-0x1e, 0x08, 0xbe, 0xe3, 0xda, 0x5b, 0xe6, 0x83,
-0x71, 0x11, 0xe8, 0xbf, 0xee, 0x71, 0xf9, 0x5d,
-0x38, 0x6c, 0x04, 0x93, 0x2e, 0xbd, 0xcc, 0x09,
-0xef, 0xac, 0x09, 0xac, 0x72, 0xc5, 0xe5, 0xe1,
-0x96, 0xe9, 0xeb, 0x63, 0x52, 0x5c, 0xb9, 0xbc,
-0xa8, 0x71, 0x91, 0xeb, 0x5b, 0xf2, 0x41, 0xf8,
-0x04, 0x1a, 0xcd, 0xa5, 0xa6, 0x3c, 0x0e, 0x97,
-0x44, 0xa3, 0xe9, 0x1a, 0x57, 0x27, 0xb5, 0x1f,
-0x2a, 0x2f, 0xdd, 0xed, 0x1a, 0x6f, 0x1e, 0x85,
-0xd0, 0xd4, 0xf5, 0x27, 0xb4, 0x2e, 0xfe, 0x3e,
-0xd4, 0x0f, 0x5c, 0xb7, 0xfb, 0xf3, 0x63, 0xca,
-0xaf, 0xcb, 0xeb, 0xcd, 0x25, 0x8f, 0x7f, 0x6a,
-0x44, 0x9a, 0x80, 0xa0, 0xe9, 0xea, 0x93, 0x3f,
-0x84, 0xf3, 0x22, 0x60, 0x6c, 0x88, 0xcb, 0xe3,
-0xca, 0xf4, 0x7a, 0x26, 0x72, 0x74, 0xd1, 0x3d,
-0xa2, 0x1b, 0xfc, 0x59, 0xd6, 0x80, 0x2f, 0xe2,
-0x49, 0xb4, 0x46, 0xd9, 0xbb, 0x30, 0x21, 0xaa,
-0xde, 0x56, 0x9f, 0x65, 0x93, 0xb0, 0xbf, 0xab,
-0xd6, 0xcc, 0x8f, 0xb3, 0x8f, 0x70, 0xf7, 0x4f,
-0xbd, 0xaf, 0xb2, 0x44, 0xd9, 0x91, 0xe0, 0xe3,
-0x8e, 0x9a, 0xdc, 0x8d, 0x7a, 0x54, 0xd2, 0x4f,
-0x73, 0xb7, 0x7b, 0x44, 0xe9, 0x15, 0xbe, 0xa4,
-0xaa, 0xb0, 0x21, 0xa8, 0x86, 0x98, 0xc1, 0xfd,
-0x6c, 0x02, 0xbf, 0x95, 0xd4, 0xdf, 0xb8, 0xf6,
-0x5d, 0xf8, 0x94, 0x28, 0xfb, 0x69, 0xeb, 0x6a,
-0xcf, 0x6c, 0xe8, 0xea, 0xbb, 0x3b, 0xe9, 0xbd,
-0x93, 0xfd, 0x2a, 0x54, 0x1e, 0xa9, 0x4c, 0xaa,
-0x2b, 0xd8, 0x9b, 0xc6, 0xbe, 0xe1, 0x39, 0xa1,
-0xbc, 0xd5, 0xec, 0x64, 0xfa, 0xfe, 0xad, 0x7c,
-0x89, 0xf1, 0x0e, 0xd4, 0x8d, 0x3a, 0x6a, 0x9b,
-0x37, 0xc0, 0x2f, 0xcd, 0x78, 0xff, 0x92, 0x9b,
-0x9a, 0x86, 0x8c, 0x5e, 0xad, 0x21, 0xe9, 0xaa,
-0x29, 0x3b, 0x2a, 0x3e, 0x86, 0x40, 0xbb, 0xd3,
-0x2f, 0x1f, 0x67, 0xd3, 0xcf, 0x6f, 0xcc, 0x3c,
-0x08, 0xbf, 0x85, 0xe0, 0xa0, 0x67, 0x5c, 0xde,
-0x05, 0xfb, 0xe0, 0x06, 0x13, 0x57, 0x6f, 0xd2,
-0xb8, 0x5f, 0xc3, 0xf7, 0x1d, 0x97, 0x27, 0xe1,
-0x8f, 0x4a, 0x63, 0x8b, 0x3a, 0x2e, 0x0f, 0xb3,
-0xe9, 0xf5, 0xe1, 0x33, 0x7b, 0xe0, 0x22, 0xf8,
-0x4d, 0x67, 0xbc, 0x79, 0x97, 0x11, 0x67, 0x6e,
-0x73, 0x69, 0x54, 0x1a, 0x81, 0x93, 0x10, 0x4c,
-0x3a, 0xe3, 0xf2, 0x07, 0xe6, 0x00, 0x04, 0x42,
-0x28, 0x0c, 0x40, 0x7a, 0x3f, 0x68, 0x51, 0x78,
-0x16, 0x4a, 0xcd, 0xfc, 0x55, 0x15, 0xb3, 0xa2,
-0x7b, 0x51, 0x58, 0xdc, 0xce, 0x06, 0xa1, 0x0b,
-0x6e, 0x34, 0x1d, 0xab, 0x9a, 0x86, 0xf4, 0x5f,
-0xc1, 0x53, 0x06, 0x5f, 0x85, 0xeb, 0x33, 0x7d,
-0xbd, 0x0e, 0x8f, 0xc1, 0x4b, 0xa2, 0x2c, 0xf9,
-0xe8, 0x6a, 0xc7, 0x8f, 0xe0, 0xa5, 0xf0, 0x9c,
-0x64, 0xdb, 0x6a, 0xcf, 0x9b, 0xd0, 0x25, 0xe6,
-0x27, 0xf3, 0x56, 0x2f, 0x7b, 0x53, 0xac, 0x15,
-0xd7, 0xdf, 0xc3, 0x57, 0x33, 0x33, 0xbd, 0xdf,
-0x46, 0x8b, 0xd7, 0xc3, 0x6e, 0xd0, 0x5f, 0xcf,
-0x0b, 0x38, 0x36, 0xf0, 0x3d, 0xc9, 0x72, 0x53,
-0xad, 0x61, 0x1f, 0xe4, 0x75, 0xc4, 0xbc, 0x21,
-0xf5, 0x06, 0x5c, 0xcf, 0x87, 0x4d, 0x5f, 0xc8,
-0xeb, 0x67, 0xc7, 0xd3, 0xd7, 0x8f, 0xcc, 0xbc,
-0x08, 0x17, 0x62, 0xd5, 0xd1, 0xfc, 0x0f, 0xd5,
-0x1e, 0xb8, 0xb4, 0xad, 0x56, 0x14, 0x7c, 0x59,
-0x3e, 0xcf, 0x1e, 0x0c, 0x05, 0x3b, 0xf3, 0x56,
-0x7c, 0x7e, 0x14, 0x5e, 0x8d, 0x2d, 0x8c, 0x3b,
-0x63, 0xf2, 0x84, 0x32, 0xfd, 0xbe, 0xad, 0x92,
-0xd0, 0x27, 0xe0, 0x45, 0xcd, 0xd5, 0x25, 0xdf,
-0x0d, 0x13, 0xec, 0x79, 0x40, 0x21, 0x19, 0x19,
-0x65, 0x41, 0x28, 0x10, 0x9d, 0x49, 0x3e, 0x01,
-0xf7, 0x31, 0x97, 0x90, 0x8f, 0xc3, 0xb4, 0x16,
-0x71, 0x6a, 0x3b, 0x9b, 0x0e, 0x41, 0xaf, 0xe1,
-0x8c, 0xca, 0xb9, 0xe1, 0x43, 0xa2, 0xb6, 0xc5,
-0xb5, 0x55, 0xfe, 0x4a, 0xd7, 0xa1, 0x45, 0xc1,
-0x90, 0xeb, 0x71, 0xf9, 0x01, 0x71, 0x28, 0x12,
-0x30, 0x36, 0x45, 0xe5, 0x01, 0x65, 0xfa, 0x7a,
-0x01, 0x5f, 0x81, 0x0e, 0x43, 0xff, 0x2f, 0x8e,
-0xab, 0xcb, 0x7e, 0x13, 0xe9, 0x10, 0x9e, 0x90,
-0xfa, 0x28, 0x2b, 0x87, 0xd7, 0xa1, 0xca, 0x50,
-0xa3, 0xee, 0xb9, 0xf0, 0x7a, 0xc8, 0x83, 0x02,
-0x4b, 0x82, 0x36, 0x75, 0x7d, 0x5d, 0x4e, 0x39,
-0xac, 0x03, 0x8f, 0xd1, 0xba, 0x19, 0x2f, 0x5b,
-0x17, 0xfa, 0x31, 0x9e, 0x0d, 0xaf, 0xa4, 0x2f,
-0xa8, 0x55, 0xdd, 0xc2, 0x76, 0xc2, 0x3a, 0xdd,
-0xba, 0xfe, 0xd5, 0xf4, 0x7e, 0xf0, 0x16, 0x3b,
-0xb7, 0xad, 0x13, 0x1e, 0xa3, 0xcd, 0xbd, 0x7e,
-0xb0, 0xa7, 0xc3, 0x1b, 0x32, 0x54, 0xf7, 0x80,
-0xb2, 0xed, 0x21, 0x70, 0x1a, 0xaa, 0xc6, 0x94,
-0xd8, 0xa3, 0x90, 0x24, 0x61, 0x60, 0x7a, 0x3b,
-0xc0, 0xea, 0xfc, 0x90, 0x48, 0x40, 0x00, 0x78,
-0x58, 0xd5, 0x45, 0x42, 0xaf, 0x95, 0xd4, 0xb0,
-0x4c, 0x47, 0x82, 0xa0, 0x0a, 0x39, 0x86, 0x42,
-0x2f, 0xe0, 0xfb, 0xbe, 0x29, 0x4d, 0x3f, 0xcf,
-0xd6, 0x99, 0xe7, 0xe0, 0xf7, 0xd0, 0x68, 0x2c,
-0x5d, 0xf6, 0xf2, 0xce, 0xd8, 0x27, 0xde, 0xa0,
-0xe1, 0x1a, 0x96, 0xce, 0x6d, 0xfb, 0x04, 0x6e,
-0x36, 0xd4, 0x61, 0x79, 0x04, 0x2e, 0xc3, 0xcd,
-0x6d, 0xae, 0xa8, 0xfc, 0x95, 0x9c, 0xe9, 0xef,
-0xb1, 0x24, 0x67, 0x2f, 0xd0, 0xd9, 0x45, 0xc7,
-0x17, 0xef, 0x15, 0xff, 0xc0, 0xaa, 0xf1, 0x1f,
-0xb2, 0x1b, 0xc4, 0x3f, 0xe4, 0xdc, 0x64, 0xac,
-0x1d, 0x96, 0xf7, 0xe2, 0xad, 0x7a, 0x5b, 0xf0,
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-0xec, 0x3d, 0xa3, 0x70, 0xe8, 0x65, 0xf9, 0x03,
-0x44, 0x83, 0x3d, 0xba, 0x0d, 0x6c, 0x3f, 0xe5,
-0x10, 0x16, 0xc2, 0xa3, 0x40, 0xd1, 0x9c, 0x3f,
-0x9b, 0x62, 0xab, 0xd1, 0xbf, 0x53, 0x7b, 0xd1,
-0xdd, 0xcc, 0x6d, 0xa9, 0x31, 0x9a, 0xf9, 0xcd,
-0xfc, 0x96, 0x7a, 0xf3, 0xce, 0xaa, 0x36, 0x63,
-0x32, 0xc6, 0x78, 0x84, 0xb5, 0xfc, 0x41, 0x63,
-0x71, 0xd0, 0xae, 0x39, 0xb7, 0x3f, 0xed, 0xea,
-0xab, 0xff, 0xcf, 0x85, 0x18, 0x03, 0x20, 0x01,
-0x83, 0x76, 0xd5, 0xc8, 0x1f, 0xbc, 0x5e, 0x5f,
-0x6d, 0xdd, 0xbd, 0xfe, 0xc3, 0x8d, 0xf7, 0x8f,
-0x9e, 0xbd, 0x7a, 0x89, 0xf8, 0xf0, 0xfb, 0xf7,
-0x34, 0x1f, 0xde, 0xc8, 0xf8, 0xb0, 0x68, 0x74,
-0x87, 0x8b, 0x19, 0x1f, 0xbe, 0x46, 0x7c, 0xf8,
-0xe0, 0xbe, 0xe6, 0xc3, 0x3f, 0x32, 0x3e, 0x3c,
-0xc5, 0x63, 0x8f, 0xab, 0xe7, 0x09, 0x0b, 0x7f,
-0x1f, 0x3c, 0xb8, 0x7f, 0xf1, 0xaf, 0x04, 0x14,
-0x91, 0x18, 0x67, 0xf0, 0x61, 0xfc, 0xdf, 0xff,
-0xfc, 0x0d, 0xfb, 0xff, 0x3d, 0x01, 0xc5, 0x8f,
-0x67, 0xf1, 0xe1, 0xcb, 0x13, 0x3e, 0x7c, 0x6e,
-0xe9, 0xd5, 0x5f, 0x0f, 0xea, 0xd4, 0xff, 0xda,
-0x54, 0xff, 0x7b, 0x4f, 0x3e, 0x7a, 0x0f, 0xa1,
-0x81, 0xbe, 0xd8, 0xe8, 0x41, 0xb3, 0xf4, 0xe4,
-0x6b, 0x61, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5,
-0x62, 0xb1, 0x58, 0xff, 0x77, 0xc5, 0xb5, 0x83,
-0xe4, 0xda, 0x81, 0xc5, 0x62, 0xb1, 0x58, 0x2c,
-0x16, 0x8b, 0xc5, 0x62, 0xcd, 0x56, 0x5c, 0x3b,
-0x14, 0xb8, 0x76, 0x60, 0xb1, 0x58, 0x2c, 0x16,
-0x8b, 0xc5, 0x62, 0xb1, 0x58, 0xb3, 0x15, 0xd7,
-0x0e, 0x56, 0x5c, 0x3b, 0xfc, 0xd7, 0x43, 0x61,
-0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1,
-0x58, 0xff, 0xa2, 0x3c, 0x7a, 0x81, 0x1c, 0x0a,
-0xb7, 0x3d, 0x88, 0xdf, 0x89, 0xc9, 0x7b, 0xa0,
-0x1e, 0xfb, 0x79, 0x42, 0xf2, 0xb7, 0x73, 0x1e,
-0x0c, 0x45, 0xb6, 0xce, 0x7b, 0xef, 0x4c, 0xf7,
-0xfb, 0x07, 0x18, 0x78, 0xae, 0x50, 0xf1, 0x33,
-0x01, 0x00,
diff --git a/board/esd/cms700/Kconfig b/board/esd/cms700/Kconfig
deleted file mode 100644
index da11bc0..0000000
--- a/board/esd/cms700/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CMS700
-
-config SYS_BOARD
- default "cms700"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "CMS700"
-
-endif
diff --git a/board/esd/cms700/MAINTAINERS b/board/esd/cms700/MAINTAINERS
deleted file mode 100644
index 0191c8b..0000000
--- a/board/esd/cms700/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CMS700 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/cms700/
-F: include/configs/CMS700.h
-F: configs/CMS700_defconfig
diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
deleted file mode 100644
index 2bf5006..0000000
--- a/board/esd/cms700/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-CPLD = ../common/xilinx_jtag/lenval.o \
- ../common/xilinx_jtag/micro.o \
- ../common/xilinx_jtag/ports.o
-
-obj-y = cms700.o flash.o \
- ../common/misc.o \
- $(CPLD) \
- ../common/esd405ep_nand.o \
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
deleted file mode 100644
index 40d7621..0000000
--- a/board/esd/cms700/cms700.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * (C) Copyright 2005-2007
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- /*
- * Reset CPLD via GPIO12 (CS3) pin
- */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
- udelay(1000); /* wait 1ms */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
- udelay(1000); /* wait 1ms */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /*
- * Setup and enable EEPROM write protection
- */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000)
-int checkboard (void)
-{
- char str[64];
- int flashcnt;
- int delay;
-
- puts ("Board: ");
-
- if (getenv_f("serial#", str, sizeof(str)) == -1) {
- puts ("### No HW ID - assuming CMS700");
- } else {
- puts(str);
- }
-
- printf(" (PLD-Version=%02d)\n",
- in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001)));
-
- /*
- * Flash LEDs
- */
- for (flashcnt = 0; flashcnt < 3; flashcnt++) {
- out_8((void *)LED_REG, 0x00); /* LEDs off */
- for (delay = 0; delay < 100; delay++)
- udelay(1000);
- out_8((void *)LED_REG, 0x0f); /* LEDs on */
- for (delay = 0; delay < 50; delay++)
- udelay(1000);
- }
- out_8((void *)LED_REG, 0x70);
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state)
-{
- if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
- return -1;
- } else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
- break;
- }
- }
- return state;
-}
-
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
- if (state < 0) {
- puts ("Query of write access state failed.\n");
- } else {
- printf ("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
- state = 0;
- }
- } else {
- if ('0' == argv[1][0]) {
- /* Disable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0) {
- puts ("Setup of write access state failed.\n");
- }
- }
-
- return state;
-}
-
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/cms700/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
deleted file mode 100644
index f3f70ff..0000000
--- a/board/esd/common/auto_update.c
+++ /dev/null
@@ -1,478 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <command.h>
-#include <image.h>
-#include <asm/byteorder.h>
-#include <fat.h>
-#include <flash.h>
-#include <part.h>
-
-#include "auto_update.h"
-
-#ifdef CONFIG_AUTO_UPDATE
-
-#if !defined(CONFIG_CMD_FAT)
-#error "must define CONFIG_CMD_FAT"
-#endif
-
-extern au_image_t au_image[];
-extern int N_AU_IMAGES;
-
-/* where to load files into memory */
-#define LOAD_ADDR ((unsigned char *)0x100000)
-#define MAX_LOADSZ 0x1c00000
-
-/* externals */
-long do_fat_read (const char *filename, void *buffer,
- unsigned long maxsize, int dols);
-
-extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
-
-int au_check_cksum_valid(int i, long nbytes)
-{
- image_header_t *hdr;
-
- hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- if ((au_image[i].type == AU_FIRMWARE) &&
- (au_image[i].size != image_get_data_size (hdr))) {
- printf ("Image %s has wrong size\n", au_image[i].name);
- return -1;
- }
-
- if (nbytes != (image_get_image_size (hdr))) {
- printf ("Image %s bad total SIZE\n", au_image[i].name);
- return -1;
- }
-
- /* check the data CRC */
- if (!image_check_dcrc (hdr)) {
- printf ("Image %s bad data checksum\n", au_image[i].name);
- return -1;
- }
- return 0;
-}
-
-int au_check_header_valid(int i, long nbytes)
-{
- image_header_t *hdr;
-
- hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- /* check the easy ones first */
- if (nbytes < image_get_header_size ()) {
- printf ("Image %s bad header SIZE\n", au_image[i].name);
- return -1;
- }
- if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) {
- printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name);
- return -1;
- }
- if (!image_check_hcrc (hdr)) {
- printf ("Image %s bad header checksum\n", au_image[i].name);
- return -1;
- }
-
- /* check the type - could do this all in one gigantic if() */
- if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) &&
- !image_check_type (hdr, IH_TYPE_FIRMWARE)) {
- printf ("Image %s wrong type\n", au_image[i].name);
- return -1;
- }
- if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) &&
- !image_check_type (hdr, IH_TYPE_SCRIPT)) {
- printf ("Image %s wrong type\n", au_image[i].name);
- return -1;
- }
-
- return 0;
-}
-
-int au_do_update(int i, long sz)
-{
- image_header_t *hdr;
- char *addr;
- long start, end;
- int off, rc;
- uint nbytes;
- int k;
-
- hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- switch (au_image[i].type & AU_TYPEMASK) {
- case AU_SCRIPT:
- printf("Executing script %s\n", au_image[i].name);
-
- /* execute a script */
- if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
- addr = (char *)((char *)hdr + image_get_header_size ());
- /* stick a NULL at the end of the script, otherwise */
- /* parse_string_outer() runs off the end. */
- addr[image_get_data_size (hdr)] = 0;
- addr += 8;
-
- /*
- * Replace cr/lf with ;
- */
- k = 0;
- while (addr[k] != 0) {
- if ((addr[k] == 10) || (addr[k] == 13)) {
- addr[k] = ';';
- }
- k++;
- }
-
- run_command(addr, 0);
- return 0;
- }
-
- break;
-
- case AU_FIRMWARE:
- case AU_NOR:
- case AU_NAND:
- start = au_image[i].start;
- end = au_image[i].start + au_image[i].size - 1;
-
- /*
- * do not update firmware when image is already in flash.
- */
- if (au_image[i].type == AU_FIRMWARE) {
- char *orig = (char*)start;
- char *new = (char *)((char *)hdr +
- image_get_header_size ());
- nbytes = image_get_data_size (hdr);
-
- while (--nbytes) {
- if (*orig++ != *new++) {
- break;
- }
- }
- if (!nbytes) {
- printf ("Skipping firmware update - "
- "images are identical\n");
- break;
- }
- }
-
- /* unprotect the address range */
- if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
- (au_image[i].type == AU_FIRMWARE)) {
- flash_sect_protect (0, start, end);
- }
-
- /*
- * erase the address range.
- */
- if (au_image[i].type != AU_NAND) {
- printf ("Updating NOR FLASH with image %s\n",
- au_image[i].name);
- debug ("flash_sect_erase(%lx, %lx);\n", start, end);
- flash_sect_erase (start, end);
- }
-
- udelay(10000);
-
- /* strip the header - except for the kernel and ramdisk */
- if (au_image[i].type != AU_FIRMWARE) {
- addr = (char *)hdr;
- off = image_get_header_size ();
- nbytes = image_get_image_size (hdr);
- } else {
- addr = (char *)((char *)hdr + image_get_header_size ());
- off = 0;
- nbytes = image_get_data_size (hdr);
- }
-
- /*
- * copy the data from RAM to FLASH
- */
- if (au_image[i].type != AU_NAND) {
- debug ("flash_write(%p, %lx, %x)\n",
- addr, start, nbytes);
- rc = flash_write ((char *)addr, start,
- (nbytes + 1) & ~1);
- } else {
- rc = -1;
- }
- if (rc != 0) {
- printf ("Flashing failed due to error %d\n", rc);
- return -1;
- }
-
- /*
- * check the dcrc of the copy
- */
- if (au_image[i].type != AU_NAND) {
- rc = crc32 (0, (uchar *)(start + off),
- image_get_data_size (hdr));
- }
- if (rc != image_get_dcrc (hdr)) {
- printf ("Image %s Bad Data Checksum After COPY\n",
- au_image[i].name);
- return -1;
- }
-
- /* protect the address range */
- /* this assumes that ONLY the firmware is protected! */
- if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
- (au_image[i].type == AU_FIRMWARE)) {
- flash_sect_protect (1, start, end);
- }
-
- break;
-
- default:
- printf("Wrong image type selected!\n");
- }
-
- return 0;
-}
-
-static void process_macros (const char *input, char *output)
-{
- char c, prev;
- const char *varname_start = NULL;
- int inputcnt = strlen (input);
- int outputcnt = CONFIG_SYS_CBSIZE;
- int state = 0; /* 0 = waiting for '$' */
- /* 1 = waiting for '(' or '{' */
- /* 2 = waiting for ')' or '}' */
- /* 3 = waiting for ''' */
-#ifdef DEBUG_PARSER
- char *output_start = output;
-
- printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n",
- strlen(input), input);
-#endif
-
- prev = '\0'; /* previous character */
-
- while (inputcnt && outputcnt) {
- c = *input++;
- inputcnt--;
-
- if (state != 3) {
- /* remove one level of escape characters */
- if ((c == '\\') && (prev != '\\')) {
- if (inputcnt-- == 0)
- break;
- prev = c;
- c = *input++;
- }
- }
-
- switch (state) {
- case 0: /* Waiting for (unescaped) $ */
- if ((c == '\'') && (prev != '\\')) {
- state = 3;
- break;
- }
- if ((c == '$') && (prev != '\\')) {
- state++;
- } else {
- *(output++) = c;
- outputcnt--;
- }
- break;
- case 1: /* Waiting for ( */
- if (c == '(' || c == '{') {
- state++;
- varname_start = input;
- } else {
- state = 0;
- *(output++) = '$';
- outputcnt--;
-
- if (outputcnt) {
- *(output++) = c;
- outputcnt--;
- }
- }
- break;
- case 2: /* Waiting for ) */
- if (c == ')' || c == '}') {
- int i;
- char envname[CONFIG_SYS_CBSIZE], *envval;
- /* Varname # of chars */
- int envcnt = input - varname_start - 1;
-
- /* Get the varname */
- for (i = 0; i < envcnt; i++) {
- envname[i] = varname_start[i];
- }
- envname[i] = 0;
-
- /* Get its value */
- envval = getenv (envname);
-
- /* Copy into the line if it exists */
- if (envval != NULL)
- while ((*envval) && outputcnt) {
- *(output++) = *(envval++);
- outputcnt--;
- }
- /* Look for another '$' */
- state = 0;
- }
- break;
- case 3: /* Waiting for ' */
- if ((c == '\'') && (prev != '\\')) {
- state = 0;
- } else {
- *(output++) = c;
- outputcnt--;
- }
- break;
- }
- prev = c;
- }
-
- if (outputcnt)
- *output = 0;
-
-#ifdef DEBUG_PARSER
- printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
- strlen (output_start), output_start);
-#endif
-}
-
-/*
- * this is called from board_init() after the hardware has been set up
- * and is usable. That seems like a good time to do this.
- * Right now the return value is ignored.
- */
-int do_auto_update(void)
-{
- block_dev_desc_t *stor_dev = NULL;
- long sz;
- int i, res, old_ctrlc;
- char buffer[32];
- char str[80];
- int n;
-
- if (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) {
- stor_dev = get_dev ("ide", 0);
- if (stor_dev == NULL) {
- debug ("ide: unknown device\n");
- return -1;
- }
- }
-
- if (fat_register_device (stor_dev, 1) != 0) {
- debug ("Unable to register ide disk 0:1\n");
- return -1;
- }
-
- /*
- * Check if magic file is present
- */
- if ((n = do_fat_read (AU_MAGIC_FILE, buffer,
- sizeof(buffer), LS_NO)) <= 0) {
- debug ("No auto_update magic file (n=%d)\n", n);
- return -1;
- }
-
-#ifdef CONFIG_AUTO_UPDATE_SHOW
- board_auto_update_show (1);
-#endif
- puts("\nAutoUpdate Disk detected! Trying to update system...\n");
-
- /* make sure that we see CTRL-C and save the old state */
- old_ctrlc = disable_ctrlc (0);
-
- /* just loop thru all the possible files */
- for (i = 0; i < N_AU_IMAGES; i++) {
- /*
- * Try to expand the environment var in the fname
- */
- process_macros (au_image[i].name, str);
- strcpy (au_image[i].name, str);
-
- printf("Reading %s ...", au_image[i].name);
- /* just read the header */
- sz = do_fat_read (au_image[i].name, LOAD_ADDR,
- image_get_header_size (), LS_NO);
- debug ("read %s sz %ld hdr %d\n",
- au_image[i].name, sz, image_get_header_size ());
- if (sz <= 0 || sz < image_get_header_size ()) {
- puts(" not found\n");
- continue;
- }
- if (au_check_header_valid (i, sz) < 0) {
- puts(" header not valid\n");
- continue;
- }
- sz = do_fat_read (au_image[i].name, LOAD_ADDR,
- MAX_LOADSZ, LS_NO);
- debug ("read %s sz %ld hdr %d\n",
- au_image[i].name, sz, image_get_header_size ());
- if (sz <= 0 || sz <= image_get_header_size ()) {
- puts(" not found\n");
- continue;
- }
- if (au_check_cksum_valid (i, sz) < 0) {
- puts(" checksum not valid\n");
- continue;
- }
- puts(" done\n");
-
- do {
- res = au_do_update (i, sz);
- /* let the user break out of the loop */
- if (ctrlc() || had_ctrlc ()) {
- clear_ctrlc ();
- break;
- }
- } while (res < 0);
- }
-
- /* restore the old state */
- disable_ctrlc (old_ctrlc);
-
- puts("AutoUpdate finished\n\n");
-#ifdef CONFIG_AUTO_UPDATE_SHOW
- board_auto_update_show (0);
-#endif
-
- return 0;
-}
-
-int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- do_auto_update();
-
- return 0;
-}
-U_BOOT_CMD(
- autoupd, 1, 1, auto_update,
- "Automatically update images",
- ""
-);
-#endif /* CONFIG_AUTO_UPDATE */
diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h
deleted file mode 100644
index be8f439..0000000
--- a/board/esd/common/auto_update.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _AUTO_UPDATE_H_
-#define _AUTO_UPDATE_H_
-
-#define MBR_MAGIC 0x07081967
-#define MBR_MAGIC_ADDR 0x100 /* offset 0x100 should be free space */
-
-#define AU_MAGIC_FILE "__auto_update"
-
-#define AU_TYPEMASK 0x000000ff
-#define AU_FLAGMASK 0xffff0000
-
-#define AU_PROTECT 0x80000000
-
-#define AU_SCRIPT 0x01
-#define AU_FIRMWARE (0x02 | AU_PROTECT)
-#define AU_NOR 0x03
-#define AU_NAND 0x04
-
-struct au_image_s {
- char name[80];
- ulong start;
- ulong size;
- ulong type;
-};
-
-typedef struct au_image_s au_image_t;
-
-int do_auto_update(void);
-#ifdef CONFIG_AUTO_UPDATE_SHOW
-void board_auto_update_show(int au_active);
-#endif
-
-#endif /* #ifndef _AUTO_UPDATE_H_ */
diff --git a/board/esd/cpci405/Kconfig b/board/esd/cpci405/Kconfig
index bc56907..0df2755 100644
--- a/board/esd/cpci405/Kconfig
+++ b/board/esd/cpci405/Kconfig
@@ -1,16 +1,3 @@
-if TARGET_CPCI405
-
-config SYS_BOARD
- default "cpci405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "CPCI405"
-
-endif
-
if TARGET_CPCI4052
config SYS_BOARD
@@ -23,29 +10,3 @@
default "CPCI4052"
endif
-
-if TARGET_CPCI405AB
-
-config SYS_BOARD
- default "cpci405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "CPCI405AB"
-
-endif
-
-if TARGET_CPCI405DT
-
-config SYS_BOARD
- default "cpci405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "CPCI405DT"
-
-endif
diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile
index b140571..7490b78 100644
--- a/board/esd/cpci405/Makefile
+++ b/board/esd/cpci405/Makefile
@@ -5,5 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y = cpci405.o flash.o ../common/misc.o ../common/auto_update.o
+obj-y = cpci405.o flash.o ../common/misc.o
obj-y += ../common/cmd_loadpci.o
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index e23ec55..bf5a4cb 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -24,13 +24,7 @@
const unsigned char fpgadata[] =
{
#if defined(CONFIG_CPCI405_VER2)
-# if defined(CONFIG_CPCI405AB)
-# include "fpgadata_cpci405ab.c"
-# else
-# include "fpgadata_cpci4052.c"
-# endif
-#else
-# include "fpgadata_cpci405.c"
+# include "fpgadata_cpci4052.c"
#endif
};
@@ -38,37 +32,6 @@
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
-#include "../common/auto_update.h"
-
-#if defined(CONFIG_CPCI405AB)
-au_image_t au_image[] = {
- {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
- {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
- {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
- {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
- {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
-};
-#else
-#if defined(CONFIG_CPCI405_VER2)
-au_image_t au_image[] = {
- {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
- {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
- {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
- {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
- {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
-};
-#else
-au_image_t au_image[] = {
- {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
- {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
- {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
- {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
- {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
-};
-#endif
-#endif
-
-int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
/* Prototypes */
int cpci405_version(void);
@@ -530,240 +493,3 @@
return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#if defined(CONFIG_CPCI405AB)
-#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_MODE), \
- in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_MODE)) | \
- CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-
-#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_MODE), \
- in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_MODE)) & \
- ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-
-#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_STATUS)) & \
- CONFIG_SYS_FPGA_MODE_1WIRE)
-
-/*
- * Generate a 1-wire reset, return 1 if no presence detect was found,
- * return 0 otherwise.
- * (NOTE: Does not handle alarm presence from DS2404/DS1994)
- */
-int OWTouchReset(void)
-{
- int result;
-
- ONE_WIRE_CLEAR;
- udelay(480);
- ONE_WIRE_SET;
- udelay(70);
-
- result = ONE_WIRE_GET;
-
- udelay(410);
- return result;
-}
-
-/*
- * Send 1 a 1-wire write bit.
- * Provide 10us recovery time.
- */
-void OWWriteBit(int bit)
-{
- if (bit) {
- /*
- * write '1' bit
- */
- ONE_WIRE_CLEAR;
- udelay(6);
- ONE_WIRE_SET;
- udelay(64);
- } else {
- /*
- * write '0' bit
- */
- ONE_WIRE_CLEAR;
- udelay(60);
- ONE_WIRE_SET;
- udelay(10);
- }
-}
-
-/*
- * Read a bit from the 1-wire bus and return it.
- * Provide 10us recovery time.
- */
-int OWReadBit(void)
-{
- int result;
-
- ONE_WIRE_CLEAR;
- udelay(6);
- ONE_WIRE_SET;
- udelay(9);
-
- result = ONE_WIRE_GET;
-
- udelay(55);
- return result;
-}
-
-void OWWriteByte(int data)
-{
- int loop;
-
- for (loop = 0; loop < 8; loop++) {
- OWWriteBit(data & 0x01);
- data >>= 1;
- }
-}
-
-int OWReadByte(void)
-{
- int loop, result = 0;
-
- for (loop = 0; loop < 8; loop++) {
- result >>= 1;
- if (OWReadBit())
- result |= 0x80;
- }
-
- return result;
-}
-
-int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned short val;
- int result;
- int i;
- unsigned char ow_id[6];
- char str[32];
-
- /*
- * Clear 1-wire bit (open drain with pull-up)
- */
- val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
- CONFIG_SYS_FPGA_MODE));
- val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
- out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
- CONFIG_SYS_FPGA_MODE), val);
-
- result = OWTouchReset();
- if (result != 0)
- puts("No 1-wire device detected!\n");
-
- OWWriteByte(0x33); /* send read rom command */
- OWReadByte(); /* skip family code ( == 0x01) */
- for (i = 0; i < 6; i++)
- ow_id[i] = OWReadByte();
- OWReadByte(); /* read crc */
-
- sprintf(str, "%02X%02X%02X%02X%02X%02X",
- ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]);
- printf("Setting environment variable 'ow_id' to %s\n", str);
- setenv("ow_id", str);
-
- return 0;
-}
-U_BOOT_CMD(
- onewire, 1, 1, do_onewire,
- "Read 1-write ID",
- ""
-);
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
-#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
-
-/*
- * Write backplane ip-address...
- */
-int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *buf;
- ulong crc;
- char str[32];
- char *ptr;
- IPaddr_t ipaddr;
-
- buf = malloc(CONFIG_ENV_SIZE_2);
- if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
- (uchar *)buf, CONFIG_ENV_SIZE_2))
- puts("\nError reading backplane EEPROM!\n");
- else {
- crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
- if (crc != *(ulong *)buf) {
- printf("ERROR: crc mismatch %08lx %08lx\n",
- crc, *(ulong *)buf);
- return -1;
- }
-
- /*
- * Find bp_ip
- */
- ptr = strstr(buf+4, "bp_ip=");
- if (ptr == NULL) {
- printf("ERROR: bp_ip not found!\n");
- return -1;
- }
- ptr += 6;
- ipaddr = string_to_ip(ptr);
-
- /*
- * Update whole ip-addr
- */
- sprintf(str, "%pI4", &ipaddr);
- setenv("ipaddr", str);
- printf("Updated ip_addr from bp_eeprom to %s!\n", str);
- }
-
- free(buf);
-
- return 0;
-}
-U_BOOT_CMD(
- getbpip, 1, 1, do_get_bpip,
- "Update IP-Address with Backplane IP-Address",
- ""
-);
-
-/*
- * Set and print backplane ip...
- */
-int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *buf;
- char str[32];
- ulong crc;
-
- if (argc < 2) {
- puts("ERROR!\n");
- return -1;
- }
-
- printf("Setting bp_ip to %s\n", argv[1]);
- buf = malloc(CONFIG_ENV_SIZE_2);
- memset(buf, 0, CONFIG_ENV_SIZE_2);
- sprintf(str, "bp_ip=%s", argv[1]);
- strcpy(buf+4, str);
- crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
- *(ulong *)buf = crc;
-
- if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
- 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
- puts("\nError writing backplane EEPROM!\n");
-
- free(buf);
-
- return 0;
-}
-U_BOOT_CMD(
- setbpip, 2, 1, do_set_bpip,
- "Write Backplane IP-Address",
- ""
-);
-
-#endif /* CONFIG_CPCI405AB */
diff --git a/board/esd/cpci405/fpgadata_cpci405.c b/board/esd/cpci405/fpgadata_cpci405.c
deleted file mode 100644
index 46c2fed..0000000
--- a/board/esd/cpci405/fpgadata_cpci405.c
+++ /dev/null
@@ -1,683 +0,0 @@
-0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
-0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d,
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-0x73, 0x30, 0x35, 0x78, 0x6c, 0x76, 0x71, 0x31,
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-0x0a, 0x0a, 0x28, 0x3c, 0x01, 0x1b, 0x5f, 0xe7,
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diff --git a/board/esd/cpci405/fpgadata_cpci405ab.c b/board/esd/cpci405/fpgadata_cpci405ab.c
deleted file mode 100644
index acbc696..0000000
--- a/board/esd/cpci405/fpgadata_cpci405ab.c
+++ /dev/null
@@ -1,2569 +0,0 @@
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-0x4a, 0xa1, 0x59, 0x81, 0x58, 0x00, 0xdf, 0x28,
-0x2b, 0x49, 0x91, 0x55, 0x85, 0x53, 0xdb, 0x11,
-0x14, 0x4c, 0x7b, 0x35, 0x97, 0x0b, 0x5c, 0x5e,
-0xb2, 0xac, 0xbc, 0x34, 0xba, 0xdf, 0x3f, 0xb7,
-0x7d, 0x03, 0x1a, 0x06, 0x37, 0xfe, 0xfb, 0x71,
-0xb9, 0x6a, 0xec, 0xc6, 0x9f, 0xbc, 0x3c, 0x76,
-0xe6, 0xdc, 0xca, 0xaa, 0xb1, 0xa5, 0xfb, 0xde,
-0xf8, 0xe4, 0x4c, 0x06, 0x97, 0x33, 0xf7, 0x99,
-0x37, 0xb6, 0x64, 0xac, 0x68, 0xec, 0xcc, 0xe8,
-0xc9, 0x79, 0x63, 0x4b, 0x8f, 0xbe, 0x71, 0xfa,
-0x4c, 0x06, 0x97, 0x33, 0x6d, 0xae, 0xe1, 0xb8,
-0x3c, 0x20, 0x70, 0xd9, 0x7f, 0x15, 0xc7, 0xe5,
-0x9b, 0x19, 0x2e, 0x3f, 0x70, 0xd6, 0x69, 0x43,
-0xda, 0x61, 0x1b, 0x54, 0x1a, 0xee, 0xa9, 0xbd,
-0x96, 0xa1, 0xb1, 0x2b, 0x87, 0x99, 0xe1, 0xb4,
-0x41, 0xbf, 0xe5, 0x38, 0xb0, 0x09, 0x46, 0xa6,
-0xd3, 0xed, 0xec, 0x55, 0xe0, 0xe8, 0x33, 0xc9,
-0x70, 0x3e, 0xdc, 0xed, 0x19, 0x30, 0xd5, 0xb4,
-0x0c, 0xbe, 0xc6, 0x0e, 0x73, 0xc3, 0xf9, 0x50,
-0xf1, 0x92, 0x4d, 0x36, 0xbc, 0xa6, 0xd3, 0xe7,
-0x2f, 0x6f, 0x65, 0xf7, 0x98, 0x31, 0x78, 0xfe,
-0xeb, 0xc3, 0x20, 0x8e, 0xa1, 0xc8, 0x6e, 0x4a,
-0xec, 0x36, 0x17, 0xfd, 0x1a, 0x6e, 0x78, 0x7b,
-0xed, 0x36, 0xee, 0x76, 0xb2, 0x0d, 0x76, 0x19,
-0xb3, 0x35, 0xf7, 0xba, 0x30, 0x37, 0xa6, 0x1e,
-0xb4, 0xaf, 0x90, 0x3f, 0xfd, 0xf9, 0xa8, 0x93,
-0x9f, 0x4f, 0xe6, 0x8a, 0xdd, 0x1f, 0x0d, 0x72,
-0x43, 0xf8, 0x34, 0xbe, 0x8f, 0xcf, 0x87, 0x1b,
-0xce, 0xf3, 0xf9, 0x3e, 0x30, 0x99, 0x85, 0x75,
-0x9f, 0x75, 0xa1, 0x2f, 0x7b, 0xce, 0x4e, 0x7f,
-0xb0, 0xf1, 0x7f, 0xf2, 0x7c, 0xf8, 0x7c, 0x7d,
-0xc9, 0x73, 0x76, 0x5a, 0x68, 0xac, 0x46, 0xf7,
-0x65, 0x1f, 0x91, 0xd3, 0xfb, 0x53, 0x3e, 0xb5,
-0xb5, 0x7f, 0xe4, 0x8f, 0x3e, 0xdf, 0x9f, 0x7a,
-0x9b, 0xff, 0xc6, 0x4f, 0xfd, 0xd8, 0xd8, 0x98,
-0x79, 0x71, 0xe3, 0xff, 0xd3, 0x6d, 0x48, 0xf6,
-0x12, 0x1e, 0x6f, 0x64, 0x1a, 0x89, 0xa5, 0x37,
-0xf1, 0x5d, 0x1d, 0xbf, 0x06, 0xff, 0x0b, 0x6b,
-0x59, 0xbb, 0x88, 0xe1, 0x7c, 0xbe, 0x74, 0x2d,
-0xdb, 0x0d, 0xbe, 0x7c, 0x05, 0x66, 0x5a, 0xa9,
-0x99, 0x25, 0xac, 0x4e, 0x58, 0xd4, 0x81, 0x3f,
-0x65, 0x2d, 0x67, 0xda, 0x88, 0xb5, 0xfc, 0x7d,
-0x5c, 0xcb, 0xd6, 0x12, 0x9e, 0xb4, 0x96, 0xd5,
-0x3f, 0xb6, 0x96, 0x9d, 0x36, 0x7f, 0xe4, 0xf9,
-0x8c, 0x5b, 0xcb, 0xc0, 0xd7, 0xb2, 0xb5, 0x84,
-0xad, 0x45, 0x8d, 0x46, 0xaf, 0xf2, 0x27, 0xdf,
-0xe7, 0x4f, 0xf1, 0x75, 0x7f, 0xca, 0x73, 0x86,
-0x0c, 0x71, 0xbe, 0xc8, 0xe7, 0xab, 0xb5, 0xfc,
-0xff, 0xbe, 0x36, 0xff, 0xf9, 0x27, 0x04, 0xba,
-0x44, 0xf8, 0xff, 0x46, 0xae, 0xff, 0x2f, 0xfe,
-0xd3, 0xaf, 0x3e, 0x5f, 0x7d, 0xbe, 0xfa, 0x7c,
-0xf5, 0xf9, 0xea, 0xf3, 0xd5, 0xe7, 0xab, 0xcf,
-0x57, 0x9f, 0xff, 0x5f, 0x7c, 0x78, 0xbc, 0x44,
-0x78, 0xbc, 0x64, 0xfc, 0x3f, 0xdd, 0x97, 0xaf,
-0x3e, 0x5f, 0x7d, 0xbe, 0xfa, 0x7c, 0xf5, 0xf9,
-0xea, 0xf3, 0xd5, 0xe7, 0xab, 0xcf, 0x57, 0x9f,
-0xff, 0xbb, 0x3f, 0x21, 0x2e, 0x0c, 0x7b, 0xa3,
-0x36, 0x04, 0xbc, 0xa8, 0x2b, 0x87, 0xc0, 0xc8,
-0xfb, 0xd3, 0xfe, 0x1d, 0x6f, 0xef, 0x0a, 0x41,
-0x42, 0xca, 0xdc, 0xa7, 0xe7, 0x1f, 0x27, 0xf6,
-0xf5, 0xff, 0x02, 0xd6, 0x2c, 0x67, 0x26, 0xbd,
-0xa4, 0x00, 0x00,
diff --git a/board/esd/cpci5200/Kconfig b/board/esd/cpci5200/Kconfig
deleted file mode 100644
index ddd9418..0000000
--- a/board/esd/cpci5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CPCI5200
-
-config SYS_BOARD
- default "cpci5200"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "cpci5200"
-
-endif
diff --git a/board/esd/cpci5200/MAINTAINERS b/board/esd/cpci5200/MAINTAINERS
deleted file mode 100644
index 184d3cc..0000000
--- a/board/esd/cpci5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CPCI5200 BOARD
-M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S: Maintained
-F: board/esd/cpci5200/
-F: include/configs/cpci5200.h
-F: configs/cpci5200_defconfig
diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile
deleted file mode 100644
index 8421f54..0000000
--- a/board/esd/cpci5200/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-# CPLD = ../common/xilinx_jtag/lenval.o \
-# ../common/xilinx_jtag/micro.o \
-# ../common/xilinx_jtag/ports.o
-
-# obj-y = cpci5200.o flash.o $(CPLD)
-obj-y = cpci5200.o strataflash.o
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
deleted file mode 100644
index 8bded0b..0000000
--- a/board/esd/cpci5200/cpci5200.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * cpci5200.c - main board support/init for the esd cpci5200.
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <command.h>
-#include <netdev.h>
-
-#include "mt46v16m16-75.h"
-
-void init_ata_reset(void);
-
-static void sdram_start(int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register: extended mode */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
- ulong dramsize = 0;
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
- /* set tap delay */
- *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
-
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
- } else {
-#if 0
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
-#else
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
-#endif
- }
-
-#if 0
- /* find RAM size using SDRAM CS1 only */
- sdram_start(0);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(1);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(0);
-#endif
- /* set SDRAM CS1 size according to the amount of RAM found */
-
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
- init_ata_reset();
- return (dramsize);
-}
-
-int checkboard(void)
-{
- puts("Board: esd CPCI5200 (cpci5200)\n");
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
- if (size == 0x02000000) {
- /* adjust mapping */
- *(vu_long *) MPC5XXX_BOOTCS_START =
- *(vu_long *) MPC5XXX_CS0_START =
- START_REG(CONFIG_SYS_BOOTCS_START | size);
- *(vu_long *) MPC5XXX_BOOTCS_STOP =
- *(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
- }
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void) {
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-
-void init_ide_reset(void)
-{
- debug("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset(int idereset)
-{
- debug("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
- }
-}
-#endif
-
-#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
-
-#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
-
-#define GPIO_WU6 0x40000000UL
-#define GPIO_USB0 0x00010000UL
-#define GPIO_USB9 0x08000000UL
-#define GPIO_USB9S 0x00080000UL
-
-void init_ata_reset(void)
-{
- debug("init_ata_reset\n");
-
- /* Configure GPIO_WU6 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
- __asm__ volatile ("sync");
-
- if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
- __asm__ volatile ("sync");
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
-int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int addr;
- unsigned int size;
- int i;
- volatile unsigned long *ptr;
-
- addr = simple_strtol(argv[1], NULL, 16);
- size = simple_strtol(argv[2], NULL, 16);
-
- printf("\nWriting at addr %08x, size %08x.\n", addr, size);
-
- while (1) {
- ptr = (volatile unsigned long *)addr;
- for (i = 0; i < (size >> 2); i++) {
- *ptr++ = i;
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
- putc('.');
- }
- return 0;
-}
-
-U_BOOT_CMD(writepci, 3, 1, do_writepci,
- "Write some data to pcibus",
- "<addr> <size>\n"
- ""
-);
diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h
deleted file mode 100644
index 63a4032..0000000
--- a/board/esd/cpci5200/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x705f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c
deleted file mode 100644
index 7dc2e58..0000000
--- a/board/esd/cpci5200/strataflash.c
+++ /dev/null
@@ -1,786 +0,0 @@
-/*
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-
-#undef DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for U-Boot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI 0x98
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xD0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xD0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
-
-#define FLASH_STATUS_DONE 0x80
-#define FLASH_STATUS_ESS 0x40
-#define FLASH_STATUS_ECLBS 0x20
-#define FLASH_STATUS_PSLBS 0x10
-#define FLASH_STATUS_VPENS 0x08
-#define FLASH_STATUS_PSS 0x04
-#define FLASH_STATUS_DPS 0x02
-#define FLASH_STATUS_R 0x01
-#define FLASH_STATUS_PROTECT 0x01
-
-#define FLASH_OFFSET_CFI 0x55
-#define FLASH_OFFSET_CFI_RESP 0x10
-#define FLASH_OFFSET_WTOUT 0x1F
-#define FLASH_OFFSET_WBTOUT 0x20
-#define FLASH_OFFSET_ETOUT 0x21
-#define FLASH_OFFSET_CETOUT 0x22
-#define FLASH_OFFSET_WMAX_TOUT 0x23
-#define FLASH_OFFSET_WBMAX_TOUT 0x24
-#define FLASH_OFFSET_EMAX_TOUT 0x25
-#define FLASH_OFFSET_CEMAX_TOUT 0x26
-#define FLASH_OFFSET_SIZE 0x27
-#define FLASH_OFFSET_INTERFACE 0x28
-#define FLASH_OFFSET_BUFFER_SIZE 0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
-#define FLASH_OFFSET_ERASE_REGIONS 0x2D
-#define FLASH_OFFSET_PROTECT 0x02
-#define FLASH_OFFSET_USER_PROTECTION 0x85
-#define FLASH_OFFSET_INTEL_PROTECTION 0x81
-
-#define FLASH_MAN_CFI 0x01000000
-
-typedef union {
- unsigned char c;
- unsigned short w;
- unsigned long l;
-} cfiword_t;
-
-typedef union {
- unsigned char *cp;
- unsigned short *wp;
- unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size(ulong base, int banknum);
-static int flash_write_cfiword(flash_info_t * info, ulong dest,
- cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector,
- ulong tout, char *prompt);
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
- int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
-{
- return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
-}
-
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
-{
- uchar *cp;
- cp = flash_make_addr(info, 0, offset);
- return (cp[info->portwidth - 1]);
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
-{
- uchar *addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ((addr[(2 * info->portwidth) - 1] << 8) |
- addr[info->portwidth - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
-{
- uchar *addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ((addr[(2 * info->portwidth) - 1] << 24) |
- (addr[(info->portwidth) - 1] << 16) |
- (addr[(4 * info->portwidth) - 1] << 8) |
- addr[(3 * info->portwidth) - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init(void)
-{
- unsigned long size;
- int i;
- unsigned long address;
-
- /* The flash is positioned back to back, with the demultiplexing of the chip
- * based on the A24 address line.
- *
- */
-
- address = CONFIG_SYS_FLASH_BASE;
- size = 0;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- size += flash_info[i].size = flash_get_size(address, i);
- address += CONFIG_SYS_FLASH_INCREMENT;
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf
- ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, flash_info[0].size, flash_info[i].size << 20);
- }
- }
-
-#if 0 /* test-only */
- /* Monitor protection ON by default */
-#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
- for (i = 0;
- flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
- i++)
- (void)flash_real_protect(&flash_info[0], i, 1);
-#endif
-#endif
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- int rcode = 0;
- int prot;
- int sect;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
- if ((s_first < 0) || (s_first > s_last)) {
- printf("- no sectors to erase\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
-
- if (flash_full_status_check
- (info, sect, info->erase_blk_tout, "erase")) {
- rcode = 1;
- } else
- printf(".");
- }
- }
- printf(" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
- int i;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- printf("CFI conformant FLASH (%d x %d)",
- (info->portwidth << 3), (info->chipwidth << 3));
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf
- (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
- info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
- info->buffer_size);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n");
- printf(" %08lX%5s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong wp;
- ulong cp;
- int aln;
- cfiword_t cword;
- int i, rc;
-
- /* get lower aligned address */
- wp = (addr & ~(info->portwidth - 1));
-
- /* handle unaligned start */
- if ((aln = addr - wp) != 0) {
- cword.l = 0;
- cp = wp;
- for (i = 0; i < aln; ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *) cp));
-
- for (; (i < info->portwidth) && (cnt > 0); i++) {
- flash_add_byte(info, &cword, *src++);
- cnt--;
- cp++;
- }
- for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *) cp));
- if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp = cp;
- }
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- while (cnt >= info->portwidth) {
- i = info->buffer_size > cnt ? cnt : info->buffer_size;
- if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
- return rc;
- wp += i;
- src += i;
- cnt -= i;
- }
-#else
- /* handle the aligned part */
- while (cnt >= info->portwidth) {
- cword.l = 0;
- for (i = 0; i < info->portwidth; i++) {
- flash_add_byte(info, &cword, *src++);
- }
- if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp += info->portwidth;
- cnt -= info->portwidth;
- }
-#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- cword.l = 0;
- for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
- flash_add_byte(info, &cword, *src++);
- --cnt;
- }
- for (; i < info->portwidth; ++i, ++cp) {
- flash_add_byte(info, &cword, (*(uchar *) cp));
- }
-
- return flash_write_cfiword(info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect(flash_info_t * info, long sector, int prot)
-{
- int retcode = 0;
-
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
- if (prot)
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
- if ((retcode =
- flash_full_status_check(info, sector, info->erase_blk_tout,
- prot ? "protect" : "unprotect")) == 0) {
-
- info->protect[sector] = prot;
- /* Intel's unprotect unprotects all locking */
- if (prot == 0) {
- int i;
- for (i = 0; i < info->sector_count; i++) {
- if (info->protect[i])
- flash_real_protect(info, i, 1);
- }
- }
- }
-
- return retcode;
-}
-
-/*-----------------------------------------------------------------------
- * wait for XSR.7 to be set. Time out with an error if it does not.
- * This routine does not set the flash to read-array mode.
- */
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
- char *prompt)
-{
- ulong start;
-
- /* Wait for command completion */
- start = get_timer(0);
- while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
- if (get_timer(start) > info->erase_blk_tout) {
- printf("Flash %s timeout at address %lx\n", prompt,
- info->start[sector]);
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return ERR_TIMOUT;
- }
- }
- return ERR_OK;
-}
-
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check(flash_info_t * info, ulong sector,
- ulong tout, char *prompt)
-{
- int retcode;
- retcode = flash_status_check(info, sector, tout, prompt);
- if ((retcode == ERR_OK)
- && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
- printf("Flash %s error at address %lx\n", prompt,
- info->start[sector]);
- if (flash_isset
- (info, sector, 0,
- FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
- printf("Command Sequence Error.\n");
- } else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
- printf("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
- } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
- printf("Locking Error\n");
- }
- if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
- printf("Block locked.\n");
- retcode = ERR_PROTECTED;
- }
- if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
- printf("Vpp Low Error.\n");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return retcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
-{
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cword->c = c;
- break;
- case FLASH_CFI_16BIT:
- cword->w = (cword->w << 8) | c;
- break;
- case FLASH_CFI_32BIT:
- cword->l = (cword->l << 8) | c;
- }
-}
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
-{
- int i;
- uchar *cp = (uchar *) cmdbuf;
- for (i = 0; i < info->portwidth; i++)
- *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
- uchar cmd)
-{
-
- volatile cfiptr_t addr;
- cfiword_t cword;
- addr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- *addr.cp = cword.c;
- break;
- case FLASH_CFI_16BIT:
- *addr.wp = cword.w;
- break;
- case FLASH_CFI_32BIT:
- *addr.lp = cword.l;
- break;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = (cptr.cp[0] == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = (cptr.wp[0] == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = (cptr.lp[0] == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
- */
-static int flash_detect_cfi(flash_info_t * info)
-{
-
- for (info->portwidth = FLASH_CFI_8BIT;
- info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
- for (info->chipwidth = FLASH_CFI_BY8;
- info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
- FLASH_CMD_CFI);
- if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
- && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
- 'R')
- && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
- 'Y'))
- return 1;
- }
- }
- return 0;
-}
-
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size(ulong base, int banknum)
-{
- flash_info_t *info = &flash_info[banknum];
- int i, j;
- int sect_cnt;
- unsigned long sector;
- unsigned long tmp;
- int size_ratio = 0;
- uchar num_erase_regions;
- int erase_region_size;
- int erase_region_count;
-
- info->start[0] = base;
-#if 0
- invalidate_dcache_range(base, base + 0x400);
-#endif
- if (flash_detect_cfi(info)) {
-
- size_ratio = info->portwidth / info->chipwidth;
- num_erase_regions =
- flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-
- sect_cnt = 0;
- sector = base;
- for (i = 0; i < num_erase_regions; i++) {
- if (i > NUM_ERASE_REGIONS) {
- printf("%d erase regions found, only %d used\n",
- num_erase_regions, NUM_ERASE_REGIONS);
- break;
- }
- tmp =
- flash_read_long(info, 0,
- FLASH_OFFSET_ERASE_REGIONS);
- erase_region_size =
- (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
- tmp >>= 16;
- erase_region_count = (tmp & 0xffff) + 1;
- for (j = 0; j < erase_region_count; j++) {
- info->start[sect_cnt] = sector;
- sector += (erase_region_size * size_ratio);
- info->protect[sect_cnt] =
- flash_isset(info, sect_cnt,
- FLASH_OFFSET_PROTECT,
- FLASH_STATUS_PROTECT);
- sect_cnt++;
- }
- }
-
- info->sector_count = sect_cnt;
- /* multiply the size by the number of chips */
- info->size =
- (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
- size_ratio;
- info->buffer_size =
- (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout =
- (tmp *
- (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
- info->buffer_write_tout =
- (tmp *
- (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
- info->write_tout =
- (tmp *
- (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
- 1000;
- info->flash_id = FLASH_MAN_CFI;
- }
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-#ifdef DEBUG_FLASH
- printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
-#ifdef DEBUG_FLASH
- printf("found %d erase regions\n", num_erase_regions);
-#endif
-#ifdef DEBUG_FLASH
- printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
-#endif
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
-{
-
- cfiptr_t cptr;
- int flag;
-
- cptr.cp = (uchar *)dest;
-
- /* Check if Flash is (sufficiently) erased */
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- flag = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- flag = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- return 2;
- }
- if (!flag)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
-
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cptr.cp[0] = cword.c;
- break;
- case FLASH_CFI_16BIT:
- cptr.wp[0] = cword.w;
- break;
- case FLASH_CFI_32BIT:
- cptr.lp[0] = cword.l;
- break;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- return flash_full_status_check(info, 0, info->write_tout, "write");
-}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector(flash_info_t * info, ulong addr)
-{
- int sector;
- for (sector = info->sector_count - 1; sector >= 0; sector--) {
- if (addr >= info->start[sector])
- break;
- }
- return sector;
-}
-
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
- int len)
-{
-
- int sector;
- int cnt;
- int retcode;
- volatile cfiptr_t src;
- volatile cfiptr_t dst;
-
- src.cp = cp;
- dst.cp = (uchar *) dest;
- sector = find_sector(info, dest);
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
- while (cnt-- > 0) {
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- *dst.lp++ = *src.lp++;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- }
- flash_write_cmd(info, sector, 0,
- FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode =
- flash_full_status_check(info, sector,
- info->buffer_write_tout,
- "buffer write");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- return retcode;
-}
-#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/cpciiser4/Kconfig b/board/esd/cpciiser4/Kconfig
deleted file mode 100644
index 4079b2f..0000000
--- a/board/esd/cpciiser4/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CPCIISER4
-
-config SYS_BOARD
- default "cpciiser4"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "CPCIISER4"
-
-endif
diff --git a/board/esd/cpciiser4/MAINTAINERS b/board/esd/cpciiser4/MAINTAINERS
deleted file mode 100644
index 85743db..0000000
--- a/board/esd/cpciiser4/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CPCIISER4 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/cpciiser4/
-F: include/configs/CPCIISER4.h
-F: configs/CPCIISER4_defconfig
diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile
deleted file mode 100644
index b8d6bea..0000000
--- a/board/esd/cpciiser4/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpciiser4.o flash.o ../common/misc.o
diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c
deleted file mode 100644
index e61cd5b..0000000
--- a/board/esd/cpciiser4/cpciiser4.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * (C) Copyright 2000
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include "cpciiser4.h"
-#include <asm/processor.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-
-/* ------------------------------------------------------------------------- */
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-#if 0
-#define FPGA_DEBUG2
-#endif
-
-/* fpga configuration data - generated by bin2cc */
-const unsigned char fpgadata[] = {
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-int board_early_init_f (void)
-{
- int index, len, i;
- int status;
-
-#ifdef FPGA_DEBUG
- /* set up serial port with default baudrate */
- (void) get_clocks ();
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init ();
- console_init_f ();
-#endif
-
- /*
- * Boot onboard FPGA
- */
- status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
- if (status != 0) {
- /* booting FPGA failed */
-#ifndef FPGA_DEBUG
- /* set up serial port with default baudrate */
- (void) get_clocks ();
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init ();
- console_init_f ();
-#endif
- printf ("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf ("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpgadata[index];
- printf ("FPGA: %s\n", &(fpgadata[index + 1]));
- index += len + 3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i = 20; i > 0; i--) {
- printf ("Rebooting in %2d seconds \r", i);
- for (index = 0; index < 1000; index++)
- udelay (1000);
- }
- putc ('\n');
- do_reset (NULL, 0, 0, NULL);
- }
-
- /*
- * Init FPGA via RESET (read access on CS3)
- */
- in_8((void *)0xf0200000);
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- /* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */
- mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- int index;
- int len;
- char str[64];
- int i = getenv_f("serial#", str, sizeof (str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming AR405");
- } else {
- puts(str);
- }
-
- puts ("\nFPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpgadata[index];
- printf ("%s ", &(fpgadata[index + 1]));
- index += len + 3;
- }
-
- putc ('\n');
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
- return 0;
-}
diff --git a/board/esd/cpciiser4/cpciiser4.h b/board/esd/cpciiser4/cpciiser4.h
deleted file mode 100644
index 75e7950..0000000
--- a/board/esd/cpciiser4/cpciiser4.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c
deleted file mode 100644
index 34bdc05..0000000
--- a/board/esd/cpciiser4/flash.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
- mtdcr(EBC0_CFGDATA, pbcr);
- /* printf("PB1CR = %x\n", pbcr); */
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -monitor_flash_len,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/cpciiser4/fpgadata.c b/board/esd/cpciiser4/fpgadata.c
deleted file mode 100644
index ac6122d..0000000
--- a/board/esd/cpciiser4/fpgadata.c
+++ /dev/null
@@ -1,4136 +0,0 @@
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-0x02, 0x06, 0x02, 0x06, 0x02, 0x01, 0x01, 0xe5,
-0x9f, 0xe6, 0x66, 0x09, 0x05, 0x03, 0x05, 0x03,
-0x05, 0x09, 0x98, 0xe8, 0x76, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x03, 0x03, 0xe5, 0x98, 0x01, 0xe5,
-0x0d, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x04, 0x01, 0xe5, 0xe5, 0x05, 0xe5,
-0xe5, 0x03, 0x01, 0xe5, 0xe5, 0x05, 0x02, 0x0b,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x0d, 0xe5, 0x01,
-0xe5, 0x01, 0x6d, 0xe5, 0xe5, 0x04, 0xe6, 0xe5,
-0x05, 0xe5, 0xe5, 0x04, 0xe5, 0x9b, 0x02, 0x01,
-0x01, 0x6d, 0x06, 0x04, 0x04, 0x02, 0x06, 0x04,
-0xa0, 0x03, 0x01, 0x74, 0x01, 0x07, 0x01, 0x07,
-0x09, 0x97, 0x01, 0x02, 0xe5, 0x27, 0x42, 0x09,
-0x09, 0x09, 0x09, 0x9a, 0x03, 0x71, 0x05, 0x03,
-0x09, 0x06, 0xa1, 0xe6, 0xe5, 0x14, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x01, 0x05, 0xe5, 0x01, 0x05, 0xe5, 0x01,
-0x05, 0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x06, 0xe5, 0x01, 0x71, 0x09, 0x09, 0x09, 0x9e,
-0xe8, 0x72, 0x09, 0x09, 0x09, 0x9c, 0x03, 0x91,
-0x08, 0x93, 0x02, 0xe5, 0x2d, 0x3d, 0x09, 0x09,
-0x09, 0x04, 0x04, 0x9a, 0xe5, 0xe5, 0x66, 0x01,
-0xe5, 0x05, 0x09, 0x01, 0xe5, 0x05, 0x09, 0x12,
-0x8b, 0xe5, 0xe6, 0xe5, 0x0e, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x06, 0xe5, 0xe5, 0x06, 0x01, 0x04,
-0x02, 0x01, 0x04, 0x02, 0xe8, 0x01, 0x02, 0x01,
-0xe5, 0x02, 0x02, 0x01, 0x02, 0xe5, 0x02, 0x01,
-0x04, 0x04, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x05,
-0x01, 0xe5, 0x05, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x08, 0x01, 0xe6, 0xe5, 0x3c, 0x35, 0x01, 0x09,
-0x0e, 0x9f, 0x01, 0xe7, 0x36, 0xe3, 0x12, 0xe5,
-0xe7, 0x46, 0x13, 0x17, 0x25, 0x8a, 0x0a, 0xe5,
-0xe5, 0x1c, 0x48, 0x0c, 0x09, 0x07, 0xe5, 0x07,
-0xa0, 0xe6, 0x47, 0x1b, 0x12, 0x0c, 0x0d, 0x06,
-0x3c, 0x5b, 0x5c, 0x03, 0x0f, 0xe5, 0x08, 0x0a,
-0xe5, 0x10, 0x16, 0xe5, 0x05, 0x6d, 0x07, 0xe5,
-0x01, 0x63, 0x21, 0x13, 0x15, 0x7e, 0x02, 0xe5,
-0x61, 0x13, 0x01, 0x0c, 0x13, 0x11, 0x05, 0x7d,
-0xe5, 0xe5, 0x91, 0x06, 0x94, 0xe5, 0x01, 0x8a,
-0x0d, 0xe5, 0x93, 0x02, 0xe5, 0x61, 0x24, 0x12,
-0x06, 0x05, 0x27, 0x09, 0x57, 0xe6, 0x37, 0x32,
-0x1b, 0x1d, 0xe5, 0x24, 0x01, 0x08, 0x54, 0xe5,
-0x01, 0xe5, 0x3a, 0x49, 0x21, 0x25, 0x60, 0xe5,
-0xe6, 0x02, 0x09, 0xe7, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x03, 0xe5, 0x01, 0xe5, 0x07, 0xe5, 0x05, 0xe7,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x05, 0xe7,
-0x09, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x01, 0x09, 0xe5, 0x01,
-0xe5, 0x0d, 0x01, 0x09, 0x09, 0x09, 0x09, 0x02,
-0x06, 0x02, 0x06, 0x07, 0x01, 0x09, 0x07, 0x01,
-0x05, 0x03, 0x09, 0x09, 0x07, 0x01, 0x0b, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x02, 0x0a, 0x03, 0x0f,
-0x05, 0x03, 0x09, 0x09, 0x09, 0x04, 0x04, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x0a, 0x11, 0x02,
-0xe5, 0x11, 0xe5, 0x03, 0x03, 0x09, 0x1d, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x11, 0xe5, 0x97,
-0x8b, 0x09, 0x01, 0xe6, 0x0e, 0x05, 0x03, 0x09,
-0x09, 0x09, 0x09, 0x04, 0x04, 0x09, 0x09, 0x04,
-0x04, 0x09, 0x06, 0x02, 0x09, 0x09, 0x06, 0x01,
-0x02, 0x09, 0x09, 0x05, 0x03, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0e,
-0xe5, 0x01, 0x0d, 0xe5, 0x05, 0x01, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x06, 0xe6, 0x07, 0xe5, 0x09,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x05, 0x01, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x10, 0xe6, 0x02, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x08, 0xe5,
-0x08, 0x03, 0x05, 0x09, 0x03, 0x05, 0x09, 0x01,
-0x07, 0x0b, 0x01, 0x07, 0x09, 0x01, 0x07, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x0b, 0x05, 0xe5, 0xe5, 0x0d, 0xe5, 0xe5,
-0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
-0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
-0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
-0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
-0xe5, 0x05, 0x09, 0x02, 0x08, 0xe5, 0x07, 0x02,
-0x06, 0xe5, 0x07, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
-0x05, 0x02, 0x06, 0x02, 0x06, 0xe5, 0xe5, 0x05,
-0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
-0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
-0xe5, 0x0b, 0x01, 0x01, 0x0e, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x0f, 0xe6, 0xe5, 0x86, 0x09, 0x15, 0x27, 0x09,
-0x4e, 0x05, 0xe5, 0x01, 0x0e, 0x09, 0x09, 0x09,
-0x09, 0x13, 0x13, 0x05, 0x03, 0x09, 0x09, 0x09,
-0x09, 0x08, 0x02, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x07, 0xe6, 0x3f, 0x13, 0x10, 0x33, 0x1d,
-0x76, 0x03, 0x10, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03, 0x05,
-0x09, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03,
-0x05, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x0e, 0xe7, 0x03, 0x37, 0x03, 0x05, 0x0d, 0x0f,
-0xe5, 0x33, 0x1c, 0x72, 0x03, 0xe6, 0xe5, 0x37,
-0x09, 0x13, 0x42, 0xe5, 0x8e, 0x04, 0xe7, 0x3f,
-0x13, 0x44, 0x90, 0x03, 0xe6, 0xe5, 0x8f, 0x9d,
-0x03, 0x13, 0x09, 0x09, 0x09, 0x1d, 0x09, 0x0c,
-0x06, 0x09, 0x09, 0x36, 0x06, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x15, 0x01,
-0xe5, 0x35, 0x05, 0x03, 0x05, 0x0d, 0x0f, 0x2a,
-0x97, 0x06, 0x02, 0xe5, 0x98, 0x8e, 0x05, 0x03,
-0xe3, 0x50, 0x14, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x02,
-0xe5, 0x04, 0xe6, 0x01, 0xe5, 0x04, 0x09, 0xe8,
-0x04, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03, 0x05,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03, 0x0f,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x03, 0x05, 0x09, 0x09, 0x08, 0xe5, 0x06, 0xe6,
-0x05, 0xe5, 0xe7, 0x07, 0xe5, 0x05, 0xe7, 0x08,
-0x09, 0x08, 0xe5, 0x07, 0xe5, 0x08, 0x07, 0xe6,
-0x08, 0x09, 0x09, 0x09, 0x09, 0x0f, 0x01, 0xe5,
-0x38, 0x09, 0x13, 0x0a, 0x36, 0x95, 0x02, 0x0d,
-0x09, 0x09, 0x09, 0x09, 0x04, 0x04, 0x03, 0xe5,
-0x03, 0x09, 0x03, 0x05, 0x04, 0x04, 0x09, 0x09,
-0x11, 0x09, 0x0b, 0x09, 0x09, 0x01, 0x09, 0x1d,
-0x0b, 0x07, 0x09, 0x09, 0x09, 0x09, 0x0f, 0x01,
-0xe7, 0x0a, 0x02, 0x07, 0x01, 0x07, 0x01, 0x07,
-0x01, 0x07, 0x03, 0x02, 0x02, 0x03, 0x01, 0xe5,
-0x01, 0x01, 0x07, 0x03, 0x05, 0x01, 0x04, 0x02,
-0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x02, 0x04,
-0x15, 0x04, 0x0e, 0x03, 0x07, 0x01, 0x07, 0x02,
-0x06, 0x02, 0x06, 0x01, 0x07, 0x09, 0x01, 0x07,
-0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
-0x05, 0xe6, 0xe5, 0xe5, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff,
diff --git a/board/esd/dp405/Kconfig b/board/esd/dp405/Kconfig
deleted file mode 100644
index c0163ae..0000000
--- a/board/esd/dp405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DP405
-
-config SYS_BOARD
- default "dp405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "DP405"
-
-endif
diff --git a/board/esd/dp405/MAINTAINERS b/board/esd/dp405/MAINTAINERS
deleted file mode 100644
index 6833d8c..0000000
--- a/board/esd/dp405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DP405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/dp405/
-F: include/configs/DP405.h
-F: configs/DP405_defconfig
diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile
deleted file mode 100644
index cfcfb66..0000000
--- a/board/esd/dp405/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-CPLD = ../common/xilinx_jtag/lenval.o \
- ../common/xilinx_jtag/micro.o \
- ../common/xilinx_jtag/ports.o
-
-obj-y = dp405.o flash.o ../common/misc.o $(CPLD)
diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c
deleted file mode 100644
index 730ff21..0000000
--- a/board/esd/dp405/dp405.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- /*
- * Reset CPLD via GPIO13 (CS4) pin
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13));
- udelay(1000); /* wait 1ms */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | (0x80000000 >> 13));
- udelay(1000); /* wait 1ms */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
- unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
- 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
- unsigned char id1, id2, rev;
-
- puts ("Board: ");
-
- if (i == -1)
- puts ("### No HW ID - assuming DP405");
- else
- puts(str);
-
- id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
- id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
-
- rev = in_8((void *)0xf0001000);
- if (rev & 0x10) /* old DP405 compatibility */
- rev = in_8((void *)0xf0000800);
-
- switch (rev & 0xc0) {
- case 0x00:
- puts(" (HW=DP405");
- break;
- case 0x80:
- puts(" (HW=DP405/CO");
- break;
- case 0xc0:
- puts(" (HW=DN405");
- break;
- }
- printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
-
- if ((rev & 0xc0) == 0xc0) {
- printf(", C5V=%s",
- in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
- }
- puts(")\n");
-
- return 0;
-}
diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/dp405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/du405/Kconfig b/board/esd/du405/Kconfig
deleted file mode 100644
index 2913fb9..0000000
--- a/board/esd/du405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DU405
-
-config SYS_BOARD
- default "du405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "DU405"
-
-endif
diff --git a/board/esd/du405/MAINTAINERS b/board/esd/du405/MAINTAINERS
deleted file mode 100644
index 5eff2a4..0000000
--- a/board/esd/du405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DU405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/du405/
-F: include/configs/DU405.h
-F: configs/DU405_defconfig
diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile
deleted file mode 100644
index 7914eab..0000000
--- a/board/esd/du405/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = du405.o flash.o ../common/misc.o
diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
deleted file mode 100644
index 8f5f4d0..0000000
--- a/board/esd/du405/du405.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include "du405.h"
-#include <asm/processor.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-i2c.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-#if 0
-#define FPGA_DEBUG2
-#endif
-
-/* fpga configuration data - generated by bin2cc */
-const unsigned char fpgadata[] = {
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-int board_early_init_f (void)
-{
- int index, len, i;
- int status;
-
-#ifdef FPGA_DEBUG
- /* set up serial port with default baudrate */
- (void) get_clocks ();
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init ();
- console_init_f ();
-#endif
-
- /*
- * Boot onboard FPGA
- */
- status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
- if (status != 0) {
- /* booting FPGA failed */
-#ifndef FPGA_DEBUG
- /* set up serial port with default baudrate */
- (void) get_clocks ();
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init ();
- console_init_f ();
-#endif
- printf ("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf ("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpgadata[index];
- printf ("FPGA: %s\n", &(fpgadata[index + 1]));
- index += len + 3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i = 20; i > 0; i--) {
- printf ("Rebooting in %2d seconds \r", i);
- for (index = 0; index < 1000; index++)
- udelay (1000);
- }
- putc ('\n');
- do_reset (NULL, 0, 0, NULL);
- }
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
- * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
- * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 100 us
- */
- mtebc (EBC0_CFG, 0xb8400000);
-
- return 0;
-}
-
-
-int misc_init_r (void)
-{
- unsigned long CPC0_CR0Reg;
-
- /*
- * Setup UART1 handshaking: use CTS instead of DSR
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- int index;
- int len;
- char str[64];
- int i = getenv_f("serial#", str, sizeof (str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming DU405");
- } else {
- puts (str);
- }
-
- puts ("\nFPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpgadata[index];
- printf ("%s ", &(fpgadata[index + 1]));
- index += len + 3;
- }
-
- putc ('\n');
-
- /*
- * Reset external DUART via FPGA
- */
- out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */
- out_8((void *)FPGA_MODE_REG, 0x00); /* low again */
-
- return 0;
-}
-
-void reset_phy(void)
-{
-#if defined(CONFIG_LXT971_NO_SLEEP)
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
diff --git a/board/esd/du405/du405.h b/board/esd/du405/du405.h
deleted file mode 100644
index 292f196..0000000
--- a/board/esd/du405/du405.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c
deleted file mode 100644
index 5650e5e..0000000
--- a/board/esd/du405/flash.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- base_b0 = FLASH_BASE0_PRELIM;
- size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- base_b1 = FLASH_BASE1_PRELIM;
- size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1) {
- mtdcr (EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr (EBC0_CFGDATA);
- mtdcr (EBC0_CFGADDR, PB0CR);
- base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 |
- (((size_b1 / 1024 / 1024) - 1) << 17);
- mtdcr (EBC0_CFGDATA, pbcr);
- /* printf("PB1CR = %x\n", pbcr); */
- }
-
- if (size_b0) {
- mtdcr (EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr (EBC0_CFGDATA);
- mtdcr (EBC0_CFGADDR, PB1CR);
- base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 |
- (((size_b0 / 1024 / 1024) - 1) << 17);
- mtdcr (EBC0_CFGDATA, pbcr);
- /* printf("PB0CR = %x\n", pbcr); */
- }
-
- size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- base_b0 + size_b0 - monitor_flash_len,
- base_b0 + size_b0 - 1, &flash_info[0]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- base_b1 + size_b1 - monitor_flash_len,
- base_b1 + size_b1 - 1, &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- flash_protect (FLAG_PROTECT_CLEAR,
- base_b0 + size_b0 - monitor_flash_len,
- base_b0 + size_b0 - 1, &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- return (size_b0 + size_b1);
-}
diff --git a/board/esd/du405/fpgadata.c b/board/esd/du405/fpgadata.c
deleted file mode 100644
index 262f2ca..0000000
--- a/board/esd/du405/fpgadata.c
+++ /dev/null
@@ -1,1405 +0,0 @@
-0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
-0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d,
-0x64, 0x75, 0x72, 0x61, 0x67, 0x34, 0x30, 0x35,
-0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b,
-0x73, 0x32, 0x30, 0x78, 0x6c, 0x74, 0x71, 0x31,
-0x34, 0x34, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30,
-0x30, 0x32, 0x2f, 0x30, 0x32, 0x2f, 0x32, 0x31,
-0x00, 0x64, 0x00, 0x09, 0x31, 0x32, 0x3a, 0x35,
-0x31, 0x3a, 0x30, 0x38, 0x00, 0x65, 0xe2, 0x01,
-0x00, 0x00, 0x2b, 0x98, 0xff, 0x30, 0xe6, 0xe5,
-0xe5, 0x02, 0x04, 0x01, 0xe6, 0x04, 0x01, 0x0d,
-0x04, 0x04, 0x02, 0x01, 0x04, 0x04, 0x03, 0x07,
-0x01, 0x03, 0x01, 0x04, 0x11, 0x01, 0x06, 0x02,
-0x15, 0x09, 0x02, 0x05, 0x07, 0x02, 0x02, 0x01,
-0x09, 0x03, 0x07, 0x01, 0x03, 0x01, 0x0b, 0x05,
-0x03, 0x01, 0x07, 0x08, 0xe5, 0xe5, 0x24, 0x05,
-0x09, 0x11, 0x01, 0x03, 0x03, 0x05, 0x0d, 0x09,
-0x0b, 0x09, 0x01, 0x1d, 0x09, 0x13, 0x03, 0x05,
-0x12, 0xe6, 0x11, 0x01, 0x03, 0x02, 0x02, 0x03,
-0x03, 0x01, 0x15, 0x01, 0x02, 0x28, 0x01, 0x05,
-0x02, 0xe5, 0xe5, 0x02, 0x02, 0x02, 0x0d, 0x02,
-0x02, 0x03, 0x02, 0xe5, 0xe5, 0x14, 0x01, 0x02,
-0xe5, 0x12, 0x0b, 0x03, 0x0f, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x04, 0x01, 0x02, 0x06, 0x02, 0x09,
-0x06, 0xe7, 0x05, 0x04, 0x06, 0x02, 0x06, 0x02,
-0x09, 0x07, 0xe6, 0x08, 0x09, 0x07, 0xe6, 0x08,
-0x09, 0x0e, 0xe5, 0xe6, 0x0d, 0x05, 0xe5, 0x01,
-0x05, 0xe5, 0x01, 0x05, 0xe5, 0x07, 0x09, 0xe5,
-0x01, 0x05, 0xe5, 0x07, 0xe6, 0xe5, 0x04, 0x03,
-0x05, 0xe8, 0x04, 0xe6, 0x02, 0x05, 0xe6, 0xe5,
-0x04, 0xe6, 0x06, 0x03, 0x05, 0xe5, 0xe6, 0x04,
-0xe5, 0x07, 0x09, 0xe5, 0xe6, 0x04, 0x09, 0x09,
-0x09, 0xe8, 0x46, 0x09, 0x14, 0xe5, 0x06, 0x0b,
-0x09, 0x15, 0x1d, 0x24, 0x02, 0xe5, 0xe5, 0x45,
-0x08, 0x15, 0x33, 0x1d, 0x28, 0x70, 0xe5, 0x09,
-0x09, 0x14, 0x42, 0x02, 0xe5, 0x30, 0x27, 0x01,
-0x15, 0x1b, 0x1d, 0x32, 0x01, 0x01, 0x5b, 0x0c,
-0x51, 0x24, 0x01, 0xe5, 0xe5, 0x28, 0xe5, 0x1c,
-0x25, 0x53, 0x19, 0xe5, 0x01, 0x2b, 0x45, 0x6c,
-0xe5, 0xe6, 0x35, 0x09, 0x07, 0x01, 0x09, 0x09,
-0x12, 0x63, 0x09, 0x02, 0x03, 0x0c, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x07, 0x01, 0x09, 0x01,
-0x07, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x0d, 0x02, 0xe5, 0x02, 0x0c,
-0x09, 0x09, 0x09, 0x06, 0x02, 0x05, 0xe5, 0x01,
-0x07, 0x01, 0x05, 0x03, 0x07, 0x01, 0x09, 0x0b,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x0d, 0xe5, 0x01, 0x05, 0x07, 0xe5, 0x05,
-0x01, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0x03,
-0x05, 0xe5, 0x07, 0x09, 0xe5, 0x07, 0x09, 0xe5,
-0x07, 0x01, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x04, 0x02, 0xe5, 0x12, 0x04,
-0x0b, 0x05, 0x02, 0xe5, 0x07, 0xe5, 0x08, 0x09,
-0x08, 0xe5, 0x08, 0x09, 0x09, 0x09, 0x06, 0x03,
-0xe5, 0x07, 0xe5, 0x08, 0x08, 0xe5, 0x07, 0xe5,
-0x08, 0x09, 0x04, 0x03, 0xe5, 0x08, 0x09, 0x0d,
-0x01, 0xe6, 0x05, 0x06, 0xe5, 0x07, 0xe5, 0xe5,
-0x05, 0xe5, 0xe5, 0x01, 0x03, 0xe5, 0x14, 0x06,
-0x09, 0x13, 0xe5, 0x09, 0xe5, 0xe5, 0x05, 0xe5,
-0xe5, 0x05, 0xe5, 0x07, 0xe5, 0xe5, 0x05, 0xe5,
-0xe5, 0x05, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0xe5,
-0x05, 0xe5, 0x07, 0xe5, 0x07, 0x02, 0x03, 0xe8,
-0x0e, 0x01, 0x09, 0x09, 0x07, 0x08, 0xe5, 0x07,
-0x09, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x08, 0x01,
-0x0b, 0x09, 0x07, 0x0b, 0x09, 0x07, 0x09, 0x13,
-0x09, 0x0e, 0x02, 0xe5, 0x0c, 0x09, 0x03, 0x05,
-0x09, 0x12, 0x09, 0xe5, 0x08, 0x13, 0x09, 0x01,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x07, 0x01,
-0x09, 0x09, 0x10, 0xe8, 0x03, 0x08, 0x02, 0x03,
-0x02, 0x02, 0x06, 0x02, 0x03, 0x02, 0x02, 0x06,
-0x02, 0x09, 0x06, 0x02, 0x06, 0x02, 0x06, 0x02,
-0x06, 0x02, 0x04, 0x01, 0x01, 0x02, 0x06, 0x02,
-0x06, 0x02, 0x06, 0x02, 0xe5, 0x04, 0x02, 0x06,
-0x02, 0x06, 0x02, 0x06, 0x02, 0x03, 0x02, 0x02,
-0x06, 0x02, 0x0d, 0x01, 0x01, 0x03, 0xe5, 0x09,
-0x09, 0x09, 0xe5, 0x0f, 0xe5, 0x25, 0x0b, 0x04,
-0xe5, 0x01, 0x02, 0x06, 0x02, 0x13, 0x09, 0x36,
-0x0d, 0x23, 0x35, 0x82, 0x01, 0x03, 0x10, 0x09,
-0x02, 0x06, 0x11, 0x09, 0x1c, 0xe5, 0x0a, 0x03,
-0xe6, 0xe5, 0x02, 0x03, 0x05, 0x0d, 0x05, 0x03,
-0x05, 0x17, 0x27, 0x02, 0xe5, 0x29, 0x50, 0x27,
-0x11, 0x28, 0xe5, 0x01, 0x10, 0x09, 0x09, 0x09,
-0x09, 0x04, 0x04, 0xe5, 0x07, 0xe5, 0x07, 0x09,
-0x09, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x0e, 0xe7, 0x0e, 0xe5, 0x02,
-0x02, 0x02, 0x06, 0x02, 0x10, 0xe5, 0xe5, 0x38,
-0x1e, 0x06, 0x02, 0x13, 0x01, 0xe5, 0x2c, 0xe6,
-0x17, 0x09, 0x06, 0x09, 0x01, 0x10, 0x19, 0x24,
-0x13, 0x13, 0x02, 0x11, 0x16, 0x05, 0x02, 0x03,
-0x01, 0x10, 0xe5, 0x08, 0x70, 0x09, 0x3f, 0x01,
-0x02, 0xe5, 0x02, 0x26, 0x11, 0x09, 0x28, 0x02,
-0x6c, 0xe5, 0xe5, 0x13, 0xca, 0x02, 0x0d, 0x01,
-0x07, 0x01, 0x07, 0x1d, 0x01, 0x04, 0x0e, 0x07,
-0x01, 0x13, 0x01, 0x07, 0xe6, 0x10, 0xe5, 0x03,
-0x46, 0x01, 0x01, 0x0d, 0x01, 0x07, 0x02, 0x03,
-0x05, 0x1d, 0x10, 0x09, 0x02, 0x0e, 0x02, 0xe5,
-0x01, 0x07, 0x35, 0x29, 0xe6, 0xe5, 0x18, 0x12,
-0xe5, 0x10, 0x08, 0x1a, 0x2c, 0x09, 0x43, 0xe5,
-0xe6, 0x14, 0x01, 0xe6, 0x04, 0x04, 0x23, 0x04,
-0x12, 0x0b, 0x09, 0x63, 0x03, 0x02, 0xe5, 0x71,
-0x30, 0x3c, 0x01, 0x17, 0xe5, 0xe5, 0x29, 0x35,
-0x5e, 0x03, 0x03, 0x09, 0x0f, 0x0b, 0x20, 0x27,
-0x71, 0x01, 0x0f, 0x04, 0x03, 0x05, 0x02, 0x01,
-0x04, 0x09, 0x09, 0x32, 0x02, 0x65, 0x01, 0x03,
-0x01, 0xe6, 0x0d, 0xe5, 0x10, 0x01, 0x27, 0x02,
-0x09, 0x89, 0x0e, 0x03, 0x33, 0x03, 0x03, 0x29,
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-0xe7, 0x70, 0x68, 0x03, 0xe5, 0xe6, 0xe5, 0x6e,
-0x6c, 0xe8, 0x70, 0x6e, 0x01, 0x02, 0xdf, 0xe5,
-0x08, 0xd2, 0x01, 0x01, 0xe5, 0xdf, 0x01, 0xe6,
-0xd9, 0x01, 0xe6, 0xe5, 0x01, 0x01, 0xd4, 0x01,
-0x03, 0x02, 0x04, 0xce, 0xe5, 0x03, 0x05, 0xe7,
-0xd3, 0x06, 0x02, 0x03, 0xd5, 0x07, 0xe5, 0xe7,
-0xda, 0x03, 0x01, 0xe5, 0xdc, 0xe9, 0xdd, 0x02,
-0xe5, 0x08, 0xd3, 0x04, 0x0a, 0x01, 0xd1, 0xe5,
-0xe7, 0x07, 0x05, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x0b, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0d, 0xe6,
-0xe6, 0x01, 0xd3, 0x04, 0x02, 0x03, 0xd5, 0x08,
-0x01, 0x01, 0xe0, 0x01, 0xde, 0xe5, 0xe6, 0xdf,
-0x01, 0xe5, 0x13, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x09, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x09, 0xe5, 0xdd, 0x03, 0xe0, 0x01,
-0xe5, 0xdc, 0xe8, 0xdf, 0x01, 0xdf, 0xe5, 0xe5,
-0x10, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x05, 0x01,
-0xe5, 0x05, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
-0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x09,
-0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
-0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
-0x01, 0x07, 0x01, 0x0c, 0xe6, 0xdd, 0xe9, 0x50,
-0x33, 0x56, 0x01, 0x02, 0x01, 0x03, 0x2c, 0x3e,
-0x6c, 0xe5, 0xe7, 0x6f, 0x6b, 0x01, 0xe5, 0xe5,
-0x12, 0x5d, 0x6e, 0xe7, 0x08, 0x1f, 0x09, 0x3c,
-0x4a, 0x15, 0x0a, 0xe9, 0x70, 0x6c, 0x02, 0xe5,
-0x05, 0x6a, 0x6c, 0xe6, 0xe5, 0x70, 0x6e, 0xe6,
-0x70, 0x6d, 0xe7, 0x09, 0x09, 0x09, 0xbf, 0x01,
-0x01, 0xde, 0xe5, 0xe6, 0x26, 0xba, 0xdc, 0x01,
-0x01, 0xe6, 0x01, 0x01, 0xd4, 0x01, 0x03, 0xe7,
-0x03, 0xcf, 0xe5, 0x02, 0x04, 0x02, 0xe5, 0xe6,
-0xd7, 0x03, 0x01, 0xe6, 0xe5, 0x06, 0x01, 0xd0,
-0x02, 0xe6, 0xda, 0x02, 0xe5, 0x01, 0xdd, 0xe6,
-0xe6, 0xda, 0xe5, 0x02, 0xe7, 0x07, 0xd3, 0x01,
-0xe7, 0x09, 0x01, 0xd5, 0xe5, 0x07, 0x05, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x0b, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x04, 0x01, 0x06, 0xe9, 0xd5, 0x04,
-0x05, 0xe5, 0xd2, 0x0a, 0x02, 0xe5, 0xdf, 0x01,
-0xdf, 0xe8, 0xdd, 0x01, 0xe5, 0x14, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x09, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0x01, 0xe5,
-0xd8, 0x05, 0xe7, 0xde, 0xe5, 0xe6, 0xdc, 0x02,
-0xe5, 0x02, 0x08, 0xd3, 0x01, 0x32, 0xab, 0xe6,
-0xe5, 0x10, 0x01, 0x02, 0x04, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x09, 0x01,
-0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x0a, 0x02, 0xe5, 0xde, 0x02, 0xe5,
-0x64, 0x15, 0x13, 0x4c, 0x02, 0xe6, 0x70, 0x6d,
-0xe5, 0xe6, 0x6f, 0x6b, 0x02, 0x01, 0x13, 0x5d,
-0x64, 0x07, 0xe5, 0xe7, 0x43, 0x2b, 0x61, 0x09,
-0xe5, 0x02, 0x25, 0x4b, 0x6e, 0x01, 0x06, 0x20,
-0x49, 0x6d, 0xe5, 0xe5, 0x70, 0x6c, 0x03, 0x03,
-0x6d, 0x6e, 0xe6, 0xe1, 0xdc, 0x01, 0xe5, 0x01,
-0xe3, 0xe7, 0xd9, 0x03, 0xe6, 0x01, 0x01, 0xd4,
-0x01, 0x02, 0x01, 0x01, 0x04, 0xd4, 0x06, 0x01,
-0xd4, 0xe5, 0x04, 0x02, 0x01, 0xe6, 0xdc, 0x01,
-0x02, 0x02, 0xd8, 0x03, 0x02, 0x01, 0xdb, 0x01,
-0xe5, 0xe5, 0xdd, 0xe5, 0x01, 0xdd, 0x01, 0xe7,
-0xdf, 0xe7, 0x0d, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x0b, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0d, 0x02,
-0x01, 0x02, 0xd8, 0x04, 0xe6, 0xdd, 0x02, 0xe5,
-0xdd, 0x01, 0xe6, 0xdd, 0xe5, 0x01, 0xe5, 0xde,
-0x01, 0x15, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x06, 0x01, 0x01, 0xde, 0x01, 0x01, 0xe3,
-0xe6, 0xdc, 0xe5, 0x01, 0xdf, 0xe7, 0x3b, 0x10,
-0x92, 0xe6, 0x10, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x07, 0x01, 0x01, 0x05, 0x01, 0x07,
-0x01, 0xe5, 0x05, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x09, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
-0x01, 0x05, 0x01, 0x07, 0x01, 0x01, 0x05, 0x01,
-0x07, 0x01, 0x01, 0x05, 0x01, 0x07, 0x01, 0x0d,
-0xe5, 0x50, 0x34, 0x58, 0x02, 0xe5, 0x50, 0x8a,
-0xe9, 0xe5, 0x02, 0x5f, 0x0a, 0xe5, 0x09, 0x12,
-0x51, 0xe5, 0x03, 0x49, 0x22, 0x14, 0x13, 0x42,
-0xe5, 0x01, 0xe6, 0x01, 0x6d, 0x6f, 0xe6, 0x2b,
-0x24, 0x1e, 0x52, 0xe5, 0x0b, 0x0a, 0xe5, 0x01,
-0xe6, 0x23, 0x05, 0x01, 0x3f, 0x03, 0x6c, 0xe5,
-0xe6, 0x26, 0x06, 0x42, 0x6c, 0x01, 0xe7, 0x6f,
-0x6d, 0xe7, 0x70, 0x6d, 0x01, 0xe5, 0x30, 0x3d,
-0x5f, 0x0e, 0x01, 0x01, 0x2d, 0x97, 0x08, 0xe5,
-0x0d, 0xe5, 0x01, 0x09, 0x23, 0x44, 0x52, 0x08,
-0x11, 0xe6, 0x02, 0x0b, 0xe5, 0x01, 0x06, 0x06,
-0xe7, 0x07, 0xe5, 0x05, 0xe7, 0x05, 0xe7, 0x05,
-0xe7, 0xe5, 0x05, 0xe5, 0x08, 0x08, 0xe5, 0x09,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
-0xe5, 0x07, 0xe5, 0x0b, 0x02, 0xe6, 0x0d, 0x01,
-0x02, 0x04, 0x01, 0x02, 0x04, 0x01, 0x02, 0x04,
-0x01, 0x07, 0x01, 0x07, 0x01, 0x02, 0x02, 0x01,
-0x01, 0x08, 0xe5, 0x0d, 0x02, 0x01, 0x0b, 0x09,
-0x09, 0x09, 0x07, 0x01, 0x01, 0xe5, 0x05, 0x09,
-0x09, 0x02, 0x06, 0x09, 0x0d, 0x02, 0xe5, 0x0f,
-0x08, 0x13, 0x09, 0x1d, 0x09, 0x04, 0x04, 0x08,
-0x02, 0x04, 0x04, 0x09, 0x04, 0x04, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x0f, 0x02, 0x14, 0x41,
-0x87, 0x01, 0xe6, 0x18, 0x03, 0x05, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x13, 0x0b, 0x09, 0x04, 0x04,
-0x09, 0x04, 0x04, 0x02, 0x06, 0x09, 0x09, 0x09,
-0x09, 0x0e, 0x01, 0x01, 0x0d, 0xe5, 0x07, 0xe6,
-0x06, 0xe6, 0x06, 0xe5, 0x07, 0xe5, 0x07, 0xe6,
-0x06, 0xe6, 0x06, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x01, 0x03, 0x03, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
-0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x0e, 0xe8,
-0x02, 0x05, 0x03, 0x09, 0x01, 0x04, 0x02, 0x01,
-0x07, 0x09, 0x09, 0x01, 0x07, 0x01, 0x07, 0x09,
-0x07, 0x01, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x14, 0x0e, 0x09, 0x09,
-0x09, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0x09,
-0x09, 0xe5, 0xe5, 0x05, 0x09, 0xe5, 0xe5, 0x07,
-0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
-0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
-0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
-0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x0f, 0x0e, 0x09,
-0x01, 0x07, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x01, 0x07, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x0f, 0x01, 0xe6, 0x47,
-0x11, 0x76, 0x0c, 0x01, 0x01, 0x0e, 0x05, 0x03,
-0x05, 0x03, 0x09, 0x05, 0x03, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x06, 0x01, 0x02, 0x05, 0x03, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x0f,
-0xe8, 0x0f, 0x13, 0x1d, 0x09, 0x24, 0x70, 0x10,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x05, 0x03,
-0x09, 0x09, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x0e, 0x01, 0xe5, 0x46,
-0x96, 0x02, 0xe5, 0x70, 0x6e, 0x01, 0x22, 0x1d,
-0x09, 0x13, 0x11, 0xe5, 0x67, 0x06, 0xe5, 0x06,
-0x06, 0x06, 0x02, 0x06, 0x02, 0x06, 0x16, 0x06,
-0x02, 0x13, 0x06, 0x79, 0xe5, 0xe5, 0x3a, 0x1d,
-0x33, 0x1d, 0x09, 0x2a, 0xe6, 0x06, 0x05, 0x08,
-0xe5, 0x07, 0xe5, 0x07, 0x14, 0x08, 0xe5, 0x12,
-0x08, 0x0a, 0x65, 0x06, 0x03, 0x71, 0x66, 0x05,
-0xe5, 0xe6, 0xdd, 0xe5, 0xe6, 0x0c, 0xe5, 0x04,
-0xe8, 0x04, 0xe8, 0x04, 0xe6, 0x06, 0x09, 0x02,
-0xe5, 0x04, 0xe8, 0x04, 0x09, 0x02, 0xe5, 0x04,
-0xe6, 0x06, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x09, 0x09, 0x01, 0xe6, 0x0c,
-0xe6, 0x05, 0xe7, 0x05, 0xe7, 0x05, 0x01, 0xe5,
-0x08, 0x07, 0xe6, 0x05, 0xe7, 0x08, 0x07, 0xe6,
-0x05, 0x02, 0x07, 0x03, 0x09, 0x09, 0x09, 0x09,
-0x09, 0x09, 0x09, 0x08, 0xe5, 0x07, 0xe5, 0x0e,
-0xe5, 0xe5, 0x33, 0x2d, 0x0e, 0x10, 0x13, 0x48,
-0x02, 0x11, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05,
-0x03, 0x01, 0x0d, 0x03, 0x05, 0x03, 0x01, 0x0d,
-0x03, 0x01, 0x03, 0x07, 0x09, 0x09, 0x09, 0x09,
-0x03, 0x05, 0x09, 0x09, 0x11, 0x13, 0x01, 0xe5,
-0x0a, 0x06, 0x09, 0x09, 0x04, 0x01, 0x02, 0x01,
-0x03, 0x07, 0x05, 0x09, 0x01, 0x03, 0x07, 0x0e,
-0xe5, 0x02, 0x06, 0xe5, 0x02, 0x04, 0x04, 0x01,
-0x07, 0x04, 0x04, 0x05, 0x03, 0x01, 0x07, 0x01,
-0x07, 0x01, 0x03, 0x03, 0x02, 0x04, 0x04, 0x06,
-0x01, 0x03, 0xe5, 0xe5, 0xe6, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff,
diff --git a/board/esd/du440/Kconfig b/board/esd/du440/Kconfig
deleted file mode 100644
index b4b3e6b..0000000
--- a/board/esd/du440/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DU440
-
-config SYS_BOARD
- default "du440"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "DU440"
-
-endif
diff --git a/board/esd/du440/MAINTAINERS b/board/esd/du440/MAINTAINERS
deleted file mode 100644
index ba26948..0000000
--- a/board/esd/du440/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DU440 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/du440/
-F: include/configs/DU440.h
-F: configs/DU440_defconfig
diff --git a/board/esd/du440/Makefile b/board/esd/du440/Makefile
deleted file mode 100644
index ef41d94..0000000
--- a/board/esd/du440/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = du440.o
-extra-y += init.o
diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk
deleted file mode 100644
index 9cb071e..0000000
--- a/board/esd/du440/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
deleted file mode 100644
index b168b24..0000000
--- a/board/esd/du440/du440.c
+++ /dev/null
@@ -1,882 +0,0 @@
-/*
- * (C) Copyright 2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <i2c.h>
-#include <asm/ppc440.h>
-#include "du440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-extern ulong flash_get_size (ulong base, int banknum);
-
-int usbhub_init(void);
-int dvi_init(void);
-int eeprom_write_enable (unsigned dev_addr, int state);
-int board_revision(void);
-
-static int du440_post_errors;
-
-int board_early_init_f(void)
-{
- u32 sdr0_cust0;
- u32 sdr0_pfc1, sdr0_pfc2;
- u32 reg;
-
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, 0xb8400000);
-
- /*
- * Setup the GPIO pins
- */
- out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
- out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
- out_be32((void*)GPIO0_OSRL, 0x50055400);
- out_be32((void*)GPIO0_OSRH, 0x55005000);
- out_be32((void*)GPIO0_TSRL, 0x50055400);
- out_be32((void*)GPIO0_TSRH, 0x55005000);
- out_be32((void*)GPIO0_ISR1L, 0x50000000);
- out_be32((void*)GPIO0_ISR1H, 0x00000000);
- out_be32((void*)GPIO0_ISR2L, 0x00000000);
- out_be32((void*)GPIO0_ISR2H, 0x00000000);
- out_be32((void*)GPIO0_ISR3L, 0x00000000);
- out_be32((void*)GPIO0_ISR3H, 0x00000000);
-
- out_be32((void*)GPIO1_OR, 0x00000000);
- out_be32((void*)GPIO1_TCR, 0xc2000000 |
- CONFIG_SYS_GPIO1_IORSTN |
- CONFIG_SYS_GPIO1_IORST2N |
- CONFIG_SYS_GPIO1_LEDUSR1 |
- CONFIG_SYS_GPIO1_LEDUSR2 |
- CONFIG_SYS_GPIO1_LEDPOST |
- CONFIG_SYS_GPIO1_LEDDU);
- out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
- out_be32((void*)GPIO1_OSRL, 0x0c280000);
- out_be32((void*)GPIO1_OSRH, 0x00000000);
- out_be32((void*)GPIO1_TSRL, 0xcc000000);
- out_be32((void*)GPIO1_TSRH, 0x00000000);
- out_be32((void*)GPIO1_ISR1L, 0x00005550);
- out_be32((void*)GPIO1_ISR1H, 0x00000000);
- out_be32((void*)GPIO1_ISR2L, 0x00050000);
- out_be32((void*)GPIO1_ISR2H, 0x00000000);
- out_be32((void*)GPIO1_ISR3L, 0x01400000);
- out_be32((void*)GPIO1_ISR3H, 0x00000000);
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- /*
- * UIC1:
- * bit30: ext. Irq 1: PLD : int 32+30
- */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xfffffffd);
- mtdcr(UIC1TR, 0x00000000);
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- /*
- * UIC2
- * bit3: ext. Irq 2: DCF77 : int 64+3
- */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /* select Ethernet pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_PFC2, sdr0_pfc2);
-
- /* setup EMAC bridge interface */
- if (board_revision() == 0) {
- /* 1 x MII */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_1_2;
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_1_2;
- } else {
- /* 2 x SMII */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_6;
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_6;
- }
-
- /* enable 2nd IIC */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
-
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* PCI arbiter enabled */
- mfsdr(SDR0_PCI0, reg);
- mtsdr(SDR0_PCI0, 0x80000000 | reg);
-
- /* setup NAND FLASH */
- mfsdr(SDR0_CUST0, sdr0_cust0);
- sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
- (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
- mtsdr(SDR0_CUST0, sdr0_cust0);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- uint pbcr;
- int size_val = 0;
- u32 reg;
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
- unsigned long sdr0_srst0, sdr0_srst1;
- int i, j;
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(gd->bd->bi_flashsize) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB0CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
- /*
- * USB suff...
- */
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB0, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-
- /* An 8-bit/60MHz interface is the only possible alternative
- when connecting the Device to the PHY */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
-
- /* To enable the USB 2.0 Device function through the UTMI interface */
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB0, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /*
- * Take USB out of reset:
- * -Initial status = all cores are in reset
- * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
- * -wait 1 ms
- * -deassert reset to PHY
- * -wait 1 ms
- * -deassert reset to HOST
- * -wait 4 ms
- * -deassert all other resets
- */
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
- SDR0_SRST1_P4OPB0 | \
- SDR0_SRST1_OPBA2 | \
- SDR0_SRST1_PLB42OPB1 | \
- SDR0_SRST1_OPB2PLB40);
- mtsdr(SDR0_SRST1, sdr0_srst1);
- udelay(1000);
-
- mfsdr(SDR0_SRST1, sdr0_srst1);
- sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
- mtsdr(SDR0_SRST1, sdr0_srst1);
- udelay(1000);
-
- mfsdr(SDR0_SRST0, sdr0_srst0);
- sdr0_srst0 &= ~SDR0_SRST0_USB2H;
- mtsdr(SDR0_SRST0, sdr0_srst0);
- udelay(4000);
-
- /* finally all the other resets */
- mtsdr(SDR0_SRST1, 0x00000000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Host(int phy)\n");
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
- /*
- * release IO-RST#
- * We have to wait at least 560ms until we may call usbhub_init
- */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
- CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
-
- /*
- * flash USR1/2 LEDs (600ms)
- * This results in the necessary delay from IORST# until
- * calling usbhub_init will succeed
- */
- for (j = 0; j < 3; j++) {
- out_be32((void*)GPIO1_OR,
- (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
- CONFIG_SYS_GPIO1_LEDUSR1);
-
- for (i = 0; i < 100; i++)
- udelay(1000);
-
- out_be32((void*)GPIO1_OR,
- (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
- CONFIG_SYS_GPIO1_LEDUSR2);
-
- for (i = 0; i < 100; i++)
- udelay(1000);
- }
-
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
- ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
-
- if (usbhub_init())
- du440_post_errors++;
-
- if (dvi_init())
- du440_post_errors++;
-
- return 0;
-}
-
-int pld_revision(void)
-{
- out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
- return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
-}
-
-int board_revision(void)
-{
- int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
- >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
-
- return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
- ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
-}
-
-#if defined(CONFIG_SHOW_ACTIVITY)
-void board_show_activity (ulong timestamp)
-{
- if ((timestamp % 100) == 0)
- out_be32((void*)GPIO1_OR,
- in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
-}
-
-void show_activity(int arg)
-{
-}
-#endif /* CONFIG_SHOW_ACTIVITY */
-
-int du440_phy_addr(int devnum)
-{
- if (board_revision() == 0)
- return devnum;
-
- return devnum + 1;
-}
-
-int checkboard(void)
-{
- char serno[32];
-
- puts("Board: DU440");
-
- if (getenv_f("serial#", serno, sizeof(serno)) > 0) {
- puts(", serial# ");
- puts(serno);
- }
-
- printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
- board_revision(), pld_revision());
- return (0);
-}
-
-int last_stage_init(void)
-{
- int e, i;
-
- /* everyting is ok: turn on POST-LED */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
-
- /* slowly blink on errors and finally keep LED off */
- for (e = 0; e < du440_post_errors; e++) {
- out_be32((void*)GPIO1_OR,
- in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
-
- for (i = 0; i < 500; i++)
- udelay(1000);
-
- out_be32((void*)GPIO1_OR,
- in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
-
- for (i = 0; i < 500; i++)
- udelay(1000);
- }
-
- return 0;
-}
-
-/*
- * read field strength from I2C ADC
- */
-int dcf77_status(void)
-{
- unsigned int oldbus;
- uchar u[2];
- int mv;
-
- oldbus = I2C_GET_BUS();
- I2C_SET_BUS(1);
-
- if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
- I2C_SET_BUS(oldbus);
- return -1;
- }
-
- mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
-
- I2C_SET_BUS(oldbus);
- return mv;
-}
-
-int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int mv;
- u32 pin, pinold;
- unsigned long long t1, t2;
- bd_t *bd = gd->bd;
-
- printf("DCF77: ");
- mv = dcf77_status();
- if (mv > 0)
- printf("signal=%d mV\n", mv);
- else
- printf("ERROR - no signal\n");
-
- t1 = t2 = 0;
- pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
- while (!ctrlc()) {
- pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
- if (pin && !pinold) { /* bit start */
- t1 = get_ticks();
- if (t2 && ((unsigned int)(t1 - t2) /
- (bd->bi_procfreq / 1000) >= 1800))
- printf("Start of minute\n");
-
- t2 = t1;
- }
- if (t1 && !pin && pinold) { /* bit end */
- printf("%5d\n", (unsigned int)(get_ticks() - t1) /
- (bd->bi_procfreq / 1000));
- }
- pinold = pin;
- }
-
- printf("Abort\n");
- return 0;
-}
-U_BOOT_CMD(
- dcf77, 1, 1, do_dcf77,
- "Check DCF77 receiver",
- ""
-);
-
-/*
- * initialize USB hub via I2C1
- */
-int usbhub_init(void)
-{
- int reg;
- int ret = 0;
- unsigned int oldbus;
- uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
- 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
- 0x32};
- uchar stcd;
-
- printf("Hub: ");
-
- oldbus = I2C_GET_BUS();
- I2C_SET_BUS(1);
-
- for (reg = 0; reg < sizeof(u); reg++)
- if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
- ret = -1;
- break;
- }
-
- if (ret == 0) {
- stcd = 0x03;
- if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
- ret = -1;
- }
-
- if (ret == 0)
- printf("initialized\n");
- else
- printf("failed - cannot initialize USB hub\n");
-
- I2C_SET_BUS(oldbus);
- return ret;
-}
-
-int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- usbhub_init();
- return 0;
-}
-U_BOOT_CMD(
- hubinit, 1, 1, do_hubinit,
- "Initialize USB hub",
- ""
-);
-
-#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
-int boot_eeprom_write (unsigned dev_addr,
- unsigned offset,
- uchar *buffer,
- unsigned cnt)
-{
- unsigned end = offset + cnt;
- unsigned blk_off;
- int rcode = 0;
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable(dev_addr, 1);
-#endif
- /*
- * Write data until done or would cross a write page boundary.
- * We must write the address again when changing pages
- * because the address counter only increments within a page.
- */
-
- while (offset < end) {
- unsigned alen, len;
- unsigned maxlen;
-
- uchar addr[2];
-
- blk_off = offset & 0xFF; /* block offset */
-
- addr[0] = offset >> 8; /* block number */
- addr[1] = blk_off; /* block offset */
- alen = 2;
- addr[0] |= dev_addr; /* insert device address */
-
- len = end - offset;
-
- /*
- * For a FRAM device there is no limit on the number of the
- * bytes that can be ccessed with the single read or write
- * operation.
- */
-#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
-
-#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
-#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
-
- maxlen = BOOT_EEPROM_PAGE_SIZE -
- BOOT_EEPROM_PAGE_OFFSET(blk_off);
-#else
- maxlen = 0x100 - blk_off;
-#endif
- if (maxlen > I2C_RXTX_LEN)
- maxlen = I2C_RXTX_LEN;
-
- if (len > maxlen)
- len = maxlen;
-
- if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
- rcode = 1;
-
- buffer += len;
- offset += len;
-
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-#endif
- }
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable(dev_addr, 0);
-#endif
- return rcode;
-}
-
-int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong sdsdp[4];
-
- if (argc > 1) {
- if (!strcmp(argv[1], "533")) {
- printf("Bootstrapping for 533MHz\n");
- sdsdp[0] = 0x87788252;
- /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
- sdsdp[1] = 0x095fa030;
- sdsdp[2] = 0x40082350;
- sdsdp[3] = 0x0d050000;
- } else if (!strcmp(argv[1], "533-66")) {
- printf("Bootstrapping for 533MHz (66MHz PCI)\n");
- sdsdp[0] = 0x87788252;
- /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
- sdsdp[1] = 0x0957a030;
- sdsdp[2] = 0x40082350;
- sdsdp[3] = 0x0d050000;
- } else if (!strcmp(argv[1], "667")) {
- printf("Bootstrapping for 667MHz\n");
- sdsdp[0] = 0x8778a256;
- /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
- sdsdp[1] = 0x0947a030;
- /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
- * -> not working when overclocking 533MHz chips
- * -> untested on 667MHz chips */
- /* sdsdp[1]=0x095fa030; */
- sdsdp[2] = 0x40082350;
- sdsdp[3] = 0x0d050000;
- } else if (!strcmp(argv[1], "667-166")) {
- printf("Bootstrapping for 667-166MHz\n");
- sdsdp[0] = 0x8778a252;
- sdsdp[1] = 0x09d7a030;
- sdsdp[2] = 0x40082350;
- sdsdp[3] = 0x0d050000;
- }
- } else {
- printf("Bootstrapping for 533MHz (default)\n");
- sdsdp[0] = 0x87788252;
- /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
- sdsdp[1] = 0x095fa030;
- sdsdp[2] = 0x40082350;
- sdsdp[3] = 0x0d050000;
- }
-
- printf("Writing boot EEPROM ...\n");
- if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
- 0, (uchar*)sdsdp, 16) != 0)
- printf("boot_eeprom_write failed\n");
- else
- printf("done (dump via 'i2c md 52 0.1 10')\n");
-
- return 0;
-}
-U_BOOT_CMD(
- sbe, 2, 0, do_setup_boot_eeprom,
- "setup boot eeprom",
- ""
-);
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/*
- * Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state)
-{
- if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
- (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
- return -1;
- else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO_SINT2. */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO_SINT2. */
- out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = (0 == (in_be32((void*)GPIO0_OR) &
- CONFIG_SYS_GPIO0_EP_EEP));
- break;
- }
- }
- return state;
-}
-
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
- if (state < 0)
- puts ("Query of write access state failed.\n");
- else {
- printf ("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
- state = 0;
- }
- } else {
- if ('0' == argv[1][0]) {
- /* Disable write access. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0)
- puts ("Setup of write access state failed.\n");
- }
-
- return state;
-}
-
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-static int got_pldirq;
-
-static int pld_interrupt(u32 arg)
-{
- int rc = -1; /* not for us */
- u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
-
- /* check for PLD interrupt */
- if (status & PWR_INT_FLAG) {
- /* reset this int */
- out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
- rc = 0;
- got_pldirq = 1; /* trigger backend */
- }
-
- return rc;
-}
-
-int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- got_pldirq = 0;
-
- /* clear any pending interrupt */
- out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
-
- irq_install_handler(CPLD_IRQ,
- (interrupt_handler_t *)pld_interrupt, 0);
-
- printf("Waiting ...\n");
- while(!got_pldirq) {
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- break;
- }
- }
- if (got_pldirq) {
- printf("Got interrupt!\n");
- printf("Power %sready!\n",
- in_8((void *)CONFIG_SYS_CPLD_BASE) &
- PWR_RDY ? "":"NOT ");
- }
-
- irq_free_handler(CPLD_IRQ);
- return 0;
-}
-U_BOOT_CMD(
- wpi, 1, 1, do_waitpwrirq,
- "Wait for power change interrupt",
- ""
-);
-
-/*
- * initialize DVI panellink transmitter
- */
-int dvi_init(void)
-{
- int i;
- int ret = 0;
- unsigned int oldbus;
- uchar u[] = {0x08, 0x34,
- 0x09, 0x20,
- 0x0a, 0x90,
- 0x0c, 0x89,
- 0x08, 0x35};
-
- printf("DVI: ");
-
- oldbus = I2C_GET_BUS();
- I2C_SET_BUS(0);
-
- for (i = 0; i < sizeof(u); i += 2)
- if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
- ret = -1;
- break;
- }
-
- if (ret == 0)
- printf("initialized\n");
- else
- printf("failed - cannot initialize DVI transmitter\n");
-
- I2C_SET_BUS(oldbus);
- return ret;
-}
-
-int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- dvi_init();
- return 0;
-}
-U_BOOT_CMD(
- dviinit, 1, 1, do_dviinit,
- "Initialize DVI Panellink transmitter",
- ""
-);
-
-/*
- * TODO: 'time' command might be useful for others as well.
- * Move to 'common' directory.
- */
-int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned long long start, end;
- char c, cmd[CONFIG_SYS_CBSIZE];
- char *p, *d = cmd;
- int ret, i;
- ulong us;
-
- for (i = 1; i < argc; i++) {
- p = argv[i];
-
- if (i > 1)
- *d++ = ' ';
-
- while ((c = *p++) != '\0') {
- *d++ = c;
- }
- }
- *d = '\0';
-
- start = get_ticks();
- ret = run_command(cmd, 0);
- end = get_ticks();
-
- printf("ticks=%ld\n", (ulong)(end - start));
- us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
- printf("usec=%ld\n", us);
-
- return ret;
-}
-U_BOOT_CMD(
- time, CONFIG_SYS_MAXARGS, 1, do_time,
- "run command and output execution time",
- ""
-);
-
-extern void video_hw_rectfill (
- unsigned int bpp, /* bytes per pixel */
- unsigned int dst_x, /* dest pos x */
- unsigned int dst_y, /* dest pos y */
- unsigned int dim_x, /* frame width */
- unsigned int dim_y, /* frame height */
- unsigned int color /* fill color */
- );
-
-/*
- * graphics demo
- * draw rectangles using pseudorandom number generator
- * (see http://www.embedded.com/columns/technicalinsights/20900500)
- */
-unsigned int rprime = 9972;
-static unsigned int r;
-static unsigned int Y;
-
-unsigned int prng(unsigned int max)
-{
- if (r == 0 || r == 1 || r == -1)
- r = rprime; /* keep from getting stuck */
-
- r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
- Y = (r >> 16) % max; /* choose upper bits and reduce */
- return Y;
-}
-
-int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int color;
- unsigned int x, y, dx, dy;
-
- while (!ctrlc()) {
- x = prng(1280 - 1);
- y = prng(1024 - 1);
- dx = prng(1280- x - 1);
- dy = prng(1024 - y - 1);
- color = prng(0x10000);
- video_hw_rectfill(2, x, y, dx, dy, color);
- }
-
- return 0;
-}
-U_BOOT_CMD(
- gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,
- "demo",
- ""
-);
diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h
deleted file mode 100644
index df065ba..0000000
--- a/board/esd/du440/du440.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDR0_USB0 0x0320 /* USB Control Register */
-
-#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
-#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
-
-#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
-#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
-
-#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
-#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4
-#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
-#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
-#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
-#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
-
-#define CPLD_VERSION_MASK 0x0f
-#define PWR_INT_FLAG 0x80
-#define PWR_RDY 0x10
-
-#define CPLD_IRQ (32+30)
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
deleted file mode 100644
index ab4b6ce..0000000
--- a/board/esd/du440/init.S
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- */
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
-
- /* TLB-entry for PCI IO */
- tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
-
- /* TLB-entries for EBC: CPLD, DUMEM, DUIO */
- tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for NAND */
- tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
- tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for Internal Registers & OCM */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
-
- /* TLB-entry PCI registers */
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
-
- /* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
- tlbtab_end
diff --git a/board/esd/hh405/Kconfig b/board/esd/hh405/Kconfig
deleted file mode 100644
index 8a8623a..0000000
--- a/board/esd/hh405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_HH405
-
-config SYS_BOARD
- default "hh405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "HH405"
-
-endif
diff --git a/board/esd/hh405/MAINTAINERS b/board/esd/hh405/MAINTAINERS
deleted file mode 100644
index b695c7b..0000000
--- a/board/esd/hh405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HH405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/hh405/
-F: include/configs/HH405.h
-F: configs/HH405_defconfig
diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile
deleted file mode 100644
index fba21a3..0000000
--- a/board/esd/hh405/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hh405.o flash.o \
- ../common/misc.o \
- ../common/esd405ep_nand.o \
- ../common/auto_update.o
diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/hh405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/hh405/fpgadata.c b/board/esd/hh405/fpgadata.c
deleted file mode 100644
index 620c714..0000000
--- a/board/esd/hh405/fpgadata.c
+++ /dev/null
@@ -1,5034 +0,0 @@
-0x1f, 0x8b, 0x08, 0x08, 0x7a, 0x8e, 0xc6, 0x43,
-0x00, 0x03, 0x68, 0x68, 0x34, 0x30, 0x35, 0x5f,
-0x31, 0x5f, 0x30, 0x36, 0x2e, 0x62, 0x69, 0x74,
-0x00, 0xec, 0xfd, 0x7f, 0x7c, 0x14, 0x55, 0x9a,
-0x2f, 0x8e, 0x3f, 0x75, 0xaa, 0x12, 0x4e, 0xba,
-0x3a, 0xe9, 0x22, 0x09, 0x4e, 0x54, 0xc4, 0x4a,
-0x27, 0x30, 0x4d, 0xec, 0x84, 0xa6, 0x83, 0x21,
-0x42, 0x48, 0x2a, 0x9d, 0xe8, 0x44, 0x40, 0xe9,
-0x71, 0xdc, 0x59, 0x76, 0xae, 0x77, 0xb6, 0x65,
-0x98, 0xbd, 0x99, 0xb9, 0xe8, 0x46, 0xc7, 0xbb,
-0x97, 0xf1, 0xce, 0x8f, 0x93, 0x4e, 0x80, 0x4e,
-0x82, 0xd0, 0x20, 0x33, 0x46, 0x87, 0x71, 0x9b,
-0x10, 0x35, 0x2a, 0x33, 0xdb, 0x04, 0x94, 0xf0,
-0x63, 0xb0, 0x12, 0xa3, 0x36, 0x10, 0x20, 0x32,
-0xdc, 0x19, 0x54, 0x46, 0x1b, 0x8c, 0x4c, 0xd4,
-0xe8, 0x04, 0x44, 0x4d, 0xf8, 0xf9, 0x7d, 0x4e,
-0x75, 0xa7, 0xbb, 0x1a, 0x77, 0xf7, 0xce, 0xfd,
-0xdc, 0xd7, 0xf7, 0xf3, 0xda, 0xd7, 0xeb, 0x73,
-0xb3, 0x7f, 0xec, 0x99, 0xea, 0x43, 0x59, 0x75,
-0xea, 0x9c, 0xe7, 0x79, 0x3f, 0xbf, 0xde, 0x0f,
-0x64, 0xd8, 0x46, 0x63, 0xff, 0x07, 0x20, 0xdc,
-0x0f, 0xb6, 0xfa, 0xfa, 0x39, 0xae, 0x5b, 0xff,
-0x7e, 0xf6, 0xdf, 0xbb, 0xca, 0x4a, 0x1e, 0xfc,
-0xde, 0x72, 0x58, 0x06, 0xb2, 0xfb, 0x47, 0xb7,
-0xba, 0xbe, 0xff, 0xc8, 0x43, 0xb3, 0xe7, 0xcc,
-0x81, 0xef, 0xe1, 0xff, 0x72, 0xb9, 0xca, 0x66,
-0xb9, 0x66, 0xcf, 0x9a, 0xed, 0x86, 0xe5, 0x90,
-0x31, 0xbb, 0x7c, 0xde, 0xec, 0x39, 0xf3, 0x4a,
-0x6f, 0x85, 0xef, 0x83, 0x50, 0xda, 0x79, 0x15,
-0xff, 0x5e, 0x78, 0xf2, 0x6f, 0xfe, 0xc1, 0x05,
-0x4c, 0x00, 0x80, 0x49, 0x2e, 0xc1, 0xc7, 0xff,
-0xbf, 0xec, 0x12, 0x54, 0x01, 0x58, 0x55, 0xb1,
-0x0b, 0x74, 0xfe, 0xbf, 0x21, 0xfe, 0x7b, 0x86,
-0x0b, 0x54, 0xf3, 0xff, 0x16, 0x5c, 0xa0, 0x81,
-0x17, 0xb4, 0xb5, 0x6a, 0x36, 0xfc, 0x15, 0x7f,
-0x92, 0xc4, 0x26, 0x86, 0x7f, 0xd5, 0x7c, 0x48,
-0xcc, 0xbf, 0x7a, 0x90, 0xfd, 0x9b, 0x93, 0x92,
-0x7f, 0x55, 0xe7, 0x42, 0xf1, 0x91, 0x4a, 0x5c,
-0xff, 0xeb, 0xe9, 0x42, 0x2d, 0x4c, 0xdc, 0xf5,
-0xbd, 0xb7, 0xff, 0x9a, 0xfb, 0xcf, 0xff, 0x62,
-0xe2, 0xfe, 0xff, 0xbb, 0xf3, 0x41, 0xf9, 0x2b,
-0xa6, 0xe3, 0xfb, 0x4e, 0x0c, 0xde, 0x53, 0x04,
-0x1f, 0xe4, 0xc1, 0x75, 0x90, 0xc6, 0x80, 0x0f,
-0xd2, 0x41, 0xf8, 0x57, 0x06, 0xf3, 0xfb, 0x27,
-0xe6, 0xeb, 0x8d, 0xfb, 0xe0, 0x08, 0x2b, 0x55,
-0xad, 0x11, 0xd1, 0x0d, 0xef, 0xe5, 0x57, 0x45,
-0x96, 0x9c, 0xcb, 0xd9, 0xd7, 0x7c, 0xf5, 0x7b,
-0x73, 0x23, 0xb6, 0x73, 0x62, 0x39, 0x3b, 0x09,
-0x3f, 0x1a, 0xb5, 0x8e, 0xe5, 0x8c, 0x4a, 0x0d,
-0x13, 0xf3, 0xe9, 0x08, 0x6d, 0x65, 0xee, 0x7c,
-0x1a, 0x90, 0xed, 0x70, 0x48, 0x29, 0x19, 0x92,
-0x1b, 0x49, 0xd1, 0xd2, 0x3d, 0xd9, 0x25, 0x47,
-0x6c, 0xfb, 0x48, 0x97, 0x16, 0x90, 0xca, 0x22,
-0x96, 0x1e, 0x31, 0x2c, 0x4d, 0xac, 0x62, 0x44,
-0x5a, 0xbb, 0xa5, 0x55, 0x98, 0xa1, 0x65, 0x30,
-0xbb, 0x0f, 0x1e, 0x17, 0x9c, 0xda, 0x8d, 0x2e,
-0xb2, 0x56, 0xda, 0xa1, 0x3a, 0x41, 0xce, 0x25,
-0x54, 0xd9, 0x20, 0x86, 0x74, 0xea, 0x22, 0xe7,
-0x84, 0xc4, 0xfd, 0xa5, 0x6d, 0xe9, 0xad, 0xcc,
-0xae, 0x65, 0x04, 0x48, 0x3e, 0x6b, 0xcb, 0x2b,
-0xd1, 0x64, 0xd6, 0xba, 0x0d, 0xf6, 0x92, 0x12,
-0x62, 0x09, 0xf6, 0x75, 0x41, 0x06, 0xfb, 0x07,
-0xdd, 0x12, 0xf6, 0x8c, 0x4a, 0xbe, 0xf8, 0xfc,
-0xea, 0x29, 0x2b, 0x20, 0xd2, 0x38, 0x67, 0x4e,
-0x71, 0xab, 0x28, 0xc2, 0xdb, 0x5a, 0xa5, 0xbe,
-0x64, 0x8e, 0xfc, 0x5b, 0xed, 0x62, 0xb0, 0x64,
-0xb0, 0x26, 0x5c, 0x9a, 0x05, 0xdf, 0x09, 0xd9,
-0x7b, 0xad, 0xe1, 0x82, 0x41, 0x98, 0xb8, 0x7f,
-0x48, 0xd8, 0x0c, 0x97, 0x68, 0x15, 0xcb, 0xd2,
-0x73, 0xba, 0xe1, 0x8a, 0x50, 0xa5, 0x2f, 0x89,
-0x36, 0xd5, 0xc3, 0x05, 0xa8, 0xd4, 0xd7, 0x87,
-0x0b, 0x46, 0xd8, 0x85, 0x8c, 0xaa, 0xb3, 0xb6,
-0x51, 0xb1, 0x0b, 0x26, 0xee, 0xdf, 0xaf, 0x6c,
-0x83, 0x71, 0xbf, 0xdb, 0x63, 0x63, 0xe2, 0x29,
-0x38, 0xa8, 0xb9, 0xf5, 0x69, 0x3b, 0x73, 0xb6,
-0xd1, 0x43, 0xe0, 0xde, 0x60, 0xdd, 0x29, 0x3a,
-0xe1, 0x10, 0x2b, 0xd3, 0x97, 0x84, 0x6b, 0x46,
-0x41, 0x8d, 0xcf, 0x3f, 0x91, 0x56, 0x21, 0x6c,
-0xd7, 0xec, 0x63, 0x8b, 0x24, 0x32, 0xcc, 0x5a,
-0xc1, 0x1d, 0x99, 0xda, 0x49, 0x9c, 0xd0, 0x26,
-0xd9, 0x19, 0x2d, 0xc7, 0xc1, 0x3b, 0x7e, 0xbb,
-0x2e, 0x87, 0xc9, 0x17, 0xb8, 0xfb, 0x27, 0xde,
-0x77, 0xb1, 0xb5, 0x5b, 0xdb, 0x16, 0x92, 0x67,
-0xa4, 0xbf, 0xaa, 0x36, 0x0a, 0x85, 0xa1, 0x0c,
-0x17, 0x59, 0x0d, 0x1b, 0x24, 0x9f, 0x6e, 0x71,
-0x10, 0x02, 0xcf, 0xd7, 0xe2, 0x7c, 0x17, 0x19,
-0xc3, 0xb3, 0x12, 0xfb, 0x1b, 0x85, 0xef, 0xb2,
-0x97, 0x59, 0xf1, 0x29, 0xd9, 0x97, 0x7e, 0x4c,
-0x12, 0x98, 0x1a, 0xa5, 0x27, 0x48, 0xb6, 0xba,
-0x69, 0x63, 0x7e, 0xd4, 0x52, 0x8f, 0x83, 0x5d,
-0x41, 0x21, 0x2a, 0xaf, 0xd4, 0xae, 0x24, 0xee,
-0x5f, 0x07, 0x8b, 0xb5, 0x6e, 0xa8, 0x60, 0xb6,
-0x7c, 0x51, 0xef, 0xeb, 0x85, 0x39, 0x8a, 0x1c,
-0x16, 0x9b, 0xc9, 0x9b, 0x10, 0xd6, 0x4a, 0x94,
-0x36, 0x20, 0xef, 0x87, 0x82, 0xba, 0xcd, 0x25,
-0x1e, 0x23, 0x13, 0xfb, 0x41, 0xbb, 0x69, 0xdf,
-0xd0, 0x17, 0x50, 0xaa, 0xdb, 0xb6, 0x88, 0x83,
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-0xc6, 0xf6, 0x8d, 0x87, 0xd0, 0x0a, 0xcf, 0x3f,
-0x24, 0x6d, 0x1f, 0x45, 0xa3, 0xf2, 0x7a, 0x88,
-0xa5, 0x65, 0x61, 0xd8, 0x4b, 0xa1, 0xdd, 0xbe,
-0xcf, 0x4b, 0xe8, 0x7b, 0x7b, 0xe1, 0x18, 0x64,
-0x07, 0x63, 0x53, 0x93, 0x25, 0x38, 0xd6, 0x94,
-0x65, 0xf7, 0x67, 0xb9, 0x89, 0xc8, 0x35, 0xa1,
-0x98, 0xb7, 0x5e, 0x14, 0xd7, 0xab, 0x8f, 0x34,
-0xe3, 0x32, 0xd9, 0x55, 0xd7, 0xb0, 0xf5, 0x6a,
-0x30, 0x65, 0xcd, 0x5b, 0xaf, 0x22, 0x7e, 0xbc,
-0x47, 0x9c, 0xe6, 0xfd, 0xe1, 0xe3, 0xf6, 0x07,
-0x86, 0xc9, 0x7e, 0xdd, 0x5e, 0x81, 0x2b, 0xe0,
-0x9a, 0x33, 0x75, 0xe3, 0xcb, 0x3f, 0x98, 0x59,
-0x7b, 0x69, 0xa2, 0x18, 0x2e, 0x22, 0x3d, 0xf6,
-0xd0, 0x04, 0x0d, 0x6f, 0x87, 0x4b, 0x0c, 0x2c,
-0x8b, 0xe1, 0x24, 0x33, 0x94, 0x9b, 0xb3, 0xbe,
-0xf9, 0xc9, 0x29, 0xa5, 0xc1, 0xd4, 0x7e, 0x5c,
-0xdf, 0xc3, 0x4a, 0xe9, 0x4c, 0xca, 0x1c, 0x8e,
-0xeb, 0x37, 0x9b, 0x86, 0xf9, 0x11, 0x7c, 0xc8,
-0x2e, 0x46, 0xf2, 0x8b, 0x85, 0xec, 0x8a, 0x70,
-0xc3, 0xe5, 0xc3, 0x86, 0x4b, 0x85, 0x94, 0x14,
-0x2c, 0xc1, 0x87, 0x36, 0xa7, 0x41, 0x34, 0x3e,
-0x2c, 0x64, 0x66, 0x26, 0x97, 0x6e, 0xcc, 0x3f,
-0xd6, 0xf6, 0xf6, 0xb6, 0x68, 0x3e, 0xa7, 0x25,
-0xf7, 0x32, 0x3e, 0xcc, 0x63, 0xc6, 0xb1, 0xb8,
-0xe1, 0xf9, 0x07, 0xcd, 0x20, 0x1a, 0x5f, 0xfc,
-0xf0, 0x48, 0x0c, 0xb9, 0x29, 0x50, 0x9b, 0x8c,
-0x18, 0xa4, 0xc0, 0x62, 0x6a, 0x92, 0x5f, 0x3b,
-0xd9, 0x26, 0x0c, 0xf8, 0x84, 0x10, 0xe8, 0x40,
-0x15, 0xba, 0xa1, 0x09, 0xf8, 0xed, 0xf2, 0xc2,
-0xf8, 0xf9, 0xb0, 0xbb, 0x21, 0xff, 0x8c, 0x87,
-0x1f, 0xa3, 0x95, 0x0b, 0xe9, 0xf5, 0xf6, 0xf8,
-0xaa, 0x56, 0xfa, 0x0d, 0x1a, 0x75, 0x3c, 0xd4,
-0x4a, 0x2f, 0x5e, 0xe8, 0x5d, 0x9f, 0x18, 0x0f,
-0x85, 0xb9, 0x89, 0xfb, 0xc6, 0x43, 0x0a, 0x15,
-0xdc, 0xf4, 0xa7, 0x70, 0xf7, 0x3f, 0xcf, 0xf8,
-0x10, 0x5c, 0xc3, 0x79, 0xe0, 0x3b, 0xd7, 0x24,
-0x1d, 0xdf, 0x78, 0x38, 0x16, 0x32, 0x3e, 0x5c,
-0x3a, 0x3a, 0xea, 0xe7, 0xc3, 0xf7, 0xeb, 0x7c,
-0xb8, 0xb7, 0x91, 0x0f, 0x39, 0x7d, 0x31, 0x3e,
-0xdc, 0x78, 0x68, 0x8b, 0x9f, 0x0f, 0xaf, 0xdf,
-0x25, 0x3e, 0xe4, 0x58, 0xf8, 0xdb, 0x54, 0x6d,
-0x61, 0xe0, 0x4f, 0x01, 0x8a, 0x07, 0xbb, 0xde,
-0x65, 0x58, 0x38, 0xf5, 0xd6, 0xc2, 0xea, 0x9a,
-0x6b, 0xfc, 0xed, 0xf9, 0xd9, 0xff, 0xb8, 0x8a,
-0xed, 0xff, 0x12, 0xa0, 0xb8, 0xb0, 0xf1, 0x10,
-0xc3, 0xc2, 0xab, 0xd7, 0x16, 0x36, 0xd6, 0x5c,
-0xd3, 0xd0, 0xbe, 0xd3, 0xe5, 0xc3, 0x4c, 0xe7,
-0xe6, 0x5f, 0xa6, 0x7b, 0x90, 0x0f, 0x33, 0x2f,
-0x6f, 0x3e, 0xc7, 0x09, 0x33, 0xc3, 0x51, 0xb3,
-0x72, 0xed, 0x3f, 0x8c, 0xdf, 0x04, 0x83, 0xb0,
-0xdb, 0x33, 0x4c, 0xc8, 0xc5, 0xef, 0xbc, 0x17,
-0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29,
-0x29, 0x29, 0xa9, 0xff, 0xbb, 0x78, 0xed, 0xa0,
-0xc8, 0xda, 0x41, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0xea, 0xd6, 0xe2,
-0xb5, 0x43, 0x54, 0xd6, 0x0e, 0x52, 0x52, 0x52,
-0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52,
-0xb7, 0x16, 0xaf, 0x1d, 0x54, 0x5e, 0x3b, 0xe0,
-0x5f, 0x91, 0xbe, 0x27, 0x77, 0xd3, 0x81, 0xfe,
-0x97, 0x76, 0x07, 0x74, 0xb6, 0xee, 0x73, 0xf0,
-0x00, 0xcd, 0x58, 0xd0, 0x70, 0x13, 0xda, 0x5d,
-0x94, 0xd2, 0xf4, 0xcc, 0x31, 0x7b, 0x69, 0xdb,
-0x97, 0x85, 0x60, 0xba, 0x87, 0x81, 0x39, 0x36,
-0x7e, 0x0a, 0x03, 0x4e, 0x30, 0xfd, 0x2b, 0xc6,
-0xcc, 0x09, 0x67, 0xe5, 0xc5, 0xd7, 0x5f, 0x09,
-0xa6, 0x7b, 0x30, 0xe7, 0xcc, 0xdf, 0x69, 0x66,
-0xbf, 0x63, 0x3a, 0xc1, 0xf4, 0x9f, 0x78, 0xf8,
-0xe0, 0x11, 0xa7, 0xe3, 0x93, 0xa7, 0xb7, 0x04,
-0xd3, 0x3d, 0xce, 0xbf, 0x18, 0x7f, 0x50, 0xf3,
-0x1f, 0x5f, 0x73, 0xdc, 0x86, 0x47, 0x57, 0x54,
-0x83, 0x9b, 0xff, 0x65, 0x18, 0x3f, 0x5b, 0x20,
-0xa8, 0xf9, 0x6f, 0xce, 0x9e, 0x9e, 0x87, 0x7b,
-0x76, 0x7c, 0xbe, 0x29, 0x98, 0xee, 0x71, 0xfe,
-0xc5, 0xf8, 0x03, 0x8b, 0xff, 0xb5, 0x6d, 0x1f,
-0xd3, 0xa5, 0xcf, 0xcf, 0xa8, 0xb7, 0x6f, 0x7a,
-0x47, 0x32, 0xe7, 0x06, 0x30, 0x7e, 0x0e, 0x05,
-0x17, 0xff, 0x1a, 0xd9, 0x00, 0xab, 0x63, 0xf7,
-0x06, 0x17, 0xff, 0x62, 0xfc, 0x41, 0xcd, 0x7f,
-0x22, 0x6d, 0x0d, 0xc3, 0xba, 0xeb, 0xd9, 0xa0,
-0xe2, 0xc7, 0xac, 0x39, 0x2c, 0x7f, 0x9a, 0xf3,
-0x4e, 0x30, 0xfd, 0x2b, 0xea, 0x81, 0x37, 0x9d,
-0x0d, 0x9f, 0xce, 0x04, 0x96, 0xff, 0xdd, 0xf1,
-0xdf, 0xfc, 0xcb, 0x04, 0x77, 0x47, 0x4a, 0x66,
-0xe6, 0x94, 0x93, 0x59, 0x31, 0x1d, 0x58, 0xfe,
-0xa9, 0xcd, 0xb3, 0xfc, 0x39, 0x1f, 0xd4, 0xfc,
-0x2f, 0xeb, 0xff, 0xf5, 0x9a, 0xd3, 0xfb, 0xe3,
-0xe3, 0x73, 0xc1, 0x74, 0x8f, 0xf3, 0x2f, 0xc6,
-0x1f, 0xd8, 0xfc, 0xf7, 0xbf, 0xf6, 0x8e, 0xfd,
-0xd0, 0x8a, 0x93, 0xb1, 0xdb, 0x37, 0xbd, 0x23,
-0x99, 0xb5, 0x39, 0x96, 0x3f, 0x03, 0x8b, 0xff,
-0x68, 0xe7, 0xa9, 0x67, 0xed, 0xec, 0x57, 0x3f,
-0x59, 0xc1, 0x74, 0x8f, 0xf3, 0x2f, 0xc6, 0x1f,
-0xd8, 0xfc, 0xaf, 0xde, 0xf1, 0x05, 0x18, 0x6d,
-0x6f, 0x07, 0x97, 0x7f, 0x6a, 0x2c, 0x7f, 0x06,
-0x17, 0xff, 0x2b, 0x23, 0x69, 0xda, 0x7f, 0x32,
-0xf1, 0x7d, 0x30, 0xdd, 0xb3, 0x1f, 0x39, 0xe1,
-0xe3, 0x0f, 0x66, 0xfe, 0x4d, 0xf6, 0x7c, 0x1c,
-0xbc, 0xd8, 0x6a, 0x82, 0xcd, 0x9e, 0x5a, 0x09,
-0x9b, 0x40, 0xff, 0xf5, 0xff, 0x13, 0xdc, 0xf7,
-0x46, 0x4c, 0xa8, 0x12, 0xaf, 0xcf, 0x2b, 0x7b,
-0x6e, 0x6c, 0xf7, 0x37, 0xea, 0xe7, 0xba, 0x8f,
-0xf0, 0x33, 0x01, 0x00,
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
deleted file mode 100644
index 8bd4223..0000000
--- a/board/esd/hh405/hh405.c
+++ /dev/null
@@ -1,895 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006-2007
- * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <pci.h>
-#include <sm501.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* FPGA internal regs */
-#define FPGA_CTRL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
-#define FPGA_STATUS ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
-#define FPGA_CTR ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
-#define FPGA_BL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
-
-/* FPGA Control Reg */
-#define FPGA_CTRL_REV0 0x0001
-#define FPGA_CTRL_REV1 0x0002
-#define FPGA_CTRL_VGA0_BL 0x0004
-#define FPGA_CTRL_VGA0_BL_MODE 0x0008
-#define FPGA_CTRL_CF_RESET 0x0040
-#define FPGA_CTRL_PS2_PWR 0x0080
-#define FPGA_CTRL_CF_PWRN 0x0100 /* low active */
-#define FPGA_CTRL_CF_BUS_EN 0x0200
-#define FPGA_CTRL_LCD_CLK 0x7000 /* mask for lcd clock */
-#define FPGA_CTRL_OW_ENABLE 0x8000
-
-#define FPGA_STATUS_CF_DETECT 0x8000
-
-#ifdef CONFIG_VIDEO_SM501
-
-#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
- (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
-
-#ifdef CONFIG_VIDEO_SM501_8BPP
-#error CONFIG_VIDEO_SM501_8BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_8BPP */
-
-#ifdef CONFIG_VIDEO_SM501_16BPP
-#define BPP 16
-
-/*
- * 800x600 display B084SN03: PCLK = 40MHz
- * => 2*PCLK = 80MHz
- * 336/4 = 84MHz
- * => PCLK = 84MHz
- */
-static const SMI_REGS init_regs_800x600 [] =
-{
-#if 1 /* test-only */
- {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
-#else
- {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
-#endif
- {0x00004, SWAP32(0x00000000)},
- /* clocks for pm1... */
- {0x00048, SWAP32(0x00021807)},
- {0x0004C, SWAP32(0x221a0a01)},
- {0x00054, SWAP32(0x00000001)},
- /* clocks for pm0... */
- {0x00040, SWAP32(0x00021807)},
- {0x00044, SWAP32(0x221a0a01)},
- {0x00054, SWAP32(0x00000000)},
- /* GPIO */
- {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
- /* panel control regs... */
- {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
- {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
- {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
- {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
- {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
- {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
- {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
- {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
- {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
- {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
- {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
- {0x80200, SWAP32(0x00010000)}, /* crt display control */
- {0, 0}
-};
-
-/*
- * 1024x768 display G150XG02: PCLK = 65MHz
- * => 2*PCLK = 130MHz
- * 288/2 = 144MHz
- * => PCLK = 72MHz
- */
-static const SMI_REGS init_regs_1024x768 [] =
-{
- {0x00004, SWAP32(0x00000000)},
- /* clocks for pm1... */
- {0x00048, SWAP32(0x00021807)},
- {0x0004C, SWAP32(0x011a0a01)},
- {0x00054, SWAP32(0x00000001)},
- /* clocks for pm0... */
- {0x00040, SWAP32(0x00021807)},
- {0x00044, SWAP32(0x011a0a01)},
- {0x00054, SWAP32(0x00000000)},
- /* GPIO */
- {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
- /* panel control regs... */
- {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
- {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
- {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
- {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
- {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
- {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
- {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
- {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
- {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
- {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
- {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
- {0x80200, SWAP32(0x00010000)}, /* crt display control */
- {0, 0}
-};
-
-#endif /* CONFIG_VIDEO_SM501_16BPP */
-
-#ifdef CONFIG_VIDEO_SM501_32BPP
-#define BPP 32
-
-/*
- * 800x600 display B084SN03: PCLK = 40MHz
- * => 2*PCLK = 80MHz
- * 336/4 = 84MHz
- * => PCLK = 84MHz
- */
-static const SMI_REGS init_regs_800x600 [] =
-{
-#if 0 /* test-only */
- {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
-#else
- {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
-#endif
- {0x00004, SWAP32(0x00000000)},
- /* clocks for pm1... */
- {0x00048, SWAP32(0x00021807)},
- {0x0004C, SWAP32(0x221a0a01)},
- {0x00054, SWAP32(0x00000001)},
- /* clocks for pm0... */
- {0x00040, SWAP32(0x00021807)},
- {0x00044, SWAP32(0x221a0a01)},
- {0x00054, SWAP32(0x00000000)},
- /* GPIO */
- {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
- /* panel control regs... */
- {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
- {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
- {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
- {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
- {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
- {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
- {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
- {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
- {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
- {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
- {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
- {0x80200, SWAP32(0x00010000)}, /* crt display control */
- {0, 0}
-};
-
-/*
- * 1024x768 display G150XG02: PCLK = 65MHz
- * => 2*PCLK = 130MHz
- * 288/2 = 144MHz
- * => PCLK = 72MHz
- */
-static const SMI_REGS init_regs_1024x768 [] =
-{
- {0x00004, SWAP32(0x00000000)},
- /* clocks for pm1... */
- {0x00048, SWAP32(0x00021807)},
- {0x0004C, SWAP32(0x011a0a01)},
- {0x00054, SWAP32(0x00000001)},
- /* clocks for pm0... */
- {0x00040, SWAP32(0x00021807)},
- {0x00044, SWAP32(0x011a0a01)},
- {0x00054, SWAP32(0x00000000)},
- /* GPIO */
- {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
- /* panel control regs... */
- {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
- {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
- {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
- {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
- {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
- {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
- {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
- {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
- {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
- {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
- {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
- {0x80200, SWAP32(0x00010000)}, /* crt display control */
- {0, 0}
-};
-
-#endif /* CONFIG_VIDEO_SM501_32BPP */
-
-#endif /* CONFIG_VIDEO_SM501 */
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-extern void lxt971_no_sleep(void);
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-/* logo bitmap data - gzip compressed and generated by bin2c */
-unsigned char logo_bmp_320[] =
-{
-#include "logo_320_240_4bpp.c"
-};
-
-unsigned char logo_bmp_320_8bpp[] =
-{
-#include "logo_320_240_8bpp.c"
-};
-
-unsigned char logo_bmp_640[] =
-{
-#include "logo_640_480_24bpp.c"
-};
-
-unsigned char logo_bmp_1024[] =
-{
-#include "logo_1024_768_8bpp.c"
-};
-
-
-/*
- * include common lcd code (for esd boards)
- */
-#include "../common/lcd.c"
-
-#include "../common/s1d13704_320_240_4bpp.h"
-#include "../common/s1d13705_320_240_8bpp.h"
-#include "../common/s1d13806_640_480_16bpp.h"
-#include "../common/s1d13806_1024_768_8bpp.h"
-
-
-/*
- * include common auto-update code (for esd boards)
- */
-#include "../common/auto_update.h"
-
-au_image_t au_image[] = {
- {"hh405/preinst.img", 0, -1, AU_SCRIPT},
- {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
- {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
- {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
- {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
- {"hh405/postinst.img", 0, 0, AU_SCRIPT},
-};
-
-int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
-
-/*
- * Get version of HH405 board from GPIO's
- */
-int board_revision(void)
-{
- unsigned long osrh_reg;
- unsigned long isr1h_reg;
- unsigned long tcr_reg;
- unsigned long value;
-
- /*
- * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
- */
- osrh_reg = in_be32((void *)GPIO0_OSRH);
- isr1h_reg = in_be32((void *)GPIO0_ISR1H);
- tcr_reg = in_be32((void *)GPIO0_TCR);
- out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
- out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
- out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
-
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void *)GPIO0_IR) & 0x80400000; /* get config bits */
-
- /*
- * Restore GPIO settings
- */
- out_be32((void *)GPIO0_OSRH, osrh_reg); /* output select */
- out_be32((void *)GPIO0_ISR1H, isr1h_reg); /* input select */
- out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
-
- if (value & 0x80000000) {
- /* Revision 1.0 or 1.1 detected */
- return 1;
- } else {
- if (value & 0x00400000) {
- /* unused */
- return 3;
- } else {
- return 2;
- }
- }
-}
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-int cf_enable(void)
-{
- int i;
-
- if (gd->board_type >= 2) {
- if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
- if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
-
- for (i=0; i<300; i++)
- udelay(1000);
-
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
-
- for (i=0; i<20; i++)
- udelay(1000);
- }
- } else {
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
- }
- }
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
- char *str;
- unsigned long contrast0 = 0xffffffff;
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_INIT pin
- */
- /* setup FPGA_INIT as output */
- out_be32((void *)GPIO0_TCR,
- in_be32((void *)GPIO0_TCR) | FPGA_INIT);
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */
- udelay(1000); /* wait 1ms */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */
- udelay(1000); /* wait 1ms */
-
- /*
- * Write Board revision into FPGA
- */
- out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
-
- /*
- * Setup and enable EEPROM write protection
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
-
- /*
- * Reset touch-screen controller
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
- udelay(1000);
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
-
- /*
- * Enable power on PS/2 interface (with reset)
- */
- out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
- for (i=0;i<500;i++)
- udelay(1000);
- out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
-
- /*
- * Get contrast value from environment variable
- */
- str = getenv("contrast0");
- if (str) {
- contrast0 = simple_strtol(str, NULL, 16);
- if (contrast0 > 255) {
- printf("ERROR: contrast0 value too high (0x%lx)!\n",
- contrast0);
- contrast0 = 0xffffffff;
- }
- }
-
- /*
- * Init lcd interface and display logo
- */
-
- str = getenv("bd_type");
- if (strcmp(str, "ppc230") == 0) {
- /*
- * Switch backlight on
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
- out_be16(FPGA_BL, 0x0000);
-
- lcd_setup(1, 0);
- lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13806_1024_768_8bpp,
- sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
- logo_bmp_1024, sizeof(logo_bmp_1024));
- } else if (strcmp(str, "ppc220") == 0) {
- /*
- * Switch backlight on
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
- out_be16(FPGA_BL, 0x0000);
-
- lcd_setup(1, 0);
- lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13806_640_480_16bpp,
- sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
- logo_bmp_640, sizeof(logo_bmp_640));
- } else if (strcmp(str, "ppc215") == 0) {
- /*
- * Set default display contrast voltage
- */
- if (contrast0 == 0xffffffff) {
- out_be16(FPGA_CTR, 0x0082);
- } else {
- out_be16(FPGA_CTR, contrast0);
- }
- out_be16(FPGA_BL, 0xffff);
- /*
- * Switch backlight on
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) |
- FPGA_CTRL_VGA0_BL |
- FPGA_CTRL_VGA0_BL_MODE);
- /*
- * Set lcd clock (small epson)
- */
- out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
- udelay(100); /* wait for 100 us */
-
- lcd_setup(0, 1);
- lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
- regs_13705_320_240_8bpp,
- sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
- logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
- } else if (strcmp(str, "ppc210") == 0) {
- /*
- * Set default display contrast voltage
- */
- if (contrast0 == 0xffffffff) {
- out_be16(FPGA_CTR, 0x0060);
- } else {
- out_be16(FPGA_CTR, contrast0);
- }
- out_be16(FPGA_BL, 0xffff);
- /*
- * Switch backlight on
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) |
- FPGA_CTRL_VGA0_BL |
- FPGA_CTRL_VGA0_BL_MODE);
- /*
- * Set lcd clock (small epson), enable 1-wire interface
- */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) |
- LCD_CLK_08330 |
- FPGA_CTRL_OW_ENABLE);
-
- lcd_setup(0, 1);
- lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
- regs_13704_320_240_4bpp,
- sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
- logo_bmp_320, sizeof(logo_bmp_320));
-#ifdef CONFIG_VIDEO_SM501
- } else {
- pci_dev_t devbusfn;
-
- /*
- * Is SM501 connected (ppc221/ppc231)?
- */
- devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
- if (devbusfn != -1) {
- puts("VGA: SM501 with 8 MB ");
- if (strcmp(str, "ppc221") == 0) {
- printf("(800*600, %dbpp)\n", BPP);
- out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
- } else if (strcmp(str, "ppc231") == 0) {
- printf("(1024*768, %dbpp)\n", BPP);
- out_be16(FPGA_BL, 0x0000);
- } else {
- printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
- return 0;
- }
- } else {
- printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
- return 0;
- }
-#endif /* CONFIG_VIDEO_SM501 */
- }
-
- cf_enable();
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming HH405");
- } else {
- puts(str);
- }
-
- if (getenv_f("bd_type", str, sizeof(str)) != -1) {
- printf(" (%s", str);
- } else {
- puts(" (Missing bd_type!");
- }
-
- gd->board_type = board_revision();
- printf(", Rev %ld.x)\n", gd->board_type);
-
- return 0;
-}
-
-#ifdef CONFIG_IDE_RESET
-void ide_set_reset(int on)
-{
- if (((gd->board_type >= 2) &&
- (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
- (gd->board_type < 2)) {
- /*
- * Assert or deassert CompactFlash Reset Pin
- */
- if (on) { /* assert RESET */
- cf_enable();
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) &
- ~FPGA_CTRL_CF_RESET);
- } else { /* release RESET */
- out_be16(FPGA_CTRL,
- in_be16(FPGA_CTRL) |
- FPGA_CTRL_CF_RESET);
- }
- }
-}
-#endif /* CONFIG_IDE_RESET */
-
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state)
-{
- if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
- return -1;
- } else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = (0 == (in_be32((void *)GPIO0_OR) &
- CONFIG_SYS_EEPROM_WP));
- break;
- }
- }
- return state;
-}
-
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
- if (state < 0) {
- puts ("Query of write access state failed.\n");
- } else {
- printf ("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
- state = 0;
- }
- } else {
- if ('0' == argv[1][0]) {
- /* Disable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0) {
- puts ("Setup of write access state failed.\n");
- }
- }
-
- return state;
-}
-
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-
-#ifdef CONFIG_VIDEO_SM501
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
- char str[64];
- char str2[64];
- int i = getenv_f("serial#", str2, sizeof(str));
-
- if (line_number == 1) {
- sprintf(str, " Board: ");
-
- if (i == -1) {
- strcat(str, "### No HW ID - assuming HH405");
- } else {
- strcat(str, str2);
- }
-
- if (getenv_f("bd_type", str2, sizeof(str2)) != -1) {
- strcat(str, " (");
- strcat(str, str2);
- } else {
- strcat(str, " (Missing bd_type!");
- }
-
- sprintf(str2, ", Rev %ld.x)", gd->board_type);
- strcat(str, str2);
- strcpy(info, str);
- } else {
- info [0] = '\0';
- }
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-
-/*
- * Returns SM501 register base address. First thing called in the driver.
- */
-unsigned int board_video_init (void)
-{
- pci_dev_t devbusfn;
- u32 addr;
-
- /*
- * Is SM501 connected (ppc221/ppc231)?
- */
- devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
- if (devbusfn != -1) {
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
- return (addr & 0xfffffffe);
- }
-
- return 0;
-}
-
-/*
- * Returns SM501 framebuffer address
- */
-unsigned int board_video_get_fb (void)
-{
- pci_dev_t devbusfn;
- u32 addr;
-
- /*
- * Is SM501 connected (ppc221/ppc231)?
- */
- devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
- if (devbusfn != -1) {
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
- addr &= 0xfffffffe;
-#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
- addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
-#endif
- return addr;
- }
-
- return 0;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen (unsigned int base)
-{
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs (void)
-{
- char *str;
-
- str = getenv("bd_type");
- if (strcmp(str, "ppc221") == 0) {
- return init_regs_800x600;
- } else {
- return init_regs_1024x768;
- }
-}
-
-int board_get_width (void)
-{
- char *str;
-
- str = getenv("bd_type");
- if (strcmp(str, "ppc221") == 0) {
- return 800;
- } else {
- return 1024;
- }
-}
-
-int board_get_height (void)
-{
- char *str;
-
- str = getenv("bd_type");
- if (strcmp(str, "ppc221") == 0) {
- return 600;
- } else {
- return 768;
- }
-}
-
-#endif /* CONFIG_VIDEO_SM501 */
-
-
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
diff --git a/board/esd/hh405/logo_1024_768_8bpp.c b/board/esd/hh405/logo_1024_768_8bpp.c
deleted file mode 100644
index 331540f..0000000
--- a/board/esd/hh405/logo_1024_768_8bpp.c
+++ /dev/null
@@ -1,5087 +0,0 @@
-0x1f, 0x8b, 0x08, 0x08, 0x20, 0xb5, 0x06, 0x40,
-0x00, 0x03, 0x48, 0x6f, 0x6c, 0x7a, 0x2d, 0x48,
-0x65, 0x72, 0x5f, 0x64, 0x74, 0x5f, 0x33, 0x43,
-0x5f, 0x31, 0x30, 0x32, 0x34, 0x78, 0x37, 0x36,
-0x38, 0x5f, 0x32, 0x35, 0x36, 0x2e, 0x62, 0x6d,
-0x70, 0x00, 0xec, 0xbd, 0x0b, 0x74, 0x23, 0xd7,
-0x79, 0xa0, 0x59, 0x14, 0x0d, 0x1d, 0x71, 0xb6,
-0xc9, 0x43, 0x37, 0xe4, 0xe4, 0xa8, 0xa2, 0x0c,
-0x80, 0x58, 0xeb, 0x14, 0x48, 0x77, 0x7a, 0xe2,
-0xb4, 0x2c, 0xcb, 0x56, 0x4b, 0xed, 0xb6, 0x8e,
-0xc2, 0x84, 0x4e, 0x6d, 0x83, 0x05, 0x80, 0x8b,
-0x09, 0x0c, 0xec, 0x28, 0x1c, 0xc3, 0x69, 0x39,
-0x41, 0x4f, 0xec, 0xc4, 0xde, 0x44, 0xc1, 0x60,
-0x6d, 0xb5, 0xdb, 0x8c, 0x9b, 0x09, 0x99, 0x75,
-0xbc, 0xd3, 0xed, 0xce, 0x64, 0xc6, 0x36, 0xd0,
-0x72, 0xa4, 0x90, 0x9d, 0x50, 0x4b, 0xb5, 0x12,
-0xef, 0x78, 0x26, 0xb6, 0x3c, 0x93, 0x2c, 0x8f,
-0x93, 0x33, 0x50, 0x9e, 0x92, 0x10, 0xc2, 0xe3,
-0xcd, 0x61, 0x98, 0xd6, 0x63, 0x77, 0x04, 0xd2,
-0x40, 0x09, 0x38, 0x7b, 0xef, 0xad, 0xd7, 0x7d,
-0x15, 0x50, 0x20, 0xd9, 0x0f, 0xa9, 0xff, 0x0f,
-0x20, 0x88, 0x47, 0xbd, 0xeb, 0xfe, 0x8f, 0xfb,
-0xdf, 0xff, 0xde, 0x7b, 0xfc, 0xa7, 0xde, 0xfd,
-0x96, 0x03, 0x0a, 0xe6, 0xdd, 0x6f, 0x51, 0x14,
-0x0d, 0xbf, 0x41, 0xff, 0x95, 0x61, 0x45, 0x19,
-0x52, 0x6e, 0x53, 0x1c, 0xde, 0xfe, 0x23, 0xd6,
-0x9f, 0xc3, 0x5b, 0x6e, 0x79, 0x8b, 0xf2, 0xe8,
-0xa7, 0x1e, 0x55, 0xee, 0x3c, 0xfe, 0x98, 0xf2,
-0xf5, 0x3f, 0xfe, 0x9a, 0xf2, 0x53, 0x8f, 0xfd,
-0x89, 0xf2, 0xfe, 0x0f, 0x3c, 0xa8, 0xdc, 0x35,
-0xf7, 0x5f, 0x94, 0xf2, 0x97, 0xd6, 0x95, 0xb7,
-0xfe, 0xd0, 0x43, 0xca, 0x0b, 0xdf, 0x79, 0x41,
-0x79, 0xf0, 0xe1, 0xc7, 0x94, 0x7f, 0xf7, 0xcd,
-0x2d, 0x25, 0xfb, 0xf0, 0x9c, 0x72, 0xe1, 0x4b,
-0x17, 0x94, 0x3b, 0x7f, 0xe8, 0x4e, 0xe5, 0xe4,
-0x57, 0xbe, 0xab, 0x1c, 0xf9, 0xd4, 0x15, 0xe5,
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diff --git a/board/esd/hh405/logo_320_240_4bpp.c b/board/esd/hh405/logo_320_240_4bpp.c
deleted file mode 100644
index 52989de..0000000
--- a/board/esd/hh405/logo_320_240_4bpp.c
+++ /dev/null
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diff --git a/board/esd/hh405/logo_320_240_8bpp.c b/board/esd/hh405/logo_320_240_8bpp.c
deleted file mode 100644
index 7500448..0000000
--- a/board/esd/hh405/logo_320_240_8bpp.c
+++ /dev/null
@@ -1,1042 +0,0 @@
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diff --git a/board/esd/hh405/logo_640_480_24bpp.c b/board/esd/hh405/logo_640_480_24bpp.c
deleted file mode 100644
index 3f8bb9e..0000000
--- a/board/esd/hh405/logo_640_480_24bpp.c
+++ /dev/null
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-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x6b, 0xbf,
-0x00, 0xff, 0xcf, 0xfd, 0x4c, 0x36, 0x10, 0x0e,
-0x00,
diff --git a/board/esd/hub405/Kconfig b/board/esd/hub405/Kconfig
deleted file mode 100644
index 2b9556a..0000000
--- a/board/esd/hub405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_HUB405
-
-config SYS_BOARD
- default "hub405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "HUB405"
-
-endif
diff --git a/board/esd/hub405/MAINTAINERS b/board/esd/hub405/MAINTAINERS
deleted file mode 100644
index e84a1d9..0000000
--- a/board/esd/hub405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HUB405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/hub405/
-F: include/configs/HUB405.h
-F: configs/HUB405_defconfig
diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile
deleted file mode 100644
index 99e18b5..0000000
--- a/board/esd/hub405/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hub405.o flash.o \
- ../common/misc.o \
- ../common/esd405ep_nand.o \
diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/hub405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
deleted file mode 100644
index 1423744..0000000
--- a/board/esd/hub405/hub405.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-int board_revision(void)
-{
- unsigned long osrl_reg;
- unsigned long isr1l_reg;
- unsigned long tcr_reg;
- unsigned long value;
-
- /*
- * Get version of HUB405 board from GPIO's
- */
-
- /*
- * Setup GPIO pin(s) (IRQ6/GPIO23)
- */
- osrl_reg = in_be32((void *)GPIO0_OSRH);
- isr1l_reg = in_be32((void *)GPIO0_ISR1H);
- tcr_reg = in_be32((void *)GPIO0_TCR);
- out_be32((void *)GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */
- out_be32((void *)GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */
- out_be32((void *)GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */
-
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void *)GPIO0_IR) & 0x00000100; /* get config bits */
-
- /*
- * Restore GPIO settings
- */
- out_be32((void *)GPIO0_OSRH, osrl_reg); /* output select */
- out_be32((void *)GPIO0_ISR1H, isr1l_reg); /* input select */
- out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
-
- if (value & 0x00000100) {
- /* Revision 1.1 or 1.2 detected */
- return 1;
- }
-
- /* Revision 1.0 */
- return 0;
-}
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-#define LED_REG (DUART0_BA + 0x20)
-int misc_init_r (void)
-{
- unsigned long val;
- int delay, flashcnt;
- char *str;
- char hw_rev[4];
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- out_8((void *)(DUART0_BA + 4), 0x08);
- out_8((void *)(DUART1_BA + 4), 0x08);
- out_8((void *)(DUART2_BA + 4), 0x08);
- out_8((void *)(DUART3_BA + 4), 0x08);
-
- /*
- * Set RS232/RS422 control (RS232 = high on GPIO)
- */
- val = in_be32((void *)GPIO0_OR);
- val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 |
- CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232);
-
- str = getenv("phys0");
- if (!str || (str && (str[0] == '0')))
- val |= CONFIG_SYS_UART2_RS232;
-
- str = getenv("phys1");
- if (!str || (str && (str[0] == '0')))
- val |= CONFIG_SYS_UART3_RS232;
-
- str = getenv("phys2");
- if (!str || (str && (str[0] == '0')))
- val |= CONFIG_SYS_UART4_RS232;
-
- str = getenv("phys3");
- if (!str || (str && (str[0] == '0')))
- val |= CONFIG_SYS_UART5_RS232;
-
- out_be32((void *)GPIO0_OR, val);
-
- /*
- * check board type and setup AP power
- */
- str = getenv("bd_type"); /* this is only set on non prototype hardware */
- if (str != NULL) {
- if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
- unsigned char led_reg_default = 0;
- str = getenv("ap_pwr");
- if (!str || (str && (str[0] == '1')))
- led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
-
- /*
- * Flash LEDs
- */
- for (flashcnt = 0; flashcnt < 3; flashcnt++) {
- /* LED_A..D off */
- out_8((void *)LED_REG, led_reg_default);
- for (delay = 0; delay < 100; delay++)
- udelay(1000);
- /* LED_A..D on */
- out_8((void *)LED_REG, led_reg_default | 0xf0);
- for (delay = 0; delay < 50; delay++)
- udelay(1000);
- }
- out_8((void *)LED_REG, led_reg_default);
- }
- }
-
- /*
- * Reset external DUARTs
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
- udelay(10); /* wait 10us */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
- udelay(1000); /* wait 1ms */
-
- /*
- * Store hardware revision in environment for further processing
- */
- sprintf(hw_rev, "1.%ld", gd->board_type);
- setenv("hw_rev", hw_rev);
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming HUB405");
- } else {
- puts(str);
- }
-
- if (getenv_f("bd_type", str, sizeof(str)) != -1) {
- printf(" (%s", str);
- } else {
- puts(" (Missing bd_type!");
- }
-
- gd->board_type = board_revision();
- printf(", Rev 1.%ld)\n", gd->board_type);
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
- return 0;
-}
diff --git a/board/esd/mecp5200/Kconfig b/board/esd/mecp5200/Kconfig
deleted file mode 100644
index cfd5307..0000000
--- a/board/esd/mecp5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MECP5200
-
-config SYS_BOARD
- default "mecp5200"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "mecp5200"
-
-endif
diff --git a/board/esd/mecp5200/MAINTAINERS b/board/esd/mecp5200/MAINTAINERS
deleted file mode 100644
index 05b7824..0000000
--- a/board/esd/mecp5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MECP5200 BOARD
-M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S: Maintained
-F: board/esd/mecp5200/
-F: include/configs/mecp5200.h
-F: configs/mecp5200_defconfig
diff --git a/board/esd/mecp5200/Makefile b/board/esd/mecp5200/Makefile
deleted file mode 100644
index 3d66c9f..0000000
--- a/board/esd/mecp5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = mecp5200.o
diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c
deleted file mode 100644
index 17a70a9..0000000
--- a/board/esd/mecp5200/mecp5200.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * pf5200.c - main board support/init for the esd pf5200.
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <command.h>
-#include <netdev.h>
-
-#include "mt46v16m16-75.h"
-
-void init_power_switch(void);
-
-static void sdram_start(int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register: extended mode */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
- ulong dramsize = 0;
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
- /* set tap delay */
- *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
-
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20))
- dramsize = 0;
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
- } else {
-#if 0
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
-#else
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
-#endif
- }
-
-#if 0
- /* find RAM size using SDRAM CS1 only */
- sdram_start(0);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(1);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(0);
-#endif
- /* set SDRAM CS1 size according to the amount of RAM found */
-
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
- init_power_switch();
- return (dramsize);
-}
-
-int checkboard(void)
-{
- puts("Board: esd CPX CPU5200 (mecp5200)\n");
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
- if (size == CONFIG_SYS_FLASH_SIZE) {
- /* adjust mapping */
- *(vu_long *) MPC5XXX_BOOTCS_START =
- *(vu_long *) MPC5XXX_CS0_START =
- START_REG(CONFIG_SYS_BOOTCS_START | size);
- *(vu_long *) MPC5XXX_BOOTCS_STOP =
- *(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
- }
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-#define GPIO_PSC1_4 0x01000000UL
-
-void init_ide_reset(void)
-{
- debug("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset(int idereset)
-{
- debug("ide_reset(%d)\n", idereset);
-
- if (idereset)
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- else
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-}
-#endif
-
-#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
-
-#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
-
-#define GPIO_WU6 0x40000000UL
-#define GPIO_USB0 0x00010000UL
-#define GPIO_USB9 0x08000000UL
-#define GPIO_USB9S 0x00080000UL
-
-void init_power_switch(void)
-{
- debug("init_power_switch\n");
-
- /* Configure GPIO_WU6 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
- __asm__ volatile ("sync");
-
- if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
- __asm__ volatile ("sync");
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h
deleted file mode 100644
index 63a4032..0000000
--- a/board/esd/mecp5200/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x705f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/esd/ocrtc/Kconfig b/board/esd/ocrtc/Kconfig
deleted file mode 100644
index 44b402d..0000000
--- a/board/esd/ocrtc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OCRTC
-
-config SYS_BOARD
- default "ocrtc"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "OCRTC"
-
-endif
diff --git a/board/esd/ocrtc/MAINTAINERS b/board/esd/ocrtc/MAINTAINERS
deleted file mode 100644
index 85c1a12..0000000
--- a/board/esd/ocrtc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OCRTC BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/ocrtc/
-F: include/configs/OCRTC.h
-F: configs/OCRTC_defconfig
diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile
deleted file mode 100644
index 44b7d5d..0000000
--- a/board/esd/ocrtc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o
diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c
deleted file mode 100644
index 6dcbd8b..0000000
--- a/board/esd/ocrtc/cmd_ocrtc.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <pci_ids.h>
-#include <asm/4xx_pci.h>
-
-
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Set device number on pci board
- */
-int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int idx = 1; /* start at 1 (skip device 0) */
- pci_dev_t bdf = 0;
- u32 addr;
-
- while (bdf >= 0) {
- if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) {
- break;
- }
- printf("Found device nr %d at %x!\n", idx-1, bdf);
- pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
- addr &= ~0xf;
- *(u32 *)addr = (bdf & 0x0000f800) >> 11;
- printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr);
- }
-
- return 0;
-}
-U_BOOT_CMD(
- setdevice, 1, 1, do_setdevice,
- "Set device number on pci adapter boards",
- ""
-);
-
-
-/*
- * Get device number on pci board
- */
-int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 device;
- char str[32];
-
- device = *(u32 *)0x0;
- device = 0x16 - device; /* calculate vxworks bp slot id */
- sprintf(str, "%d", device);
- setenv("slot", str);
- printf("Variabel slot set to %x\n", device);
-
- return 0;
-}
-U_BOOT_CMD(
- getdevice, 1, 1, do_getdevice,
- "Get device number and set slot env variable",
- ""
-);
-
-#endif
diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c
deleted file mode 100644
index 279746e..0000000
--- a/board/esd/ocrtc/flash.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- base_b0 = FLASH_BASE0_PRELIM;
- size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- base_b1 = FLASH_BASE1_PRELIM;
- size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
-
- if (size_b1) {
- mtdcr (EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr (EBC0_CFGDATA);
- mtdcr (EBC0_CFGADDR, PB0CR);
- base_b1 = -size_b1;
- switch (size_b1) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
- mtdcr (EBC0_CFGDATA, pbcr);
- /* printf("PB1CR = %x\n", pbcr); */
- }
-
- if (size_b0) {
- mtdcr (EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr (EBC0_CFGDATA);
- mtdcr (EBC0_CFGADDR, PB1CR);
- base_b0 = base_b1 - size_b0;
- switch (size_b1) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr (EBC0_CFGDATA, pbcr);
- /* printf("PB0CR = %x\n", pbcr); */
- }
-
- size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- base_b0 + size_b0 - monitor_flash_len,
- base_b0 + size_b0 - 1, &flash_info[0]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- base_b1 + size_b1 - monitor_flash_len,
- base_b1 + size_b1 - 1, &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- flash_protect (FLAG_PROTECT_CLEAR,
- base_b0 + size_b0 - monitor_flash_len,
- base_b0 + size_b0 - 1, &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- return (size_b0 + size_b1);
-}
diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c
deleted file mode 100644
index b815961..0000000
--- a/board/esd/ocrtc/ocrtc.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include "ocrtc.h"
-#include <asm/processor.h>
-#include <i2c.h>
-#include <command.h>
-
-
-extern void lxt971_no_sleep(void);
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
- mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
- mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
- * transfers, set device-paced timeout to 256 cycles
- */
- mtebc (EBC0_CFG, 0x20400000);
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof (str));
-
- puts ("Board: ");
-
- if (i == -1) {
-#ifdef CONFIG_OCRTC
- puts ("### No HW ID - assuming OCRTC");
-#endif
-#ifdef CONFIG_ORSG
- puts ("### No HW ID - assuming ORSG");
-#endif
- } else {
- puts (str);
- }
-
- putc ('\n');
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
- return (0);
-}
diff --git a/board/esd/ocrtc/ocrtc.h b/board/esd/ocrtc/ocrtc.h
deleted file mode 100644
index 029e27e..0000000
--- a/board/esd/ocrtc/ocrtc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- * Start Address Length
- * +-----------------------+ 0x4000_0000 Start of Flash -----------------
- * | MON8xx code | 0x4000_0100 Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused) |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses | 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) | 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address | 0x04
- * +-----------------------+ 0x4001_FFC0 ^
- * | Hardware Information | 0x40 | MON8xx
- * +=======================+ 0x4002_0000 (sector border) -----------------
- * | Autostart Header | | Applications
- * | ... | v
- *
- *****************************************************************************/
diff --git a/board/esd/pci405/Kconfig b/board/esd/pci405/Kconfig
deleted file mode 100644
index 0a6524d..0000000
--- a/board/esd/pci405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PCI405
-
-config SYS_BOARD
- default "pci405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "PCI405"
-
-endif
diff --git a/board/esd/pci405/MAINTAINERS b/board/esd/pci405/MAINTAINERS
deleted file mode 100644
index cf9c1c9..0000000
--- a/board/esd/pci405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PCI405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/pci405/
-F: include/configs/PCI405.h
-F: configs/PCI405_defconfig
diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile
deleted file mode 100644
index 9e659c7..0000000
--- a/board/esd/pci405/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pci405.o flash.o ../common/misc.o cmd_pci405.o
-obj-y += writeibm.o
diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c
deleted file mode 100644
index 29c688a..0000000
--- a/board/esd/pci405/cmd_pci405.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <asm/4xx_pci.h>
-#include <asm/processor.h>
-
-#include "pci405.h"
-
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Command loadpci: wait for signal from host and boot image.
- */
-int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int *ptr;
- int count = 0;
- int count2 = 0;
- int i;
- char addr[16];
- char str[] = "\\|/-";
- char *local_args[2];
-
- /*
- * Mark sync address
- */
- ptr = 0;
- /* cppcheck-suppress nullPointer */
- *ptr = 0xffffffff;
- puts("\nWaiting for image from pci host -");
-
- /*
- * Wait for host to write the start address
- */
- /* cppcheck-suppress nullPointer */
- while (*ptr == 0xffffffff) {
- count++;
- if (!(count % 100)) {
- count2++;
- putc(0x08); /* backspace */
- putc(str[count2 % 4]);
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- udelay(1000);
- }
-
- if (*ptr == PCI_RECONFIG_MAGIC) {
- /*
- * Save own pci configuration in PRAM
- */
- memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
- ptr = (unsigned int *)PCI_REGS_ADDR + 1;
- for (i=0; i<0x40; i+=4) {
- pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
- }
- ptr = (unsigned int *)PCI_REGS_ADDR;
- *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
-
- printf("\nStoring PCI Configuration Regs...\n");
- } else {
- sprintf(addr, "%08x", *ptr);
-
- /*
- * Boot image via bootm
- */
- printf("\nBooting Image at addr 0x%s ...\n", addr);
- setenv("loadaddr", addr);
-
- local_args[0] = argv[0];
- local_args[1] = NULL;
- do_bootm (cmdtp, 0, 1, local_args);
- }
-
- return 0;
-}
-U_BOOT_CMD(
- loadpci, 1, 1, do_loadpci,
- "Wait for pci-image and boot it",
- ""
-);
-#endif
diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c
deleted file mode 100644
index 113111d..0000000
--- a/board/esd/pci405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -monitor_flash_len,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/pci405/fpgadata.c b/board/esd/pci405/fpgadata.c
deleted file mode 100644
index d145826..0000000
--- a/board/esd/pci405/fpgadata.c
+++ /dev/null
@@ -1,1492 +0,0 @@
-0x1f, 0x8b, 0x08, 0x08, 0xcd, 0x78, 0x61, 0x3f,
-0x00, 0x03, 0x70, 0x63, 0x69, 0x34, 0x30, 0x35,
-0x5f, 0x31, 0x5f, 0x30, 0x34, 0x2e, 0x62, 0x69,
-0x74, 0x00, 0xed, 0x9c, 0x7f, 0x78, 0x14, 0xc7,
-0x99, 0xe7, 0xdf, 0xae, 0xee, 0x11, 0x2d, 0xcd,
-0x88, 0x69, 0x89, 0x11, 0x1e, 0x3b, 0x32, 0xdb,
-0x1a, 0x09, 0x3c, 0xc1, 0x23, 0x69, 0x18, 0x61,
-0x85, 0x60, 0x79, 0xd4, 0x8c, 0x04, 0x19, 0x1b,
-0xd9, 0x4c, 0x6c, 0x27, 0x61, 0xf3, 0xf8, 0xc9,
-0x8e, 0x1d, 0x92, 0x23, 0x59, 0x92, 0x47, 0x90,
-0xdc, 0x2e, 0x49, 0x9c, 0x6c, 0x8d, 0x24, 0xd0,
-0x00, 0xb2, 0x19, 0x30, 0x97, 0xb0, 0x59, 0xce,
-0x3b, 0x60, 0x12, 0x0b, 0x9b, 0x64, 0x07, 0x61,
-0x1b, 0x61, 0x88, 0xdd, 0x92, 0x85, 0x23, 0x40,
-0x06, 0x85, 0xf5, 0x79, 0xb1, 0xcd, 0xe2, 0xc1,
-0x91, 0xbd, 0xb2, 0x23, 0x63, 0x19, 0xb3, 0x8e,
-0x00, 0x19, 0xdd, 0x5b, 0xdd, 0x3d, 0xdd, 0x2d,
-0xe1, 0xfd, 0x71, 0xb7, 0xf7, 0xdc, 0xde, 0xf3,
-0x9c, 0xdb, 0x7f, 0xb8, 0x50, 0xa9, 0xba, 0xab,
-0xab, 0xde, 0xfa, 0xd4, 0xf7, 0x7d, 0xdf, 0x6a,
-0x41, 0xbe, 0x7b, 0x54, 0xff, 0x0f, 0x80, 0xbb,
-0x1f, 0xa4, 0xe6, 0xaf, 0x7f, 0x6b, 0x7e, 0xf0,
-0x96, 0x3f, 0x9b, 0xf7, 0x67, 0xc1, 0xf9, 0x55,
-0xdf, 0xfd, 0xfa, 0x0a, 0x78, 0x00, 0x0a, 0x42,
-0xdf, 0x9b, 0x77, 0xcb, 0xf7, 0x57, 0xcf, 0x9b,
-0x3f, 0x1f, 0xbe, 0x0e, 0xce, 0x50, 0x30, 0x58,
-0x53, 0x1d, 0x5c, 0x50, 0x1d, 0xba, 0x05, 0x56,
-0x40, 0xfe, 0xbc, 0x05, 0x0b, 0x83, 0xb7, 0x2c,
-0x9c, 0x57, 0x03, 0xdf, 0x00, 0x88, 0x27, 0x27,
-0xf0, 0x7a, 0xe2, 0xaf, 0xbf, 0xf4, 0xcd, 0x20,
-0x50, 0x0e, 0x00, 0xa6, 0x05, 0xb9, 0x38, 0xfb,
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-0x9e, 0x8e, 0x35, 0xdc, 0x7d, 0xf4, 0x2b, 0xf2,
-0xf5, 0xfd, 0x5a, 0xe1, 0x2f, 0x91, 0x59, 0x66,
-0x1d, 0x8f, 0x50, 0x91, 0x82, 0x82, 0x8b, 0x63,
-0x85, 0xa2, 0x90, 0xe0, 0x2a, 0xb2, 0xee, 0x59,
-0x3f, 0xb1, 0x6c, 0xe2, 0xef, 0x27, 0x2e, 0x4e,
-0x7c, 0x6c, 0x16, 0xe0, 0xdf, 0x75, 0x85, 0xdf,
-0x58, 0x76, 0xb5, 0xf7, 0xa5, 0xcc, 0xfe, 0x1f,
-0x87, 0x5f, 0x77, 0xd6, 0xb2, 0xc2, 0x2a, 0xdb,
-0x3d, 0xeb, 0x97, 0x4d, 0xcc, 0xa8, 0xe9, 0x1b,
-0xf8, 0xb8, 0xbe, 0xae, 0xe9, 0x24, 0x2b, 0x7c,
-0x60, 0xab, 0xf3, 0x46, 0xcf, 0x16, 0xcf, 0x6b,
-0xeb, 0xf8, 0xc1, 0xad, 0xde, 0xe8, 0x8b, 0x33,
-0x0e, 0x60, 0xc1, 0xaa, 0x9b, 0x06, 0xab, 0x95,
-0x1d, 0xb1, 0x9b, 0x3c, 0xf9, 0x47, 0x48, 0xb3,
-0x52, 0x2a, 0xdd, 0x24, 0xe4, 0x5b, 0xef, 0x20,
-0x98, 0x9c, 0x77, 0xac, 0xe6, 0x74, 0xce, 0x9b,
-0x75, 0x1a, 0xe7, 0xe3, 0xc5, 0x5e, 0x61, 0xbd,
-0xc9, 0x79, 0xab, 0x5d, 0xfc, 0x7e, 0xed, 0xef,
-0xa9, 0x08, 0x16, 0xaf, 0xad, 0x31, 0x13, 0xd6,
-0x24, 0x4a, 0xd5, 0x2f, 0xc8, 0x45, 0xfd, 0xc2,
-0x1a, 0xae, 0x94, 0x62, 0xc1, 0xba, 0x27, 0x00,
-0xb6, 0x93, 0xf3, 0x44, 0xdb, 0x1f, 0x64, 0x31,
-0x6b, 0x24, 0x61, 0x0e, 0x97, 0x4f, 0x23, 0xcd,
-0xd2, 0xcf, 0x85, 0xd9, 0x9c, 0x48, 0x19, 0xe7,
-0xcd, 0xba, 0x32, 0x58, 0x9a, 0x28, 0x4e, 0x37,
-0x76, 0x16, 0x55, 0x09, 0x51, 0xaa, 0x15, 0xcc,
-0xa7, 0xa9, 0x55, 0xb8, 0x66, 0x3d, 0xd4, 0x11,
-0xe4, 0xee, 0x82, 0x7b, 0x70, 0xcd, 0x62, 0xc1,
-0xd8, 0x52, 0xd9, 0x81, 0x5a, 0xe1, 0x16, 0x28,
-0x52, 0x84, 0xe5, 0x9c, 0x07, 0xbe, 0x40, 0xd9,
-0x82, 0xe2, 0x8c, 0x6d, 0x1a, 0xdb, 0x29, 0x44,
-0x62, 0xa7, 0xde, 0xd8, 0x01, 0x32, 0x30, 0x0a,
-0x56, 0x9d, 0xc0, 0x00, 0x88, 0xcb, 0x80, 0x62,
-0x61, 0x3b, 0x5b, 0x0f, 0xd4, 0xa8, 0x93, 0x38,
-0x05, 0x55, 0xc7, 0x76, 0x98, 0x03, 0xf9, 0x94,
-0x3c, 0x80, 0xef, 0x80, 0x85, 0x16, 0xe3, 0x71,
-0xca, 0xe2, 0xbb, 0xf3, 0xe2, 0xc8, 0xf9, 0x06,
-0x51, 0xea, 0x15, 0x82, 0x7a, 0x21, 0xc7, 0x10,
-0x05, 0x6f, 0x2f, 0x1b, 0x78, 0xc7, 0xe7, 0x18,
-0x05, 0xa3, 0x1d, 0x38, 0x21, 0x48, 0xd9, 0xfe,
-0x00, 0xbd, 0x10, 0xec, 0xd1, 0x0a, 0x66, 0xdd,
-0xe2, 0x06, 0xa1, 0x19, 0x31, 0xbd, 0x44, 0x44,
-0xbe, 0xc4, 0x7b, 0xb4, 0x02, 0xcd, 0xdd, 0x93,
-0x63, 0x9c, 0x17, 0x91, 0x75, 0xc0, 0xf6, 0x29,
-0x17, 0x2b, 0xe4, 0xc6, 0x2c, 0xc6, 0x21, 0x97,
-0xcc, 0x76, 0xd8, 0x17, 0xd6, 0xce, 0xbc, 0xa7,
-0x82, 0xef, 0xe1, 0x81, 0xc5, 0x6c, 0x6c, 0x70,
-0x0b, 0x64, 0x85, 0x88, 0x71, 0xcf, 0x28, 0x4e,
-0xca, 0x22, 0x2a, 0xc5, 0x05, 0xaf, 0x90, 0x2b,
-0x98, 0xec, 0x89, 0x6a, 0xe7, 0x6c, 0x10, 0xef,
-0xa2, 0x80, 0xee, 0x9b, 0x5e, 0x00, 0xf3, 0x9e,
-0x8c, 0xf3, 0x0c, 0xef, 0xf9, 0x4b, 0x8c, 0x42,
-0xa1, 0xc9, 0x3a, 0x6e, 0x89, 0xb0, 0x3a, 0x51,
-0x1a, 0xff, 0x82, 0xb7, 0xe8, 0x45, 0x61, 0xf5,
-0xba, 0x1d, 0xac, 0x60, 0xbe, 0x1f, 0x8e, 0xf2,
-0x6a, 0xba, 0x23, 0x7e, 0x93, 0x37, 0xff, 0x45,
-0xb2, 0x9a, 0xde, 0xc7, 0x0a, 0xb9, 0xba, 0x18,
-0xe3, 0x3c, 0x6e, 0x0b, 0xb8, 0x3f, 0xbc, 0xe8,
-0x60, 0x37, 0xc0, 0x42, 0xaf, 0x39, 0x9e, 0xc5,
-0x50, 0x41, 0x6f, 0x97, 0x8b, 0xa3, 0xc2, 0x56,
-0xae, 0x82, 0x36, 0xd9, 0xed, 0x53, 0xc1, 0x77,
-0x28, 0xa3, 0xde, 0x78, 0x9e, 0x97, 0x5b, 0x0f,
-0xf7, 0x27, 0xb4, 0x82, 0x69, 0x4b, 0x8b, 0xe3,
-0x8e, 0x05, 0xdc, 0x2c, 0x34, 0x87, 0xa2, 0xac,
-0xb0, 0x56, 0x2f, 0x98, 0x73, 0xc4, 0xdd, 0x0d,
-0x2b, 0xe8, 0xf5, 0x72, 0x5e, 0x94, 0xdb, 0x8a,
-0x05, 0xc3, 0x50, 0x73, 0xfd, 0x64, 0xe3, 0xc9,
-0xf6, 0x00, 0xa9, 0x25, 0x57, 0xb0, 0xc6, 0x33,
-0x02, 0x31, 0x44, 0x7f, 0xa3, 0x58, 0x44, 0x04,
-0x85, 0x6a, 0x05, 0x30, 0xfb, 0x49, 0x20, 0x86,
-0x7b, 0x80, 0xc3, 0xc5, 0x35, 0xe4, 0x0a, 0x8a,
-0xd9, 0x4f, 0x51, 0x78, 0x00, 0x72, 0xba, 0x46,
-0x2f, 0x58, 0xe3, 0x19, 0x21, 0x40, 0x0d, 0xce,
-0x1b, 0x05, 0xf3, 0x9e, 0x9c, 0x52, 0x11, 0x77,
-0x78, 0x61, 0x92, 0x7d, 0x9a, 0xfd, 0x54, 0x80,
-0xfd, 0xa5, 0x85, 0x39, 0x4a, 0x7e, 0x8a, 0xac,
-0x80, 0x52, 0xcd, 0x50, 0xcd, 0x7b, 0xc6, 0xe7,
-0xf8, 0xb9, 0xe9, 0xd0, 0x40, 0xa5, 0xac, 0xb0,
-0x80, 0xbb, 0x81, 0x15, 0x72, 0xef, 0x1e, 0xc3,
-0xa5, 0x51, 0xa6, 0xb8, 0x62, 0xbc, 0x07, 0x8e,
-0xd0, 0x79, 0x8a, 0x28, 0xf1, 0x82, 0xcd, 0x3e,
-0x05, 0x98, 0xad, 0x14, 0x4a, 0xfc, 0xbd, 0xf0,
-0x3b, 0x98, 0xbf, 0x48, 0xfb, 0xa5, 0x5e, 0xab,
-0x9f, 0xc2, 0xfd, 0x3d, 0xde, 0xe0, 0x92, 0xd2,
-0xa2, 0x56, 0x66, 0x9f, 0xc1, 0x25, 0x2e, 0x9b,
-0x7d, 0x2a, 0x68, 0xea, 0xb6, 0xf5, 0x65, 0xe3,
-0xbc, 0xc2, 0x45, 0x1b, 0x43, 0x0c, 0xef, 0x65,
-0x45, 0x1d, 0x8d, 0x0f, 0x5c, 0xaf, 0x15, 0x6c,
-0xf6, 0xa9, 0x4a, 0x3f, 0xf0, 0xcc, 0x5a, 0x5c,
-0xb4, 0x45, 0x69, 0x8c, 0xc5, 0x3c, 0xc2, 0x62,
-0xae, 0x48, 0xb1, 0xd6, 0x11, 0x1b, 0x7a, 0x22,
-0x94, 0x25, 0xc4, 0xb8, 0xa2, 0x4f, 0x06, 0x98,
-0x57, 0x0e, 0xef, 0x42, 0x01, 0x67, 0x14, 0xac,
-0xf1, 0xbc, 0x93, 0xbf, 0x47, 0x79, 0x79, 0xf0,
-0x96, 0xf9, 0x85, 0x66, 0xc1, 0xbc, 0x27, 0x17,
-0xad, 0x58, 0x53, 0x58, 0x4a, 0xbe, 0x50, 0x56,
-0xa4, 0x36, 0xae, 0xc9, 0xdf, 0x31, 0x99, 0x59,
-0x33, 0x6c, 0x9c, 0xef, 0x29, 0x0a, 0x35, 0x36,
-0x6d, 0xb1, 0x9e, 0xf7, 0xbf, 0xcb, 0xf9, 0x4a,
-0x5b, 0xbb, 0xab, 0x53, 0x38, 0x5f, 0x63, 0xbf,
-0xe7, 0x14, 0xce, 0xdf, 0xea, 0xbd, 0xeb, 0x8d,
-0x47, 0x0e, 0x0c, 0xbd, 0x77, 0xe9, 0xd6, 0x9f,
-0xdc, 0x75, 0x76, 0x06, 0x2b, 0x58, 0x75, 0xe8,
-0xc3, 0xec, 0x04, 0xbf, 0x52, 0x50, 0xda, 0x6b,
-0x14, 0x24, 0xab, 0x4e, 0x23, 0x1f, 0x8e, 0x9d,
-0x64, 0x15, 0xac, 0x4b, 0x8b, 0x38, 0x31, 0x1a,
-0x9a, 0x85, 0x6b, 0xda, 0x95, 0xaa, 0xd7, 0xb6,
-0x63, 0xd9, 0x67, 0x48, 0xea, 0x21, 0x1f, 0xbd,
-0x60, 0xd6, 0x4c, 0x99, 0x71, 0xa3, 0x60, 0xd4,
-0x5d, 0xdb, 0xce, 0x56, 0x77, 0x4d, 0x4b, 0xeb,
-0x4f, 0x86, 0x15, 0xb4, 0x87, 0x76, 0x42, 0xa7,
-0x32, 0x57, 0x2a, 0x68, 0x23, 0x5a, 0xa1, 0xb4,
-0xd7, 0x6c, 0xa7, 0xf5, 0x73, 0x12, 0x99, 0xac,
-0x7b, 0x5e, 0xfb, 0x7e, 0x66, 0x9d, 0xc4, 0xfe,
-0x3e, 0xda, 0x40, 0xee, 0xfd, 0x06, 0xe0, 0x7b,
-0x50, 0xda, 0x6b, 0x5a, 0x8c, 0xfe, 0x27, 0x34,
-0x14, 0x52, 0xaa, 0x1a, 0x05, 0xc9, 0xea, 0x0b,
-0x11, 0x58, 0x0c, 0x96, 0x7d, 0x6f, 0x6d, 0x14,
-0xec, 0x93, 0xab, 0x3d, 0x06, 0x72, 0xcf, 0xb3,
-0xff, 0xd1, 0x33, 0x89, 0xf2, 0x41, 0x18, 0xc8,
-0xfd, 0x4b, 0x2f, 0x18, 0xbe, 0xf6, 0xbf, 0x76,
-0xd5, 0xd5, 0x5d, 0xfb, 0x33, 0xb7, 0xfb, 0xdf,
-0x6c, 0xf6, 0x1f, 0xb8, 0xea, 0x27, 0x26, 0x26,
-0xd4, 0x49, 0x85, 0xff, 0x37, 0xeb, 0x72, 0x36,
-0x2f, 0x91, 0xff, 0xf3, 0x36, 0xff, 0x49, 0xed,
-0xa6, 0xda, 0xae, 0x35, 0xb7, 0xff, 0x97, 0x6c,
-0xde, 0x6e, 0xd7, 0xd6, 0x26, 0xfc, 0xbf, 0x6c,
-0xf3, 0x80, 0xa6, 0xae, 0xbd, 0xdf, 0x54, 0x9b,
-0xff, 0x17, 0xdb, 0xc1, 0x27, 0xbc, 0x9f, 0xed,
-0xfa, 0x17, 0xde, 0x1c, 0x98, 0xcd, 0xc3, 0x35,
-0xd7, 0xa7, 0x36, 0xff, 0x1f, 0xa8, 0xfb, 0x97,
-0x2f, 0xf6, 0xb7, 0x1c, 0x89, 0xf6, 0xff, 0x45,
-0xbf, 0xfd, 0xf7, 0xb6, 0xf9, 0xf4, 0xfa, 0xf4,
-0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4,
-0xfa, 0xff, 0xe5, 0xd2, 0xf6, 0x49, 0xa2, 0xed,
-0x93, 0xea, 0x7f, 0x76, 0x5f, 0x3e, 0xbd, 0x3e,
-0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e,
-0xbd, 0xfe, 0x33, 0xae, 0x20, 0xfb, 0x73, 0x09,
-0x50, 0xf9, 0x6b, 0xe3, 0xef, 0xff, 0xf3, 0x41,
-0x50, 0xa6, 0xfd, 0xeb, 0xbf, 0xaf, 0xfd, 0x9e,
-0x23, 0x08, 0x69, 0xce, 0x6a, 0xbf, 0x3b, 0x35,
-0xb5, 0xaf, 0xff, 0x13, 0x87, 0x7b, 0xf6, 0xdd,
-0xd4, 0x60, 0x00, 0x00,
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
deleted file mode 100644
index 566f6f7..0000000
--- a/board/esd/pci405/pci405.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <malloc.h>
-#include <pci.h>
-#include <asm/4xx_pci.h>
-#include <asm/io.h>
-
-#include "pci405.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Prototypes */
-unsigned long fpga_done_state(void);
-unsigned long fpga_init_state(void);
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* predefine these here */
-#define FPGA_DONE_STATE (fpga_done_state())
-#define FPGA_INIT_STATE (fpga_init_state())
-
-/* fpga configuration data - generated by bin2cc */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
-#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
-
-#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
-#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
-
-
-int board_revision(void)
-{
- unsigned long CPC0_CR0Reg;
- unsigned long value;
-
- /*
- * Get version of PCI405 board from GPIO's
- */
-
- /*
- * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
- out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
-
- /*
- * Restore GPIO settings
- */
- mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
- switch (value) {
- case 0x00100200:
- /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
- return 1;
- case 0x00000200:
- /* CS2==0 && IRQ5==1 -> version 1.2 */
- return 2;
- case 0x00000000:
- /* CS2==0 && IRQ5==0 -> version 1.3 */
- return 3;
-#if 0 /* not yet manufactured ! */
- case 0x00100000:
- /* CS2==1 && IRQ5==0 -> version 1.4 */
- return 4;
-#endif
- default:
- /* should not be reached! */
- return 0;
- }
-}
-
-
-unsigned long fpga_done_state(void)
-{
- if (gd->board_type < 2) {
- return FPGA_DONE_STATE_V11;
- } else {
- return FPGA_DONE_STATE_V12;
- }
-}
-
-
-unsigned long fpga_init_state(void)
-{
- if (gd->board_type < 2) {
- return FPGA_INIT_STATE_V11;
- } else {
- return FPGA_INIT_STATE_V12;
- }
-}
-
-
-int board_early_init_f (void)
-{
- unsigned long CPC0_CR0Reg;
-
- /*
- * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
- */
- out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
- out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
- out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
- out_be32((void*)GPIO0_OR, 0); /* pull prg low */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
-
- /*
- * Setup GPIO pins (CS6+CS7 as GPIO)
- */
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
- unsigned int *ptr;
- unsigned int *magic;
-
- /*
- * On PCI-405 the environment is saved in eeprom!
- * FPGA can be gzip compressed (malloc) and booted this late.
- */
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-
- /*
- * Check if magic for pci reconfig is written
- */
- magic = (unsigned int *)0x00000004;
- if (*magic == PCI_RECONFIG_MAGIC) {
- /*
- * Rewrite pci config regs (only after soft-reset with magic set)
- */
- ptr = (unsigned int *)PCI_REGS_ADDR;
- if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
- puts("Restoring PCI Configurations Regs!\n");
- ptr = (unsigned int *)PCI_REGS_ADDR + 1;
- for (i=0; i<0x40; i+=4) {
- pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
- }
- }
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- *magic = 0; /* clear pci reconfig magic again */
- }
-
- /*
- * Decrease PLB latency timeout and reduce priority of the PCI bridge master
- */
-#define PCI0_BRDGOPT1 0x4a
- pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
-
- /*
- * Enable fairness and high bus utilization
- */
- mtdcr(PLB0_ACR, 0x98000000);
-
- free(dst);
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming PCI405");
- } else {
- puts (str);
- }
-
- gd->board_type = board_revision();
- printf(" (Rev 1.%ld", gd->board_type);
-
- if (gd->board_type >= 2) {
- unsigned long CPC0_CR0Reg;
- unsigned long value;
-
- /*
- * Setup GPIO pins (Trace/GPIO1 to GPIO)
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
- out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
- if (value) {
- puts(", 33 MHz PCI");
- } else {
- puts(", 66 MHz PCI");
- }
- }
-
- puts(")\n");
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-#define UART1_MCR 0xef600404
-int wpeeprom(int wp)
-{
- int wp_state = wp;
-
- if (wp == 1) {
- out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
- } else if (wp == 0) {
- out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
- } else {
- if (in_8((void *)UART1_MCR) & 0x02) {
- wp_state = 0;
- } else {
- wp_state = 1;
- }
- }
- return wp_state;
-}
-
-int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int wp = -1;
- if (argc >= 2) {
- if (argv[1][0] == '1') {
- wp = 1;
- } else if (argv[1][0] == '0') {
- wp = 0;
- }
- }
-
- wp = wpeeprom(wp);
- printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
- return 0;
-}
-
-U_BOOT_CMD(
- wpeeprom, 2, 1, do_wpeeprom,
- "Check/Enable/Disable I2C EEPROM write protection",
- "wpeeprom\n"
- " - check I2C EEPROM write protection state\n"
- "wpeeprom 1\n"
- " - enable I2C EEPROM write protection\n"
- "wpeeprom 0\n"
- " - disable I2C EEPROM write protection"
-);
diff --git a/board/esd/pci405/pci405.h b/board/esd/pci405/pci405.h
deleted file mode 100644
index a62c9c2..0000000
--- a/board/esd/pci405/pci405.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PCI405_H_
-#define _PCI405_H_
-
-#define PCI_REGS_LEN 0x100
-#define PCI_REGS_ADDR ((unsigned long)0x01000000 - PCI_REGS_LEN)
-
-#define PCI_RECONFIG_MAGIC 0x07081967
-
-#endif /* _PCI405_H_ */
diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S
deleted file mode 100644
index 03eaf97..0000000
--- a/board/esd/pci405/writeibm.S
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*----------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* Bank 0 - Flash and SRAM */
-/* Bank 1 - NVRAM/RTC */
-/* Bank 2 - Keyboard/Mouse controller */
-/* Bank 3 - IR controller */
-/* Bank 4 - not used */
-/* Bank 5 - not used */
-/* Bank 6 - not used */
-/* Bank 7 - FPGA registers */
-/*----------------------------------------------------------------------------- */
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl write_without_sync
-write_without_sync:
- /*
- * Write one values to host via pci busmastering
- * ptr = 0xc0000000 -> 0x01000000 (PCI)
- * *ptr = 0x01234567;
- */
- addi r31,0,0
- lis r31,0xc000
-
-start1:
- lis r0,0x0123
- ori r0,r0,0x4567
- stw r0,0(r31)
-
- /*
- * Read one value back
- * ptr = (volatile unsigned long *)addr;
- * val = *ptr;
- */
-
- lwz r0,0(r31)
-
- /*
- * One pci config write
- * ibmPciConfigWrite(0x2e, 2, 0x1234);
- */
- /* subsystem id */
-
- li r4,0x002C
- oris r4,r4,0x8000
- lis r3,0xEEC0
- stwbrx r4,0,r3
-
- li r5,0x1234
- ori r3,r3,0x4
- stwbrx r5,0,r3
-
- b start1
-
- blr /* never reached !!!! */
-
- .globl write_with_sync
-write_with_sync:
- /*
- * Write one values to host via pci busmastering
- * ptr = 0xc0000000 -> 0x01000000 (PCI)
- * *ptr = 0x01234567;
- */
- addi r31,0,0
- lis r31,0xc000
-
-start2:
- lis r0,0x0123
- ori r0,r0,0x4567
- stw r0,0(r31)
-
- /*
- * Read one value back
- * ptr = (volatile unsigned long *)addr;
- * val = *ptr;
- */
-
- lwz r0,0(r31)
-
- /*
- * One pci config write
- * ibmPciConfigWrite(0x2e, 2, 0x1234);
- */
- /* subsystem id */
-
- li r4,0x002C
- oris r4,r4,0x8000
- lis r3,0xEEC0
- stwbrx r4,0,r3
- sync
-
- li r5,0x1234
- ori r3,r3,0x4
- stwbrx r5,0,r3
- sync
-
- b start2
-
- blr /* never reached !!!! */
-
- .globl write_with_less_sync
-write_with_less_sync:
- /*
- * Write one values to host via pci busmastering
- * ptr = 0xc0000000 -> 0x01000000 (PCI)
- * *ptr = 0x01234567;
- */
- addi r31,0,0
- lis r31,0xc000
-
-start2b:
- lis r0,0x0123
- ori r0,r0,0x4567
- stw r0,0(r31)
-
- /*
- * Read one value back
- * ptr = (volatile unsigned long *)addr;
- * val = *ptr;
- */
-
- lwz r0,0(r31)
-
- /*
- * One pci config write
- * ibmPciConfigWrite(0x2e, 2, 0x1234);
- */
- /* subsystem id */
-
- li r4,0x002C
- oris r4,r4,0x8000
- lis r3,0xEEC0
- stwbrx r4,0,r3
- sync
-
- li r5,0x1234
- ori r3,r3,0x4
- stwbrx r5,0,r3
-/* sync */
-
- b start2b
-
- blr /* never reached !!!! */
-
- .globl write_with_more_sync
-write_with_more_sync:
- /*
- * Write one values to host via pci busmastering
- * ptr = 0xc0000000 -> 0x01000000 (PCI)
- * *ptr = 0x01234567;
- */
- addi r31,0,0
- lis r31,0xc000
-
-start3:
- lis r0,0x0123
- ori r0,r0,0x4567
- stw r0,0(r31)
- sync
-
- /*
- * Read one value back
- * ptr = (volatile unsigned long *)addr;
- * val = *ptr;
- */
-
- lwz r0,0(r31)
- sync
-
- /*
- * One pci config write
- * ibmPciConfigWrite(0x2e, 2, 0x1234);
- */
- /* subsystem id (PCIC0_SBSYSVID)*/
-
- li r4,0x002C
- oris r4,r4,0x8000
- lis r3,0xEEC0
- stwbrx r4,0,r3
- sync
-
- li r5,0x1234
- ori r3,r3,0x4
- stwbrx r5,0,r3
- sync
-
- b start3
-
- blr /* never reached !!!! */
diff --git a/board/esd/pf5200/Kconfig b/board/esd/pf5200/Kconfig
deleted file mode 100644
index c596e7a..0000000
--- a/board/esd/pf5200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PF5200
-
-config SYS_BOARD
- default "pf5200"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "pf5200"
-
-endif
diff --git a/board/esd/pf5200/MAINTAINERS b/board/esd/pf5200/MAINTAINERS
deleted file mode 100644
index b6e624e..0000000
--- a/board/esd/pf5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PF5200 BOARD
-M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S: Maintained
-F: board/esd/pf5200/
-F: include/configs/pf5200.h
-F: configs/pf5200_defconfig
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
deleted file mode 100644
index a54289c..0000000
--- a/board/esd/pf5200/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-# CPLD = ../common/xilinx_jtag/lenval.o \
-# ../common/xilinx_jtag/micro.o \
-# ../common/xilinx_jtag/ports.o
-
-# obj-y = pf5200.o flash.o $(CPLD)
-obj-y = pf5200.o flash.o
diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c
deleted file mode 100644
index e1b13bf..0000000
--- a/board/esd/pf5200/flash.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-
-#define FLASH_ID_MASK 0x00FF
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1 0x0555
-#define FLASH_CYCLE2 0x0aaa
-#define FLASH_ID1 0x00
-#define FLASH_ID2 0x01
-#define FLASH_ID3 0x0E
-#define FLASH_ID4 0x0F
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV * addr, flash_info_t * info);
-static void flash_reset(flash_info_t * info);
-static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init(void)
-{
- unsigned long size = 0;
- int i = 0;
- extern void flash_preinit(void);
- extern void flash_afterinit(uint, ulong, ulong);
-
- ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
- flash_preinit();
-
- /* There is only ONE FLASH device */
- memset(&flash_info[i], 0, sizeof(flash_info_t));
- flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
- size += flash_info[i].size;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
- flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
- return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t * info) {
- FPWV *base = (FPWV *) (info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- *base = (FPW) 0x00FF00FF; /* Intel Read Mode */
- } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
- *base = (FPW) 0x00F000F0; /* AMD Read Mode */
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base) {
- int i;
- flash_info_t *info;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- info = &flash_info[i];
- if ((info->size) && (info->start[0] <= base)
- && (base <= info->start[0] + info->size - 1)) {
- break;
- }
- }
- return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info(flash_info_t * info) {
- int i;
- char *fmt;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMLV256U:
- fmt = "29LV256M (256 Mbit)\n";
- break;
- default:
- fmt = "Unknown Chip Type\n";
- break;
- }
-
- printf(fmt);
- printf(" Size: %ld MB in %d Sectors\n", info->size >> 20,
- info->sector_count);
- printf(" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; ++i) {
- ulong size;
- int erased;
- ulong *flash = (unsigned long *)info->start[i];
-
- if ((i % 5) == 0) {
- printf("\n ");
- }
-
- /*
- * Check if whole sector is erased
- */
- size =
- (i !=
- (info->sector_count - 1)) ? (info->start[i + 1] -
- info->start[i]) >> 2 : (info->
- start
- [0] +
- info->
- size -
- info->
- start
- [i])
- >> 2;
-
- for (flash = (unsigned long *)info->start[i], erased = 1;
- (flash != (unsigned long *)info->start[i] + size)
- && erased; flash++) {
- erased = *flash == ~0x0UL;
- }
- printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
- info->protect[i] ? "(RO)" : " ");
- }
-
- printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size(FPWV * addr, flash_info_t * info) {
- int i;
-
- /* Write auto select command: read Manufacturer ID */
- /* Write auto select command sequence and test FLASH answer */
- addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte. */
- /* This works for any bus width and any FLASH device width. */
- udelay(100);
- switch (addr[FLASH_ID1] & 0x00ff) {
- case (uchar) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- default:
- printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) {
- switch ((FPW) addr[FLASH_ID2]) {
- case (FPW) AMD_ID_MIRROR:
- /* MIRROR BIT FLASH, read more ID bytes */
- if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
- && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
- /* attention: only the first 16 MB will be used in u-boot */
- info->flash_id += FLASH_AMLV256U;
- info->sector_count = 512;
- info->size = 0x02000000;
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] =
- (ulong) addr + 0x10000 * i;
- }
- break;
- }
- /* fall thru to here ! */
- default:
- printf("unknown AMD device=%x %x %x",
- (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
- (FPW) addr[FLASH_ID4]);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0x800000;
- break;
- }
-
- /* Put FLASH back in read mode */
- flash_reset(info);
- }
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last) {
- FPWV *addr;
- int flag, prot, sect;
- int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMLV256U:
- break;
- case FLASH_UNKNOWN:
- default:
- printf("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- last = get_timer(0);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
- if (info->protect[sect] != 0) { /* protected, skip it */
- continue;
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr = (FPWV *) (info->start[sect]);
- if (intel) {
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
- } else {
- /* must be AMD style if not Intel */
- FPWV *base; /* first address in bank */
-
- base = (FPWV *) (info->start[0]);
- base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
- *addr = (FPW) 0x00300030; /* erase sector */
- }
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
- start = get_timer(0);
-
- /* wait at least 50us for AMD, 80us for Intel. */
- /* Let's wait 1 ms. */
- udelay(1000);
-
- while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- if (intel) {
- /* suspend erase */
- *addr = (FPW) 0x00B000B0;
- }
- flash_reset(info); /* reset to read mode */
- rcode = 1; /* failed */
- break;
- }
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) {
- /* every second */
- putc('.');
- last = get_timer(0);
- }
- }
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) {
- /* every second */
- putc('.');
- last = get_timer(0);
- }
- flash_reset(info); /* reset to read mode */
- }
- printf(" done\n");
- return (rcode);
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
- int bytes; /* number of bytes to program in current word */
- int left; /* number of bytes left to program */
- int i, res;
-
- for (left = cnt, res = 0;
- left > 0 && res == 0;
- addr += sizeof(data), left -= sizeof(data) - bytes) {
-
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
-
- /* combine source and destination data so can program
- * an entire word of 16 or 32 bits
- */
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left)
- data += *((uchar *) addr + i);
- else
- data += *src++;
- }
-
- /* write one word to the flash */
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- res = write_word_amd(info, (FPWV *) addr, data);
- break;
- default:
- /* unknown flash type, error! */
- printf("missing or unknown FLASH type\n");
- res = 1; /* not really a timeout, but gives error */
- break;
- }
- }
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
- base = (FPWV *) (info->start[0]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag) {
- enable_interrupts();
- }
- start = get_timer(0);
-
- /* data polling for D7 */
- while (res == 0
- && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW) 0x00F000F0; /* reset bank */
- res = 1;
- }
- }
- return (res);
-}
diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h
deleted file mode 100644
index 63a4032..0000000
--- a/board/esd/pf5200/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x705f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
deleted file mode 100644
index 7a9ed22..0000000
--- a/board/esd/pf5200/pf5200.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * pf5200.c - main board support/init for the esd pf5200.
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <command.h>
-#include <netdev.h>
-
-#include "mt46v16m16-75.h"
-
-void init_power_switch(void);
-
-static void sdram_start(int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register: extended mode */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *) MPC5XXX_SDRAM_CTRL =
- SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
- ulong dramsize = 0;
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
- /* set tap delay */
- *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
-
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
- } else {
-#if 0
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
-#else
- *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
- 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
-#endif
- }
-
-#if 0
- /* find RAM size using SDRAM CS1 only */
- sdram_start(0);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(1);
- get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- sdram_start(0);
-#endif
- /* set SDRAM CS1 size according to the amount of RAM found */
-
- *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
- init_power_switch();
- return (dramsize);
-}
-
-int checkboard(void)
-{
- puts("Board: esd ParaFinder (pf5200)\n");
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
- if (size == 0x02000000) {
- /* adjust mapping */
- *(vu_long *) MPC5XXX_BOOTCS_START =
- *(vu_long *) MPC5XXX_CS0_START =
- START_REG(CONFIG_SYS_BOOTCS_START | size);
- *(vu_long *) MPC5XXX_BOOTCS_STOP =
- *(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
- }
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void) {
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset(void)
-{
- debug("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-}
-
-void ide_set_reset(int idereset)
-{
- debug("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
- }
-}
-#endif
-
-#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
-#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
-#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
-
-#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
-#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
-#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
-#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
-
-#define GPIO_WU6 0x40000000UL
-#define GPIO_USB0 0x00010000UL
-#define GPIO_USB9 0x08000000UL
-#define GPIO_USB9S 0x00080000UL
-
-void init_power_switch(void)
-{
- debug("init_power_switch\n");
-
- /* Configure GPIO_WU6 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
- __asm__ volatile ("sync");
-
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
- __asm__ volatile ("sync");
-
- if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
- __asm__ volatile ("sync");
- }
- *(vu_char *) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */
- __asm__ volatile ("sync");
-
- *(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
- __asm__ volatile ("sync");
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
-void power_set_reset(int power)
-{
- debug("ide_set_reset(%d)\n", power);
-
- if (power) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
- *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
- if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
- 0) {
- *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
- GPIO_USB0;
- }
-
- }
-}
-
-int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- power_set_reset(1);
- return (0);
-}
-
-U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", "");
-
-int phypower(int flag)
-{
- u32 addr;
- vu_long *reg;
- int status;
- pci_dev_t dev;
-
- dev = PCI_BDF(0, 0x18, 0);
- status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
- if (status == 0) {
- reg = (vu_long *) (addr + 0x00000040);
- *reg |= 0x40000000;
- __asm__ volatile ("sync");
-
- reg = (vu_long *) (addr + 0x001000c);
- *reg |= 0x20000000;
- __asm__ volatile ("sync");
-
- reg = (vu_long *) (addr + 0x0010004);
- if (flag != 0) {
- *reg &= ~0x20000000;
- } else {
- *reg |= 0x20000000;
- }
- __asm__ volatile ("sync");
- }
- return (status);
-}
-
-int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- if (argv[1][0] == '0')
- (void)phypower(0);
- else
- (void)phypower(1);
-
- return (0);
-}
-
-U_BOOT_CMD(phypower, 2, 2, do_phypower,
- "Switch power of ethernet phy", "");
-
-int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int addr;
- unsigned int size;
- int i;
- volatile unsigned long *ptr;
-
- addr = simple_strtol(argv[1], NULL, 16);
- size = simple_strtol(argv[2], NULL, 16);
-
- printf("\nWriting at addr %08x, size %08x.\n", addr, size);
-
- while (1) {
- ptr = (volatile unsigned long *)addr;
- for (i = 0; i < (size >> 2); i++) {
- *ptr++ = i;
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
- putc('.');
- }
- return 0;
-}
-
-U_BOOT_CMD(writepci, 3, 1, do_writepci,
- "Write some data to pcibus",
- "<addr> <size>\n"
- ""
-);
diff --git a/board/esd/pmc405/Kconfig b/board/esd/pmc405/Kconfig
deleted file mode 100644
index 3738c68..0000000
--- a/board/esd/pmc405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PMC405
-
-config SYS_BOARD
- default "pmc405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "PMC405"
-
-endif
diff --git a/board/esd/pmc405/MAINTAINERS b/board/esd/pmc405/MAINTAINERS
deleted file mode 100644
index 148a596..0000000
--- a/board/esd/pmc405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PMC405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/pmc405/
-F: include/configs/PMC405.h
-F: configs/PMC405_defconfig
diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile
deleted file mode 100644
index ad98207..0000000
--- a/board/esd/pmc405/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-CPLD = ../common/xilinx_jtag/lenval.o \
- ../common/xilinx_jtag/micro.o \
- ../common/xilinx_jtag/ports.o
-
-obj-y = pmc405.o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
deleted file mode 100644
index e67ff30..0000000
--- a/board/esd/pmc405/pmc405.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2005-2009
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register:
- * set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000);
-
- /*
- * Setup GPIO pins
- */
- mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
- CONFIG_SYS_FPGA_DONE |
- CONFIG_SYS_XEREADY |
- CONFIG_SYS_NONMONARCH |
- CONFIG_SYS_REV1_2) << 5));
-
- if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
- /* rev 1.2 boards */
- mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
- CONFIG_SYS_SELF_RST) << 5));
- }
-
- out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
- /* setup for output */
- out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
- CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
-
- /*
- * - check if rev1_2 is low, then:
- * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
- * in TCR to assert INTA# or SELFRST#
- */
- return 0;
-}
-
-int misc_init_r (void)
-{
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /* deassert EREADY# */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
- return (0);
-}
-
-ushort pmc405_pci_subsys_deviceid(void)
-{
- ulong val;
-
- val = in_be32((void *)GPIO0_IR);
- if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
- /* check monarch# signal */
- if (val & CONFIG_SYS_NONMONARCH)
- return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
- return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
- }
- return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard (void)
-{
- ulong val;
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1)
- puts ("### No HW ID - assuming PMC405");
- else
- puts(str);
-
- val = in_be32((void *)GPIO0_IR);
- if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
- puts(" rev1.2 (");
- if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
- puts("non-");
- puts("monarch)");
- } else
- puts(" <=rev1.1");
-
- putc ('\n');
-
- return 0;
-}
-
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
diff --git a/board/esd/tasreg/Kconfig b/board/esd/tasreg/Kconfig
deleted file mode 100644
index 85417d4..0000000
--- a/board/esd/tasreg/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_TASREG
-
-config SYS_CPU
- default "mcf52x2"
-
-config SYS_BOARD
- default "tasreg"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "TASREG"
-
-endif
diff --git a/board/esd/tasreg/MAINTAINERS b/board/esd/tasreg/MAINTAINERS
deleted file mode 100644
index 10bc7a4..0000000
--- a/board/esd/tasreg/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TASREG BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/tasreg/
-F: include/configs/TASREG.h
-F: configs/TASREG_defconfig
diff --git a/board/esd/tasreg/Makefile b/board/esd/tasreg/Makefile
deleted file mode 100644
index 46f2550..0000000
--- a/board/esd/tasreg/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = tasreg.o flash.o
diff --git a/board/esd/tasreg/config.mk b/board/esd/tasreg/config.mk
deleted file mode 100644
index 40f7570..0000000
--- a/board/esd/tasreg/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0xffc00000
diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c
deleted file mode 100644
index 7138881..0000000
--- a/board/esd/tasreg/flash.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-/*#include <asm/ppc4xx.h>*/
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* test-only: todo: Re-do sizing to get full correct info */
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-1,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/tasreg/fpgadata.c b/board/esd/tasreg/fpgadata.c
deleted file mode 100644
index 427b1d0..0000000
--- a/board/esd/tasreg/fpgadata.c
+++ /dev/null
@@ -1,10661 +0,0 @@
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-0x9a, 0xdf, 0xdc, 0x58, 0x42, 0x9c, 0x7d, 0xb9,
-0x51, 0x5e, 0xd2, 0x5b, 0x1a, 0x9a, 0x3f, 0x59,
-0x58, 0x85, 0x1b, 0x59, 0xcb, 0x7c, 0x2f, 0xdb,
-0xa4, 0x4a, 0x43, 0xb9, 0x60, 0x10, 0x34, 0x9c,
-0x16, 0xb8, 0x21, 0x25, 0x39, 0x66, 0xb2, 0x96,
-0x49, 0x6c, 0xd7, 0x9b, 0xe4, 0xda, 0xbf, 0x0c,
-0x4e, 0xc0, 0x44, 0xb4, 0xd6, 0x6c, 0xe0, 0xdc,
-0x00, 0x3e, 0x8b, 0xac, 0xbb, 0x3d, 0x14, 0x14,
-0xba, 0xb3, 0x06, 0xf3, 0x16, 0x70, 0x2a, 0x9c,
-0xdf, 0x25, 0x44, 0x9b, 0x96, 0x14, 0x96, 0xca,
-0xf3, 0x85, 0xf5, 0xdc, 0x97, 0x60, 0x78, 0x39,
-0x56, 0x58, 0xfa, 0x00, 0x62, 0x61, 0x0e, 0x9c,
-0x05, 0x68, 0x69, 0x28, 0x64, 0x78, 0x79, 0xad,
-0x1c, 0xd3, 0xf0, 0xdc, 0x95, 0xe3, 0x65, 0xb9,
-0xa1, 0xcc, 0xf6, 0xc3, 0x61, 0xff, 0x6a, 0x6a,
-0xd6, 0x4a, 0xe4, 0x5b, 0x73, 0x60, 0xdb, 0x6a,
-0x2e, 0x2c, 0x91, 0x73, 0x84, 0x42, 0xc3, 0x40,
-0xe3, 0x56, 0x30, 0x78, 0x97, 0xf0, 0x12, 0xb4,
-0x08, 0x25, 0x39, 0x39, 0x85, 0xd8, 0xa5, 0xe1,
-0x18, 0x81, 0xb5, 0xc8, 0x82, 0xa0, 0x19, 0xf6,
-0xf3, 0xa5, 0xc0, 0x0a, 0x94, 0xc4, 0x73, 0xc8,
-0x03, 0xf0, 0x40, 0x13, 0xed, 0x41, 0x3c, 0x2c,
-0x0a, 0x35, 0x60, 0x8b, 0xde, 0x4a, 0x62, 0x77,
-0xf0, 0xa7, 0x3f, 0x1a, 0x6b, 0x60, 0xa2, 0x39,
-0xec, 0x11, 0x2f, 0x11, 0x73, 0x74, 0x21, 0xca,
-0x5e, 0x0c, 0x38, 0xc6, 0xfa, 0x08, 0x80, 0x7c,
-0x3b, 0x48, 0x12, 0x89, 0x26, 0xcb, 0x6c, 0x2c,
-0x5c, 0x26, 0xb6, 0x62, 0x0b, 0x82, 0xe2, 0x56,
-0x6c, 0x21, 0x1e, 0x22, 0x52, 0x92, 0x6c, 0x06,
-0xa3, 0xd0, 0x1e, 0x93, 0x83, 0x06, 0x09, 0x64,
-0xf6, 0xaf, 0xcf, 0x03, 0xf2, 0x6d, 0x1f, 0x28,
-0x9b, 0xb9, 0x16, 0x8c, 0x28, 0x40, 0xe0, 0x99,
-0x0f, 0x7c, 0x5e, 0xf8, 0x92, 0xd2, 0x6e, 0x96,
-0xcd, 0xcc, 0xff, 0xbc, 0x28, 0x18, 0xe6, 0xc0,
-0x55, 0x21, 0xe5, 0xf3, 0x52, 0xb1, 0xd1, 0x07,
-0x5d, 0xde, 0xcf, 0x4b, 0x5f, 0x6c, 0x6a, 0x7f,
-0x69, 0xea, 0x4c, 0x25, 0xbf, 0xf8, 0x4b, 0xc6,
-0x09, 0xf8, 0x2b, 0x7b, 0xff, 0x82, 0x79, 0x06,
-0x0f, 0x7f, 0x33, 0x3a, 0xff, 0xfd, 0xb9, 0xe8,
-0xf3, 0xff, 0xad, 0x0b, 0x17, 0xf4, 0x4f, 0x6a,
-0x01, 0x50, 0xfc, 0x39, 0x5d, 0xe8, 0x9f, 0x74,
-0x0f, 0xb9, 0x2b, 0xfe, 0x39, 0x80, 0xc9, 0x62,
-0x8b, 0xb0, 0x89, 0xfe, 0xb3, 0x6b, 0x8c, 0x69,
-0xff, 0xb0, 0x72, 0xc5, 0x30, 0xb5, 0x50, 0x3b,
-0x7a, 0x59, 0x60, 0xcc, 0x90, 0xd7, 0x0a, 0x88,
-0x97, 0x11, 0x0b, 0x2f, 0x01, 0x50, 0x6c, 0x02,
-0x82, 0xf6, 0x2e, 0x29, 0xd7, 0xa2, 0x07, 0x39,
-0x5e, 0xd6, 0x0c, 0x40, 0xd0, 0x2e, 0xbc, 0x3c,
-0xcf, 0xbe, 0x0c, 0xe0, 0xe5, 0xcf, 0x5d, 0x02,
-0xe4, 0xfb, 0x9d, 0x1f, 0xd6, 0xff, 0x61, 0xd1,
-0x85, 0x7f, 0xbb, 0x72, 0xef, 0x95, 0x67, 0xb9,
-0x01, 0xe0, 0xf1, 0xfa, 0x3f, 0x30, 0x50, 0xfc,
-0x9d, 0x4b, 0xf5, 0x68, 0x5c, 0xfe, 0x7f, 0x0b,
-0x2f, 0x4f, 0x7a, 0xfa, 0xe5, 0x17, 0x53, 0xd6,
-0xf7, 0x79, 0xf7, 0xde, 0x5d, 0xcf, 0x06, 0x7f,
-0xb5, 0xe0, 0x3e, 0x06, 0x9c, 0xa7, 0xfc, 0x6a,
-0x01, 0x22, 0xe8, 0x6f, 0xad, 0x80, 0x96, 0xfb,
-0x0f, 0xbe, 0x9a, 0xba, 0xb0, 0x22, 0x62, 0x61,
-0xea, 0xff, 0x1b, 0x8c, 0xfb, 0xd9, 0x18, 0xe7,
-0x3a, 0x35, 0x75, 0x9f, 0x7b, 0xf1, 0xdf, 0x6a,
-0xfa, 0xac, 0xeb, 0x7c, 0x78, 0xef, 0xf1, 0x67,
-0x6b, 0x6e, 0x5e, 0x78, 0x81, 0x01, 0xe7, 0xeb,
-0x6f, 0x66, 0x08, 0xfa, 0xdb, 0x67, 0xa1, 0xe5,
-0x4a, 0x71, 0xa4, 0xef, 0xe2, 0xd9, 0x7a, 0x0b,
-0x53, 0x5f, 0x02, 0xe3, 0x0a, 0x1b, 0xe3, 0x5c,
-0x67, 0xce, 0x14, 0xa3, 0xaf, 0x68, 0xc6, 0xa0,
-0x57, 0x98, 0xd3, 0xf2, 0x85, 0xe7, 0x1e, 0xd9,
-0x25, 0x9f, 0xb9, 0x65, 0x8e, 0x16, 0x7d, 0x6e,
-0xc3, 0x8c, 0xf6, 0x77, 0x47, 0x25, 0xed, 0x0b,
-0x2f, 0x14, 0xef, 0x1a, 0xcc, 0x1f, 0x85, 0xae,
-0xd7, 0x1e, 0x49, 0xb5, 0x9f, 0xf9, 0xe6, 0x9c,
-0x95, 0xd1, 0x57, 0x8b, 0x6e, 0x6e, 0x5f, 0xfb,
-0xcd, 0x39, 0xa5, 0x5f, 0x78, 0x0d, 0xc7, 0x9c,
-0x76, 0xae, 0x23, 0xb6, 0x93, 0x2d, 0x24, 0xf0,
-0x8f, 0x1e, 0x8d, 0x1b, 0x86, 0xdb, 0x58, 0x15,
-0xca, 0xb4, 0x1c, 0x75, 0x77, 0x79, 0x0f, 0xda,
-0x63, 0x9c, 0xcb, 0xb8, 0x42, 0x83, 0xcc, 0x11,
-0x23, 0xee, 0x50, 0x86, 0x65, 0x64, 0x87, 0x0f,
-0x49, 0x56, 0x97, 0x73, 0x42, 0xd6, 0x8e, 0xcc,
-0x5b, 0x06, 0x7b, 0x29, 0x4c, 0x64, 0x74, 0xb0,
-0x54, 0x2b, 0x71, 0x8c, 0xe1, 0x74, 0x11, 0x6b,
-0xe7, 0xb1, 0xbe, 0xc6, 0x3f, 0xea, 0x13, 0x7c,
-0x0d, 0x65, 0x52, 0x38, 0xd3, 0x72, 0xd4, 0xd5,
-0xe5, 0x0e, 0x70, 0x3a, 0xbf, 0x8b, 0x8e, 0x3b,
-0xf8, 0x03, 0xe3, 0xe8, 0xb8, 0x96, 0x8f, 0x33,
-0xf8, 0xef, 0xfa, 0x4f, 0x0f, 0xff, 0x63, 0x57,
-0x62, 0xd7, 0x61, 0x34, 0x77, 0x1d, 0xfc, 0x7d,
-0xc9, 0x0d, 0x36, 0xa2, 0x03, 0x46, 0x58, 0x2d,
-0xe2, 0x98, 0x2e, 0x85, 0x0d, 0x26, 0x56, 0x8b,
-0xfd, 0x99, 0xf8, 0x1f, 0x39, 0xfa, 0x9f, 0xfd,
-0x46, 0xf6, 0xf7, 0x91, 0x3d, 0xed, 0xe2, 0x16,
-0xb2, 0xdd, 0x98, 0xae, 0xfd, 0x69, 0x86, 0x28,
-0xd8, 0xbf, 0x6b, 0xfc, 0x32, 0xfd, 0xef, 0x18,
-0xce, 0xfc, 0x7c, 0xd2, 0xfd, 0xf3, 0x49, 0x06,
-0xb1, 0xef, 0x9f, 0x49, 0x21, 0xe1, 0x28, 0xf9,
-0x47, 0x32, 0xd9, 0xfc, 0x93, 0x8c, 0x83, 0xf2,
-0x7f, 0xe5, 0xfb, 0x4c, 0x36, 0xed, 0x16, 0x31,
-0x73, 0x23, 0xfe, 0x09, 0xb7, 0x8d, 0xe6, 0xb4,
-0x64, 0x3e, 0x7f, 0xca, 0xcd, 0xa7, 0x65, 0xdf,
-0x85, 0x38, 0x3f, 0xe6, 0x1f, 0x7b, 0x59, 0x7e,
-0xdc, 0xc7, 0x9b, 0xf9, 0x2b, 0x9e, 0x1f, 0x15,
-0xfa, 0x53, 0xae, 0x92, 0x75, 0x45, 0x83, 0xfd,
-0x2f, 0xa4, 0xff, 0x57, 0xaf, 0x63, 0x4d, 0xd1,
-0x24, 0xf3, 0xbf, 0x78, 0x21, 0x61, 0xf8, 0xbf,
-0x78, 0x81, 0xff, 0x43, 0x9f, 0xfa, 0x2b, 0x57,
-0xae, 0x98, 0x7f, 0xba, 0xf1, 0xe9, 0x75, 0xfe,
-0x5f, 0xbe, 0xce, 0x04, 0xdb, 0xf1, 0xff, 0x8e,
-0xe1, 0x5c, 0xe7, 0xbf, 0xf8, 0x5e, 0xcd, 0x5c,
-0x67, 0xdc, 0x9e, 0xfb, 0x31, 0x86, 0x6b, 0xa7,
-0x9e, 0xe0, 0xbd, 0x4a, 0xc8, 0x7f, 0xfe, 0x5f,
-0xb7, 0x5c, 0x08, 0x32, 0xd1, 0xbe, 0xfc, 0xdf,
-0xb2, 0x9b, 0xfe, 0xf7, 0xee, 0xcb, 0xce, 0x56,
-0x3b, 0x76, 0x83, 0xfe, 0x24, 0x23, 0xeb, 0xfb,
-0xfc, 0x89, 0x6f, 0xfa, 0xb1, 0xfb, 0x32, 0xc1,
-0x1d, 0xf6, 0xe8, 0xf6, 0x7f, 0x9c, 0x70, 0xf3,
-0x5d, 0x15, 0x86, 0x2e, 0x97, 0x31, 0xf9, 0x30,
-0xeb, 0x72, 0x0f, 0xce, 0xfc, 0xae, 0xff, 0xbe,
-0x7d, 0x59, 0xff, 0xb8, 0x5d, 0x8f, 0x4e, 0xdc,
-0x45, 0xc6, 0xdf, 0x3f, 0x0a, 0xdb, 0x97, 0xc9,
-0xb8, 0x3d, 0x97, 0xb7, 0xb0, 0x9b, 0x64, 0x7c,
-0x97, 0xc1, 0xbb, 0xfe, 0x1b, 0xf6, 0xe5, 0x8c,
-0xf1, 0x5f, 0xdb, 0x97, 0x33, 0xc6, 0x7f, 0xf3,
-0xfd, 0x4c, 0x32, 0x01, 0x91, 0x3f, 0xf1, 0xc3,
-0xf3, 0xe7, 0xff, 0xbb, 0x3e, 0x75, 0x75, 0xff,
-0xc5, 0x0b, 0xf8, 0x7c, 0xff, 0x2d, 0xdf, 0xe3,
-0xff, 0xbb, 0x9f, 0xff, 0xaf, 0xed, 0x3b, 0x9f,
-0x5e, 0xe7, 0x8f, 0x5f, 0xe7, 0xbf, 0xe7, 0x13,
-0x22, 0xba, 0x20, 0xb2, 0xff, 0x37, 0x6d, 0xf8,
-0x3f, 0x70, 0xf9, 0x4f, 0x3f, 0x9f, 0x7e, 0x3e,
-0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9, 0xe7,
-0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0x9f, 0x7e,
-0x3e, 0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9,
-0xe7, 0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0xff,
-0x7f, 0xf8, 0x61, 0x67, 0x4a, 0x22, 0x3b, 0x53,
-0xa2, 0xff, 0xbf, 0xfe, 0x2e, 0x9f, 0x7e, 0x3e,
-0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9, 0xe7,
-0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0x9f, 0x7e,
-0x3e, 0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9,
-0xe7, 0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0x9f,
-0x7e, 0xfe, 0xcf, 0x7e, 0x42, 0x04, 0x53, 0x21,
-0x3d, 0x7f, 0x15, 0x22, 0x14, 0x0b, 0x2c, 0xa4,
-0x10, 0x31, 0x8a, 0xfe, 0xfb, 0xae, 0xcd, 0xae,
-0x99, 0x13, 0x22, 0x49, 0x21, 0xf3, 0x6f, 0xcd,
-0xbe, 0x3c, 0x76, 0xdc, 0xff, 0x03, 0xe6, 0xeb,
-0xaf, 0xb2, 0x8c, 0x8c, 0x02, 0x00,
diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c
deleted file mode 100644
index 09a90ed..0000000
--- a/board/esd/tasreg/tasreg.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/m5249.h>
-#include <asm/io.h>
-
-
-/* Prototypes */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
-
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* predefine these here for FPGA programming (before including fpga.c) */
-#define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data)
-#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE)
-#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT)
-#define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */
-#define out32(a,b) /* nothing to do (gpio already configured) */
-
-
-/* fpga configuration data - generated by bin2cc */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-int checkboard (void) {
- ulong val;
- uchar val8;
-
- puts ("Board: ");
- puts("esd TASREG");
- val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
- printf(" (Switch=%1X)\n", val8);
-
- /*
- * Set LED on
- */
- val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
- mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
-
- return 0;
-};
-
-
-phys_size_t initdram (int board_type) {
- unsigned long junk = 0xa5a59696;
-
- /*
- * Note:
- * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
- */
-
-#ifdef CONFIG_SYS_FAST_CLK
- /*
- * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
- * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
- */
- mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CONFIG_SYS_PLL_BYPASS
- /*
- * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
- * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
- */
- mbar_writeShort(MCFSIM_DCR, 0x8202);
-#else
- /*
- * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
- * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
- */
- mbar_writeShort(MCFSIM_DCR, 0x8222);
-#endif
-
- /*
- * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
- * PM=1 (continuous page mode)
- */
-
- /* RE=0 (keep auto-refresh disabled while setting up registers) */
- mbar_writeLong(MCFSIM_DACR0, 0x00003324);
-
- /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
- mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
-
- /** Precharge sequence **/
- mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
- out_be32((void *)0, junk); /* write to a memory location to init. precharge */
- udelay(0x10); /* Allow several Precharge cycles */
-
- /** Refresh Sequence **/
- mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
- udelay(0x7d0); /* Allow gobs of refresh cycles */
-
- /** Mode Register initialization **/
- mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
- out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-};
-
-
-int testdram (void) {
- /* TODO: XXX XXX XXX */
- printf ("DRAM test not implemented!\n");
-
- return (0);
-}
-
-
-int misc_init_r (void)
-{
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
- uchar buf[8];
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- free(dst);
-
- /*
- *
- */
- buf[0] = 0x00;
- buf[1] = 0x32;
- buf[2] = 0x3f;
- i2c_write(0x38, 0, 0, buf, 3);
-
- return (0);
-}
-
-
-#if 1 /* test-only: board specific test commands */
-int i2c_probe(uchar addr);
-
-/*
- */
-int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr;
-
- if (argc < 2) {
- puts("ERROR!\n");
- return -1;
- }
-
- addr = simple_strtol (argv[1], NULL, 16);
-
- printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
-
- for (;;) {
- i2c_probe(addr);
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- udelay(1000);
- }
-
- return 0;
-}
-U_BOOT_CMD(
- iploop, 2, 1, do_iploop,
- "i2c probe loop <addr>",
- ""
-);
-
-/*
- */
-int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uchar buf[8];
-
- out_be16((void *)0xe0000000, 0x4000);
-
- udelay(5000); /* wait for 5ms */
-
- buf[0] = 0x10;
- buf[1] = 0x07;
- buf[2] = 0x03;
- i2c_write(0x10, 0, 0, buf, 3);
-
- buf[0] = 0x10;
- buf[1] = 0x01;
- buf[2] = 0x80;
- i2c_write(0x10, 0, 0, buf, 3);
-
- buf[0] = 0x10;
- buf[1] = 0x02;
- buf[2] = 0x03;
- i2c_write(0x10, 0, 0, buf, 3);
-
- buf[0] = 0x10;
- buf[1] = 0x03;
- buf[2] = 0x29;
- i2c_write(0x10, 0, 0, buf, 3);
-
- buf[0] = 0x10;
- buf[1] = 0x04;
- buf[2] = 0x00;
- i2c_write(0x10, 0, 0, buf, 3);
-
- buf[0] = 0x10;
- buf[1] = 0x05;
- buf[2] = 0x00;
- i2c_write(0x10, 0, 0, buf, 3);
-
- buf[0] = 0x10;
- buf[1] = 0x07;
- buf[2] = 0x02;
- i2c_write(0x10, 0, 0, buf, 3);
-
- return 0;
-}
-U_BOOT_CMD(
- codec, 1, 1, do_codec,
- "Enable codec",
- ""
-);
-
-/*
- */
-int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr;
- ulong instr;
- ulong cntrl;
- ulong data;
- uchar buf[8];
-
- if (argc < 5) {
- puts("ERROR!\n");
- return -1;
- }
-
- addr = simple_strtol (argv[1], NULL, 16);
- instr = simple_strtol (argv[2], NULL, 16);
- cntrl = simple_strtol (argv[3], NULL, 16);
- data = simple_strtol (argv[4], NULL, 16);
-
- buf[0] = (uchar)instr;
- buf[1] = (uchar)cntrl;
- buf[2] = (uchar)data;
- i2c_write(addr, 0, 0, buf, 3);
-
- return 0;
-}
-U_BOOT_CMD(
- saa, 5, 1, do_saa,
- "Write to SAA1064 <addr> <instr> <cntrl> <data>",
- ""
-);
-
-/*
- */
-int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr;
- ulong data0;
- ulong data1;
- ulong data2;
- ulong data3;
- uchar buf[8];
- int cnt;
-
- if (argc < 3) {
- puts("ERROR!\n");
- return -1;
- }
-
- addr = simple_strtol (argv[1], NULL, 16);
- cnt = simple_strtol (argv[2], NULL, 16);
- data0 = simple_strtol (argv[3], NULL, 16);
- data1 = simple_strtol (argv[4], NULL, 16);
- data2 = simple_strtol (argv[5], NULL, 16);
- data3 = simple_strtol (argv[6], NULL, 16);
-
- printf("Writing %d bytes to device %lx!\n", cnt, addr);
- buf[0] = (uchar)data0;
- buf[1] = (uchar)data1;
- buf[2] = (uchar)data2;
- buf[3] = (uchar)data3;
- i2c_write(addr, 0, 0, buf, cnt);
-
- return 0;
-}
-U_BOOT_CMD(
- iwrite, 6, 1, do_iwrite,
- "Write n bytes to I2C-device",
- "addr cnt data0 ... datan"
-);
-
-/*
- */
-int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr;
- ulong cnt;
- uchar buf[32];
- int i;
-
- if (argc < 3) {
- puts("ERROR!\n");
- return -1;
- }
-
- addr = simple_strtol (argv[1], NULL, 16);
- cnt = simple_strtol (argv[2], NULL, 16);
-
- i2c_read(addr, 0, 0, buf, cnt);
- printf("I2C Data:");
- for (i=0; i<cnt; i++) {
- printf(" %02X", buf[i]);
- }
- printf("\n");
-
- return 0;
-}
-U_BOOT_CMD(
- iread, 3, 1, do_iread,
- "Read from I2C <addr> <cnt>",
- ""
-);
-
-/*
- */
-int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr;
- uchar buf[32];
- int cnt;
-
- if (argc < 2) {
- puts("ERROR!\n");
- return -1;
- }
-
- addr = simple_strtol (argv[1], NULL, 16);
- cnt = 1;
-
- printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
-
- for (;;) {
- i2c_read(addr, 0, 0, buf, cnt);
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- udelay(3000);
- }
-
- return 0;
-}
-U_BOOT_CMD(
- ireadl, 2, 1, do_ireadl,
- "Read-loop from I2C <addr>",
- ""
-);
-#endif
diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds
deleted file mode 100644
index 7f9e41c..0000000
--- a/board/esd/tasreg/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(m68k)
-
-SECTIONS
-{
- .text :
- {
- arch/m68k/cpu/mcf52x2/start.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
-
- .reloc :
- {
- __got_start = .;
- KEEP(*(.got))
- __got_end = .;
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- _sbss = .;
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = .;
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/esd/voh405/Kconfig b/board/esd/voh405/Kconfig
deleted file mode 100644
index d9fe9d2..0000000
--- a/board/esd/voh405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_VOH405
-
-config SYS_BOARD
- default "voh405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "VOH405"
-
-endif
diff --git a/board/esd/voh405/MAINTAINERS b/board/esd/voh405/MAINTAINERS
deleted file mode 100644
index 0039f5d..0000000
--- a/board/esd/voh405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VOH405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/voh405/
-F: include/configs/VOH405.h
-F: configs/VOH405_defconfig
diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile
deleted file mode 100644
index 3d82399..0000000
--- a/board/esd/voh405/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = voh405.o flash.o \
- ../common/misc.o \
- ../common/esd405ep_nand.o \
diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/voh405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/voh405/fpgadata.c b/board/esd/voh405/fpgadata.c
deleted file mode 100644
index 9ad9650..0000000
--- a/board/esd/voh405/fpgadata.c
+++ /dev/null
@@ -1,4021 +0,0 @@
-0x1f, 0x8b, 0x08, 0x08, 0x38, 0x6c, 0x35, 0x42,
-0x00, 0x03, 0x76, 0x6f, 0x68, 0x34, 0x30, 0x35,
-0x5f, 0x31, 0x5f, 0x30, 0x33, 0x2e, 0x62, 0x69,
-0x74, 0x00, 0xed, 0xfd, 0x7d, 0x7c, 0x1c, 0xd5,
-0x91, 0x2f, 0x8c, 0x57, 0x9f, 0x6e, 0xc9, 0xad,
-0xe9, 0x91, 0xa6, 0xf5, 0x62, 0x22, 0x40, 0x98,
-0xd6, 0x48, 0x98, 0x41, 0x19, 0x49, 0x63, 0xc9,
-0x18, 0x63, 0xcc, 0xa8, 0x2d, 0x09, 0x22, 0x6c,
-0x07, 0x4f, 0x80, 0xcd, 0xfa, 0x66, 0xb9, 0xd9,
-0x31, 0xf1, 0x66, 0xbd, 0xfb, 0x73, 0xb8, 0x82,
-0xe4, 0xd9, 0x75, 0x72, 0xb3, 0xe4, 0x68, 0x24,
-0xdb, 0x23, 0xcb, 0xc1, 0x83, 0x71, 0x88, 0x20,
-0xde, 0xec, 0xd8, 0x78, 0x89, 0x21, 0x4e, 0xee,
-0x58, 0x36, 0x20, 0x63, 0x16, 0x5a, 0x46, 0x80,
-0x6c, 0x8c, 0x51, 0x58, 0x27, 0xeb, 0x10, 0x42,
-0xc6, 0x44, 0x21, 0x82, 0x18, 0x22, 0x8c, 0x49,
-0xe4, 0xf7, 0xe7, 0xd4, 0xe9, 0x97, 0xe9, 0x99,
-0x91, 0xd9, 0xcd, 0xbd, 0xf7, 0x79, 0xee, 0x7e,
-0x7e, 0x8f, 0x27, 0x7f, 0xa4, 0xe8, 0x39, 0x6e,
-0xf5, 0xa9, 0x39, 0x5d, 0xf5, 0x3d, 0x55, 0xdf,
-0xaa, 0x03, 0x45, 0xbe, 0x09, 0xf3, 0x7f, 0x00,
-0xc2, 0x32, 0x50, 0xff, 0xee, 0xbf, 0xad, 0x98,
-0x1d, 0xba, 0xf6, 0x2f, 0x67, 0xfd, 0x65, 0xa8,
-0xb9, 0xe1, 0xee, 0x2f, 0x2d, 0x87, 0xbb, 0x40,
-0x69, 0xfa, 0xea, 0xb5, 0xa1, 0xbf, 0xfa, 0xda,
-0x3d, 0xb3, 0x66, 0xcf, 0x86, 0x2f, 0xb1, 0xff,
-0x0a, 0x85, 0xae, 0x6d, 0x0c, 0x35, 0x37, 0xce,
-0x9a, 0x0d, 0xcb, 0xa1, 0x68, 0xd6, 0xac, 0x79,
-0xb3, 0xaf, 0x9f, 0xd7, 0x34, 0x17, 0xfe, 0x0a,
-0x84, 0xe6, 0x6d, 0xe7, 0xd9, 0xe7, 0x89, 0x87,
-0xff, 0xec, 0xcb, 0x21, 0xa0, 0x02, 0x00, 0x4c,
-0x0b, 0x09, 0x51, 0xfc, 0x7f, 0x25, 0x24, 0x68,
-0x02, 0xd0, 0x96, 0xfa, 0x10, 0x18, 0xf8, 0xdf,
-0x60, 0x7d, 0x5f, 0x14, 0x02, 0xcd, 0xfd, 0xdf,
-0x42, 0x08, 0x74, 0x88, 0x80, 0xbe, 0x5e, 0x2d,
-0x83, 0x7f, 0xff, 0x23, 0xe8, 0x12, 0xb5, 0xe5,
-0x3f, 0x71, 0xfc, 0xf9, 0x03, 0xf4, 0x82, 0xc3,
-0x32, 0x9f, 0x96, 0xe3, 0x49, 0x4b, 0x52, 0x49,
-0xe8, 0x3f, 0x72, 0x7f, 0xb0, 0xef, 0xfa, 0xfb,
-0x37, 0xfe, 0x43, 0xf7, 0xff, 0x83, 0x7d, 0xff,
-0x3f, 0x75, 0x3c, 0xa8, 0xff, 0x81, 0xe1, 0x00,
-0x92, 0xf3, 0x3c, 0xaa, 0xa0, 0x41, 0x07, 0x14,
-0x82, 0x40, 0x21, 0x0a, 0x95, 0x17, 0x10, 0x5a,
-0x86, 0xed, 0xf1, 0x86, 0x70, 0x0e, 0xce, 0xd3,
-0x96, 0x03, 0xbe, 0x81, 0xee, 0x7b, 0xe1, 0x1c,
-0x84, 0xf5, 0xe2, 0x09, 0xf1, 0x3e, 0xf5, 0x4d,
-0xb5, 0x45, 0xf3, 0xbd, 0x24, 0x1e, 0x87, 0x33,
-0xb4, 0xb9, 0xd2, 0xbb, 0x4f, 0x0c, 0x41, 0xa7,
-0x3d, 0x3e, 0xfe, 0x63, 0xd8, 0x4b, 0x1b, 0x26,
-0x94, 0x13, 0x7d, 0x7e, 0x58, 0x67, 0x34, 0xec,
-0xf3, 0x9c, 0x28, 0xab, 0xad, 0xe8, 0x8d, 0x34,
-0x68, 0x4a, 0x8c, 0xbc, 0x03, 0x83, 0xd4, 0x2f,
-0xcb, 0xb1, 0x7d, 0xa1, 0x5a, 0x5b, 0x8b, 0x23,
-0xd2, 0x7a, 0xd8, 0x05, 0x41, 0x43, 0x69, 0x22,
-0x00, 0x03, 0x0b, 0x82, 0x23, 0x97, 0xce, 0x22,
-0x2b, 0x20, 0xa1, 0xad, 0xd4, 0x94, 0x42, 0x62,
-0xc0, 0x20, 0x68, 0x95, 0x72, 0x39, 0x69, 0x02,
-0xcd, 0xbe, 0xbf, 0xb4, 0x03, 0xf6, 0x42, 0x83,
-0xa1, 0xa4, 0x88, 0x46, 0xd7, 0x91, 0x86, 0xb4,
-0x27, 0x45, 0x02, 0x6a, 0x3c, 0x7e, 0xab, 0xae,
-0xc4, 0x49, 0x5a, 0xdf, 0x43, 0xfd, 0x9a, 0xdc,
-0x4f, 0x42, 0x92, 0xfd, 0x3c, 0x37, 0x4d, 0x3f,
-0x06, 0xa7, 0xd9, 0x78, 0x5f, 0xaa, 0xcd, 0x0f,
-0xa7, 0x92, 0xe1, 0x0f, 0x8b, 0x53, 0x0b, 0x16,
-0xc3, 0x11, 0x63, 0x86, 0xe0, 0x7b, 0x44, 0x4c,
-0xc3, 0x84, 0x36, 0xb0, 0xc2, 0xbb, 0x5e, 0x54,
-0xdb, 0xed, 0xf1, 0x49, 0xe1, 0x59, 0x78, 0x1e,
-0xae, 0x64, 0xe3, 0xd9, 0x77, 0x1f, 0x24, 0xc2,
-0x86, 0x38, 0xe1, 0x3f, 0xc1, 0xee, 0xd0, 0xa2,
-0xfa, 0xa8, 0x78, 0x02, 0x35, 0x00, 0xbe, 0x44,
-0xdb, 0x38, 0xd3, 0x94, 0xf9, 0x19, 0x55, 0x77,
-0xb0, 0x6f, 0xc3, 0x86, 0x2f, 0x24, 0x26, 0xd5,
-0x53, 0xd0, 0x34, 0x5a, 0x9c, 0x12, 0x8f, 0xc1,
-0x49, 0x68, 0xea, 0xf2, 0x25, 0x6f, 0x0f, 0x56,
-0x8f, 0xab, 0xe1, 0x98, 0x77, 0x4b, 0x77, 0x48,
-0xb2, 0x9f, 0x7f, 0xa4, 0x20, 0xa8, 0xee, 0x85,
-0x46, 0x43, 0x99, 0x28, 0x9b, 0x16, 0x5f, 0x07,
-0x73, 0x0c, 0x79, 0x82, 0x1c, 0x83, 0x3d, 0x11,
-0xbf, 0xa1, 0xac, 0xf6, 0x37, 0xb0, 0xaf, 0x1a,
-0x64, 0x39, 0x41, 0xe6, 0xb0, 0xd5, 0x6f, 0xcf,
-0x77, 0x31, 0x3c, 0x08, 0xb5, 0x86, 0x12, 0x22,
-0x14, 0x06, 0x88, 0xdf, 0x90, 0x53, 0x64, 0x31,
-0x0c, 0xa8, 0x01, 0x43, 0x09, 0x10, 0x05, 0x1e,
-0x1d, 0x69, 0x48, 0xca, 0xdb, 0x0b, 0x57, 0xb1,
-0x77, 0xc5, 0xfc, 0x4c, 0xc0, 0x17, 0xe1, 0x69,
-0x5a, 0x9f, 0x56, 0x56, 0x91, 0x32, 0xf8, 0x76,
-0xe2, 0xaa, 0xb4, 0xbc, 0xaa, 0xf0, 0x67, 0xb0,
-0x1b, 0xaf, 0x2c, 0x25, 0x33, 0x54, 0xf6, 0x55,
-0x54, 0x5e, 0x4a, 0xee, 0x73, 0xee, 0xdf, 0x01,
-0x8b, 0xd5, 0x8f, 0x60, 0xbe, 0xe1, 0x9b, 0x2b,
-0x52, 0xf8, 0x50, 0x0d, 0x4d, 0x7a, 0x43, 0xe2,
-0x08, 0x9d, 0x60, 0x8a, 0xf7, 0x95, 0xf6, 0x41,
-0xf2, 0x2e, 0x98, 0xaf, 0x7b, 0x0b, 0xc5, 0xdb,
-0x88, 0xbd, 0x90, 0xf4, 0x2b, 0x9e, 0x85, 0xf3,
-0xd0, 0xc2, 0xf4, 0xd3, 0x35, 0xaa, 0x7f, 0x58,
-0x1a, 0x8e, 0x97, 0xec, 0x14, 0x27, 0xe1, 0x8c,
-0xda, 0x7c, 0x87, 0xef, 0x27, 0xe2, 0x04, 0x7e,
-0xd5, 0xbe, 0x61, 0x54, 0x4c, 0x14, 0xda, 0xfa,
-0x91, 0x81, 0xeb, 0x67, 0xcc, 0x3b, 0xd0, 0x0d,
-0xf0, 0x06, 0x0d, 0xa5, 0xbd, 0xbb, 0xbb, 0x83,
-0x6c, 0x58, 0xd3, 0x88, 0x6f, 0x42, 0x7c, 0x0f,
-0xf6, 0xb7, 0x37, 0x1a, 0xde, 0xb4, 0xe8, 0x71,
-0x7e, 0xdf, 0x91, 0xca, 0xcd, 0xf0, 0x34, 0xd4,
-0x8f, 0x14, 0xdf, 0x2b, 0x26, 0xe0, 0xa7, 0x50,
-0x6d, 0x14, 0xfc, 0x9d, 0x78, 0x07, 0xfb, 0x45,
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diff --git a/board/esd/voh405/logo_320_240_4bpp.c b/board/esd/voh405/logo_320_240_4bpp.c
deleted file mode 100644
index 5dfc1f7..0000000
--- a/board/esd/voh405/logo_320_240_4bpp.c
+++ /dev/null
@@ -1,153 +0,0 @@
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diff --git a/board/esd/voh405/logo_640_480_24bpp.c b/board/esd/voh405/logo_640_480_24bpp.c
deleted file mode 100644
index defa69f..0000000
--- a/board/esd/voh405/logo_640_480_24bpp.c
+++ /dev/null
@@ -1,3443 +0,0 @@
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-0xc4, 0x98, 0x77, 0x79, 0x80, 0xfe, 0x3b, 0xf6,
-0x6c, 0xaa, 0xdf, 0x62, 0x7a, 0x95, 0x00, 0x00,
-0x00, 0x40, 0xe8, 0xa0, 0xc3, 0xab, 0x82, 0x4d,
-0x41, 0x2f, 0x1a, 0x67, 0x7a, 0x89, 0x00, 0x00,
-0x00, 0x40, 0xe8, 0xa0, 0x48, 0x3f, 0x5d, 0xff,
-0xde, 0x00, 0xfd, 0x77, 0xfc, 0x47, 0x31, 0x0e,
-0x18, 0x00, 0x00, 0x00, 0x28, 0x84, 0xe6, 0x07,
-0x59, 0x05, 0xcd, 0x74, 0x62, 0x87, 0xe9, 0x25,
-0x02, 0x00, 0x00, 0x00, 0xa1, 0x83, 0x8e, 0x04,
-0x9d, 0x82, 0xbe, 0xc9, 0xf4, 0x12, 0x01, 0x00,
-0x00, 0x80, 0xd0, 0x41, 0x43, 0xbd, 0xc1, 0xa6,
-0xa0, 0xef, 0xfc, 0x34, 0xc5, 0x22, 0xa6, 0x57,
-0x09, 0x00, 0x00, 0x00, 0x84, 0x0c, 0x22, 0x9a,
-0xf5, 0xab, 0x00, 0xfd, 0xf7, 0xe2, 0xd7, 0xd1,
-0xc9, 0xbd, 0xa6, 0x17, 0x09, 0x00, 0x00, 0x00,
-0x84, 0x0e, 0x3a, 0xf0, 0x22, 0x5d, 0x78, 0x56,
-0x80, 0x16, 0xfc, 0xe2, 0x04, 0xd3, 0x4b, 0x04,
-0x00, 0x00, 0x00, 0x42, 0x07, 0xc5, 0x86, 0xe8,
-0xda, 0x77, 0x05, 0xe8, 0xbf, 0xb7, 0x7f, 0xd2,
-0x4a, 0xc4, 0x4d, 0xaf, 0x12, 0x00, 0x00, 0x00,
-0x08, 0x1d, 0x34, 0xeb, 0x97, 0x01, 0xfa, 0xef,
-0x98, 0xb3, 0xe9, 0xf4, 0x41, 0xd3, 0x4b, 0x04,
-0x00, 0x00, 0x00, 0x42, 0x07, 0xed, 0x5b, 0x1c,
-0xa0, 0xff, 0x32, 0x2d, 0xbb, 0xd7, 0xf4, 0x12,
-0x01, 0x00, 0x00, 0x80, 0xd0, 0x41, 0x03, 0x1d,
-0x74, 0xd5, 0xdb, 0x03, 0xf4, 0xdf, 0xfb, 0xfe,
-0x8d, 0x92, 0x48, 0x41, 0x03, 0x00, 0x00, 0x00,
-0x79, 0x10, 0xcd, 0xf8, 0x59, 0x80, 0xfe, 0x3b,
-0xf6, 0x6c, 0x6a, 0xa9, 0x35, 0xbd, 0x46, 0x00,
-0x00, 0x00, 0x20, 0x74, 0xd0, 0x9e, 0x45, 0xc1,
-0xa6, 0xa0, 0x97, 0x4f, 0x34, 0xbd, 0x44, 0x00,
-0x00, 0x00, 0x20, 0x74, 0xd0, 0x50, 0x0f, 0x5d,
-0xf5, 0xb6, 0x40, 0x53, 0xd0, 0x56, 0x22, 0x66,
-0x7a, 0x95, 0x00, 0x00, 0x00, 0x40, 0xd8, 0x20,
-0x7a, 0xec, 0x87, 0x01, 0xfa, 0xef, 0xa5, 0x6f,
-0x44, 0x0a, 0x1a, 0x00, 0x00, 0x00, 0x28, 0x84,
-0xb6, 0xcd, 0x09, 0x36, 0x05, 0xbd, 0xe6, 0x21,
-0xd3, 0x4b, 0x04, 0x00, 0x00, 0x00, 0x42, 0x07,
-0xf5, 0xb6, 0xd0, 0xe5, 0x6f, 0x0e, 0xd0, 0x7f,
-0x1f, 0xf8, 0xf2, 0xff, 0x07, 0x66, 0x87, 0xe4,
-0x0f, 0x36, 0x10, 0x0e, 0x00,
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
deleted file mode 100644
index 3cc2206..0000000
--- a/board/esd/voh405/voh405.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <malloc.h>
-
-/* ------------------------------------------------------------------------- */
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-extern void lxt971_no_sleep(void);
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-/* logo bitmap data - gzip compressed and generated by bin2c */
-unsigned char logo_bmp_320[] =
-{
-#include "logo_320_240_4bpp.c"
-};
-
-unsigned char logo_bmp_640[] =
-{
-#include "logo_640_480_24bpp.c"
-};
-
-
-/*
- * include common lcd code (for esd boards)
- */
-#include "../common/lcd.c"
-
-#include "../common/s1d13704_320_240_4bpp.h"
-#include "../common/s1d13806_320_240_4bpp.h"
-#include "../common/s1d13806_640_480_16bpp.h"
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
- unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
- unsigned short *lcd_contrast =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
- unsigned short *lcd_backlight =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
- char *str;
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_INIT pin
- */
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
- udelay(1000); /* wait 1ms */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
- udelay(1000); /* wait 1ms */
-
- /*
- * Reset external DUARTs
- */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
- udelay(10); /* wait 10us */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
- udelay(1000); /* wait 1ms */
-
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
-
- /*
- * Setup EEPROM write protection
- */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- out_8(duart0_mcr, 0x08);
- out_8(duart1_mcr, 0x08);
-
- /*
- * Init lcd interface and display logo
- */
- str = getenv("bd_type");
- if (strcmp(str, "voh405_bw") == 0) {
- lcd_setup(0, 1);
- lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
- regs_13704_320_240_4bpp,
- sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
- logo_bmp_320, sizeof(logo_bmp_320));
- } else if (strcmp(str, "voh405_bwbw") == 0) {
- lcd_setup(0, 1);
- lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
- regs_13704_320_240_4bpp,
- sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
- logo_bmp_320, sizeof(logo_bmp_320));
- lcd_setup(1, 1);
- lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13806_320_240_4bpp,
- sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
- logo_bmp_320, sizeof(logo_bmp_320));
- } else if (strcmp(str, "voh405_bwc") == 0) {
- lcd_setup(0, 1);
- lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
- regs_13704_320_240_4bpp,
- sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
- logo_bmp_320, sizeof(logo_bmp_320));
- lcd_setup(1, 0);
- lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
- regs_13806_640_480_16bpp,
- sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
- logo_bmp_640, sizeof(logo_bmp_640));
- } else {
- printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
- return 0;
- }
-
- /*
- * Set invert bit in small lcd controller
- */
- out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
- in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
-
- /*
- * Set default contrast voltage on epson vga controller
- */
- out_be16(lcd_contrast, 0x4646);
-
- /*
- * Enable backlight
- */
- out_be16(lcd_backlight, 0xffff);
-
- /*
- * Enable external I2C bus
- */
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming VOH405");
- } else {
- puts(str);
- }
-
- if (getenv_f("bd_type", str, sizeof(str)) != -1) {
- printf(" (%s)", str);
- } else {
- puts(" (Missing bd_type!)");
- }
-
- putc ('\n');
-
- return 0;
-}
-
-#ifdef CONFIG_IDE_RESET
-#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
-void ide_set_reset(int on)
-{
- /*
- * Assert or deassert CompactFlash Reset Pin
- */
- if (on) { /* assert RESET */
- out_be16((void *)FPGA_MODE,
- in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
- } else { /* release RESET */
- out_be16((void *)FPGA_MODE,
- in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
- }
-}
-#endif /* CONFIG_IDE_RESET */
-
-#if defined(CONFIG_RESET_PHY_R)
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-#endif
-}
-#endif
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state)
-{
- if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
- return -1;
- } else {
- switch (state) {
- case 1:
- /* Enable write access, clear bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- case 0:
- /* Disable write access, set bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
- state = 0;
- break;
- default:
- /* Read current status back. */
- state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
- break;
- }
- }
- return state;
-}
-
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int query = argc == 1;
- int state = 0;
-
- if (query) {
- /* Query write access state. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
- if (state < 0) {
- puts ("Query of write access state failed.\n");
- } else {
- printf ("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
- state = 0;
- }
- } else {
- if ('0' == argv[1][0]) {
- /* Disable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
- } else {
- /* Enable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0) {
- puts ("Setup of write access state failed.\n");
- }
- }
-
- return state;
-}
-
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- ""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/wuh405/Kconfig b/board/esd/wuh405/Kconfig
deleted file mode 100644
index 8a7df4d..0000000
--- a/board/esd/wuh405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_WUH405
-
-config SYS_BOARD
- default "wuh405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "WUH405"
-
-endif
diff --git a/board/esd/wuh405/MAINTAINERS b/board/esd/wuh405/MAINTAINERS
deleted file mode 100644
index 782c72a..0000000
--- a/board/esd/wuh405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-WUH405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/wuh405/
-F: include/configs/WUH405.h
-F: configs/WUH405_defconfig
diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile
deleted file mode 100644
index b9beeff..0000000
--- a/board/esd/wuh405/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = wuh405.o flash.o \
- ../common/misc.o \
- ../common/esd405ep_nand.o \
diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/wuh405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/wuh405/fpgadata.c b/board/esd/wuh405/fpgadata.c
deleted file mode 100644
index a964f9f..0000000
--- a/board/esd/wuh405/fpgadata.c
+++ /dev/null
@@ -1,3636 +0,0 @@
-0x1f, 0x8b, 0x08, 0x08, 0xe2, 0x44, 0xc5, 0x42,
-0x00, 0x03, 0x77, 0x75, 0x68, 0x34, 0x30, 0x35,
-0x5f, 0x31, 0x2e, 0x62, 0x69, 0x74, 0x00, 0xec,
-0xbd, 0x0d, 0x74, 0x14, 0xd7, 0x95, 0x2e, 0xba,
-0xeb, 0x54, 0x49, 0x94, 0xba, 0x5b, 0xea, 0x42,
-0x48, 0x1e, 0xd9, 0x60, 0x5c, 0x6a, 0x09, 0xd2,
-0x28, 0x8d, 0x68, 0x24, 0x47, 0x60, 0x21, 0x4b,
-0x45, 0x8b, 0x78, 0x14, 0x20, 0x41, 0xe3, 0x78,
-0x12, 0xee, 0x7d, 0x5e, 0x99, 0xb6, 0x43, 0x66,
-0x78, 0x33, 0xc4, 0x97, 0xc4, 0xb9, 0x77, 0x88,
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-0x2e, 0x59, 0x8b, 0x5d, 0xe0, 0x4b, 0x68, 0x92,
-0x6b, 0x20, 0x4c, 0x1b, 0x9a, 0xd8, 0x85, 0x92,
-0x68, 0x51, 0xf2, 0x49, 0x31, 0x3f, 0x22, 0xe9,
-0xf1, 0x0d, 0xd7, 0x8c, 0xf8, 0x90, 0x0e, 0x94,
-0xcf, 0x04, 0x6d, 0xa7, 0xd2, 0x0f, 0xc9, 0x85,
-0x2b, 0x02, 0x1d, 0xed, 0xd5, 0x66, 0x3c, 0x0c,
-0xa1, 0x57, 0xa6, 0x1d, 0xe4, 0x73, 0x34, 0xa3,
-0x21, 0x16, 0xce, 0xf0, 0xdd, 0x15, 0xab, 0x12,
-0x0f, 0xce, 0x64, 0x4c, 0x32, 0x41, 0x62, 0x11,
-0x6e, 0xa1, 0xf9, 0x4a, 0x80, 0x69, 0xe7, 0x1d,
-0x2a, 0x5b, 0xd0, 0x84, 0x87, 0x5c, 0x75, 0x3f,
-0xcd, 0x07, 0x70, 0x89, 0xec, 0x87, 0xec, 0x2c,
-0x3c, 0x2a, 0x1f, 0x21, 0x07, 0x20, 0xcb, 0xed,
-0x47, 0xf4, 0x12, 0x9a, 0xa3, 0x68, 0x7a, 0x2e,
-0x81, 0x34, 0x11, 0x1f, 0x32, 0x32, 0x01, 0xde,
-0x32, 0xf2, 0x21, 0xc6, 0xc3, 0x3d, 0xde, 0xee,
-0xc7, 0x10, 0x0b, 0xf9, 0xb4, 0xc0, 0xc2, 0x02,
-0x99, 0xe7, 0x41, 0x68, 0xb8, 0x12, 0x0f, 0xce,
-0xb7, 0x9b, 0x72, 0xfe, 0xfc, 0xa4, 0x8c, 0x34,
-0x58, 0xc5, 0x32, 0x6a, 0xb6, 0xdc, 0xe0, 0xc3,
-0xb2, 0x98, 0x6f, 0x82, 0x0f, 0xd5, 0xf5, 0x45,
-0x20, 0xe3, 0xb4, 0x86, 0xf3, 0xa7, 0x64, 0x79,
-0x79, 0x13, 0x59, 0x8a, 0xa1, 0xc9, 0xa1, 0xa1,
-0xa1, 0xc9, 0x44, 0x3c, 0xc6, 0x18, 0x96, 0x94,
-0xf7, 0x1d, 0xdf, 0x30, 0x61, 0x2f, 0xae, 0x23,
-0xa7, 0x4a, 0x52, 0x24, 0xeb, 0x15, 0x6b, 0xd8,
-0x82, 0x06, 0xea, 0x86, 0x91, 0x28, 0x1e, 0x93,
-0xfa, 0xb6, 0xe4, 0x43, 0xce, 0xba, 0x30, 0xdb,
-0xc4, 0x91, 0x0f, 0x59, 0x1d, 0x0b, 0x9b, 0x06,
-0x94, 0xf5, 0x35, 0xec, 0xb5, 0x96, 0x78, 0xd5,
-0x33, 0x17, 0x63, 0x5d, 0x48, 0x83, 0x58, 0x62,
-0x0b, 0x3e, 0x9c, 0x43, 0x12, 0xdb, 0x3b, 0x87,
-0x09, 0xa3, 0x22, 0xf8, 0x70, 0x0e, 0x94, 0xf5,
-0xc5, 0xae, 0xca, 0x24, 0x83, 0x39, 0xb7, 0xec,
-0x49, 0x53, 0xc2, 0xfc, 0x63, 0xbb, 0xf0, 0x6d,
-0x62, 0xf3, 0x3f, 0x04, 0x16, 0xa2, 0x4e, 0xac,
-0x9d, 0x37, 0xd7, 0x17, 0xf6, 0xe7, 0xd3, 0xd0,
-0x0e, 0x89, 0x8c, 0x59, 0xe1, 0x01, 0xdc, 0x88,
-0x63, 0x46, 0xae, 0xc0, 0x4c, 0x1f, 0xe6, 0x9f,
-0x18, 0xa9, 0xac, 0x61, 0x8e, 0x46, 0x53, 0x52,
-0xd7, 0x57, 0xc0, 0x8e, 0xc0, 0x7e, 0x88, 0xcf,
-0xd6, 0xaa, 0xfc, 0x08, 0xd9, 0x4f, 0xb2, 0xbc,
-0xf2, 0x88, 0x9e, 0x6f, 0x11, 0x77, 0x90, 0x3f,
-0x9a, 0x3e, 0x92, 0xdc, 0x1f, 0xc7, 0x3b, 0xc8,
-0x9b, 0xe3, 0x53, 0xc4, 0xf2, 0xfb, 0x9b, 0xc1,
-0xfe, 0x53, 0xf1, 0x05, 0xf8, 0x05, 0xf8, 0x2c,
-0x65, 0xc5, 0x29, 0x7c, 0x88, 0xb9, 0x53, 0x9a,
-0x95, 0x46, 0x8b, 0x7a, 0xbf, 0x28, 0x0c, 0xb0,
-0x96, 0x62, 0x7c, 0xa2, 0xb2, 0xc0, 0xfb, 0x59,
-0x4b, 0x26, 0xee, 0xc0, 0x3d, 0xda, 0x5f, 0x48,
-0x15, 0x43, 0xc3, 0x52, 0x13, 0x71, 0xc7, 0x5a,
-0x25, 0x56, 0x33, 0x9e, 0x2c, 0x0d, 0x56, 0x5c,
-0x7f, 0xc4, 0x85, 0x1f, 0x95, 0x99, 0x30, 0xa6,
-0x7d, 0x2d, 0x6c, 0x49, 0xd9, 0xd7, 0x21, 0x58,
-0x29, 0x08, 0xc3, 0x2d, 0x65, 0x7c, 0xa0, 0x1b,
-0xb3, 0xb4, 0xfa, 0xf2, 0xe4, 0xee, 0x67, 0xbc,
-0xd7, 0x8a, 0xd6, 0x57, 0xa1, 0xc1, 0x87, 0x3c,
-0x77, 0x4e, 0x98, 0x4e, 0xeb, 0x63, 0xe4, 0x43,
-0x4b, 0x60, 0xe1, 0x22, 0x9c, 0xb3, 0xcd, 0x90,
-0x0f, 0x9b, 0xe3, 0x99, 0x67, 0xb9, 0xd7, 0xed,
-0xb4, 0x93, 0xcf, 0xf3, 0x13, 0xd3, 0x45, 0xdb,
-0x31, 0xf2, 0xc4, 0x62, 0x0c, 0xd3, 0x8e, 0x81,
-0xf9, 0x27, 0x07, 0xd8, 0x42, 0xf3, 0x40, 0xa2,
-0xf5, 0x8e, 0xf3, 0x21, 0xac, 0x8c, 0xbb, 0x64,
-0xe6, 0xb3, 0x66, 0x0d, 0x39, 0x37, 0x41, 0x14,
-0x31, 0xc4, 0xac, 0xd7, 0x0b, 0x25, 0x88, 0x78,
-0x5e, 0xf0, 0x21, 0x87, 0x2a, 0x43, 0x1a, 0xa4,
-0xb1, 0x32, 0x43, 0x50, 0xa4, 0x2a, 0x28, 0x86,
-0x26, 0xea, 0xcd, 0xf2, 0xaf, 0x91, 0x49, 0x46,
-0x1f, 0x9c, 0x7d, 0xc5, 0x6d, 0x49, 0xb4, 0xb1,
-0xf5, 0x07, 0x9d, 0x87, 0x53, 0x2d, 0xf1, 0x49,
-0x34, 0x03, 0x87, 0x8d, 0xd7, 0xea, 0x46, 0xc9,
-0x3f, 0x78, 0xbd, 0x3d, 0x17, 0x33, 0x4b, 0xc8,
-0x87, 0xef, 0xfe, 0xbe, 0x47, 0xec, 0xfe, 0x7b,
-0xbc, 0x74, 0x2d, 0x31, 0x23, 0x79, 0xa0, 0xbd,
-0x01, 0x06, 0x4a, 0xfe, 0x01, 0xf8, 0xda, 0x5b,
-0x23, 0x0f, 0xdf, 0xbd, 0xbd, 0xfc, 0x9d, 0x1b,
-0x2f, 0xbe, 0x35, 0x26, 0xf8, 0xf0, 0xfd, 0x3a,
-0x1f, 0x2e, 0x47, 0x7c, 0xb8, 0xeb, 0x19, 0xf7,
-0x50, 0xc4, 0x87, 0xc7, 0x05, 0x1f, 0xee, 0xd4,
-0xf9, 0xf0, 0x69, 0xc4, 0x87, 0xbb, 0x78, 0xec,
-0xf3, 0xea, 0xab, 0x02, 0x0b, 0xff, 0x5a, 0xd9,
-0xd9, 0x1e, 0xda, 0xaa, 0x83, 0x22, 0x12, 0xe3,
-0x73, 0xf8, 0x50, 0xfe, 0xf4, 0xbf, 0x6f, 0x62,
-0xff, 0x4f, 0x1b, 0xa0, 0x78, 0xf9, 0x79, 0x7c,
-0x38, 0xd8, 0xe0, 0xc3, 0xee, 0x03, 0xe3, 0x1b,
-0xf3, 0xfd, 0x9b, 0x4f, 0x1e, 0x0f, 0x5d, 0x7a,
-0xa6, 0xff, 0xe3, 0x2f, 0x1e, 0xbd, 0x0f, 0x1e,
-0x11, 0x2f, 0x28, 0x7c, 0xc8, 0xa6, 0xbe, 0xf8,
-0x59, 0xb4, 0xb4, 0xb4, 0xb4, 0xb4, 0xb4, 0xb4,
-0xb4, 0xb4, 0xb4, 0xb4, 0xfe, 0xdf, 0x25, 0x6b,
-0x07, 0xaa, 0x6b, 0x07, 0x2d, 0x2d, 0x2d, 0x2d,
-0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0xad, 0xe7,
-0x4b, 0xd6, 0x0e, 0x09, 0x5d, 0x3b, 0x68, 0x69,
-0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69,
-0x69, 0x3d, 0x5f, 0xb2, 0x76, 0x30, 0x65, 0xed,
-0xf0, 0xbf, 0x0e, 0x45, 0x4b, 0x4b, 0x4b, 0x4b,
-0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0xeb, 0xbf,
-0x28, 0x5f, 0xfc, 0xd1, 0x24, 0xf8, 0xe7, 0x79,
-0x1f, 0xb8, 0xf8, 0xce, 0x53, 0xdc, 0x07, 0xf6,
-0xb9, 0xdf, 0x27, 0xd4, 0x3f, 0x6b, 0xf8, 0x50,
-0x25, 0xd1, 0x39, 0x1f, 0x9f, 0x7e, 0xb6, 0xdf,
-0xbf, 0x00, 0x34, 0x34, 0xbf, 0x69, 0xee, 0x33,
-0x01, 0x00,
diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
deleted file mode 100644
index 71d16e4..0000000
--- a/board/esd/wuh405/wuh405.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <malloc.h>
-
-/* ------------------------------------------------------------------------- */
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-
- /*
- * Reset external DUARTs
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
- udelay(10); /* wait 10us */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
- udelay(1000); /* wait 1ms */
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- out_8((void *)(DUART0_BA + 4), 0x08);
- out_8((void *)(DUART1_BA + 4), 0x08);
- out_8((void *)(DUART2_BA + 4), 0x08);
- out_8((void *)(DUART3_BA + 4), 0x08);
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming WUH405");
- } else {
- puts(str);
- }
-
- putc ('\n');
-
- return 0;
-}
diff --git a/board/evb64260/64260.h b/board/evb64260/64260.h
deleted file mode 100644
index d106ced..0000000
--- a/board/evb64260/64260.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __64260_H__
-#define __64260_H__
-
-/* CPU Configuration bits */
-#define CPU_CONF_ADDR_MISS_EN (1 << 8)
-#define CPU_CONF_AACK_DELAY (1 << 11)
-#define CPU_CONF_ENDIANESS (1 << 12)
-#define CPU_CONF_PIPELINE (1 << 13)
-#define CPU_CONF_TA_DELAY (1 << 15)
-#define CPU_CONF_RD_OOO (1 << 16)
-#define CPU_CONF_STOP_RETRY (1 << 17)
-#define CPU_CONF_MULTI_DECODE (1 << 18)
-#define CPU_CONF_DP_VALID (1 << 19)
-#define CPU_CONF_PERR_PROP (1 << 22)
-#define CPU_CONF_FAST_CLK (1 << 23)
-#define CPU_CONF_AACK_DELAY_2 (1 << 25)
-#define CPU_CONF_AP_VALID (1 << 26)
-#define CPU_CONF_REMAP_WR_DIS (1 << 27)
-#define CPU_CONF_CONF_SB_DIS (1 << 28)
-#define CPU_CONF_IO_SB_DIS (1 << 29)
-#define CPU_CONF_CLK_SYNC (1 << 30)
-
-/* CPU Master Control bits */
-#define CPU_MAST_CTL_ARB_EN (1 << 8)
-#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
-#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
-#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
-#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
-#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
-
-#endif /* __64260_H__ */
diff --git a/board/evb64260/Kconfig b/board/evb64260/Kconfig
deleted file mode 100644
index 933e6d6..0000000
--- a/board/evb64260/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if TARGET_P3G4
-
-config SYS_BOARD
- default "evb64260"
-
-config SYS_CONFIG_NAME
- default "P3G4"
-
-endif
-
-if TARGET_ZUMA
-
-config SYS_BOARD
- default "evb64260"
-
-config SYS_CONFIG_NAME
- default "ZUMA"
-
-endif
diff --git a/board/evb64260/MAINTAINERS b/board/evb64260/MAINTAINERS
deleted file mode 100644
index d50dda5..0000000
--- a/board/evb64260/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-EVB64260 BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/evb64260/
-F: include/configs/P3G4.h
-F: configs/P3G4_defconfig
-
-ZUMA BOARD
-#M: Nye Liu <nyet@zumanetworks.com>
-S: Orphan (since 2014-04)
-F: include/configs/ZUMA.h
-F: configs/ZUMA_defconfig
diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile
deleted file mode 100644
index ae2ebed..0000000
--- a/board/evb64260/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = misc.o
-obj-y += evb64260.o flash.o serial.o memory.o pci.o \
- eth.o eth_addrtbl.o mpsc.o i2c.o \
- sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o
diff --git a/board/evb64260/README b/board/evb64260/README
deleted file mode 100644
index 74211de..0000000
--- a/board/evb64260/README
+++ /dev/null
@@ -1,54 +0,0 @@
-This file contains status information for the port of U-Boot to the
-Galileo Evaluation Board.
-
-Author: Josh Huber <huber@mclx.com>
- Mission Critical Linux, Inc.
-
-The support for the Galileo Evaluation board is fairly minimal now.
-It's sufficient to boot Linux, but doesn't provide too much more than
-what's required to do this.
-
-Both DUART channels are supported (to use the second one, you have to
-modify the board -- see the schematics for where to solder on the
-devices module). The ethernet ports are supported, and the MPSC is
-supported as a console driver. (keep in mind that the kernel has no
-support for this yet)
-
-There are still occaisonal lockups with the MPSC console driver due to
-(we think!) overrun problems. If you're looking for something stable
-to use for Linux development, consider sticking with the DUART console
-for now.
-
-Automatic memory sizing mostly works. We've had problems with some
-combinations of memory. Please send us email if you're having trouble
-with respect to the memory detection.
-
-Right now, only the 512k boot flash is supported. Support for the
-16MB flash on the devices module is forthcoming. Right now the flash
-is stored at the 256k boundry in flash, wasting a whole sector (64k!)
-for environment data. This isn't really a big deal since we're not
-using the 512k for anything else. (Just U-Boot and the environment)
-
-Finally, here is a sample output session:
-
-U-Boot 1.0.0-pre1 (Jun 6 2001 - 12:45:11)
-
-Initializing...
- CPU: MPC7400 (altivec enabled) v2.9
- Board: EVB64260
- DRAM: 256 MB
- FLASH: 512 kB
- In: serial
- Out: serial
- Err: serial
-
-=>
-
-The default configuration should be correct for the evaluation board,
-as it's shipped from Galileo. Keep in mind that the default baudrate
-is set to 38400, 8N1.
-
-Good luck, and make sure to send any bugreports to us (or the
-u-boot-users list).
-
-Josh
diff --git a/board/evb64260/README.EVB-64260-750CX b/board/evb64260/README.EVB-64260-750CX
deleted file mode 100644
index 5ea38ea..0000000
--- a/board/evb64260/README.EVB-64260-750CX
+++ /dev/null
@@ -1,7 +0,0 @@
-The EVB-64260-750CX is quite similar to the EVB-64260-BP already
-supported except the following differences:
-* It has an IBM-750CXe soldiered on board instead of the slot-1 in the
- BP.
-* It has a single PCI male connector instead of the 4 PCI female
- connectors on the BP. It also gets power trough the PCI connector.
-* It has only a single DIMM slot instead of the 2 slots in the BP.
diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt
deleted file mode 100644
index 6cae9ea..0000000
--- a/board/evb64260/bootseq.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-(cpu/mpc7xxx/start.S)
-
-start:
- b boot_cold
-
-start_warm:
- b boot_warm
-
-
-boot_cold:
-boot_warm:
- clear bats
- init l2 (if enabled)
- init altivec (if enabled)
- invalidate l2 (if enabled)
- setup bats (from defines in config_EVB)
- enable_addr_trans: (if MMU enabled)
- enable MSR_IR and MSR_DR
- jump to in_flash
-
-in_flash:
- enable l1 dcache
- gal_low_init: (board/evb64260/sdram_init.S)
- config SDRAM (CFG, TIMING, DECODE)
- init scratch regs (810 + 814)
-
- detect DIMM0 (bank 0 only)
- config SDRAM_PARA0 to 256/512Mbit
- bl sdram_op_mode
- detect bank0 width
- write scratch reg 810
- config SDRAM_PARA0 with results
- config SDRAM_PARA1 with results
-
- detect DIMM1 (bank 2 only)
- config SDRAM_PARA2 to 256/512Mbit
- detect bank2 width
- write scratch reg 814
- config SDRAM_PARA2 with results
- config SDRAM_PARA3 with results
-
- setup device bus timings/width
- setup boot device timings/width
-
- setup CPU_CONF (0x0)
- setup cpu master control register 0x160
- setup PCI0 TIMEOUT
- setup PCI1 TIMEOUT
- setup PCI0 BAR
- setup PCI1 BAR
-
- setup MPP control 0-3
- setup GPP level control
- setup Serial ports multiplex
-
- setup stack pointer (r1)
- setup GOT
- call cpu_init_f
- debug leds
- board_init_f: (common/board.c)
- board_early_init_f:
- remap gt regs?
- map PCI mem/io
- map device space
- clear out interrupts
- init_timebase
- env_init
- serial_init
- console_init_f
- display_options
- initdram: (board/evb64260/evb64260.c)
- detect memory
- for each bank:
- dram_size()
- setup PCI slave memory mappings
- setup SCS
- setup monitor
- alloc board info struct
- init bd struct
- relocate_code: (cpu/mpc7xxx/start.S)
- copy,got,clearbss
- board_init_r(bd, dest_addr) (common/board.c)
- setup bd function pointers
- trap_init
- flash_init: (board/evb64260/flash.c)
- setup bd flash info
- cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
- nothing
- mem_malloc_init
- malloc_bin_reloc
- spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
- env_relocated
- misc_init_r(bd): (board/evb64260/evb64260.c)
- mpsc_init2
diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
deleted file mode 100644
index d7f63bd..0000000
--- a/board/evb64260/eth.c
+++ /dev/null
@@ -1,805 +0,0 @@
-/**************************************************************************
-Etherboot - BOOTP/TFTP Bootstrap Program
-Skeleton NIC driver for Etherboot
-***************************************************************************/
-
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This file is a modified version from the Galileo polled mode
- * network driver for the ethernet contained within the GT64260
- * chip. It has been modified to fit into the U-Boot framework, from
- * the original (etherboot) setup. Also, additional cleanup and features
- * were added.
- *
- * - Josh Huber <huber@mclx.com>
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <galileo/gt64260R.h>
-#include <galileo/core.h>
-#include <asm/cache.h>
-#include <miiphy.h>
-#include <net.h>
-#include <netdev.h>
-
-#include "eth.h"
-#include "eth_addrtbl.h"
-
-#if defined(CONFIG_CMD_NET)
-
-#define GT6426x_ETH_BUF_SIZE 1536
-
-/* if you like verbose output, turn this on! */
-#undef DEBUG
-
-/* Restart autoneg if we detect link is up on phy init. */
-
-/*
- * The GT doc's say that after Rst is deasserted, and the PHY
- * reports autoneg complete, it runs through its autoneg
- * procedures. This doesn't seem to be the case for MII
- * PHY's. To work around this check for link up && autoneg
- * complete when initilizing the port. If they are both set,
- * then restart PHY autoneg. Of course, it may be something
- * completly different.
- */
-#ifdef CONFIG_ETHER_PORT_MII
-# define RESTART_AUTONEG
-#endif
-
-/* do this if you dont want to use snooping */
-#define USE_SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef USE_SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-/* bummer - w/o flush, nothing works, even with snooping - FIXME */
-/* #define FLUSH_DCACHE(a,b) */
-#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-struct eth_dev_s {
- eth0_tx_desc_single *eth_tx_desc;
- eth0_rx_desc_single *eth_rx_desc;
- char *eth_tx_buffer;
- char *eth_rx_buffer[NR];
- int tdn, rdn;
- int dev;
- unsigned int reg_base;
-};
-
-
-#ifdef CONFIG_INTEL_LXT97X
-/* for intel LXT972 */
-static const char ether_port_phy_addr[3]={0,1,2};
-#else
-static const char ether_port_phy_addr[3]={4,5,6};
-#endif
-
-/* MII PHY access routines are common for all i/f, use gal_ent0 */
-#define GT6426x_MII_DEVNAME "gal_enet0"
-
-int gt6426x_miiphy_read(const char *devname, unsigned char phy,
- unsigned char reg, unsigned short *val);
-
-static inline unsigned short
-miiphy_read_ret(unsigned short phy, unsigned short reg)
-{
- unsigned short val;
- gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
- return val;
-}
-
-
-/**************************************************************************
-RESET - Reset adapter
-***************************************************************************/
-void
-gt6426x_eth_reset(void *v)
-{
- /* we should do something here...
- struct eth_device *wp = (struct eth_device *)v;
- struct eth_dev_s *p = wp->priv;
- */
-
- printf ("RESET\n");
- /* put the card in its initial state */
-}
-
-static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
-{
-#ifdef DEBUG
- printf("SMI interrupt: ");
-
- if(icr&0x20000000) {
- printf("SMI done\n");
- }
-#endif
-
- if(icr&0x10000000) {
-#ifdef DEBUG
- unsigned int psr;
-
- psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
- printf("PHY state change:\n"
- " GT:%s:%s:%s:%s\n",
- psr & 1 ? "100" : " 10",
- psr & 8 ? " Link" : "nLink",
- psr & 2 ? "FD" : "HD",
- psr & 4 ? " FC" : "nFC");
-
-#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
- {
- unsigned short mii_11;
- mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11);
-
- printf(" mii:%s:%s:%s:%s %s:%s %s\n",
- mii_11 & (1 << 14) ? "100" : " 10",
- mii_11 & (1 << 10) ? " Link" : "nLink",
- mii_11 & (1 << 9) ? "FD" : "HD",
- mii_11 & (1 << 4) ? " FC" : "nFC",
-
- mii_11 & (1 << 7) ? "ANc" : "ANnc",
- mii_11 & (1 << 8) ? "AN" : "Manual",
- ""
- );
- }
-#endif /* CONFIG_INTEL_LXT97X */
-#endif /* DEBUG */
- }
-}
-
-static int
-gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
-{
- int eth_len=0;
- char *eth_data;
-
- eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)];
-
- INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
-
- if (rx->command_status & 0x80000000) {
- return 0; /* No packet received */
- }
-
- eth_len = (unsigned int)
- (rx->buff_size_byte_count) & 0x0000ffff;
- eth_data = (char *) p->eth_rx_buffer[p->rdn];
-
-#ifdef DEBUG
- if (eth_len) {
- printf ("%s: Recived %d byte Packet @ 0x%p\n",
- __FUNCTION__, eth_len, eth_data);
- }
-#endif
- /*
- * packet is now in:
- * eth0_rx_buffer[RDN_ETH0];
- */
-
- /* let the upper layer handle the packet */
- NetReceive ((uchar *)eth_data, eth_len);
-
- rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
-
-
- /* GT96100 Owner */
- rx->command_status = 0x80000000;
-
- FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
-
- p->rdn ++;
- if (p->rdn == NR) {p->rdn = 0;}
-
- sync();
-
- /* Start Rx*/
- GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
-
-#ifdef DEBUG
- {
- int i;
- for (i=0;i<12;i++) {
- printf(" %02x", eth_data[i]);
- }
- }
- printf(": %d bytes\n", eth_len);
-#endif
- INVALIDATE_DCACHE((unsigned int)eth_data,
- (unsigned int)eth_data+eth_len);
- return eth_len;
-}
-
-/**************************************************************************
-POLL - look for an rx frame, handle other conditions
-***************************************************************************/
-int
-gt6426x_eth_poll(void *v)
-{
- struct eth_device *wp = (struct eth_device *)v;
- struct eth_dev_s *p = wp->priv;
- unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
-
- if(icr) {
- GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
-#ifdef DEBUG
- printf("poll got ICR %08x\n", icr);
-#endif
- /* SMI done or PHY state change*/
- if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
- }
- /* always process. We aren't using RX interrupts */
- return gt6426x_eth_receive(p, icr);
-}
-
-/**************************************************************************
-TRANSMIT - Transmit a frame
-***************************************************************************/
-int gt6426x_eth_transmit(void *v, char *p, unsigned int s)
-{
- struct eth_device *wp = (struct eth_device *)v;
- struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
-#ifdef DEBUG
- unsigned int old_command_stat,old_psr;
-#endif
- eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn];
-
- /* wait for tx to be ready */
- INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
- while (tx->command_status & 0x80000000) {
- int i;
- for(i=0;i<1000;i++);
- INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
- }
-
- GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
- (unsigned int)tx);
-
-#ifdef DEBUG
- printf("copying to tx_buffer [%p], length %x, desc = %p\n",
- dev->eth_tx_buffer, s, dev->eth_tx_desc);
-#endif
- memcpy(dev->eth_tx_buffer, (char *) p, s);
-
- tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
- tx->bytecount_reserved = ((__u16)s) << 16;
-
- /* 31 - own
- * 22 - gencrc
- * 18:16 - pad, last, first */
- tx->command_status = (1<<31) | (1<<22) | (7<<16);
-#if 0
- /* FEr #18 */
- tx->next_desc = NULL;
-#else
- tx->next_desc =
- (struct eth0_tx_desc_struct *)
- &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
-
- /* cpu owned */
- dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */
-#endif
-
-#ifdef DEBUG
- old_command_stat=tx->command_status,
- old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
-#endif
-
- FLUSH_DCACHE((unsigned int)tx,
- (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
-
- FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
-
- GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
-
-#ifdef DEBUG
- {
- unsigned int command_stat=0;
- printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
- /* wait for tx to be ready */
- do {
- unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
- command_stat=tx->command_status;
- if(command_stat!=old_command_stat || psr !=old_psr) {
- printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
- old_command_stat = command_stat;
- old_psr = psr;
- }
- /* gt6426x_eth0_poll(); */
- } while (command_stat & 0x80000000);
-
- printf("sent %d byte frame\n", s);
-
- if((command_stat & (3<<15)) == 3) {
- printf("frame had error (stat=%08x)\n", command_stat);
- }
- }
-#endif
- return 0;
-}
-
-/**************************************************************************
-DISABLE - Turn off ethernet interface
-***************************************************************************/
-void
-gt6426x_eth_disable(void *v)
-{
- struct eth_device *wp = (struct eth_device *)v;
- struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
-
- GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
-}
-
-/**************************************************************************
-MII utilities - write: write to an MII register via SMI
-***************************************************************************/
-int
-gt6426x_miiphy_write(const char *devname, unsigned char phy,
- unsigned char reg, unsigned short data)
-{
- unsigned int temp= (reg<<21) | (phy<<16) | data;
-
- while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */
-
- GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
- return 0;
-}
-
-/**************************************************************************
-MII utilities - read: read from an MII register via SMI
-***************************************************************************/
-int
-gt6426x_miiphy_read(const char *devname, unsigned char phy,
- unsigned char reg, unsigned short *val)
-{
- unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
-
- while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */
-
- GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
-
- while(1) {
- temp=GTREGREAD(ETHERNET_SMI_REGISTER);
- if(temp & (1<<27)) break; /* wait for ReadValid */
- }
- *val = temp & 0xffff;
-
- return 0;
-}
-
-#ifdef DEBUG
-/**************************************************************************
-MII utilities - dump mii registers
-***************************************************************************/
-static void
-gt6426x_dump_mii(bd_t *bis, unsigned short phy)
-{
- printf("mii reg 0 - 3: %04x %04x %04x %04x\n",
- miiphy_read_ret(phy, 0x0),
- miiphy_read_ret(phy, 0x1),
- miiphy_read_ret(phy, 0x2),
- miiphy_read_ret(phy, 0x3)
- );
- printf(" 4 - 7: %04x %04x %04x %04x\n",
- miiphy_read_ret(phy, 0x4),
- miiphy_read_ret(phy, 0x5),
- miiphy_read_ret(phy, 0x6),
- miiphy_read_ret(phy, 0x7)
- );
- printf(" 8: %04x\n",
- miiphy_read_ret(phy, 0x8)
- );
- printf(" 16-19: %04x %04x %04x %04x\n",
- miiphy_read_ret(phy, 0x10),
- miiphy_read_ret(phy, 0x11),
- miiphy_read_ret(phy, 0x12),
- miiphy_read_ret(phy, 0x13)
- );
- printf(" 20,30: %04x %04x\n",
- miiphy_read_ret(phy, 20),
- miiphy_read_ret(phy, 30)
- );
-}
-#endif
-
-#ifdef RESTART_AUTONEG
-
-/* If link is up && autoneg compleate, and if
- * GT and PHY disagree about link capabilitys,
- * restart autoneg - something screwy with FD/HD
- * unless we do this. */
-static void
-check_phy_state(struct eth_dev_s *p)
-{
- int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR);
- int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
-
- if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) {
- int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) &
- miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA);
- int want;
-
- if (nego & LPA_100FULL) {
- want = 0x3;
- printf("MII: 100Base-TX, Full Duplex\n");
- } else if (nego & LPA_100HALF) {
- want = 0x1;
- printf("MII: 100Base-TX, Half Duplex\n");
- } else if (nego & LPA_10FULL) {
- want = 0x2;
- printf("MII: 10Base-T, Full Duplex\n");
- } else if (nego & LPA_10HALF) {
- want = 0x0;
- printf("MII: 10Base-T, Half Duplex\n");
- } else {
- printf("MII: Unknown link-foo! %x\n", nego);
- return;
- }
-
- if ((psr & 0x3) != want) {
- printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
- psr & 0x3, want);
- miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
- miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
- udelay(10000); /* the EVB's GT takes a while to notice phy
- went down and up */
- }
- }
-}
-#endif
-
-/**************************************************************************
-PROBE - Look for an adapter, this routine's visible to the outside
-***************************************************************************/
-int
-gt6426x_eth_probe(void *v, bd_t *bis)
-{
- struct eth_device *wp = (struct eth_device *)v;
- struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
- int dev = p->dev;
- unsigned int reg_base = p->reg_base;
- unsigned long temp;
- int i;
-
- if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
- { /* This should never happen */
- printf("%s: Invalid device %d\n", __FUNCTION__, dev );
- return 0;
- }
-
-#ifdef DEBUG
- printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
- printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
- GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
- GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
-#endif
-
- /* clear MIB counters */
- for(i=0;i<255; i++)
- temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
-
-#ifdef CONFIG_INTEL_LXT97X
- /* for intel LXT972 */
-
- /* led 1: 0x1=txact
- led 2: 0xc=link/rxact
- led 3: 0x2=rxact (N/C)
- strch: 0,2=30 ms, enable */
- miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
-
- /* 2.7ns port rise time */
- /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
-#else
- /* already set up in mpsc.c */
- /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */
-
- /* already set up in sdram_init.S... */
- /* MPSC0, MPSC1, RMII */
- /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */
-#endif
- GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
- ether_port_phy_addr[0] |
- (ether_port_phy_addr[1]<<5) |
- (ether_port_phy_addr[2]<<10)); /* 2000 */
-
- /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes)
- * 9 - 1: RIFB - interrupt on frame boundaries only
- * 6:7 - 00: big endian rx and tx
- * 5:2 - 1111: 15 retries */
- GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
- (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */
-
-#ifndef USE_SOFTWARE_CACHE_MANAGEMENT
- /* enable rx/tx desc/buffer cache snoop */
- GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
- &temp); /* f200 */
- temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
- GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
- temp);
-#endif
-
- /* 31 28 27 24 23 20 19 16
- * 0000 0000 0000 0000 [0004]
- * 15 12 11 8 7 4 3 0
- * 1000 1101 0000 0000 [4d00]
- * 20 - 0=MII 1=RMII
- * 19 - 0=speed autoneg
- * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
- * 11 - no force link pass
- * 10 - 1=disable fctl autoneg
- * 8 - override prio ?? */
- temp = 0x00004d00;
-#ifndef CONFIG_ETHER_PORT_MII
- temp |= (1<<20); /* RMII */
-#endif
- /* set En */
- GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
- temp); /* 2408 */
-
- /* hardcode E1 also? */
- /* -- according to dox, this is safer due to extra pulldowns? */
- if (dev<2) {
- GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
- temp); /* 2408 */
- }
-
- /* wake up MAC */ /* 2400 */
- GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
- temp |= (1<<7); /* enable port */
-#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
- temp |= (1<<12); /* hash size 1/2k */
-#else
- temp |= 1; /* promisc */
-#endif
- GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
- /* 2400 */
-
-#ifdef RESTART_AUTONEG
- check_phy_state(p);
-#endif
-
- printf("%s: Waiting for link up..\n", wp->name);
- temp = 10 * 1000;
- /* wait for link back up */
- while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
- && (--temp > 0)){
- udelay(1000); /* wait 1 ms */
- }
- if ( temp == 0) {
- printf("%s: Failed!\n", wp->name);
- return (0);
- }
-
- printf("%s: OK!\n", wp->name);
-
- p->tdn = 0;
- p->rdn = 0;
- p->eth_tx_desc[p->tdn].command_status = 0;
-
- /* Initialize Rx Side */
- for (temp = 0; temp < NR; temp++) {
- p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
- p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
-
- /* GT96100 Owner */
- p->eth_rx_desc[temp].command_status = 0x80000000;
- p->eth_rx_desc[temp].next_desc =
- (struct eth0_rx_desc_struct *)
- &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
- }
-
- FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
- (unsigned int)&p->eth_tx_desc[NR]);
- FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
- (unsigned int)&p->eth_rx_desc[NR]);
-
- GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
- (unsigned int) p->eth_tx_desc);
- GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
- (unsigned int) p->eth_rx_desc);
- GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
- (unsigned int) p->eth_rx_desc);
-
-#ifdef DEBUG
- printf ("\nRx descriptor pointer is %08x %08x\n",
- GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
- GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
- printf ("\n\n%08x %08x\n",
- (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
-
- printf ("Descriptor dump:\n");
- printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
- printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
- printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
- printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
- printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
- printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
- printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
- printf ("%08x\n\n",
- *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
-#endif
-
-#ifdef DEBUG
- gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
-#endif
-
-#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
- {
- unsigned int hashtable_base;
- u8 *b = (u8 *)(wp->enetaddr);
- u32 macH, macL;
-
- /* twist the MAC up into the way the discovery wants it */
- macH= (b[0]<<8) | b[1];
- macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
-
- /* mode 0, size 0x800 */
- hashtable_base =initAddressTable(dev,0,1);
-
- if(!hashtable_base) {
- printf("initAddressTable failed\n");
- return 0;
- }
-
- addAddressTableEntry(dev, macH, macL, 1, 0);
- GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
- hashtable_base);
- }
-#endif
-
- /* Start Rx*/
- GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
- printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
- return 1;
-}
-
-/* enter all the galileo ethernet devs into MULTI-BOOT */
-void
-gt6426x_eth_initialize(bd_t *bis)
-{
- struct eth_device *dev;
- struct eth_dev_s *p;
- int devnum, x, temp;
- char *s, *e, buf[64];
-
-#ifdef DEBUG
- printf( "\n%s\n", __FUNCTION );
-#endif
-
- for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
- dev = calloc(sizeof(*dev), 1);
- if (!dev) {
- printf( "%s: gal_enet%d allocation failure, %s\n",
- __FUNCTION__, devnum, "eth_device structure");
- return;
- }
-
- /* must be less than sizeof(dev->name) */
- sprintf(dev->name, "gal_enet%d", devnum);
-
-#ifdef DEBUG
- printf( "Initializing %s\n", dev->name );
-#endif
-
- /* Extract the MAC address from the environment */
- switch (devnum)
- {
- case 0: s = "ethaddr"; break;
-#if (GAL_ETH_DEVS > 1)
- case 1: s = "eth1addr"; break;
-#endif
-#if (GAL_ETH_DEVS > 2)
- case 2: s = "eth2addr"; break;
-#endif
- default: /* this should never happen */
- printf( "%s: Invalid device number %d\n",
- __FUNCTION__, devnum );
- return;
- }
-
- temp = getenv_f(s, buf, sizeof(buf));
- s = (temp > 0) ? buf : NULL;
-
-#ifdef DEBUG
- printf ("Setting MAC %d to %s\n", devnum, s );
-#endif
- for (x = 0; x < 6; ++x) {
- dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
- if (s)
- s = (*e) ? e+1 : e;
- }
-
- dev->init = (void*)gt6426x_eth_probe;
- dev->halt = (void*)gt6426x_eth_reset;
- dev->send = (void*)gt6426x_eth_transmit;
- dev->recv = (void*)gt6426x_eth_poll;
-
- p = calloc( sizeof(*p), 1 );
- dev->priv = (void*)p;
- if (!p)
- {
- printf( "%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name, "Private Device Structure");
- free(dev);
- return;
- }
-
- p->dev = devnum;
- p->tdn=0;
- p->rdn=0;
- p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
-
- p->eth_tx_desc =
- (eth0_tx_desc_single *)
- (((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
- (NT+1)) & 0xfffffff0) + 0x10);
- if (!p)
- {
- printf( "%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name, "Tx Descriptor");
- free(dev);
- return;
- }
-
- p->eth_rx_desc =
- (eth0_rx_desc_single *)
- (((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
- (NR+1)) & 0xfffffff0) + 0x10);
- if (!p->eth_rx_desc)
- {
- printf( "%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name, "Rx Descriptor");
- free(dev);
- free(p);
- return;
- }
-
- p->eth_tx_buffer =
- (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
- if (!p->eth_tx_buffer)
- {
- printf( "%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name, "Tx Bufffer");
- free(dev);
- free(p);
- free(p->eth_rx_desc);
- return;
- }
-
- for (temp = 0 ; temp < NR ; temp ++) {
- p->eth_rx_buffer[temp] =
- (char *)
- (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
- if (!p->eth_rx_buffer[temp])
- {
- printf( "%s: %s allocation failure, %s\n",
- __FUNCTION__, dev->name, "Rx Buffers");
- free(dev);
- free(p);
- free(p->eth_tx_buffer);
- free(p->eth_rx_desc);
- free(p->eth_tx_desc);
- while (temp >= 0)
- free(p->eth_rx_buffer[--temp]);
- return;
- }
- }
-
-
- eth_register(dev);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- miiphy_register(dev->name,
- gt6426x_miiphy_read, gt6426x_miiphy_write);
-#endif
- }
-
-}
-#endif
diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h
deleted file mode 100644
index 99581f0..0000000
--- a/board/evb64260/eth.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * eth.h - header file for the polled mode GT ethernet driver
- */
-
-#ifndef __GT6426x_ETH_H__
-#define __GT6426x_ETH_H__
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <common.h>
-
-typedef struct eth0_tx_desc_struct {
- volatile __u32 bytecount_reserved;
- volatile __u32 command_status;
- volatile struct eth0_tx_desc_struct * next_desc;
- /* Note - the following will not work for 64 bit addressing */
- volatile unsigned char * buff_pointer;
-} __attribute__ ((packed)) eth0_tx_desc_single;
-
-typedef struct eth0_rx_desc_struct {
- volatile __u32 buff_size_byte_count;
- volatile __u32 command_status;
- volatile struct eth0_rx_desc_struct * next_desc;
- volatile unsigned char * buff_pointer;
-} __attribute__ ((packed)) eth0_rx_desc_single;
-
-#define NT 20 /* Number of Transmit buffers */
-#define NR 20 /* Number of Receive buffers */
-#define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) /* 1600 */
-#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
-
-unsigned long TDN_ETH0 , RDN_ETH0; /* Rx/Tx current Descriptor Number*/
-unsigned int EVB64260_ETH0_irq;
-
-#define CLOSED 0
-#define OPENED 1
-
-#define PORT_ETH0 0
-
-extern eth0_tx_desc_single *eth0_tx_desc;
-extern eth0_rx_desc_single *eth0_rx_desc;
-extern char *eth0_tx_buffer;
-extern char *eth0_rx_buffer[NR];
-extern char *eth_data;
-
-extern int gt6426x_eth_poll(void *v);
-extern int gt6426x_eth_transmit(void *v, char *p, unsigned int s);
-extern void gt6426x_eth_disable(void *v);
-extern int gt6426x_eth_probe(void *v, bd_t *bis);
-
-#endif /* __GT64260x_ETH_H__ */
diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c
deleted file mode 100644
index 8c2c17f..0000000
--- a/board/evb64260/eth_addrtbl.c
+++ /dev/null
@@ -1,218 +0,0 @@
-#include <common.h>
-#include <malloc.h>
-#include <galileo/gt64260R.h>
-#include <galileo/core.h>
-#include <asm/cache.h>
-#include "eth.h"
-#include "eth_addrtbl.h"
-
-#define PRINTF printf
-
-#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
-
-static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, };
-static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, };
-static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, };
-static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, };
-
-static const u32 hashLength[2] = {
- (0x8000), /* 8K * 4 entries */
- (0x8000 / 16), /* 512 * 4 entries */
-};
-
-/* Initialize the address table for a port, if needed */
-unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector)
-{
- unsigned int tableBase;
-
- if (port < 0 || port >= GAL_ETH_DEVS) {
- printf ("%s: Invalid port number %d\n", __FUNCTION__, port);
- return 0;
- }
-
- if (hashMode > 1) {
- printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port);
- return 0;
- }
-
- if (realAddrTableBase[port] &&
- (addressTableHashSize[port] != hashSizeSelector)) {
- /* we have been here before,
- * but now we want a different sized table
- */
- free (realAddrTableBase[port]);
- realAddrTableBase[port] = 0;
- addressTableBase[port] = 0;
-
- }
-
- tableBase = (unsigned int) addressTableBase[port];
- /* we get called for every probe, so only do this once */
- if (!tableBase) {
- int bytes =
- hashLength[hashSizeSelector] * sizeof (addrTblEntry);
-
- realAddrTableBase[port] =
- malloc (bytes + 64);
- tableBase = (unsigned int)realAddrTableBase;
-
- if (!tableBase) {
- printf ("%s: alloc memory failed \n", __FUNCTION__);
- return 0;
- }
-
- /* align to octal byte */
- if (tableBase & 63)
- tableBase = (tableBase + 63) & ~63;
-
- addressTableHashMode[port] = hashMode;
- addressTableHashSize[port] = hashSizeSelector;
- addressTableBase[port] = (addrTblEntry *) tableBase;
-
- memset ((void *) tableBase, 0, bytes);
- }
-
- return tableBase;
-}
-
-/*
- * ----------------------------------------------------------------------------
- * This function will calculate the hash function of the address.
- * depends on the hash mode and hash size.
- * Inputs
- * macH - the 2 most significant bytes of the MAC address.
- * macL - the 4 least significant bytes of the MAC address.
- * hashMode - hash mode 0 or hash mode 1.
- * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800)
- * Outputs
- * return the calculated entry.
- */
-u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
-{
- u32 hashResult;
- u32 addrH;
- u32 addrL;
- u32 addr0;
- u32 addr1;
- u32 addr2;
- u32 addr3;
- u32 addrHSwapped;
- u32 addrLSwapped;
-
-
- addrH = NIBBLE_SWAPPING_16_BIT (macH);
- addrL = NIBBLE_SWAPPING_32_BIT (macL);
-
- addrHSwapped = FLIP_4_BITS (addrH & 0xf)
- + ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4)
- + ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8)
- + ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12);
-
- addrLSwapped = FLIP_4_BITS (addrL & 0xf)
- + ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4)
- + ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8)
- + ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12)
- + ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16)
- + ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20)
- + ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24)
- + ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28);
-
- addrH = addrHSwapped;
- addrL = addrLSwapped;
-
- if (hash_mode == 0) {
- addr0 = (addrL >> 2) & 0x03f;
- addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
- addr2 = (addrL >> 15) & 0x1ff;
- addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
- } else {
- addr0 = FLIP_6_BITS (addrL & 0x03f);
- addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff));
- addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff);
- addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) |
- ((addrH & 0x1) << 8)));
- }
-
- hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
-
- if (HashSize == _8K_TABLE) {
- hashResult = hashResult & 0xffff;
- } else {
- hashResult = hashResult & 0x07ff;
- }
-
- return (hashResult);
-}
-
-
-/*
- * ----------------------------------------------------------------------------
- * This function will add an entry to the address table.
- * depends on the hash mode and hash size that was initialized.
- * Inputs
- * port - ETHERNET port number.
- * macH - the 2 most significant bytes of the MAC address.
- * macL - the 4 least significant bytes of the MAC address.
- * skip - if 1, skip this address.
- * rd - the RD field in the address table.
- * Outputs
- * address table entry is added.
- * true if success.
- * false if table full
- */
-int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
-{
- addrTblEntry *entry;
- u32 newHi;
- u32 newLo;
- u32 i;
-
- newLo = (((macH >> 4) & 0xf) << 15)
- | (((macH >> 0) & 0xf) << 11)
- | (((macH >> 12) & 0xf) << 7)
- | (((macH >> 8) & 0xf) << 3)
- | (((macL >> 20) & 0x1) << 31)
- | (((macL >> 16) & 0xf) << 27)
- | (((macL >> 28) & 0xf) << 23)
- | (((macL >> 24) & 0xf) << 19)
- | (skip << SKIP_BIT) | (rd << 2) | VALID;
-
- newHi = (((macL >> 4) & 0xf) << 15)
- | (((macL >> 0) & 0xf) << 11)
- | (((macL >> 12) & 0xf) << 7)
- | (((macL >> 8) & 0xf) << 3)
- | (((macL >> 21) & 0x7) << 0);
-
- /*
- * Pick the appropriate table, start scanning for free/reusable
- * entries at the index obtained by hashing the specified MAC address
- */
- entry = addressTableBase[port];
- entry += hashTableFunction (macH, macL, addressTableHashSize[port],
- addressTableHashMode[port]);
- for (i = 0; i < HOP_NUMBER; i++, entry++) {
- if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) {
- break;
- } else { /* if same address put in same position */
- if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
- && (entry->hi == newHi)) {
- break;
- }
- }
- }
-
- if (i == HOP_NUMBER) {
- PRINTF ("addGT64260addressTableEntry: table section is full\n");
- return false;
- }
-
- /*
- * Update the selected entry
- */
- entry->hi = newHi;
- entry->lo = newLo;
- DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
- return true;
-}
-
-#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */
diff --git a/board/evb64260/eth_addrtbl.h b/board/evb64260/eth_addrtbl.h
deleted file mode 100644
index 5a62c67..0000000
--- a/board/evb64260/eth_addrtbl.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef _ADDRESS_TABLE_H
-#define _ADDRESS_TABLE_H 1
-
-/*
- * ----------------------------------------------------------------------------
- * addressTable.h - this file has all the declarations of the address table
- */
-
-#define _8K_TABLE 0
-#define ADDRESS_TABLE_ALIGNMENT 8
-#define HASH_DEFAULT_MODE 14
-#define HASH_MODE 13
-#define HASH_SIZE 12
-#define HOP_NUMBER 12
-#define MAC_ADDRESS_STRING_SIZE 12
-#define MAC_ENTRY_SIZE sizeof(addrTblEntry)
-#define MAX_NUMBER_OF_ADDRESSES_TO_STORE 1000
-#define PROMISCUOUS_MODE 0
-#define SKIP 1<<1
-#define SKIP_BIT 1
-#define VALID 1
-
-/*
- * ----------------------------------------------------------------------------
- * XXX_MIKE - potential sign-extension bugs lurk here...
- */
-#define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \
- | (((X) & 0x0f0f0f0f) << 4) )
-
-#define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \
- | (((X) & 0x00000f0f) << 4) )
-
-#define FLIP_4_BITS(X) ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \
- | (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) )
-
-#define FLIP_6_BITS(X) ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \
- | (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \
- | (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) )
-
-#define FLIP_9_BITS(X) ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \
- | (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \
- | (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \
- | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) )
-
-/*
- * V: value we're operating on
- * O: offset of rightmost bit in field
- * W: width of field to shift
- * S: distance to shift left
- */
-#define MASK( fieldWidth ) ((1 << (fieldWidth)) - 1)
-#define leftShiftedBitfield( V,O,W,S) (((V) & (MASK(W) << (O))) << (S))
-#define rightShiftedBitfield(V,O,W,S) (((u32)((V) & (MASK(W) << (O)))) >> (S))
-
-
-/*
- * Push to main memory all cache lines associated with
- * the specified range of virtual memory addresses
- *
- * A: Address of first byte in range to flush
- * N: Number of bytes to flush
- * Note - flush_dcache_range() does a "sync", does NOT invalidate
- */
-#define DCACHE_FLUSH_N_SYNC( A, N ) flush_dcache_range( (A), ((A)+(N)) )
-
-
-typedef struct addressTableEntryStruct {
- u32 hi;
- u32 lo;
-} addrTblEntry;
-
-u32
-uncachedPages( u32 pages );
-u32
-hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode );
-
-unsigned int
-initAddressTable( u32 port, u32 hashMode, u32 hashSize );
-
-int
-addAddressTableEntry( u32 port, u32 macH, u32 macL, u32 rd, u32 skip );
-
-#endif /* #ifndef _ADDRESS_TABLE_H */
diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c
deleted file mode 100644
index 74f8819..0000000
--- a/board/evb64260/evb64260.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * evb64260.c - main board support/init for the Galileo Eval board.
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include <galileo/memory.h>
-#include <galileo/pci.h>
-#include <galileo/gt64260R.h>
-#include <net.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-
-#include <asm/io.h>
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64260.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_ZUMA_V2
-extern void zuma_mbox_init(void);
-#endif
-
-#undef DEBUG
-#define MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/* this is the current GT register space location */
-/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
-
-/* Unfortunately, we cant change it while we are in flash, so we initialize it
- * to the "final" value. This means that any debug_led calls before
- * board_early_init_f wont work right (like in cpu_init_f).
- * See also my_remap_gt_regs below. (NTL)
- */
-
-unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * This is a version of the GT register space remapping function that
- * doesn't touch globals (meaning, it's ok to run from flash.)
- *
- * Unfortunately, this has the side effect that a writable
- * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
- */
-
-void
-my_remap_gt_regs(u32 cur_loc, u32 new_loc)
-{
- u32 temp;
-
- /* check and see if it's already moved */
- temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
- if ((temp & 0xffff) == new_loc >> 20)
- return;
-
- temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
- 0xffff0000) | (new_loc >> 20);
-
- out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
-
- while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
-}
-
-static void
-gt_pci_config(void)
-{
- /* move PCI stuff out of the way - NTL */
- /* map PCI Host 0 */
- pciMapSpace(PCI_HOST0, PCI_REGION0, CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_0_MEM_SPACE, CONFIG_SYS_PCI0_MEM_SIZE);
-
- pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
- pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
- pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
-
- pciMapSpace(PCI_HOST0, PCI_IO, CONFIG_SYS_PCI0_IO_SPACE_PCI,
- CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE);
-
- /* map PCI Host 1 */
- pciMapSpace(PCI_HOST1, PCI_REGION0, CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_0_MEM_SPACE, CONFIG_SYS_PCI1_MEM_SIZE);
-
- pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
- pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
- pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
-
- pciMapSpace(PCI_HOST1, PCI_IO, CONFIG_SYS_PCI1_IO_SPACE_PCI,
- CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE);
-
- /* PCI interface settings */
- GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
- GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
- GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
- GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
-
-
-}
-
-/* Setup CPU interface paramaters */
-static void
-gt_cpu_config(void)
-{
- cpu_t cpu = get_cpu_type();
- ulong tmp;
-
- /* cpu configuration register */
- tmp = GTREGREAD(CPU_CONFIGURATION);
-
- /* set the AACK delay bit
- * see Res#14 */
- tmp |= CPU_CONF_AACK_DELAY;
- tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
-
- /* Galileo claims this is necessary for all busses >= 100 MHz */
- tmp |= CPU_CONF_FAST_CLK;
-
- if (cpu == CPU_750CX) {
- tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
- tmp &= ~CPU_CONF_AP_VALID;
- } else {
- tmp |= CPU_CONF_DP_VALID;
- tmp |= CPU_CONF_AP_VALID;
- }
-
- /* this only works with the MPX bus */
- tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
- tmp |= CPU_CONF_PIPELINE;
- tmp |= CPU_CONF_TA_DELAY;
-
- GT_REG_WRITE(CPU_CONFIGURATION, tmp);
-
- /* CPU master control register */
- tmp = GTREGREAD(CPU_MASTER_CONTROL);
-
- tmp |= CPU_MAST_CTL_ARB_EN;
-
- if ((cpu == CPU_7400) ||
- (cpu == CPU_7410) ||
- (cpu == CPU_7450)) {
-
- tmp |= CPU_MAST_CTL_CLEAN_BLK;
- tmp |= CPU_MAST_CTL_FLUSH_BLK;
-
- } else {
- /* cleanblock must be cleared for CPUs
- * that do not support this command
- * see Res#1 */
- tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
- tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
- }
- GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);
-}
-
-/*
- * board_early_init_f.
- *
- * set up gal. device mappings, etc.
- */
-int board_early_init_f (void)
-{
- uchar sram_boot = 0;
-
- /*
- * set up the GT the way the kernel wants it
- * the call to move the GT register space will obviously
- * fail if it has already been done, but we're going to assume
- * that if it's not at the power-on location, it's where we put
- * it last time. (huber)
- */
- my_remap_gt_regs(CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
-
- gt_pci_config();
-
- /* mask all external interrupt sources */
- GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
- GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
- GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
- GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
- GT_REG_WRITE(CPU_INT_0_MASK, 0);
- GT_REG_WRITE(CPU_INT_1_MASK, 0);
- GT_REG_WRITE(CPU_INT_2_MASK, 0);
- GT_REG_WRITE(CPU_INT_3_MASK, 0);
-
- /* now, onto the configuration */
- GT_REG_WRITE(SDRAM_CONFIGURATION, CONFIG_SYS_SDRAM_CONFIG);
-
- /* ----- DEVICE BUS SETTINGS ------ */
-
- /*
- * EVB
- * 0 - SRAM
- * 1 - RTC
- * 2 - UART
- * 3 - Flash
- * boot - BootCS
- *
- * Zuma
- * 0 - Flash
- * boot - BootCS
- */
-
- /*
- * the dual 7450 module requires burst access to the boot
- * device, so the serial rom copies the boot device to the
- * on-board sram on the eval board, and updates the correct
- * registers to boot from the sram. (device0)
- */
-#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
- /* Zuma has no SRAM */
- sram_boot = 0;
-#else
- if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CONFIG_SYS_MONITOR_BASE)
- sram_boot = 1;
-#endif
-
- memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
-
- memoryMapDeviceSpace(DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
- memoryMapDeviceSpace(DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
- memoryMapDeviceSpace(DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
-
- /* configure device timing */
-#ifdef CONFIG_SYS_DEV0_PAR
- if (!sram_boot)
- GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
-#endif
-
-#ifdef CONFIG_SYS_DEV1_PAR
- GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
-#endif
-#ifdef CONFIG_SYS_DEV2_PAR
- GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
-#endif
-
-#ifdef CONFIG_EVB64260
-#ifdef CONFIG_SYS_32BIT_BOOT_PAR
- /* detect if we are booting from the 32 bit flash */
- if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
- /* 32 bit boot flash */
- GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
- GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
- } else {
- /* 8 bit boot flash */
- GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
- GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
- }
-#else
- /* 8 bit boot flash only */
- GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
-#endif
-#else /* CONFIG_EVB64260 not defined */
- /* We are booting from 16-bit flash.
- */
- GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_16BIT_BOOT_PAR);
-#endif
-
- gt_cpu_config();
-
- /* MPP setup */
- GT_REG_WRITE(MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
- GT_REG_WRITE(MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
- GT_REG_WRITE(MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
- GT_REG_WRITE(MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
-
- GT_REG_WRITE(GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
- GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CONFIG_SYS_SERIAL_PORT_MUX);
-
- return 0;
-}
-
-/* various things to do after relocation */
-
-int misc_init_r (void)
-{
- icache_enable();
-#ifdef CONFIG_SYS_L2
- l2cache_enable();
-#endif
-
-#ifdef CONFIG_MPSC
- mpsc_init2();
-#endif
-
-#ifdef CONFIG_ZUMA_V2
- zuma_mbox_init();
-#endif
- return (0);
-}
-
-void
-after_reloc(ulong dest_addr)
-{
- /* check to see if we booted from the sram. If so, move things
- * back to the way they should be. (we're running from main
- * memory at this point now */
-
- if (memoryGetDeviceBaseAddress(DEVICE0) == CONFIG_SYS_MONITOR_BASE) {
- memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
- memoryMapDeviceSpace(BOOT_DEVICE, CONFIG_SYS_FLASH_BASE, _1M);
- }
-
- /* now, jump to the main U-Boot board init code */
- board_init_r ((gd_t *)gd, dest_addr);
-
- /* NOTREACHED */
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int
-checkboard (void)
-{
- puts ("Board: " CONFIG_SYS_BOARD_NAME "\n");
- return (0);
-}
-
-/* utility functions */
-void
-debug_led(int led, int mode)
-{
-#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
- volatile int *addr = NULL;
- __maybe_unused int dummy;
-
- if (mode == 1) {
- switch (led) {
- case 0:
- addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x08000);
- break;
-
- case 1:
- addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x0c000);
- break;
-
- case 2:
- addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x10000);
- break;
- }
- } else if (mode == 0) {
- switch (led) {
- case 0:
- addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x14000);
- break;
-
- case 1:
- addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x18000);
- break;
-
- case 2:
- addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x1c000);
- break;
- }
- }
- WRITE_CHAR(addr, 0);
- dummy = *addr;
-#endif /* CONFIG_ZUMA_V2 */
-}
-
-void
-display_mem_map(void)
-{
- int i,j;
- unsigned int base,size,width;
- /* SDRAM */
- printf("SDRAM\n");
- for(i=0;i<=BANK3;i++) {
- base = memoryGetBankBaseAddress(i);
- size = memoryGetBankSize(i);
- if(size !=0)
- {
- printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20);
- }
- }
-
- /* CPU's PCI windows */
- for(i=0;i<=PCI_HOST1;i++) {
- printf("\nCPU's PCI %d windows\n", i);
- base=pciGetSpaceBase(i,PCI_IO);
- size=pciGetSpaceSize(i,PCI_IO);
- printf(" IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20);
- for(j=0;j<=PCI_REGION3;j++) {
- base = pciGetSpaceBase(i,j);
- size = pciGetSpaceSize(i,j);
- printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base,
- size>>20);
- }
- }
-
- /* Devices */
- printf("\nDEVICES\n");
- for(i=0;i<=DEVICE3;i++) {
- base = memoryGetDeviceBaseAddress(i);
- size = memoryGetDeviceSize(i);
- width= memoryGetDeviceWidth(i) * 8;
- printf("DEV %d: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
- i, base, size>>20, width);
- }
-
- /* Bootrom */
- base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
- size = memoryGetDeviceSize(BOOT_DEVICE);
- width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
- printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
- base, size>>20, width);
-}
-
-int board_eth_init(bd_t *bis)
-{
- gt6426x_eth_initialize(bis);
- return 0;
-}
diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c
deleted file mode 100644
index f3b0074..0000000
--- a/board/evb64260/flash.c
+++ /dev/null
@@ -1,837 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * flash.c - flash support for the 512k, 8bit boot flash on the GEVB
- * most of this file was based on the existing U-Boot
- * flash drivers.
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <galileo/gt64260R.h>
-#include <galileo/memory.h>
-#include "intel_flash.h"
-
-#define FLASH_ROM 0xFFFD /* unknown flash type */
-#define FLASH_RAM 0xFFFE /* unknown flash type */
-#define FLASH_MAN_UNKNOWN 0xFFFF0000
-
-/* #define DEBUG */
-/* #define FLASH_ID_OVERRIDE */ /* Hack to set type to 040B if ROM emulator is installed.
- * Can be used to program a ROM in circuit if a programmer
- * is not available by swapping the rom out. */
-
-/* Intel flash commands */
-int flash_erase_intel(flash_info_t *info, int s_first, int s_last);
-int write_word_intel(bank_addr_t addr, bank_word_t value);
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long
-flash_init (void)
-{
- unsigned int i;
- unsigned long size_b0 = 0, size_b1 = 0;
- unsigned long base, flash_size;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* the boot flash */
- base = CONFIG_SYS_FLASH_BASE;
-#ifndef CONFIG_SYS_BOOT_FLASH_WIDTH
-#define CONFIG_SYS_BOOT_FLASH_WIDTH 1
-#endif
- size_b0 = flash_get_size(CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *)base,
- &flash_info[0]);
-
-#ifndef CONFIG_P3G4
- printf("[");
- print_size (size_b0, "");
- printf("@%08lX] ", base);
-#endif
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
- base, size_b0, size_b0<<20);
- }
-
- base = memoryGetDeviceBaseAddress(CONFIG_SYS_EXTRA_FLASH_DEVICE);
- for(i=1;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) {
- unsigned long size = flash_get_size(CONFIG_SYS_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]);
-
-#ifndef CONFIG_P3G4
- printf("[");
- print_size (size, "");
- printf("@%08lX] ", base);
-#endif
-
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- if(i==1) {
- printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
- base, size_b1, size_b1<<20);
- }
- break;
- }
- size_b1+=size;
- base+=size;
- }
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
- flash_size = size_b0 + size_b1;
- return flash_size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void
-flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
- int sector_size;
-
- if(!info->sector_count) return;
-
- /* set up sector start address table */
- switch(info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- case FLASH_28F128J3A:
- case FLASH_28F640J3A:
- case FLASH_RAM:
- /* this chip has uniformly spaced sectors */
- sector_size=info->size/info->sector_count;
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * sector_size);
- break;
- default:
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-flash_info_t *flash_get_info(ulong base)
-{
- int i;
- flash_info_t * info;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
- info = & flash_info[i];
- if (info->start[0] <= base && base <= info->start[0] + info->size - 1)
- break;
- }
-
- return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-void
-flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf ("AM29LV040B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400B:
- printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_28F640J3A:
- printf ("28F640J3A (64 Mbit)\n");
- break;
- case FLASH_28F128J3A:
- printf ("28F128J3A (128 Mbit)\n");
- break;
- case FLASH_ROM:
- printf ("ROM\n");
- break;
- case FLASH_RAM:
- printf ("RAM\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- puts (" Size: ");
- print_size (info->size, "");
- printf (" in %d Sectors\n", info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static inline void flash_cmd(int width, volatile unsigned char *addr, int offset, unsigned char cmd)
-{
- /* supports 1x8, 1x16, and 2x16 */
- /* 2x8 and 4x8 are not supported */
- if(width==4) {
- /* assuming chips are in 16 bit mode */
- /* 2x16 */
- unsigned long cmd32=(cmd<<16)|cmd;
- *(volatile unsigned long *)(addr+offset*2)=cmd32;
- } else if (width == 2) {
- /* 1x16 */
- *(volatile unsigned short *)((unsigned short*)addr+offset)=cmd;
- } else {
- /* 1x8 */
- *(volatile unsigned char *)(addr+offset)=cmd;
- }
-}
-
-static ulong
-flash_get_size (int portwidth, vu_long *addr, flash_info_t *info)
-{
- short i;
- volatile unsigned char *caddr = (unsigned char *)addr;
- volatile unsigned short *saddr = (unsigned short *)addr;
- volatile unsigned long *laddr = (unsigned long *)addr;
- char old[2], save;
- ulong id, manu, base = (ulong)addr;
-
- info->portwidth=portwidth;
-
- save = *caddr;
-
- flash_cmd(portwidth,caddr,0,0xf0);
- flash_cmd(portwidth,caddr,0,0xf0);
-
- udelay(10);
-
- old[0] = caddr[0];
- old[1] = caddr[1];
-
-
- if(old[0]!=0xf0) {
- flash_cmd(portwidth,caddr,0,0xf0);
- flash_cmd(portwidth,caddr,0,0xf0);
-
- udelay(10);
-
- if(*caddr==0xf0) {
- /* this area is ROM */
- *caddr=save;
-#ifndef FLASH_ID_OVERRIDE
- info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
- info->sector_count = 8;
- info->size = 0x80000;
-#else
- info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x80000;
- info->chipwidth=1;
-#endif
- flash_get_offsets(base, info);
- return info->size;
- }
- } else {
- *caddr=0;
-
- udelay(10);
-
- if(*caddr==0) {
- /* this area is RAM */
- *caddr=save;
- info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN;
- info->sector_count = 8;
- info->size = 0x80000;
- flash_get_offsets(base, info);
- return info->size;
- }
- flash_cmd(portwidth,caddr,0,0xf0);
-
- udelay(10);
- }
-
- /* Write auto select command: read Manufacturer ID */
- flash_cmd(portwidth,caddr,0x555,0xAA);
- flash_cmd(portwidth,caddr,0x2AA,0x55);
- flash_cmd(portwidth,caddr,0x555,0x90);
-
- udelay(10);
-
- if ((caddr[0] == old[0]) &&
- (caddr[1] == old[1])) {
-
- /* this area is ROM */
-#ifndef FLASH_ID_OVERRIDE
- info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
- info->sector_count = 8;
- info->size = 0x80000;
-#else
- info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x80000;
- info->chipwidth=1;
-#endif
- flash_get_offsets(base, info);
- return info->size;
-#ifdef DEBUG
- } else {
- printf("%px%d: %02x:%02x -> %02x:%02x\n",
- caddr, portwidth, old[0], old[1],
- caddr[0], caddr[1]);
-#endif
- }
-
- switch(portwidth) {
- case 1:
- manu = caddr[0];
- manu |= manu<<16;
- id = caddr[1];
- break;
- case 2:
- manu = saddr[0];
- manu |= manu<<16;
- id = saddr[1];
- id |= id<<16;
- break;
- case 4:
- manu = laddr[0];
- id = laddr[1];
- break;
- default:
- id = manu = -1;
- break;
- }
-
-#ifdef DEBUG
- printf("\n%08lx:%08lx:%08lx\n", base, manu, id);
- printf("%08lx %08lx %08lx %08lx\n",
- laddr[0],laddr[1],laddr[2],laddr[3]);
-#endif
-
- switch (manu) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- printf("Unknown Mfr [%08lx]:%08lx\n", manu, id);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- switch (id) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- info->chipwidth=1;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- info->chipwidth=1;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- info->chipwidth=1;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- info->chipwidth=1;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- info->chipwidth=1;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- info->chipwidth=1;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- case AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x80000;
- info->chipwidth=1;
- break;
-
- case INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */
- info->chipwidth=2;
- if(portwidth==4) info->size*=2; /* 2x16 */
- break;
-
- case INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */
- info->chipwidth=2;
- if(portwidth==4) info->size*=2; /* 2x16 */
- break;
-
- default:
- printf("Unknown id %lx:[%lx]\n", manu, id);
- info->flash_id = FLASH_UNKNOWN;
- info->chipwidth=1;
- return (0); /* => no or unknown flash */
-
- }
-
- flash_get_offsets(base, info);
-
-#if 0
- /* set up sector start address table */
- if (info->flash_id & FLASH_AM040) {
- /* this chip has uniformly spaced sectors */
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
-
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-#endif
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0)=0x02 */
- /* D0 = 1 if protected */
- caddr = (volatile unsigned char *)(info->start[i]);
- saddr = (volatile unsigned short *)(info->start[i]);
- laddr = (volatile unsigned long *)(info->start[i]);
- if(portwidth==1)
- info->protect[i] = caddr[2] & 1;
- else if(portwidth==2)
- info->protect[i] = saddr[2] & 1;
- else
- info->protect[i] = laddr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (volatile unsigned char *)info->start[0];
-
- flash_cmd(portwidth,caddr,0,0xF0); /* reset bank */
- }
-
- return (info->size);
-}
-
-/* TODO: 2x16 unsupported */
-int
-flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile unsigned char *addr = (uchar *)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- /* TODO: 2x16 unsupported */
- if(info->portwidth==4) return 1;
-
- if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
- if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
- for (sect = s_first; sect<=s_last; sect++) {
- int sector_size=info->size/info->sector_count;
- addr = (uchar *)(info->start[sect]);
- memset((void *)addr, 0, sector_size);
- }
- return 0;
- }
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- return flash_erase_intel(info,
- (unsigned short)s_first,
- (unsigned short)s_last);
- }
-
-#if 0
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-#endif
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- flash_cmd(info->portwidth,addr,0x555,0xAA);
- flash_cmd(info->portwidth,addr,0x2AA,0x55);
- flash_cmd(info->portwidth,addr,0x555,0x80);
- flash_cmd(info->portwidth,addr,0x555,0xAA);
- flash_cmd(info->portwidth,addr,0x2AA,0x55);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (uchar *)(info->start[sect]);
- flash_cmd(info->portwidth,addr,0,0x30);
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (volatile unsigned char *)(info->start[l_sect]);
- /* broken for 2x16: TODO */
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned char *)info->start[0];
- flash_cmd(info->portwidth,addr,0,0xf0);
- flash_cmd(info->portwidth,addr,0,0xf0);
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-/* broken for 2x16: TODO */
-int
-write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- if(info->portwidth==4) return 1;
-
- if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0;
- if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
- memcpy((void *)addr, src, cnt);
- return 0;
- }
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-/* broken for 2x16: TODO */
-static int
-write_word (flash_info_t *info, ulong dest, ulong data)
-{
- volatile unsigned char *addr = (uchar *)(info->start[0]);
- ulong start;
- int flag, i;
-
- if(info->portwidth==4) return 1;
-
- if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
- if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
- *(unsigned long *)dest=data;
- return 0;
- }
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- unsigned short low = data & 0xffff;
- unsigned short hi = (data >> 16) & 0xffff;
- int ret = write_word_intel((bank_addr_t)dest, hi);
-
- if (!ret) ret = write_word_intel((bank_addr_t)(dest+2), low);
-
- return ret;
- }
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* first, perform an unlock bypass command to speed up flash writes */
- addr[0x555] = 0xAA;
- addr[0x2AA] = 0x55;
- addr[0x555] = 0x20;
-
- /* write each byte out */
- for (i = 0; i < 4; i++) {
- char *data_ch = (char *)&data;
- addr[0] = 0xA0;
- *(((char *)dest)+i) = data_ch[i];
- udelay(10); /* XXX */
- }
-
- /* we're done, now do an unlock bypass reset */
- addr[0] = 0x90;
- addr[0] = 0x00;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c
deleted file mode 100644
index 8119fce..0000000
--- a/board/evb64260/i2c.c
+++ /dev/null
@@ -1,310 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <malloc.h>
-#include <galileo/gt64260R.h>
-#include <galileo/core.h>
-
-#define MAX_I2C_RETRYS 10
-#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */
-#undef DEBUG_I2C
-
-#ifdef DEBUG_I2C
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-/* Assuming that there is only one master on the bus (us) */
-
-static void
-i2c_init(int speed, int slaveaddr)
-{
- unsigned int n, m, freq, margin, power;
- unsigned int actualn = 0, actualm = 0;
- unsigned int control, status;
- unsigned int minmargin = 0xffffffff;
- unsigned int tclk = 125000000;
-
- DP(puts("i2c_init\n"));
-
- for (n = 0 ; n < 8 ; n++) {
- for (m = 0 ; m < 16 ; m++) {
- power = 2 << n; /* power = 2^(n+1) */
- freq = tclk / (10 * (m + 1) * power);
- if (speed > freq)
- margin = speed - freq;
- else
- margin = freq - speed;
- if (margin < minmargin) {
- minmargin = margin;
- actualn = n;
- actualm = m;
- }
- }
- }
-
- DP(puts("setup i2c bus\n"));
-
- /* Setup bus */
-
- GT_REG_WRITE(I2C_SOFT_RESET, 0);
-
- DP(puts("udelay...\n"));
-
- udelay(I2C_DELAY);
-
- DP(puts("set baudrate\n"));
-
- GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualm << 3) | actualn);
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
-
- udelay(I2C_DELAY * 10);
-
- DP(puts("read control, baudrate\n"));
-
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
- GT_REG_READ(I2C_CONTROL, &control);
-}
-
-static uchar
-i2c_start(void)
-{
- unsigned int control, status;
- int count = 0;
-
- DP(puts("i2c_start\n"));
-
- /* Set the start bit */
-
- GT_REG_READ(I2C_CONTROL, &control);
- control |= (0x1 << 5);
- GT_REG_WRITE(I2C_CONTROL, control);
-
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
-
- count = 0;
- while ((status & 0xff) != 0x08) {
- udelay(I2C_DELAY);
- if (count > 20) {
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
- return status;
- }
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
-
- return 0;
-}
-
-static uchar
-i2c_select_device(uchar dev_addr, uchar read, int ten_bit)
-{
- unsigned int status, data, bits = 7;
- int count = 0;
-
- DP(puts("i2c_select_device\n"));
-
- /* Output slave address */
-
- if (ten_bit)
- bits = 10;
-
- data = (dev_addr << 1);
- /* set the read bit */
- data |= read;
- GT_REG_WRITE(I2C_DATA, data);
- /* assert the address */
- RESET_REG_BITS(I2C_CONTROL, BIT3);
-
- udelay(I2C_DELAY);
-
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
- count = 0;
- while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
- udelay(I2C_DELAY);
- if (count > 20) {
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
- return status;
- }
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
-
- if (bits == 10) {
- printf("10 bit I2C addressing not yet implemented\n");
- return 0xff;
- }
-
- return 0;
-}
-
-static uchar
-i2c_get_data(uchar *return_data, int len) {
-
- unsigned int data, status = 0;
- int count = 0;
-
- DP(puts("i2c_get_data\n"));
-
- while (len) {
-
- /* Get and return the data */
-
- RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
-
- udelay(I2C_DELAY * 5);
-
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
- count++;
- while ((status & 0xff) != 0x50) {
- udelay(I2C_DELAY);
- if (count > 2) {
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
- return 0;
- }
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- GT_REG_READ(I2C_DATA, &data);
- len--;
- *return_data = (uchar)data;
- return_data++;
- }
- RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3);
- while ((status & 0xff) != 0x58) {
- udelay(I2C_DELAY);
- if (count > 200) {
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
- return status;
- }
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */
-
- return 0;
-}
-
-static uchar
-i2c_write_data(unsigned int data, int len)
-{
- unsigned int status;
- int count = 0;
-
- DP(puts("i2c_write_data\n"));
-
- if (len > 4)
- return -1;
-
- while (len) {
- /* Set and assert the data */
-
- GT_REG_WRITE(I2C_DATA, (unsigned int)data);
- RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
-
- udelay(I2C_DELAY);
-
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
- count++;
- while ((status & 0xff) != 0x28) {
- udelay(I2C_DELAY);
- if (count > 20) {
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
- return status;
- }
- GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
- count++;
- }
- len--;
- }
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
- GT_REG_WRITE(I2C_CONTROL, (0x1 << 4));
-
- udelay(I2C_DELAY * 10);
-
- return 0;
-}
-
-static uchar
-i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit)
-{
- uchar status;
-
- DP(puts("i2c_set_dev_offset\n"));
-
- status = i2c_select_device(dev_addr, 0, ten_bit);
- if (status) {
-#ifdef DEBUG_I2C
- printf("Failed to select device setting offset: 0x%02x\n",
- status);
-#endif
- return status;
- }
-
- status = i2c_write_data(offset, 1);
- if (status) {
-#ifdef DEBUG_I2C
- printf("Failed to write data: 0x%02x\n", status);
-#endif
- return status;
- }
-
- return 0;
-}
-
-uchar
-i2c_read(uchar dev_addr, unsigned int offset, int len, uchar *data,
- int ten_bit)
-{
- uchar status = 0;
- unsigned int i2cfreq = 400000;
-
- DP(puts("i2c_read\n"));
-
- i2c_init(i2cfreq, 0);
-
- status = i2c_start();
-
- if (status) {
-#ifdef DEBUG_I2C
- printf("Transaction start failed: 0x%02x\n", status);
-#endif
- return status;
- }
-
- status = i2c_set_dev_offset(dev_addr, 0, 0);
- if (status) {
-#ifdef DEBUG_I2C
- printf("Failed to set offset: 0x%02x\n", status);
-#endif
- return status;
- }
-
- i2c_init(i2cfreq, 0);
-
- status = i2c_start();
- if (status) {
-#ifdef DEBUG_I2C
- printf("Transaction restart failed: 0x%02x\n", status);
-#endif
- return status;
- }
-
- status = i2c_select_device(dev_addr, 1, ten_bit);
- if (status) {
-#ifdef DEBUG_I2C
- printf("Address not acknowledged: 0x%02x\n", status);
-#endif
- return status;
- }
-
- status = i2c_get_data(data, len);
- if (status) {
-#ifdef DEBUG_I2C
- printf("Data not received: 0x%02x\n", status);
-#endif
- return status;
- }
-
- return 0;
-}
diff --git a/board/evb64260/i2c.h b/board/evb64260/i2c.h
deleted file mode 100644
index 9c21992..0000000
--- a/board/evb64260/i2c.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __I2C_H__
-#define __I2C_H__
-
-/* function declarations */
-uchar i2c_read(uchar, unsigned int, int, uchar*, int);
-
-#endif
diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c
deleted file mode 100644
index 9acc3a0..0000000
--- a/board/evb64260/intel_flash.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <galileo/gt64260R.h>
-#include <galileo/memory.h>
-#include "intel_flash.h"
-
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET 0x01
-#define FLAG_PROTECT_CLEAR 0x02
-
-static void
-bank_reset(flash_info_t *info, int sect)
-{
- bank_addr_t addrw, eaddrw;
-
- addrw = (bank_addr_t)info->start[sect];
- eaddrw = BANK_ADDR_NEXT_WORD(addrw);
-
- while (addrw < eaddrw) {
-#ifdef FLASH_DEBUG
- printf(" writing reset cmd to addr 0x%08lx\n",
- (unsigned long)addrw);
-#endif
- *addrw = BANK_CMD_RST;
- addrw++;
- }
-}
-
-static void
-bank_erase_init(flash_info_t *info, int sect)
-{
- bank_addr_t addrw, saddrw, eaddrw;
- int flag;
-
-#ifdef FLASH_DEBUG
- printf("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
- printf("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
- printf("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
- printf("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
- printf("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
- printf("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
- printf("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
-#endif
-
- saddrw = (bank_addr_t)info->start[sect];
- eaddrw = BANK_ADDR_NEXT_WORD(saddrw);
-
-#ifdef FLASH_DEBUG
- printf("erasing sector %d, start addr = 0x%08lx "
- "(bank next word addr = 0x%08lx)\n", sect,
- (unsigned long)saddrw, (unsigned long)eaddrw);
-#endif
-
- /* Disable intrs which might cause a timeout here */
- flag = disable_interrupts();
-
- for (addrw = saddrw; addrw < eaddrw; addrw++) {
-#ifdef FLASH_DEBUG
- printf(" writing erase cmd to addr 0x%08lx\n",
- (unsigned long)addrw);
-#endif
- *addrw = BANK_CMD_ERASE1;
- *addrw = BANK_CMD_ERASE2;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-}
-
-static int
-bank_erase_poll(flash_info_t *info, int sect)
-{
- bank_addr_t addrw, saddrw, eaddrw;
- int sectdone, haderr;
-
- saddrw = (bank_addr_t)info->start[sect];
- eaddrw = BANK_ADDR_NEXT_WORD(saddrw);
-
- sectdone = 1;
- haderr = 0;
-
- for (addrw = saddrw; addrw < eaddrw; addrw++) {
- bank_word_t stat = *addrw;
-
-#ifdef FLASH_DEBUG
- printf(" checking status at addr "
- "0x%08x [0x%08x]\n",
- (unsigned long)addrw, stat);
-#endif
- if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
- sectdone = 0;
- else if ((stat & BANK_STAT_ERR) != 0) {
- printf(" failed on sector %d "
- "(stat = 0x%08x) at "
- "address 0x%p\n",
- sect, stat, addrw);
- *addrw = BANK_CMD_CLR_STAT;
- haderr = 1;
- }
- }
-
- if (haderr)
- return (-1);
- else
- return (sectdone);
-}
-
-int
-write_word_intel(bank_addr_t addr, bank_word_t value)
-{
- bank_word_t stat;
- ulong start;
- int flag, retval;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = BANK_CMD_PROG;
-
- *addr = value;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- retval = 0;
-
- /* data polling for D7 */
- start = get_timer (0);
- do {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- retval = 1;
- goto done;
- }
- stat = *addr;
- } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
-
- if ((stat & BANK_STAT_ERR) != 0) {
- printf("flash program failed (stat = 0x%08lx) "
- "at address 0x%08lx\n", (ulong)stat, (ulong)addr);
- *addr = BANK_CMD_CLR_STAT;
- retval = 3;
- }
-
-done:
- /* reset to read mode */
- *addr = BANK_CMD_RST;
-
- return (retval);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int
-flash_erase_intel(flash_info_t *info, int s_first, int s_last)
-{
- int prot, sect, haderr;
- ulong start, now, last;
-
-#ifdef FLASH_DEBUG
- printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
- " Bank # %d: ", s_last - s_first + 1, s_first, s_last,
- (info - flash_info) + 1);
- flash_print_info(info);
-#endif
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sector%s will not be erased!\n",
- prot, (prot > 1 ? "s" : ""));
- }
-
- start = get_timer (0);
- last = 0;
- haderr = 0;
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- ulong estart;
- int sectdone;
-
- bank_erase_init(info, sect);
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- estart = get_timer(start);
-
- do {
- now = get_timer(start);
-
- if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout (sect %d)\n", sect);
- haderr = 1;
- break;
- }
-
-#ifndef FLASH_DEBUG
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
-#endif
-
- sectdone = bank_erase_poll(info, sect);
-
- if (sectdone < 0) {
- haderr = 1;
- break;
- }
-
- } while (!sectdone);
-
- if (haderr)
- break;
- }
- }
-
- if (haderr > 0)
- printf (" failed\n");
- else
- printf (" done\n");
-
- /* reset to read mode */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- bank_reset(info, sect);
- }
- }
- return haderr;
-}
diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h
deleted file mode 100644
index cc3a339..0000000
--- a/board/evb64260/intel_flash.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
-
-/*
- * acceptable chips types are:
- *
- * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
- */
-
-/* register addresses, valid only following an CHIP_CMD_RD_ID command */
-#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
-#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
-#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
-#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
-
-/* Commands */
-#define CHIP_CMD_RST 0xFF /* reset flash */
-#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
-#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
-#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
-#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
-#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
-#define CHIP_CMD_PROG 0x40 /* program word command */
-#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
-#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
-#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
-#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
-#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
-#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
-#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
-
-/* status register bits */
-#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
-#define CHIP_STAT_VPPS 0x08 /* VPP Status */
-#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
-#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
-#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
-#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
-
-#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
- CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
-
-/* ID and Lock Configuration */
-#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
-#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID
-
-/* dimensions */
-#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
-#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
-#define CHIP_NBLOCKS 128
-#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
-#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
-
-/********************** DEFINES for Hymod Flash ******************************/
-
-/*
- * The hymod board has 2 x 28F320J5 chips running in
- * 16 bit mode, for a 32 bit wide bank.
- */
-
-typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
-typedef volatile bank_word_t *bank_addr_t;
-typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
-
-#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
-#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
-
-#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
-#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
-#define BANK_NBLOCKS CHIP_NBLOCKS
-#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
-#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
-
-#define MAX_BANKS 1 /* only one bank possible */
-
-/* align bank addresses and sizes to bank word boundaries */
-#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_WIDTH - 1)))
-#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
- (bank_size_t)(s) + (BANK_WIDTH - 1)))
-
-/* align bank addresses and sizes to bank block boundaries */
-#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_BLKSZ - 1)))
-#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
- (bank_size_t)(s) + (BANK_BLKSZ - 1)))
-
-/* align bank addresses and sizes to bank boundaries */
-#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
- & ~(BANK_SIZE - 1)))
-#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
- (bank_size_t)(s) + (BANK_SIZE - 1)))
-
-/* add an offset to a bank address */
-#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
- (bank_size_t)(o))
-
-/* get base address of bank b, given flash base address a */
-#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- (bank_size_t)(b) * BANK_SIZE)
-
-/* adjust a bank address to start of next word, block or bank */
-#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
- BANK_WIDTH)
-#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
- BANK_BLKSZ)
-#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- BANK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
- ((bank_size_t)(r) << BANK_WSHIFT))
-
-/* make a bank address for each chip register address */
-
-#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
-#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
-#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
-#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the bank_word_t type, and take into account the
- * chip width and bank layout
- */
-
-#define BANK_FILL_WORD(o) ((bank_word_t)(o))
-
-/* make a bank word value for each chip cmd/stat/rd value */
-
-/* Commands */
-#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
-#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
-#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
-#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
-#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
-#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
-#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
-#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
-#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
-#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
-#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
-#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
-#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
-#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
-#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
-#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
-#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
-
-#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
-#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
-#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/evb64260/local.h b/board/evb64260/local.h
deleted file mode 100644
index 8a3f4b2..0000000
--- a/board/evb64260/local.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * include/local.h - local configuration options, board specific
- */
-
-#ifndef __LOCAL_H
-#define __LOCAL_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* This tells U-Boot that the config options are compiled in */
-/* #undef ENV_IS_EMBEDDED */
-/* Don't touch this! U-Boot figures this out based on other
- * magic. */
-
-/* Uncomment and define any of the below options */
-
-/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
- /* Note: If you defined CONFIG_EVB64260_750CX this */
- /* gets defined automatically. */
-
-/* These want string arguments */
-/* #define CONFIG_BOOTARGS */
-/* #define CONFIG_BOOTCOMMAND */
-/* #define CONFIG_RAMBOOTCOMMAND */
-/* #define CONFIG_NFSBOOTCOMMAND */
-/* #define CONFIG_SYS_AUTOLOAD */
-/* #define CONFIG_PREBOOT */
-
-/* These don't */
-
-/* #define CONFIG_BOOTDELAY */
-/* #define CONFIG_BAUDRATE */
-/* #define CONFIG_LOADS_ECHO */
-/* #define CONFIG_ETHADDR */
-/* #define CONFIG_ETH2ADDR */
-/* #define CONFIG_ETH3ADDR */
-/* #define CONFIG_IPADDR */
-/* #define CONFIG_SERVERIP */
-/* #define CONFIG_ROOTPATH */
-/* #define CONFIG_GATEWAYIP */
-/* #define CONFIG_NETMASK */
-/* #define CONFIG_HOSTNAME */
-/* #define CONFIG_BOOTFILE */
-/* #define CONFIG_LOADADDR */
-
-/* these hardware addresses are pretty bogus, please change them to
- suit your needs */
-
-/* first ethernet */
-#define CONFIG_ETHADDR 00:11:22:33:44:55
-
-/* next two ethernet hwaddrs */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:11:22:33:44:66
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:11:22:33:44:77
-
-#define CONFIG_ENV_OVERWRITE
-#endif /* __CONFIG_H */
diff --git a/board/evb64260/memory.c b/board/evb64260/memory.c
deleted file mode 100644
index e339854..0000000
--- a/board/evb64260/memory.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/* Memory.c - Memory mappings and remapping functions */
-
-/* Copyright - Galileo technology. */
-
-/* modified by Josh Huber to clean some things up, and
- * fit it into the U-Boot framework */
-
-#include <galileo/core.h>
-#include <galileo/memory.h>
-
-/********************************************************************
-* memoryGetBankBaseAddress - Gets the base address of a memory bank
-* - If the memory bank size is 0 then this base address has no meaning!!!
-*
-*
-* INPUTS: MEMORY_BANK bank - The bank we ask for its base Address.
-* OUTPUT: N/A
-* RETURNS: Memory bank base address.
-*********************************************************************/
-static unsigned long memoryGetBankRegOffset(MEMORY_BANK bank)
-{
- switch (bank)
- {
- case BANK0:
- return SCS_0_LOW_DECODE_ADDRESS;
- case BANK1:
- return SCS_1_LOW_DECODE_ADDRESS;
- case BANK2:
- return SCS_2_LOW_DECODE_ADDRESS;
- case BANK3:
- return SCS_3_LOW_DECODE_ADDRESS;
- }
- return SCS_0_LOW_DECODE_ADDRESS; /* default value */
-}
-
-unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank)
-{
- unsigned int base;
- unsigned int regOffset=memoryGetBankRegOffset(bank);
-
- GT_REG_READ(regOffset,&base);
- base = base << 20;
- return base;
-}
-
-/********************************************************************
-* memoryGetDeviceBaseAddress - Gets the base address of a device.
-* - If the device size is 0 then this base address has no meaning!!!
-*
-*
-* INPUT: DEVICE device - The device we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: Device base address.
-*********************************************************************/
-static unsigned int memoryGetDeviceRegOffset(DEVICE device)
-{
- switch (device)
- {
- case DEVICE0:
- return CS_0_LOW_DECODE_ADDRESS;
- case DEVICE1:
- return CS_1_LOW_DECODE_ADDRESS;
- case DEVICE2:
- return CS_2_LOW_DECODE_ADDRESS;
- case DEVICE3:
- return CS_3_LOW_DECODE_ADDRESS;
- case BOOT_DEVICE:
- return BOOTCS_LOW_DECODE_ADDRESS;
- }
- return CS_0_LOW_DECODE_ADDRESS; /* default value */
-}
-
-unsigned int memoryGetDeviceBaseAddress(DEVICE device)
-{
- unsigned int regBase;
- unsigned int regEnd;
- unsigned int regOffset=memoryGetDeviceRegOffset(device);
-
- GT_REG_READ(regOffset, ®Base);
- GT_REG_READ(regOffset+8, ®End);
-
- if(regEnd<=regBase) return 0xffffffff; /* ERROR !!! */
-
- regBase = regBase << 20;
- return regBase;
-}
-
-/********************************************************************
-* memoryGetBankSize - Returns the size of a memory bank.
-*
-*
-* INPUT: MEMORY_BANK bank - The bank we ask for its size.
-* OUTPUT: N/A
-* RETURNS: Memory bank size.
-*********************************************************************/
-unsigned int memoryGetBankSize(MEMORY_BANK bank)
-{
- unsigned int size,base;
- unsigned int highValue;
- unsigned int highAddress=memoryGetBankRegOffset(bank)+8;
-
- base = memoryGetBankBaseAddress(bank);
- GT_REG_READ(highAddress,&highValue);
- highValue = (highValue + 1) << 20;
- if(base > highValue)
- size=0;
- else
- size = highValue - base;
- return size;
-}
-
-/********************************************************************
-* memoryGetDeviceSize - Returns the size of a device memory space
-*
-*
-* INPUT: DEVICE device - The device we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: Size of a device memory space.
-*********************************************************************/
-unsigned int memoryGetDeviceSize(DEVICE device)
-{
- unsigned int size,base;
- unsigned int highValue;
- unsigned int highAddress=memoryGetDeviceRegOffset(device)+8;
-
- base = memoryGetDeviceBaseAddress(device);
- GT_REG_READ(highAddress,&highValue);
- if (highValue == 0xfff)
- {
- size = (~base) + 1; /* what the heck is this? */
- return size;
- }
- else
- highValue = (highValue + 1) << 20;
-
- if(base > highValue)
- size=0;
- else
- size = highValue - base;
- return size;
-}
-
-/********************************************************************
-* memoryGetDeviceWidth - A device can be with: 1,2,4 or 8 Bytes data width.
-* The width is determine in registers: 'Device Parameters'
-* registers (0x45c, 0x460, 0x464, 0x468, 0x46c - for each device.
-* at bits: [21:20].
-*
-* INPUT: DEVICE device - Device number
-* OUTPUT: N/A
-* RETURNS: Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
-*********************************************************************/
-unsigned int memoryGetDeviceWidth(DEVICE device)
-{
- unsigned int width;
- unsigned int regValue;
-
- GT_REG_READ(DEVICE_BANK0PARAMETERS + device*4,®Value);
- width = (regValue & 0x00300000) >> 20;
- switch (width)
- {
- case 0:
- return 1;
- case 1:
- return 2;
- case 2:
- return 4;
- case 3:
- return 8;
- default:
- return 0;
- }
-}
-
-bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength)
-{
- unsigned int low=0xfff;
- unsigned int high=0x0;
- unsigned int regOffset=memoryGetBankRegOffset(bank);
-
- if(bankLength!=0) {
- low = (bankBase >> 20) & 0xffff;
- high=((bankBase+bankLength)>>20)-1;
- }
-
-#ifdef DEBUG
- {
- unsigned int oldLow, oldHigh;
- GT_REG_READ(regOffset,&oldLow);
- GT_REG_READ(regOffset+8,&oldHigh);
-
- printf("b%d %x-%x->%x-%x\n", bank, oldLow, oldHigh, low, high);
- }
-#endif
-
- GT_REG_WRITE(regOffset,low);
- GT_REG_WRITE(regOffset+8,high);
-
- return true;
-}
-bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength)
-{
- /* TODO: what are appropriate "unmapped" values? */
- unsigned int low=0xfff;
- unsigned int high=0x0;
- unsigned int regOffset=memoryGetDeviceRegOffset(device);
-
- if(deviceLength != 0) {
- low=deviceBase>>20;
- high=((deviceBase+deviceLength)>>20)-1;
- } else {
- /* big problems in here... */
- /* this will HANG */
- }
-
- GT_REG_WRITE(regOffset,low);
- GT_REG_WRITE(regOffset+8,high);
-
- return true;
-}
-
-
-/********************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internals
-* registers.
-*
-* INPUTS: unsigned int internalRegBase - The new base address.
-* RETURNS: true on success, false on failure
-*********************************************************************/
-bool memoryMapInternalRegistersSpace(unsigned int internalRegBase)
-{
- unsigned int currentValue;
- unsigned int internalValue = internalRegBase;
-
- internalRegBase = (internalRegBase >> 20);
- GT_REG_READ(INTERNAL_SPACE_DECODE,¤tValue);
- internalRegBase = (currentValue & 0xffff0000) | internalRegBase;
- GT_REG_WRITE(INTERNAL_SPACE_DECODE,internalRegBase);
- INTERNAL_REG_BASE_ADDR = internalValue;
- return true;
-}
-
-/********************************************************************
-* memoryGetInternalRegistersSpace - Gets internal registers Base Address.
-*
-* INPUTS: unsigned int internalRegBase - The new base address.
-* RETURNS: true on success, false on failure
-*********************************************************************/
-unsigned int memoryGetInternalRegistersSpace(void)
-{
- return INTERNAL_REG_BASE_ADDR;
-}
-
-/********************************************************************
-* memorySetProtectRegion - This function modifys one of the 8 regions with
-* one of the three protection mode.
-* - Be advised to check the spec before modifying them.
-*
-*
-* Inputs: CPU_PROTECT_REGION - one of the eight regions.
-* CPU_ACCESS - general access.
-* CPU_WRITE - read only access.
-* CPU_CACHE_PROTECT - chache access.
-* we defining CPU because there is another protect from the pci SIDE.
-* Returns: false if one of the parameters is wrong and true else
-*********************************************************************/
-bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
- MEMORY_ACCESS memAccess,
- MEMORY_ACCESS_WRITE memWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int protectHigh = baseAddress + regionLength;
-
- if(regionLength == 0) /* closing the region */
- {
- GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,0x0000ffff);
- GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,0);
- return true;
- }
- baseAddress = (baseAddress & 0xfff00000) >> 20;
- baseAddress = baseAddress | memAccess << 16 | memWrite << 17
- | cacheProtection << 18;
- GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,baseAddress);
- protectHigh = (protectHigh & 0xfff00000) >> 20;
- GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,protectHigh - 1);
- return true;
-}
-
-/********************************************************************
-* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
-* supports Cache Coherency.
-*
-*
-* Inputs: SNOOP_REGION region - One of the four regions.
-* SNOOP_TYPE snoopType - There is four optional Types:
-* 1. No Snoop.
-* 2. Snoop to WT region.
-* 3. Snoop to WB region.
-* 4. Snoop & Invalidate to WB region.
-* unsigned int baseAddress - Base Address of this region.
-* unsigned int topAddress - Top Address of this region.
-* Returns: false if one of the parameters is wrong and true else
-*********************************************************************/
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
- MEMORY_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
-
- if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
- return false;
- snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
- snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
- if(regionLength == 0) /* closing the region */
- {
- GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
- GT_REG_WRITE(snoopXtopAddress,0);
- return true;
- }
- baseAddress = baseAddress & 0xffff0000;
- data = (baseAddress >> 16) | snoopType << 16;
- GT_REG_WRITE(snoopXbaseAddress,data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
- return true;
-}
-
-/********************************************************************
-* memoryRemapAddress - This fubction used for address remapping.
-*
-*
-* Inputs: regOffset: remap register
-* remapValue :
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue)
-{
- unsigned int valueForReg;
- valueForReg = (remapValue & 0xfff00000) >> 20;
- GT_REG_WRITE(remapReg, valueForReg);
- return true;
-}
-
-/********************************************************************
-* memoryGetDeviceParam - This function used for getting device parameters from
-* DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK
-* PARAMETERS REGISTER
-* - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum)
-{
- unsigned int valueOfReg;
- unsigned int calcData;
-
- GT_REG_READ(DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
- calcData = (0x7 & valueOfReg) + ((0x400000 & valueOfReg) >> 19);
- deviceParam -> turnOff = calcData; /* Turn Off */
-
- calcData = ((0x78 & valueOfReg) >> 3) + ((0x800000 & valueOfReg) >> 19);
- deviceParam -> acc2First = calcData; /* Access To First */
-
- calcData = ((0x780 & valueOfReg) >> 7) + ((0x1000000 & valueOfReg) >> 20);
- deviceParam -> acc2Next = calcData; /* Access To Next */
-
- calcData = ((0x3800 & valueOfReg) >> 11) + ((0x2000000 & valueOfReg) >> 22);
- deviceParam -> ale2Wr = calcData; /* Ale To Write */
-
- calcData = ((0x1c000 & valueOfReg) >> 14) + ((0x4000000 & valueOfReg) >> 23);
- deviceParam -> wrLow = calcData; /* Write Active */
-
- calcData = ((0xe0000 & valueOfReg) >> 17) + ((0x8000000 & valueOfReg) >> 24);
- deviceParam -> wrHigh = calcData; /* Write High */
-
- calcData = ((0x300000 & valueOfReg) >> 20);
- switch (calcData)
- {
- case 0:
- deviceParam -> deviceWidth = 1; /* one Byte - 8-bit */
- break;
- case 1:
- deviceParam -> deviceWidth = 2; /* two Bytes - 16-bit */
- break;
- case 2:
- deviceParam -> deviceWidth = 4; /* four Bytes - 32-bit */
- break;
- case 3:
- deviceParam -> deviceWidth = 8; /* eight Bytes - 64-bit */
- break;
- default:
- deviceParam -> deviceWidth = 1;
- break;
- }
- return true;
-}
-
-/********************************************************************
-* memorySetDeviceParam - This function used for setting device parameters to
-* DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK
-* PARAMETERS REGISTER
-* - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum)
-{
- unsigned int valueForReg;
-
- if((deviceParam -> turnOff >= 0xf) || (deviceParam -> acc2First >= 0x1f) ||
- (deviceParam -> acc2Next >= 0x1f) || (deviceParam -> ale2Wr >= 0xf) ||
- (deviceParam -> wrLow >= 0xf) || (deviceParam -> wrHigh >= 0xf))
- return false;
- valueForReg = (((deviceParam -> turnOff) & 0x7) |
- (((deviceParam -> turnOff) & 0x8) << 19) |
- (((deviceParam -> acc2First) & 0xf) << 3) |
- (((deviceParam -> acc2First) & 0x10) << 19) |
- (((deviceParam -> acc2Next) & 0xf) << 7) |
- (((deviceParam -> acc2Next) & 0x10) << 20) |
- (((deviceParam -> ale2Wr) & 0x7) << 11) |
- (((deviceParam -> ale2Wr) & 0xf) << 22) |
- (((deviceParam -> wrLow) & 0x7) << 14) |
- (((deviceParam -> wrLow) & 0xf) << 23) |
- (((deviceParam -> wrHigh) & 0x7) << 17) |
- (((deviceParam -> wrHigh) & 0xf) << 24));
- /* insert the device width: */
- switch(deviceParam->deviceWidth)
- {
- case 1:
- valueForReg = valueForReg | _8BIT;
- break;
- case 2:
- valueForReg = valueForReg | _16BIT;
- break;
- case 4:
- valueForReg = valueForReg | _32BIT;
- break;
- case 8:
- valueForReg = valueForReg | _64BIT;
- break;
- default:
- valueForReg = valueForReg | _8BIT;
- break;
- }
- GT_REG_WRITE(DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
- return true;
-}
diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S
deleted file mode 100644
index f09528d..0000000
--- a/board/evb64260/misc.S
+++ /dev/null
@@ -1,182 +0,0 @@
-#include <config.h>
-#include <74xx_7xx.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#include <galileo/gt64260R.h>
-
-#ifdef CONFIG_ECC
- /* Galileo specific asm code for initializing ECC */
- .globl board_relocate_rom
-board_relocate_rom:
- mflr r7
- /* update the location of the GT registers */
- lis r11, CONFIG_SYS_GT_REGS@h
- /* if we're using ECC, we must use the DMA engine to copy ourselves */
- bl start_idma_transfer_0
- bl wait_for_idma_0
- bl stop_idma_engine_0
-
- mtlr r7
- blr
-
- .globl board_init_ecc
-board_init_ecc:
- mflr r7
- /* NOTE: r10 still contains the location we've been relocated to
- * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
-
- /* now that we're running from ram, init the rest of main memory
- * for ECC use */
- lis r8, CONFIG_SYS_MONITOR_LEN@h
- ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
-
- divw r3, r10, r8
-
- /* set up the counter, and init the starting address */
- mtctr r3
- li r12, 0
-
- /* bytes per transfer */
- mr r5, r8
-about_to_init_ecc:
-1: mr r3, r12
- mr r4, r12
- bl start_idma_transfer_0
- bl wait_for_idma_0
- bl stop_idma_engine_0
- add r12, r12, r8
- bdnz 1b
-
- mtlr r7
- blr
-
- /* r3: dest addr
- * r4: source addr
- * r5: byte count
- * r11: gt regbase
- * trashes: r6, r5
- */
-start_idma_transfer_0:
- /* set the byte count, including the OWN bit */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
- stwbrx r5, 0, (r6)
-
- /* set the source address */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
- stwbrx r4, 0, (r6)
-
- /* set the dest address */
- mr r6, r11
- ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
- stwbrx r3, 0, (r6)
-
- /* set the next record pointer */
- li r5, 0
- mr r6, r11
- ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
- stwbrx r5, 0, (r6)
-
- /* set the low control register */
- /* bit 9 is NON chained mode, bit 31 is new style descriptors.
- bit 12 is channel enable */
- ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
- /* 15 shifted by 16 (oris) == bit 31 */
- oris r5, r5, (1 << 15)
- mr r6, r11
- ori r6, r6, CHANNEL0CONTROL
- stwbrx r5, 0, (r6)
-
- blr
-
- /* this waits for the bytecount to return to zero, indicating
- * that the trasfer is complete */
-wait_for_idma_0:
- mr r5, r11
- lis r6, 0xff
- ori r6, r6, 0xffff
- ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
-1: lwbrx r4, 0, (r5)
- and. r4, r4, r6
- bne 1b
-
- blr
-
- /* this turns off channel 0 of the idma engine */
-stop_idma_engine_0:
- /* shut off the DMA engine */
- li r5, 0
- mr r6, r11
- ori r6, r6, CHANNEL0CONTROL
- stwbrx r5, 0, (r6)
-
- blr
-#endif
-
-#ifdef CONFIG_SYS_BOARD_ASM_INIT
- /* NOTE: trashes r3-r7 */
- .globl board_asm_init
-board_asm_init:
- /* just move the GT registers to where they belong */
- lis r3, CONFIG_SYS_DFL_GT_REGS@h
- ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
- lis r4, CONFIG_SYS_GT_REGS@h
- ori r4, r4, CONFIG_SYS_GT_REGS@l
- li r5, INTERNAL_SPACE_DECODE
-
- /* test to see if we've already moved */
- lwbrx r6, r5, r4
- andi. r6, r6, 0xffff
- rlwinm r7, r4, 12, 16, 31
- cmp cr0, r7, r6
- beqlr
-
- /* nope, have to move the registers */
- lwbrx r6, r5, r3
- andis. r6, r6, 0xffff
- or r6, r6, r7
- stwbrx r6, r5, r3
-
- /* now, poll for the change */
-1: lwbrx r7, r5, r4
- cmp cr0, r7, r6
- bne 1b
-
- /* done! */
- blr
-#endif
-
-/* For use of the debug LEDs */
- .global led_on0
-led_on0:
- xor r18, r18, r18
- lis r18, 0x1c80
- ori r18, r18, 0x8000
- stw r18, 0x0(r18)
- sync
- blr
-
- .global led_on1
-led_on1:
- xor r18, r18, r18
- lis r18, 0x1c80
- ori r18, r18, 0xc000
- stw r18, 0x0(r18)
- sync
- blr
-
- .global led_on2
-led_on2:
- xor r18, r18, r18
- lis r18, 0x1c81
- ori r18, r18, 0x0000
- stw r18, 0x0(r18)
- sync
- blr
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
deleted file mode 100644
index c9da57c..0000000
--- a/board/evb64260/mpsc.c
+++ /dev/null
@@ -1,838 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mpsc.c - driver for console over the MPSC.
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/cache.h>
-
-#include <malloc.h>
-#include "mpsc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int (*mpsc_putchar)(char ch) = mpsc_putchar_early;
-
-static volatile unsigned int *rx_desc_base=NULL;
-static unsigned int rx_desc_index=0;
-static volatile unsigned int *tx_desc_base=NULL;
-static unsigned int tx_desc_index=0;
-
-/* local function declarations */
-static int galmpsc_connect(int channel, int connect);
-static int galmpsc_route_serial(int channel, int connect);
-static int galmpsc_route_rx_clock(int channel, int brg);
-static int galmpsc_route_tx_clock(int channel, int brg);
-static int galmpsc_write_config_regs(int mpsc, int mode);
-static int galmpsc_config_channel_regs(int mpsc);
-static int galmpsc_set_char_length(int mpsc, int value);
-static int galmpsc_set_stop_bit_length(int mpsc, int value);
-static int galmpsc_set_parity(int mpsc, int value);
-static int galmpsc_enter_hunt(int mpsc);
-static int galmpsc_set_brkcnt(int mpsc, int value);
-static int galmpsc_set_tcschar(int mpsc, int value);
-static int galmpsc_set_snoop(int mpsc, int value);
-static int galmpsc_shutdown(int mpsc);
-
-static int galsdma_set_RFT(int channel);
-static int galsdma_set_SFM(int channel);
-static int galsdma_set_rxle(int channel);
-static int galsdma_set_txle(int channel);
-static int galsdma_set_burstsize(int channel, unsigned int value);
-static int galsdma_set_RC(int channel, unsigned int value);
-
-static int galbrg_set_CDV(int channel, int value);
-static int galbrg_enable(int channel);
-static int galbrg_disable(int channel);
-static int galbrg_set_clksrc(int channel, int value);
-static int galbrg_set_CUV(int channel, int value);
-
-static void galsdma_enable_rx(void);
-
-/* static int galbrg_reset(int channel); */
-
-#define SOFTWARE_CACHE_MANAGEMENT
-
-#ifdef SOFTWARE_CACHE_MANAGEMENT
-#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
-#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
-#else
-#define FLUSH_DCACHE(a,b)
-#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
-#define INVALIDATE_DCACHE(a,b)
-#endif
-
-
-/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
-#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->arch.mirror_hack[0]))
-
-#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
-#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
-
-#define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);}
-#define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i])
-
-/* make sure this isn't bigger than 16 long words (u-boot.h) */
-struct _tag_mirror_hack {
- unsigned GALMPSC_PROTOCONF_REG_M[2]; /* 8008 */
- unsigned GALMPSC_CHANNELREG_1_M[2]; /* 800c */
- unsigned GALMPSC_CHANNELREG_2_M[2]; /* 8010 */
- unsigned GALBRG_0_CONFREG_M[2]; /* b200 */
-
- unsigned GALMPSC_ROUTING_REGISTER_M; /* b400 */
- unsigned GALMPSC_RxC_ROUTE_M; /* b404 */
- unsigned GALMPSC_TxC_ROUTE_M; /* b408 */
-
- unsigned int baudrate; /* current baudrate, for tsc delay calc */
-};
-
-/* static struct _tag_mirror_hack *mh = NULL; */
-
-/* special function for running out of flash. doesn't modify any
- * global variables [josh] */
-int
-mpsc_putchar_early(char ch)
-{
- int mpsc=CHANNEL;
- int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
- galmpsc_set_tcschar(mpsc,ch);
- GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp|0x200);
-
-#define MAGIC_FACTOR (10*1000000)
-
- udelay(MAGIC_FACTOR / MIRROR_HACK->baudrate);
- return 0;
-}
-
-/* This is used after relocation, see serial.c and mpsc_init2 */
-static int
-mpsc_putchar_sdma(char ch)
-{
- volatile unsigned int *p;
- unsigned int temp;
-
-
- /* align the descriptor */
- p = tx_desc_base;
- memset((void *)p, 0, 8 * sizeof(unsigned int));
-
- /* fill one 64 bit buffer */
- /* word swap, pad with 0 */
- p[4] = 0; /* x */
- p[5] = (unsigned int)ch; /* x */
-
- /* CHANGED completely according to GT64260A dox - NTL */
- p[0] = 0x00010001; /* 0 */
- p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* 4 */
- p[2] = 0; /* 8 */
- p[3] = (unsigned int)&p[4]; /* c */
-
-#if 0
- p[9] = DESC_FIRST | DESC_LAST;
- p[10] = (unsigned int)&p[0];
- p[11] = (unsigned int)&p[12];
-#endif
-
- FLUSH_DCACHE(&p[0], &p[8]);
-
- GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
- (unsigned int)&p[0]);
- GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
- (unsigned int)&p[0]);
-
- temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF));
- temp |= (TX_DEMAND | TX_STOP);
- GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp);
-
- INVALIDATE_DCACHE(&p[1], &p[2]);
-
- while(p[1] & DESC_OWNER) {
- udelay(100);
- INVALIDATE_DCACHE(&p[1], &p[2]);
- }
-
- return 0;
-}
-
-char mpsc_getchar (void)
-{
- static unsigned int done = 0;
- volatile char ch;
- unsigned int len = 0, idx = 0, temp;
-
- volatile unsigned int *p;
-
-
- do {
- p = &rx_desc_base[rx_desc_index * 8];
-
- INVALIDATE_DCACHE (&p[0], &p[1]);
- /* Wait for character */
- while (p[1] & DESC_OWNER) {
- udelay (100);
- INVALIDATE_DCACHE (&p[0], &p[1]);
- }
-
- /* Handle error case */
- if (p[1] & (1 << 15)) {
- printf ("oops, error: %08x\n", p[1]);
-
- temp = GTREGREAD_MIRROR (GALMPSC_CHANNELREG_2,
- CHANNEL, GALMPSC_REG_GAP);
- temp |= (1 << 23);
- GT_REG_WRITE_MIRROR (GALMPSC_CHANNELREG_2, CHANNEL,
- GALMPSC_REG_GAP, temp);
-
- /* Can't poll on abort bit, so we just wait. */
- udelay (100);
-
- galsdma_enable_rx ();
- }
-
- /* Number of bytes left in this descriptor */
- len = p[0] & 0xffff;
-
- if (len) {
- /* Where to look */
- idx = 5;
- if (done > 3)
- idx = 4;
- if (done > 7)
- idx = 7;
- if (done > 11)
- idx = 6;
-
- INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
- ch = p[idx] & 0xff;
- done++;
- }
-
- if (done < len) {
- /* this descriptor has more bytes still
- * shift down the char we just read, and leave the
- * buffer in place for the next time around
- */
- p[idx] = p[idx] >> 8;
- FLUSH_DCACHE (&p[idx], &p[idx + 1]);
- }
-
- if (done == len) {
- /* nothing left in this descriptor.
- * go to next one
- */
- p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
- p[0] = 0x00100000;
- FLUSH_DCACHE (&p[0], &p[1]);
- /* Next descriptor */
- rx_desc_index = (rx_desc_index + 1) % RX_DESC;
- done = 0;
- }
- } while (len == 0); /* galileo bug.. len might be zero */
-
- return ch;
-}
-
-int
-mpsc_test_char(void)
-{
- volatile unsigned int *p = &rx_desc_base[rx_desc_index*8];
-
- INVALIDATE_DCACHE(&p[1], &p[2]);
-
- if (p[1] & DESC_OWNER) return 0;
- else return 1;
-}
-
-int
-mpsc_init(int baud)
-{
- memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack));
- MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff;
-
- /* BRG CONFIG */
- galbrg_set_baudrate(CHANNEL, baud);
-#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
- galbrg_set_clksrc(CHANNEL,0x8); /* connect TCLK -> BRG */
-#else
- galbrg_set_clksrc(CHANNEL,0);
-#endif
- galbrg_set_CUV(CHANNEL, 0);
- galbrg_enable(CHANNEL);
-
- /* Set up clock routing */
- galmpsc_connect(CHANNEL, GALMPSC_CONNECT);
- galmpsc_route_serial(CHANNEL, GALMPSC_CONNECT);
- galmpsc_route_rx_clock(CHANNEL, CHANNEL);
- galmpsc_route_tx_clock(CHANNEL, CHANNEL);
-
- /* reset MPSC state */
- galmpsc_shutdown(CHANNEL);
-
- /* SDMA CONFIG */
- galsdma_set_burstsize(CHANNEL, L1_CACHE_BYTES/8); /* in 64 bit words (8 bytes) */
- galsdma_set_txle(CHANNEL);
- galsdma_set_rxle(CHANNEL);
- galsdma_set_RC(CHANNEL, 0xf);
- galsdma_set_SFM(CHANNEL);
- galsdma_set_RFT(CHANNEL);
-
- /* MPSC CONFIG */
- galmpsc_write_config_regs(CHANNEL, GALMPSC_UART);
- galmpsc_config_channel_regs(CHANNEL);
- galmpsc_set_char_length(CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
- galmpsc_set_parity(CHANNEL, GALMPSC_PARITY_NONE); /* N */
- galmpsc_set_stop_bit_length(CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
-
- /* COMM_MPSC CONFIG */
-#ifdef SOFTWARE_CACHE_MANAGEMENT
- galmpsc_set_snoop(CHANNEL, 0); /* disable snoop */
-#else
- galmpsc_set_snoop(CHANNEL, 1); /* enable snoop */
-#endif
-
- return 0;
-}
-
-void
-mpsc_init2(void)
-{
- int i;
-
- mpsc_putchar = mpsc_putchar_sdma;
-
- /* RX descriptors */
- rx_desc_base = (unsigned int *)malloc(((RX_DESC+1)*8) *
- sizeof(unsigned int));
-
- /* align descriptors */
- rx_desc_base = (unsigned int *)
- (((unsigned int)rx_desc_base+32) & 0xFFFFFFF0);
-
- rx_desc_index = 0;
-
- memset((void *)rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int));
-
- for (i = 0; i < RX_DESC; i++) {
- rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; /* Buffer */
- rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[(i+1)*8]; /* Next descriptor */
- rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* Command & control */
- rx_desc_base[i*8] = 0x00100000;
- }
- rx_desc_base[(i-1)*8 + 2] = (unsigned int)&rx_desc_base[0];
-
- FLUSH_DCACHE(&rx_desc_base[0], &rx_desc_base[RX_DESC*8]);
- GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
- (unsigned int)&rx_desc_base[0]);
-
- /* TX descriptors */
- tx_desc_base = (unsigned int *)malloc(((TX_DESC+1)*8) *
- sizeof(unsigned int));
-
- /* align descriptors */
- tx_desc_base = (unsigned int *)
- (((unsigned int)tx_desc_base+32) & 0xFFFFFFF0);
-
- tx_desc_index = -1;
-
- memset((void *)tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int));
-
- for (i = 0; i < TX_DESC; i++) {
- tx_desc_base[i*8 + 5] = (unsigned int)0x23232323;
- tx_desc_base[i*8 + 4] = (unsigned int)0x23232323;
- tx_desc_base[i*8 + 3] = (unsigned int)&tx_desc_base[i*8 + 4];
- tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[(i+1)*8];
- tx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
-
- /* set sbytecnt and shadow byte cnt to 1 */
- tx_desc_base[i*8] = 0x00010001;
- }
- tx_desc_base[(i-1)*8 + 2] = (unsigned int)&tx_desc_base[0];
-
- FLUSH_DCACHE(&tx_desc_base[0], &tx_desc_base[TX_DESC*8]);
-
- udelay(100);
-
- galsdma_enable_rx();
-
- return;
-}
-
-int
-galbrg_set_baudrate(int channel, int rate)
-{
- int clock;
-
- galbrg_disable(channel);
-
-#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
- /* from tclk */
- clock = (CONFIG_SYS_BUS_CLK/(16*rate)) - 1;
-#else
- clock = (3686400/(16*rate)) - 1;
-#endif
-
- galbrg_set_CDV(channel, clock);
-
- galbrg_enable(channel);
-
- MIRROR_HACK->baudrate = rate;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------ */
-
-/* Below are all the private functions that no one else needs */
-
-static int
-galbrg_set_CDV(int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
- temp &= 0xFFFF0000;
- temp |= (value & 0x0000FFFF);
- GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel,GALBRG_REG_GAP, temp);
-
- return 0;
-}
-
-static int
-galbrg_enable(int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
- temp |= 0x00010000;
- GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp);
-
- return 0;
-}
-
-static int
-galbrg_disable(int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
- temp &= 0xFFFEFFFF;
- GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp);
-
- return 0;
-}
-
-static int
-galbrg_set_clksrc(int channel, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP);
- temp &= 0xFF83FFFF;
- temp |= (value << 18);
- GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp);
-
- return 0;
-}
-
-static int
-galbrg_set_CUV(int channel, int value)
-{
- GT_REG_WRITE(GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
-
- return 0;
-}
-
-#if 0
-static int
-galbrg_reset(int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
- temp |= 0x20000;
- GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
-
- return 0;
-}
-#endif
-
-static int
-galsdma_set_RFT(int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
- temp |= 0x00000001;
- GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
-
- return 0;
-}
-
-static int
-galsdma_set_SFM(int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
- temp |= 0x00000002;
- GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
-
- return 0;
-}
-
-static int
-galsdma_set_rxle(int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
- temp |= 0x00000040;
- GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
-
- return 0;
-}
-
-static int
-galsdma_set_txle(int channel)
-{
- unsigned int temp;
-
- temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
- temp |= 0x00000080;
- GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
-
- return 0;
-}
-
-static int
-galsdma_set_RC(int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
- temp &= ~0x0000003c;
- temp |= (value << 2);
- GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
-
- return 0;
-}
-
-static int
-galsdma_set_burstsize(int channel, unsigned int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
- temp &= 0xFFFFCFFF;
- switch (value) {
- case 8:
- GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
- (temp | (0x3 << 12)));
- break;
-
- case 4:
- GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
- (temp | (0x2 << 12)));
- break;
-
- case 2:
- GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
- (temp | (0x1 << 12)));
- break;
-
- case 1:
- GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
- (temp | (0x0 << 12)));
- break;
-
- default:
- return -1;
- break;
- }
-
- return 0;
-}
-
-static int
-galmpsc_connect(int channel, int connect)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER);
-
- if ((channel == 0) && connect)
- temp &= ~0x00000007;
- else if ((channel == 1) && connect)
- temp &= ~(0x00000007 << 6);
- else if ((channel == 0) && !connect)
- temp |= 0x00000007;
- else
- temp |= (0x00000007 << 6);
-
- /* Just in case... */
- temp &= 0x3fffffff;
-
- GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp);
-
- return 0;
-}
-
-static int
-galmpsc_route_serial(int channel, int connect)
-{
- unsigned int temp;
-
- temp = GTREGREAD(GALMPSC_SERIAL_MULTIPLEX);
-
- if ((channel == 0) && connect)
- temp |= 0x00000100;
- else if ((channel == 1) && connect)
- temp |= 0x00001000;
- else if ((channel == 0) && !connect)
- temp &= ~0x00000100;
- else
- temp &= ~0x00001000;
-
- GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX,temp);
-
- return 0;
-}
-
-static int
-galmpsc_route_rx_clock(int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE);
-
- if (channel == 0)
- temp |= brg;
- else
- temp |= (brg << 8);
-
- GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp);
-
- return 0;
-}
-
-static int
-galmpsc_route_tx_clock(int channel, int brg)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE);
-
- if (channel == 0)
- temp |= brg;
- else
- temp |= (brg << 8);
-
- GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp);
-
- return 0;
-}
-
-static int
-galmpsc_write_config_regs(int mpsc, int mode)
-{
- if (mode == GALMPSC_UART) {
- /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
- GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP),
- 0x000004c4);
-
- /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
- GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP),
- 0x024003f8);
- /* 22 2222 1111 */
- /* 54 3210 9876 */
- /* 0000 0010 0000 0000 */
- /* 1 */
- /* 098 7654 3210 */
- /* 0000 0011 1111 1000 */
- } else
- return -1;
-
- return 0;
-}
-
-static int
-galmpsc_config_channel_regs(int mpsc)
-{
- GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0);
- GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0);
- GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1);
- GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0);
- GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0);
- GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0);
- GT_REG_WRITE(GALMPSC_CHANNELREG_7+(mpsc*GALMPSC_REG_GAP), 0);
- GT_REG_WRITE(GALMPSC_CHANNELREG_8+(mpsc*GALMPSC_REG_GAP), 0);
- GT_REG_WRITE(GALMPSC_CHANNELREG_9+(mpsc*GALMPSC_REG_GAP), 0);
- GT_REG_WRITE(GALMPSC_CHANNELREG_10+(mpsc*GALMPSC_REG_GAP), 0);
-
- galmpsc_set_brkcnt(mpsc, 0x3);
- galmpsc_set_tcschar(mpsc, 0xab);
-
- return 0;
-}
-
-static int
-galmpsc_set_brkcnt(int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
- temp &= 0x0000FFFF;
- temp |= (value << 16);
- GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);
-
- return 0;
-}
-
-static int
-galmpsc_set_tcschar(int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
- temp &= 0xFFFF0000;
- temp |= value;
- GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);
-
- return 0;
-}
-
-static int
-galmpsc_set_char_length(int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
- temp &= 0xFFFFCFFF;
- temp |= (value << 12);
- GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp);
-
- return 0;
-}
-
-static int
-galmpsc_set_stop_bit_length(int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
- temp |= (value << 14);
- GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp);
-
- return 0;
-}
-
-static int
-galmpsc_set_parity(int mpsc, int value)
-{
- unsigned int temp;
-
- temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
- if (value != -1) {
- temp &= 0xFFF3FFF3;
- temp |= ((value << 18) | (value << 2));
- temp |= ((value << 17) | (value << 1));
- } else {
- temp &= 0xFFF1FFF1;
- }
-
- GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);
-
- return 0;
-}
-
-static int
-galmpsc_enter_hunt(int mpsc)
-{
- int temp;
-
- temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
- temp |= 0x80000000;
- GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);
-
- /* Should Poll on Enter Hunt bit, but the register is write-only */
- /* errata suggests pausing 100 system cycles */
- udelay(100);
-
- return 0;
-}
-
-
-static int
-galmpsc_shutdown(int mpsc)
-{
-#if 0
- unsigned int temp;
-
- /* cause RX abort (clears RX) */
- temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
- temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
- temp &= ~MPSC_ENTER_HUNT;
- GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp);
-#endif
-
- GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0);
- GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF,
- SDMA_TX_ABORT | SDMA_RX_ABORT);
-
- /* shut down the MPSC */
- GT_REG_WRITE(GALMPSC_MCONF_LOW, 0);
- GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0);
- GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0);
-
- udelay(100);
-
- /* shut down the sdma engines. */
- /* reset config to default */
- GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF,
- 0x000000fc);
-
- udelay(100);
-
- /* clear the SDMA current and first TX and RX pointers */
- GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
- GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
- GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
-
- udelay(100);
-
- return 0;
-}
-
-static void
-galsdma_enable_rx(void)
-{
- int temp;
-
- /* Enable RX processing */
- temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF));
- temp |= RX_ENABLE;
- GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp);
-
- galmpsc_enter_hunt(CHANNEL);
-}
-
-static int
-galmpsc_set_snoop(int mpsc, int value)
-{
- int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW;
- int temp=GTREGREAD(reg);
- if(value)
- temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30);
- else
- temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30));
- GT_REG_WRITE(reg, temp);
- return 0;
-}
diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h
deleted file mode 100644
index 0747477..0000000
--- a/board/evb64260/mpsc.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2001
- * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mpsc.h - header file for MPSC in uart mode (console driver)
- */
-
-#ifndef __MPSC_H__
-#define __MPSC_H__
-
-/* include actual Galileo defines */
-#include <galileo/gt64260R.h>
-
-/* driver related defines */
-
-int mpsc_init(int baud);
-void mpsc_init2(void);
-char mpsc_getchar(void);
-int mpsc_test_char(void);
-int galbrg_set_baudrate(int channel, int rate);
-
-int mpsc_putchar_early(char ch);
-extern int (*mpsc_putchar)(char ch);
-
-#define CHANNEL CONFIG_MPSC_PORT
-
-#define TX_DESC 5
-#define RX_DESC 20
-
-#define DESC_FIRST 0x00010000
-#define DESC_LAST 0x00020000
-#define DESC_OWNER 0x80000000
-
-#define TX_DEMAND 0x00800000
-#define TX_STOP 0x00010000
-#define RX_ENABLE 0x00000080
-
-#define SDMA_RX_ABORT (1 << 15)
-#define SDMA_TX_ABORT (1 << 31)
-#define MPSC_TX_ABORT (1 << 7)
-#define MPSC_RX_ABORT (1 << 23)
-#define MPSC_ENTER_HUNT (1 << 31)
-
-/* MPSC defines */
-
-#define GALMPSC_CONNECT 0x1
-#define GALMPSC_DISCONNECT 0x0
-
-#define GALMPSC_UART 0x1
-
-#define GALMPSC_STOP_BITS_1 0x0
-#define GALMPSC_STOP_BITS_2 0x1
-#define GALMPSC_CHAR_LENGTH_8 0x3
-#define GALMPSC_CHAR_LENGTH_7 0x2
-
-#define GALMPSC_PARITY_ODD 0x0
-#define GALMPSC_PARITY_EVEN 0x2
-#define GALMPSC_PARITY_MARK 0x3
-#define GALMPSC_PARITY_SPACE 0x1
-#define GALMPSC_PARITY_NONE -1
-
-#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
-#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
-#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
-#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
-#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
-#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
-#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
-
-#define GALMPSC_REG_GAP 0x1000
-
-#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
-#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
-#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
-#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
-#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
-#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
-#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
-#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
-#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
-#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
-#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
-
-#define GALSDMA_COMMAND_FIRST (1 << 16)
-#define GALSDMA_COMMAND_LAST (1 << 17)
-#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
-#define GALSDMA_COMMAND_AUTO (1 << 30)
-#define GALSDMA_COMMAND_OWNER (1 << 31)
-
-#define GALSDMA_RX 0
-#define GALSDMA_TX 1
-
-/* CHANNEL2 should be CHANNEL1, according to documentation,
- * but to work with the current GTREGS file...
- */
-#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
-#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
-#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
-#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
-#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
-#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
-#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
-#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
-#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
-#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
-#define GALSDMA_REG_DIFF 0x2000
-
-/* WRONG in gt64260R.h */
-#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
-#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
-
-#define GALSDMA_MODE_UART 0
-#define GALSDMA_MODE_BISYNC 1
-#define GALSDMA_MODE_HDLC 2
-#define GALSDMA_MODE_TRANSPARENT 3
-
-#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
-#define GALBRG_REG_GAP 0x0008
-#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
-
-#endif /* __MPSC_H__ */
diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c
deleted file mode 100644
index 582f24c..0000000
--- a/board/evb64260/pci.c
+++ /dev/null
@@ -1,760 +0,0 @@
-/* PCI.c - PCI functions */
-
-/* Copyright - Galileo technology. */
-
-#include <common.h>
-#include <pci.h>
-
-#include <galileo/pci.h>
-
-static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
-#ifdef CONFIG_ZUMA_V2
- {0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0},
- {0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0}
-#else /* EVB??? This is a guess */
- {0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0},
- {0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0}
-#endif
-};
-
-static const unsigned int pci_p2p_configuration_reg[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static const unsigned int pci_configuration_address[] = {
- PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
-};
-
-static const unsigned int pci_configuration_data[] = {
- PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
- PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
-};
-
-static const unsigned int pci_error_cause_reg[] = {
- PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
-};
-
-static const unsigned int pci_arbiter_control[] = {
- PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
-};
-
-static const unsigned int pci_snoop_control_base_0_low[] = {
- PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_snoop_control_top_0[] = {
- PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
-};
-
-static const unsigned int pci_access_control_base_0_low[] = {
- PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
-};
-static const unsigned int pci_access_control_top_0[] = {
- PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
-};
-
-static const unsigned int pci_scs_bank_size[2][4] = {
- {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
- PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
- {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
- PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
-};
-
-static const unsigned int pci_p2p_configuration[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
-};
-
-static unsigned int local_buses[] = { 0, 0 };
-
-/********************************************************************
-* pciWriteConfigReg - Write to a PCI configuration register
-* - Make sure the GT is configured as a master before writing
-* to another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-*
-*
-* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
-* (or any other PCI device spec)
-* pciDevNum: The device number needs to be addressed.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum, unsigned int data)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int functionNum;
- unsigned int busNum = PCI_BUS (pciDevNum);
- unsigned int addr;
-
- if (pciDevNum > 32) /* illegal device Number */
- return;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &addr);
- if (addr != DataForAddrReg)
- return;
- GT_REG_WRITE (pci_configuration_data[host], data);
-}
-
-/********************************************************************
-* pciReadConfigReg - Read from a PCI0 configuration register
-* - Make sure the GT is configured as a master before reading
-* from another device on the PCI.
-* - The function takes care of Big/Little endian conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec)
-* pciDevNum: The device number needs to be addressed.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|00|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum)
-{
- volatile unsigned int DataForAddrReg;
- unsigned int data;
- unsigned int functionNum;
- unsigned int busNum = PCI_BUS (pciDevNum);
-
- if (pciDevNum > 32) /* illegal device Number */
- return 0xffffffff;
- if (pciDevNum == SELF) { /* configure our configuration space. */
- pciDevNum =
- (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
- 0x1f;
- busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
- 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg =
- (regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
- GT_REG_READ (pci_configuration_address[host], &data);
- if (data != DataForAddrReg)
- return 0xffffffff;
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
-}
-
-/********************************************************************
-* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
-* the agent is placed on another Bus. For more
-* information read P2P in the PCI spec.
-*
-* Inputs: unsigned int regOffset - The register offset as it apears in the
-* GT spec (or any other PCI device spec).
-* unsigned int pciDevNum - The device number needs to be addressed.
-* unsigned int busNum - On which bus does the Target agent connect
-* to.
-* unsigned int data - data to be written.
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-* The configuration Address is configure as type-I (bits[1:0] = '01') due to
-* PCI spec referring to P2P.
-*
-*********************************************************************/
-void pciOverBridgeWriteConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum, unsigned int data)
-{
- unsigned int DataForReg;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
- } else {
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT31 | BIT0;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- if (pciDevNum == SELF) { /* This board */
- GT_REG_WRITE (pci_configuration_data[host], data);
- } else { /* configuration Transaction over the pci. */
-
- /* The PCI is working in LE Mode So it swap the Data. */
- GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data));
- }
-}
-
-
-/********************************************************************
-* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
-* the agent target locate on another PCI bus.
-* - Make sure the GT is configured as a master
-* before reading from another device on the PCI.
-* - The function takes care of Big/Little endian
-* conversion.
-* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
-* spec). (configuration register offset.)
-* pciDevNum: The device number needs to be addressed.
-* busNum: the Bus number where the agent is place.
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
-* cause register to make sure the data is valid
-*
-* Configuration Address 0xCF8:
-*
-* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
-* |congif|Reserved| Bus |Device|Function|Register|01|
-* |Enable| |Number|Number| Number | Number | | <=field Name
-*
-*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum)
-{
- unsigned int DataForReg;
- unsigned int data;
- unsigned int functionNum;
-
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) { /* This board */
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
- } else { /* agent on another bus */
-
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT0 | BIT31;
- }
- GT_REG_WRITE (pci_configuration_address[host], DataForReg);
- if (pciDevNum == SELF) { /* This board */
- GT_REG_READ (pci_configuration_data[host], &data);
- return data;
- } else { /* The PCI is working in LE Mode So it swap the Data. */
-
- GT_REG_READ (pci_configuration_data[host], &data);
- return WORD_SWAP (data);
- }
-}
-
-/********************************************************************
-* pciGetRegOffset - Gets the register offset for this region config.
-*
-* INPUT: Bus, Region - The bus and region we ask for its base address.
-* OUTPUT: N/A
-* RETURNS: PCI register base address
-*********************************************************************/
-static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0:
- return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1:
- return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2:
- return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3:
- return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
- }
- }
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
-}
-
-static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
-{
- switch (host) {
- case PCI_HOST0:
- switch (region) {
- case PCI_IO:
- return PCI_0I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_0MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_0MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_0MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_0MEMORY3_ADDRESS_REMAP;
- }
- case PCI_HOST1:
- switch (region) {
- case PCI_IO:
- return PCI_1I_O_ADDRESS_REMAP;
- case PCI_REGION0:
- return PCI_1MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1:
- return PCI_1MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2:
- return PCI_1MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3:
- return PCI_1MEMORY3_ADDRESS_REMAP;
- }
- }
- return PCI_0MEMORY0_ADDRESS_REMAP;
-}
-
-bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
- unsigned int bankBase, unsigned int bankLength)
-{
- unsigned int low = 0xfff;
- unsigned int high = 0x0;
- unsigned int regOffset = pciGetRegOffset (host, region);
- unsigned int remapOffset = pciGetRemapOffset (host, region);
-
- if (bankLength != 0) {
- low = (bankBase >> 20) & 0xfff;
- high = ((bankBase + bankLength) >> 20) - 1;
- }
-
- GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
- GT_REG_WRITE (regOffset + 8, high);
-
- if (bankLength != 0) { /* must do AFTER writing maps */
- GT_REG_WRITE (remapOffset, remapBase >> 20); /* sorry, 32 bits only.
- dont support upper 32
- in this driver */
- }
- return true;
-}
-
-unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- return (low & 0xfff) << 20;
-}
-
-unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
-{
- unsigned int low, high;
- unsigned int regOffset = pciGetRegOffset (host, region);
-
- GT_REG_READ (regOffset, &low);
- GT_REG_READ (regOffset + 8, &high);
- high &= 0xfff;
- low &= 0xfff;
- if (high <= low)
- return 0;
- return (high + 1 - low) << 20;
-}
-
-/********************************************************************
-* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
-*
-* Inputs: base and size of PCI SCS
-*********************************************************************/
-void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
- unsigned int pciDramBase, unsigned int pciDramSize)
-{
- pciDramBase = pciDramBase & 0xfffff000;
- pciDramBase = pciDramBase | (pciReadConfigReg (host,
- PCI_SCS_0_BASE_ADDRESS
- + 4 * bank,
- SELF) & 0x00000fff);
- pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF,
- pciDramBase);
- if (pciDramSize == 0)
- pciDramSize++;
- GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
-}
-
-
-/********************************************************************
-* pciSetRegionFeatures - This function modifys one of the 8 regions with
-* feature bits given as an input.
-* - Be advised to check the spec before modifying them.
-* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
-* unsigned int features - See file: pci.h there are defintion for those
-* region features.
-* unsigned int baseAddress - The region base Address.
-* unsigned int topAddress - The region top Address.
-* Returns: false if one of the parameters is erroneous true otherwise.
-*********************************************************************/
-bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
- unsigned int features, unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int accessLow;
- unsigned int accessHigh;
- unsigned int accessTop = baseAddress + regionLength;
-
- if (regionLength == 0) { /* close the region. */
- pciDisableAccessRegion (host, region);
- return true;
- }
- /* base Address is store is bits [11:0] */
- accessLow = (baseAddress & 0xfff00000) >> 20;
- /* All the features are update according to the defines in pci.h (to be on
- the safe side we disable bits: [11:0] */
- accessLow = accessLow | (features & 0xfffff000);
- /* write to the Low Access Region register */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- accessLow);
-
- accessHigh = (accessTop & 0xfff00000) >> 20;
-
- /* write to the High Access Region register */
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
- accessHigh - 1);
- return true;
-}
-
-/********************************************************************
-* pciDisableAccessRegion - Disable The given Region by writing MAX size
-* to its low Address and MIN size to its high Address.
-*
-* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
-* Returns: N/A.
-*********************************************************************/
-void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
-{
- /* writing back the registers default values. */
- GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
- 0x01001fff);
- GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
-}
-
-/********************************************************************
-* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true.
-*********************************************************************/
-bool pciArbiterEnable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
- return true;
-}
-
-/********************************************************************
-* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
-*
-* Inputs: N/A
-* Returns: true
-*********************************************************************/
-bool pciArbiterDisable (PCI_HOST host)
-{
- unsigned int regData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
- return true;
-}
-
-/********************************************************************
-* pciParkingDisable - Park on last option disable, with this function you can
-* disable the park on last mechanism for each agent.
-* disabling this option for all agents results parking
-* on the internal master.
-*
-* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
-* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
-* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
-* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
-* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
-* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
-* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
-* Returns: true
-*********************************************************************/
-bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
- PCI_AGENT_PARK externalAgent0,
- PCI_AGENT_PARK externalAgent1,
- PCI_AGENT_PARK externalAgent2,
- PCI_AGENT_PARK externalAgent3,
- PCI_AGENT_PARK externalAgent4,
- PCI_AGENT_PARK externalAgent5)
-{
- unsigned int regData;
- unsigned int writeData;
-
- GT_REG_READ (pci_arbiter_control[host], ®Data);
- writeData = (internalAgent << 14) + (externalAgent0 << 15) +
- (externalAgent1 << 16) + (externalAgent2 << 17) +
- (externalAgent3 << 18) + (externalAgent4 << 19) +
- (externalAgent5 << 20);
- regData = (regData & ~(0x7f << 14)) | writeData;
- GT_REG_WRITE (pci_arbiter_control[host], regData);
- return true;
-}
-
-/********************************************************************
-* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
-* supports Cache Coherency in the PCI_n interface.
-* Inputs: region - One of the four regions.
-* snoopType - There is four optional Types:
-* 1. No Snoop.
-* 2. Snoop to WT region.
-* 3. Snoop to WB region.
-* 4. Snoop & Invalidate to WB region.
-* baseAddress - Base Address of this region.
-* regionLength - Region length.
-* Returns: false if one of the parameters is wrong otherwise return true.
-*********************************************************************/
-bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
- PCI_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength)
-{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
-
- if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
- return false;
- snoopXbaseAddress =
- pci_snoop_control_base_0_low[host] + 0x10 * region;
- snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
- if (regionLength == 0) { /* closing the region */
- GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
- GT_REG_WRITE (snoopXtopAddress, 0);
- return true;
- }
- baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
- data = (baseAddress >> 20) | snoopType << 12;
- GT_REG_WRITE (snoopXbaseAddress, data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
- return true;
-}
-
-/*
- *
- */
-
-static int gt_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
- PCI_DEV (dev));
- } else {
- *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
- cfg_addr, offset,
- PCI_DEV (dev), bus);
- }
- return 0;
-}
-
-static int gt_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 value)
-{
- int bus = PCI_BUS (dev);
-
- if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
- PCI_DEV (dev), value);
- } else {
- pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
- offset, PCI_DEV (dev), value,
- bus);
- }
- return 0;
-}
-
-/*
- *
- */
-
-static void gt_setup_ide (struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
- static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
- u32 bar_response, bar_value;
- int bar;
-
- for (bar = 0; bar < 6; bar++) {
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
- 0x0);
- pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
- &bar_response);
-
- pciauto_region_allocate (bar_response &
- PCI_BASE_ADDRESS_SPACE_IO ? hose->
- pci_io : hose->pci_mem, ide_bar[bar],
- &bar_value);
-
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
- bar_value);
- }
-}
-
-#ifndef CONFIG_P3G4
-static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
-{
- unsigned char pin, irq;
-
- pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
-
- if (pin == 1) { /* only allow INT A */
- irq = pci_irq_swizzle[(PCI_HOST) hose->
- cfg_addr][PCI_DEV (dev)];
- if (irq)
- pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
- }
-}
-#endif
-
-struct pci_config_table gt_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
- {}
-};
-
-struct pci_controller pci0_hose = {
-#ifndef CONFIG_P3G4
- fixup_irq:gt_fixup_irq,
-#endif
- config_table:gt_config_table,
-};
-
-struct pci_controller pci1_hose = {
-#ifndef CONFIG_P3G4
- fixup_irq:gt_fixup_irq,
-#endif
- config_table:gt_config_table,
-};
-
-void pci_init_board (void)
-{
- unsigned int command;
-
- pci0_hose.first_busno = 0;
- pci0_hose.last_busno = 0xff;
- local_buses[0] = pci0_hose.first_busno;
- /* PCI memory space */
- pci_set_region (pci0_hose.regions + 0,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_0_MEM_SPACE,
- CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci0_hose.regions + 1,
- CONFIG_SYS_PCI0_IO_SPACE_PCI,
- CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci0_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
-
- pci0_hose.region_count = 2;
-
- pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
-
- pci_register_hose (&pci0_hose);
-
-#ifndef CONFIG_P3G4
- pciArbiterEnable (PCI_HOST0);
- pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
-#endif
-
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
- pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
-
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-
- pci1_hose.first_busno = pci0_hose.last_busno + 1;
- pci1_hose.last_busno = 0xff;
- pci1_hose.current_busno = pci0_hose.current_busno;
- local_buses[1] = pci1_hose.first_busno;
-
- /* PCI memory space */
- pci_set_region (pci1_hose.regions + 0,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_0_MEM_SPACE,
- CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region (pci1_hose.regions + 1,
- CONFIG_SYS_PCI1_IO_SPACE_PCI,
- CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
-
- pci_set_ops (&pci1_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
-
- pci1_hose.region_count = 2;
-
- pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
-
- pci_register_hose (&pci1_hose);
-
-#ifndef CONFIG_P3G4
- pciArbiterEnable (PCI_HOST1);
- pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
-#endif
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-
- pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
-
- command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
-}
diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c
deleted file mode 100644
index 12b1308..0000000
--- a/board/evb64260/sdram_init.c
+++ /dev/null
@@ -1,650 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* sdram_init.c - automatic memory sizing */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include <galileo/memory.h>
-#include <galileo/pci.h>
-#include <galileo/gt64260R.h>
-#include <net.h>
-#include <linux/compiler.h>
-
-#include "eth.h"
-#include "mpsc.h"
-#include "i2c.h"
-#include "64260.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* #define DEBUG */
-#define MAP_PCI
-
-#ifdef DEBUG
-#define DP(x) x
-#else
-#define DP(x)
-#endif
-
-#define GB (1 << 30)
-
-/* structure to store the relevant information about an sdram bank */
-typedef struct sdram_info {
- uchar drb_size;
- uchar registered, ecc;
- uchar tpar;
- uchar tras_clocks;
- uchar burst_len;
- uchar banks, slot;
- int size; /* detected size, not from I2C but from dram_size() */
-} sdram_info_t;
-
-#ifdef DEBUG
-void dump_dimm_info (struct sdram_info *d)
-{
- static const char *ecc_legend[] = { "", " Parity", " ECC" };
-
- printf ("dimm%s %sDRAM: %dMibytes:\n",
- ecc_legend[d->ecc],
- d->registered ? "R" : "", (d->size >> 20));
- printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
- d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
- d->banks, d->slot);
-}
-#endif
-
-static int
-memory_map_bank (unsigned int bankNo,
- unsigned int bankBase, unsigned int bankLength)
-{
-#ifdef DEBUG
- if (bankLength > 0) {
- printf ("mapping bank %d at %08x - %08x\n",
- bankNo, bankBase, bankBase + bankLength - 1);
- } else {
- printf ("unmapping bank %d\n", bankNo);
- }
-#endif
-
- memoryMapBank (bankNo, bankBase, bankLength);
-
- return 0;
-}
-
-#ifdef MAP_PCI
-static int
-memory_map_bank_pci (unsigned int bankNo,
- unsigned int bankBase, unsigned int bankLength)
-{
- PCI_HOST host;
-
- for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
- const int features =
- PREFETCH_ENABLE |
- DELAYED_READ_ENABLE |
- AGGRESSIVE_PREFETCH |
- READ_LINE_AGGRESSIVE_PREFETCH |
- READ_MULTI_AGGRESSIVE_PREFETCH |
- MAX_BURST_4 | PCI_NO_SWAP;
-
- pciMapMemoryBank (host, bankNo, bankBase, bankLength);
-
- pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
- bankLength);
-
- pciSetRegionFeatures (host, bankNo, features, bankBase,
- bankLength);
- }
- return 0;
-}
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/* much of this code is based on (or is) the code in the pip405 port */
-/* thanks go to the authors of said port - Josh */
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NS10to10PS (unsigned char spd_byte)
-{
- unsigned short ns, ns10;
-
- /* isolate upper nibble */
- ns = (spd_byte >> 4) & 0x0F;
- /* isolate lower nibble */
- ns10 = (spd_byte & 0x0F);
-
- return (ns * 100 + ns10 * 10);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-static inline unsigned short NSto10PS (unsigned char spd_byte)
-{
- return (spd_byte * 100);
-}
-
-#ifdef CONFIG_ZUMA_V2
-static int check_dimm (uchar slot, sdram_info_t * info)
-{
- /* assume 2 dimms, 2 banks each 256M - we dont have an
- * dimm i2c so rely on the detection routines later */
-
- memset (info, 0, sizeof (*info));
-
- info->slot = slot;
- info->banks = 2; /* Detect later */
- info->registered = 0;
- info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
- but doesn't matter, both do same
- thing in setup_sdram() */
- info->tpar = 3;
- info->tras_clocks = 5;
- info->burst_len = 4;
-#ifdef CONFIG_ECC
- info->ecc = 0; /* Detect later */
-#endif /* CONFIG_ECC */
- return 0;
-}
-
-#elif defined(CONFIG_P3G4)
-
-static int check_dimm (uchar slot, sdram_info_t * info)
-{
- memset (info, 0, sizeof (*info));
-
- if (slot)
- return 0;
-
- info->slot = slot;
- info->banks = 1;
- info->registered = 0;
- info->drb_size = 4;
- info->tpar = 3;
- info->tras_clocks = 6;
- info->burst_len = 4;
-#ifdef CONFIG_ECC
- info->ecc = 2;
-#endif
- return 0;
-}
-
-#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
-
-/* This code reads the SPD chip on the sdram and populates
- * the array which is passed in with the relevant information */
-static int check_dimm (uchar slot, sdram_info_t * info)
-{
- uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
- int ret;
- uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
- ulong tmemclk;
- uchar trp_clocks, trcd_clocks;
- uchar data[128];
-
- get_clocks ();
-
- tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
-
-#ifdef CONFIG_EVB64260_750CX
- if (0 != slot) {
- printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
- printf (" called with slot=%d insetad!\n", slot);
- return 0;
- }
-#endif
- DP (puts ("before i2c read\n"));
-
- ret = i2c_read (addr, 0, 128, data, 0);
-
- DP (puts ("after i2c read\n"));
-
- /* zero all the values */
- memset (info, 0, sizeof (*info));
-
- if (ret) {
- DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
- return 0;
- }
-
- /* first, do some sanity checks */
- if (data[2] != 0x4) {
- printf ("Not SDRAM in slot %d\n", slot);
- return 0;
- }
-
- /* get various information */
- rows = data[3];
- cols = data[4];
- info->banks = data[5];
- sdram_banks = data[17];
- width = data[13] & 0x7f;
-
- DP (printf
- ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
-
- /* check if the memory is registered */
- if (data[21] & (BIT1 | BIT4))
- info->registered = 1;
-
-#ifdef CONFIG_ECC
- /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
- info->ecc = (data[11] & 2) >> 1;
-#endif
-
- /* bit 1 is CL2, bit 2 is CL3 */
- supp_cal = (data[18] & 0x6) >> 1;
-
- /* compute the relevant clock values */
- trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
- trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
- info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
-
- DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
- trp_clocks, trcd_clocks, info->tras_clocks));
-
- /* try a CAS latency of 3 first... */
- cal_val = 0;
- if (supp_cal & 3) {
- if (NS10to10PS (data[9]) <= tmemclk)
- cal_val = 3;
- }
-
- /* then 2... */
- if (supp_cal & 2) {
- if (NS10to10PS (data[23]) <= tmemclk)
- cal_val = 2;
- }
-
- DP (printf ("cal_val = %d\n", cal_val));
-
- /* bummer, did't work... */
- if (cal_val == 0) {
- DP (printf ("Couldn't find a good CAS latency\n"));
- return 0;
- }
-
- /* get the largest delay -- these values need to all be the same
- * see Res#6 */
- info->tpar = cal_val;
- if (trp_clocks > info->tpar)
- info->tpar = trp_clocks;
- if (trcd_clocks > info->tpar)
- info->tpar = trcd_clocks;
-
- DP (printf ("tpar set to: %d\n", info->tpar));
-
-#ifdef CONFIG_SYS_BROKEN_CL2
- if (info->tpar == 2) {
- info->tpar = 3;
- DP (printf ("tpar fixed-up to: %d\n", info->tpar));
- }
-#endif
- /* compute the module DRB size */
- info->drb_size =
- (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
-
- DP (printf ("drb_size set to: %d\n", info->drb_size));
-
- /* find the burst len */
- info->burst_len = data[16] & 0xf;
- if ((info->burst_len & 8) == 8) {
- info->burst_len = 1;
- } else if ((info->burst_len & 4) == 4) {
- info->burst_len = 0;
- } else {
- return 0;
- }
-
- info->slot = slot;
- return 0;
-}
-#endif /* ! CONFIG_ZUMA_V2 */
-
-static int setup_sdram_common (sdram_info_t info[2])
-{
- ulong tmp;
- int tpar = 2, tras_clocks = 5, registered = 1;
- __maybe_unused int ecc = 2;
-
- if (!info[0].banks && !info[1].banks)
- return 0;
-
- if (info[0].banks) {
- if (info[0].tpar > tpar)
- tpar = info[0].tpar;
- if (info[0].tras_clocks > tras_clocks)
- tras_clocks = info[0].tras_clocks;
- if (!info[0].registered)
- registered = 0;
- if (info[0].ecc != 2)
- ecc = 0;
- }
-
- if (info[1].banks) {
- if (info[1].tpar > tpar)
- tpar = info[1].tpar;
- if (info[1].tras_clocks > tras_clocks)
- tras_clocks = info[1].tras_clocks;
- if (!info[1].registered)
- registered = 0;
- if (info[1].ecc != 2)
- ecc = 0;
- }
-
- /* SDRAM configuration */
- tmp = GTREGREAD (SDRAM_CONFIGURATION);
-
- /* Turn on physical interleave if both DIMMs
- * have even numbers of banks. */
- if ((info[0].banks == 0 || info[0].banks == 2) &&
- (info[1].banks == 0 || info[1].banks == 2)) {
- /* physical interleave on */
- tmp &= ~(1 << 15);
- } else {
- /* physical interleave off */
- tmp |= (1 << 15);
- }
-
- tmp |= (registered << 17);
-
- /* Use buffer 1 to return read data to the CPU
- * See Res #12 */
- tmp |= (1 << 26);
-
- GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
- DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
-
- /* SDRAM timing */
- tmp = (((tpar == 3) ? 2 : 1) |
- (((tpar == 3) ? 2 : 1) << 2) |
- (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
-
-#ifdef CONFIG_ECC
- /* Setup ECC */
- if (ecc == 2)
- tmp |= 1 << 13;
-#endif /* CONFIG_ECC */
-
- GT_REG_WRITE (SDRAM_TIMING, tmp);
- DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
- GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
-
- /* SDRAM address decode register */
- /* program this with the default value */
- GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
- DP (printf ("SDRAM decode: %08x\n",
- GTREGREAD (SDRAM_ADDRESS_DECODE)));
-
- return 0;
-}
-
-/* sets up the GT properly with information passed in */
-static int setup_sdram (sdram_info_t * info)
-{
- ulong tmp;
- ulong *addr = 0;
- __maybe_unused ulong check;
- int i;
-
- /* sanity checking */
- if (!info->banks)
- return 0;
-
- /* ---------------------------- */
- /* Program the GT with the discovered data */
-
- /* bank parameters */
- tmp = (0xf << 16); /* leave all virt bank pages open */
-
- DP (printf ("drb_size: %d\n", info->drb_size));
- switch (info->drb_size) {
- case 1:
- tmp |= (1 << 14);
- break;
- case 4:
- case 8:
- tmp |= (2 << 14);
- break;
- case 16:
- case 32:
- tmp |= (3 << 14);
- break;
- default:
- printf ("Error in dram size calculation\n");
- return 1;
- }
-
- /* SDRAM bank parameters */
- /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
- GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
- GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
- DP (printf
- ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
- info->slot * 2, (info->slot * 2) + 1, tmp));
-
- /* set the SDRAM configuration for each bank */
- for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
- DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
-
- /* map the bank */
- memory_map_bank (i, 0, GB / 4);
-
- /* set SDRAM mode */
- GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
- check = GTREGREAD (SDRAM_OPERATION_MODE);
-
- /* dummy write */
- *addr = 0;
-
- /* wait for the command to complete */
- while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
-
- /* switch back to normal operation mode */
- GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
- check = GTREGREAD (SDRAM_OPERATION_MODE);
-
- /* unmap the bank */
- memory_map_bank (i, 0, 0);
- DP (printf ("*** MRS cycle for bank %d done ***\n", i));
- }
-
- return 0;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-static long int dram_size (long int *base, long int maxsize)
-{
- volatile long int *addr, *b = base;
- long int cnt, val, save1, save2;
-
-#define STARTVAL (1<<20) /* start test at 1M */
- for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
- cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save1 = *addr; /* save contents of addr */
- save2 = *b; /* save contents of base */
-
- *addr = cnt; /* write cnt to addr */
- *b = 0; /* put null at base */
-
- /* check at base address */
- if ((*b) != 0) {
- *addr = save1; /* restore *addr */
- *b = save2; /* restore *b */
- return (0);
- }
- val = *addr; /* read *addr */
-
- *addr = save1;
- *b = save2;
-
- if (val != cnt) {
- /* fix boundary condition.. STARTVAL means zero */
- if (cnt == STARTVAL / sizeof (long))
- cnt = 0;
- return (cnt * sizeof (long));
- }
- }
- return maxsize;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* U-Boot interface function to SDRAM init - this is where all the
- * controlling logic happens */
-phys_size_t initdram (int board_type)
-{
- ulong checkbank[4] = {[0 ... 3] = 0 };
- int bank_no;
- ulong total;
- int nhr;
- sdram_info_t dimm_info[2];
-
-
- /* first, use the SPD to get info about the SDRAM */
-
- /* check the NHR bit and skip mem init if it's already done */
- nhr = get_hid0 () & (1 << 16);
-
- if (nhr) {
- printf ("Skipping SDRAM setup due to NHR bit being set\n");
- } else {
- /* DIMM0 */
- check_dimm (0, &dimm_info[0]);
-
- /* DIMM1 */
-#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
- check_dimm (1, &dimm_info[1]);
-#else /* CONFIG_EVB64260_750CX */
- memset (&dimm_info[1], 0, sizeof (sdram_info_t));
-#endif
-
- /* unmap all banks */
- memory_map_bank (0, 0, 0);
- memory_map_bank (1, 0, 0);
- memory_map_bank (2, 0, 0);
- memory_map_bank (3, 0, 0);
-
- /* Now, program the GT with the correct values */
- if (setup_sdram_common (dimm_info)) {
- printf ("Setup common failed.\n");
- }
-
- if (setup_sdram (&dimm_info[0])) {
- printf ("Setup for DIMM1 failed.\n");
- }
-
- if (setup_sdram (&dimm_info[1])) {
- printf ("Setup for DIMM2 failed.\n");
- }
-
- /* set the NHR bit */
- set_hid0 (get_hid0 () | (1 << 16));
- }
- /* next, size the SDRAM banks */
-
- total = 0;
- if (dimm_info[0].banks > 0)
- checkbank[0] = 1;
- if (dimm_info[0].banks > 1)
- checkbank[1] = 1;
- if (dimm_info[0].banks > 2)
- printf ("Error, SPD claims DIMM1 has >2 banks\n");
-
- if (dimm_info[1].banks > 0)
- checkbank[2] = 1;
- if (dimm_info[1].banks > 1)
- checkbank[3] = 1;
- if (dimm_info[1].banks > 2)
- printf ("Error, SPD claims DIMM2 has >2 banks\n");
-
- /* Generic dram sizer: works even if we don't have i2c DIMMs,
- * as long as the timing settings are more or less correct */
-
- /*
- * pass 1: size all the banks, using first bat (0-256M)
- * limitation: we only support 256M per bank due to
- * us only having 1 BAT for all DRAM
- */
- for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
- /* skip over banks that are not populated */
- if (!checkbank[bank_no])
- continue;
-
- DP (printf ("checking bank %d\n", bank_no));
-
- memory_map_bank (bank_no, 0, GB / 4);
- checkbank[bank_no] = dram_size (NULL, GB / 4);
- memory_map_bank (bank_no, 0, 0);
-
- DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
- }
-
- /*
- * pass 2: contiguously map each bank into physical address
- * space.
- */
- dimm_info[0].banks = dimm_info[1].banks = 0;
- for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
- if (!checkbank[bank_no])
- continue;
-
- dimm_info[bank_no / 2].banks++;
- dimm_info[bank_no / 2].size += checkbank[bank_no];
-
- memory_map_bank (bank_no, total, checkbank[bank_no]);
-#ifdef MAP_PCI
- memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
-#endif
- total += checkbank[bank_no];
- }
-
-#ifdef CONFIG_ECC
-#ifdef CONFIG_ZUMA_V2
- /*
- * We always enable ECC when bank 2 and 3 are unpopulated
- * If we 2 or 3 are populated, we CAN'T support ECC.
- * (Zuma boards only support ECC in banks 0 and 1; assume that
- * in that configuration, ECC chips are mounted, even for stacked
- * chips)
- */
- if (checkbank[2] == 0 && checkbank[3] == 0) {
- dimm_info[0].ecc = 2;
- GT_REG_WRITE (SDRAM_TIMING,
- GTREGREAD (SDRAM_TIMING) | (1 << 13));
- /* TODO: do we have to run MRS cycles again? */
- }
-#endif /* CONFIG_ZUMA_V2 */
-
- if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
- puts ("[ECC] ");
- }
-#endif /* CONFIG_ECC */
-
-#ifdef DEBUG
- dump_dimm_info (&dimm_info[0]);
- dump_dimm_info (&dimm_info[1]);
-#endif
- /* TODO: return at MOST 256M? */
- /* return total > GB/4 ? GB/4 : total; */
- return total;
-}
diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c
deleted file mode 100644
index 83a4217..0000000
--- a/board/evb64260/serial.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * serial.c - serial support for the gal ev board
- */
-
-/* supports both the 16650 duart and the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <galileo/memory.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
-#include <ns16550.h>
-#endif
-
-#include "mpsc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
-const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1,
- (NS16550_t) CONFIG_SYS_NS16550_COM2 };
-#endif
-
-#ifdef CONFIG_MPSC
-
-static int evb64260_serial_init(void)
-{
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-#endif
-
- mpsc_init(gd->baudrate);
-
- /* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit(COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit(COM_PORTS[1], clock_divisor);
-#endif
- return (0);
-}
-
-static void evb64260_serial_putc(const char c)
-{
- if (c == '\n')
- mpsc_putchar('\r');
-
- mpsc_putchar(c);
-}
-
-static int evb64260_serial_getc(void)
-{
- return mpsc_getchar();
-}
-
-static int evb64260_serial_tstc(void)
-{
- return mpsc_test_char();
-}
-
-static void evb64260_serial_setbrg(void)
-{
- galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-#else /* ! CONFIG_MPSC */
-
-static int evb64260_serial_init(void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- (void)NS16550_init(COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- (void)NS16550_init(COM_PORTS[1], clock_divisor);
-#endif
-
- return (0);
-}
-
-static void evb64260_serial_putc(const char c)
-{
- if (c == '\n')
- NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
- NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-static int evb64260_serial_getc(void)
-{
- return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static int evb64260_serial_tstc(void)
-{
- return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static void evb64260_serial_setbrg(void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit(COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit(COM_PORTS[1], clock_divisor);
-#endif
-}
-
-#endif /* CONFIG_MPSC */
-
-static struct serial_device evb64260_serial_drv = {
- .name = "evb64260_serial",
- .start = evb64260_serial_init,
- .stop = NULL,
- .setbrg = evb64260_serial_setbrg,
- .putc = evb64260_serial_putc,
- .puts = default_serial_puts,
- .getc = evb64260_serial_getc,
- .tstc = evb64260_serial_tstc,
-};
-
-void evb64260_serial_initialize(void)
-{
- serial_register(&evb64260_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &evb64260_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void
-kgdb_serial_init(void)
-{
-}
-
-void
-putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void
-putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int
-getDebugChar (void)
-{
- return serial_getc();
-}
-
-void
-kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds
deleted file mode 100644
index 712df6d..0000000
--- a/board/evb64260/u-boot.lds
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- .text :
- {
- arch/powerpc/cpu/74xx_7xx/start.o (.text*)
- *(.text*)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.ppcenv*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c
deleted file mode 100644
index aa15fa0..0000000
--- a/board/evb64260/zuma_pbb.c
+++ /dev/null
@@ -1,220 +0,0 @@
-#include <common.h>
-#include <malloc.h>
-
-#if defined(CONFIG_CMD_BSP)
-#include <command.h>
-#endif
-
-#include <pci.h>
-#include <galileo/pci.h>
-#include "zuma_pbb.h"
-
-#undef DEBUG
-
-#define PAT_LO 0x00010203
-#define PAT_HI 0x04050607
-
-static PBB_DMA_REG_MAP *zuma_pbb_reg = NULL;
-static char test_buf1[2048];
-static char test_buf2[2048];
-void zuma_init_pbb(void);
-int zuma_mbox_init(void);
-int zuma_test_dma(int cmd, int size);
-
-int zuma_test_dma (int cmd, int size)
-{
- static const char *const test_legend[] = {
- "write", "verify",
- "copy", "compare",
- "write inc", "verify inc"
- };
- register int i, j;
- unsigned int p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff);
- unsigned int p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff);
- volatile unsigned int *ps = (unsigned int *) p1;
- volatile unsigned int *pd = (unsigned int *) p2;
- unsigned int funct, pat_lo = PAT_LO, pat_hi = PAT_HI;
- DMA_INT_STATUS stat;
- int ret = 0;
-
- if (!zuma_pbb_reg) {
- printf ("not initted\n");
- return -1;
- }
-
- if (cmd < 0 || cmd > 5) {
- printf ("inv cmd %d\n", cmd);
- return -1;
- }
-
- if (cmd == 2 || cmd == 3) {
- /* not implemented */
- return 0;
- }
-
- if (size <= 0 || size > 1024)
- size = 1024;
-
- size &= (~7); /* throw away bottom 3 bits */
-
- p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff);
- p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff);
-
- memset ((void *) p1, 0, size);
- memset ((void *) p2, 0, size);
-
- for (i = 0; i < size / 4; i += 2) {
- ps[i] = pat_lo;
- ps[i + 1] = pat_hi;
- if (cmd == 4 || cmd == 5) {
- unsigned char *pl = (unsigned char *) &pat_lo;
- unsigned char *ph = (unsigned char *) &pat_hi;
-
- for (j = 0; j < 4; j++) {
- pl[j] += 8;
- ph[j] += 8;
- }
- }
- }
-
- funct = (1 << 31) | (cmd << 24) | (size);
-
- zuma_pbb_reg->int_mask.pci_bits.chan0 =
- EOF_RX_FLAG | EOF_TX_FLAG | EOB_TX_FLAG;
-
- zuma_pbb_reg->debug_57 = PAT_LO; /* patl */
- zuma_pbb_reg->debug_58 = PAT_HI; /* path */
-
- zuma_pbb_reg->debug_54 = cpu_to_le32 (p1); /* src 0x01b0 */
- zuma_pbb_reg->debug_55 = cpu_to_le32 (p2); /* dst 0x01b8 */
- zuma_pbb_reg->debug_56 = cpu_to_le32 (funct); /* func, 0x01c0 */
-
- /* give DMA time to chew on things.. dont use DRAM or PCI */
- /* if you can avoid it. */
- do {
- for (i = 0; i < 1000 * 10; i++);
- } while (le32_to_cpu (zuma_pbb_reg->debug_56) & (1 << 31));
-
- stat.word = zuma_pbb_reg->status.word;
- zuma_pbb_reg->int_mask.word = 0;
-
- printf ("stat: %08x (%x)\n", stat.word, stat.pci_bits.chan0);
-
- printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56));
- printf ("src @%08x: %08x %08x %08x %08x\n", p1, ps[0], ps[1], ps[2],
- ps[3]);
- printf ("dst @%08x: %08x %08x %08x %08x\n", p2, pd[0], pd[1], pd[2],
- pd[3]);
- printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56));
-
-
- if (cmd == 0 || cmd == 4) {
- /* this is a write */
- if (!(stat.pci_bits.chan0 & EOF_RX_FLAG) || /* not done */
- (memcmp ((void *) ps, (void *) pd, size) != 0)) { /* cmp error */
- for (i = 0; i < size / 4; i += 2) {
- if ((ps[i] != pd[i]) || (ps[i + 1] != pd[i + 1])) {
- printf ("s @%p:%08x %08x\n", &ps[i], ps[i], ps[i + 1]);
- printf ("d @%p:%08x %08x\n", &pd[i], pd[i], pd[i + 1]);
- }
- }
- ret = -1;
- }
- } else {
- /* this is a verify */
- if (!(stat.pci_bits.chan0 & EOF_TX_FLAG) || /* not done */
- (stat.pci_bits.chan0 & EOB_TX_FLAG)) { /* cmp error */
- printf ("%08x: %08x %08x\n",
- le32_to_cpu (zuma_pbb_reg->debug_63),
- zuma_pbb_reg->debug_61, zuma_pbb_reg->debug_62);
- ret = -1;
- }
- }
-
- printf ("%s cmd %d, %d bytes: %s!\n", test_legend[cmd], cmd, size,
- (ret == 0) ? "PASSED" : "FAILED");
- return 0;
-}
-
-void zuma_init_pbb (void)
-{
- unsigned int iobase;
- pci_dev_t dev =
- pci_find_device (VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
-
- if (dev == -1) {
- printf ("no zuma pbb\n");
- return;
- }
-
- pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase);
-
- iobase &= PCI_BASE_ADDRESS_MEM_MASK;
-
- zuma_pbb_reg = (PBB_DMA_REG_MAP *)iobase;
-
-
- if (!zuma_pbb_reg) {
- printf ("zuma pbb bar none! (hah hah, get it?)\n");
- return;
- }
-
- zuma_pbb_reg->int_mask.word = 0;
-
- printf ("pbb @ %p v%d.%d, timestamp %08x\n", zuma_pbb_reg,
- zuma_pbb_reg->version.pci_bits.rev_major,
- zuma_pbb_reg->version.pci_bits.rev_minor,
- zuma_pbb_reg->timestamp);
-
-}
-
-#if defined(CONFIG_CMD_BSP)
-
-static int last_cmd = 4; /* write increment */
-static int last_size = 64;
-
-int
-do_zuma_init_pbb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- zuma_init_pbb ();
- return 0;
-}
-
-int
-do_zuma_test_dma (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc > 1) {
- last_cmd = simple_strtoul (argv[1], NULL, 10);
- }
- if (argc > 2) {
- last_size = simple_strtoul (argv[2], NULL, 10);
- }
- zuma_test_dma (last_cmd, last_size);
- return 0;
-}
-
-int
-do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- zuma_mbox_init ();
- return 0;
-}
-
-U_BOOT_CMD(
- zinit, 1, 0, do_zuma_init_pbb,
- "init zuma pbb",
- "\n"
-);
-U_BOOT_CMD(
- zdtest, 3, 1, do_zuma_test_dma,
- "run dma test",
- "[cmd [count]]\n"
- " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes"
-);
-U_BOOT_CMD(
- zminit, 1, 0, do_zuma_init_mbox,
- "init zuma mbox",
- "\n"
-);
-
-#endif
diff --git a/board/evb64260/zuma_pbb.h b/board/evb64260/zuma_pbb.h
deleted file mode 100644
index 300b2fe..0000000
--- a/board/evb64260/zuma_pbb.h
+++ /dev/null
@@ -1,346 +0,0 @@
-#ifndef ZUMA_PBB_H
-#define ZUMA_PBB_H
-
-#define MAX_NUM_BUFFER_PER_RING 32
-
-#ifdef __BIG_ENDIAN
-#define cpu_bits _be_s_bits /* use with le32_to_cpu only */
-#define pci_bits _be_bits /* may contain swapped bytes,
- but dont need le32_to_cpu */
-#endif
-
-#ifdef __LITTLE_ENDIAN
-#define cpu_bits _le_bits
-#define pci_bits _le_bits
-#endif
-
-#define VENDOR_ID_ZUMA 0x1172
-#define DEVICE_ID_ZUMA_PBB 0x0004
-
-#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch*8 */
-#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch*8 + 4 */
-#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch*8 + 64 */
-#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch*8 + 68 */
-
-#define PBB_DMA_OWN_BIT 0x80000000
-#define PBB_DMA_LAST_BIT 0x40000000
-
-#define EOF_RX_FLAG 1 /* bit 0 */
-#define EOB_RX_FLAG 2 /* bit 1 */
-#define EOF_TX_FLAG 4 /* bit 2 */
-#define EOB_TX_FLAG 8 /* bit 3 */
-
-#define TX_MODE(m) (((m)&7) << 16)
-
-#define RX_DESC(i) (cs->rx_desc[i])
-#define TX_DESC(i) (cs->tx_desc[i])
-
-#define RX_CONTROL(i) (RX_DESC(i).control.word)
-#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size)
-#define TX_CONTROL(i) (TX_DESC(i).control.word)
-
-#define RX_DATA_P(i) (&RX_DESC(i).ptr)
-#define TX_DATA_P(i) (&TX_DESC(i).ptr)
-
-typedef volatile unsigned char V8;
-typedef volatile unsigned short V16;
-typedef volatile unsigned int V32;
-
-/* RAM descriptor layout */
-typedef struct _tag_dma_descriptor {
- V32 ptr;
- union {
- struct {
- V32 owner:1;
- V32 last:1;
- V32 reserved0: 10;
- V32 tx_mode: 4;
-
- V32 reserved1: 5;
- V32 size: 11;
- } tx;
- struct {
- V32 owner:1;
- V32 last:1;
- V32 reserved0: 14;
-
- V32 reserved1: 5;
- V32 size: 11;
- } rx;
- V32 word;
- } control;
-} DMA_DESCRIPTOR;
-
-/*
- * NOTE: DO NOT USE structure to write non-word values... all registers
- * MUST be written 4 bytes at a time in SI version 0.
- * Non-word writes will result in "unaccessed" bytes written as zero.
- *
- * Byte reads are allowed.
- *
- * V32 pads are because the registers are spaced every 8 bytes (64 bits)
- *
- */
-
-/* NOTE!!! 4 dwords */
-typedef struct _tag_dma_descriptor_ring {
- DMA_DESCRIPTOR *base;
- V32 pad1; /* skip high dword */
- volatile DMA_DESCRIPTOR *current;
- V32 pad3; /* skip high dword */
-} DMA_DESCRIPTOR_RING;
-
-/* 1 dword */
-typedef union _tag_dma_generic {
- struct { /* byte 3 2 1 0 */
- V32 chan7:4; /* bits 31-28 */
- V32 chan6:4; /* bits 27-24 */
- V32 chan5:4; /* bits 23-20 */
- V32 chan4:4; /* bits 19-16 */
- V32 chan3:4; /* bits 15-12 */
- V32 chan2:4; /* bits 11-8 */
- V32 chan1:4; /* bits 7-4 */
- V32 chan0:4; /* bits 3-0 */
- } _be_s_bits;
- struct { /* byte 0 1 2 3 */
- V32 chan1:4; /* bits 7-4 */
- V32 chan0:4; /* bits 3-0 */
- V32 chan3:4; /* bits 15-12 */
- V32 chan2:4; /* bits 11-8 */
- V32 chan5:4; /* bits 23-20 */
- V32 chan4:4; /* bits 19-16 */
- V32 chan7:4; /* bits 31-28 */
- V32 chan6:4; /* bits 27-24 */
- } _be_bits;
- struct { /* byte 0 1 2 3 */
- V32 chan0:4; /* bits 0-3 */
- V32 chan1:4; /* bits 4-7 */
- V32 chan2:4; /* bits 8-11 */
- V32 chan3:4; /* bits 12-15 */
- V32 chan4:4; /* bits 16-19 */
- V32 chan5:4; /* bits 20-23 */
- V32 chan6:4; /* bits 24-27 */
- V32 chan7:4; /* bits 28-31 */
- } _le_bits;
- V8 byte[4];
- V32 word;
-} DMA_RXTX_ENABLE, DMA_RX_DELETE,
- DMA_INT_STATUS, DMA_INT_MASK,
- DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK;
-
-/* 1 dword */
-typedef union _tag_dma_rx_timer{
- struct {
- V32 res0:8; /* bits 32-24 */
- V32 res1:7; /* bits 23-17 */
- V32 enable:1; /* bit 16 */
- V32 value:16; /* bits 15-0 */
- } _be_s_bits;
- struct {
- /* crosses byte boundary. must use swap. */
- V32 s_value:16; /* bits 7-0,15-8 */
- V32 enable:1; /* bit 16 */
- V32 res1:7; /* bits 23-17 */
- V32 res0:8; /* bits 32-24 */
- } _be_bits;
- struct {
- V32 value:16; /* bits 0-15 */
- V32 enable:1; /* bit 16 */
- V32 res1:7; /* bits 17-23 */
- V32 res0:8; /* bits 24-32 */
- } _le_bits;
- V8 byte[4];
- V32 word;
-} DMA_RX_TIMER;
-
-/* NOTE!!!: 2 dwords */
-typedef struct _tag_dma_desc_level{
- union {
- struct {
- V32 res1:8; /* bits 31-24 */
- V32 res0:7; /* bits 23-17 */
- V32 write:1; /* bit 16 */
- V32 thresh:8; /* bits 15-8 */
- V32 level:8; /* bits 7-0 */
- } _be_s_bits;
- struct {
- V32 level:8; /* bits 7-0 */
- V32 thresh:8; /* bits 15-8 */
- V32 res0:7; /* bits 30-17 */
- V32 write:1; /* bit 16 */
- V32 res1:8; /* bits 31-24 */
- } _be_bits;
- struct {
- V32 level:8; /* bits 0-7 */
- V32 thresh:8; /* bits 8-15 */
- V32 write:1; /* bit 16 */
- V32 res0:7; /* bit 17-30 */
- V32 res1:8; /* bits 24-31 */
- } _le_bits;
- V8 byte[4];
- V32 word;
- } desc;
- V32 pad1;
-} DMA_DESC_LEVEL;
-
-typedef struct _tag_pbb_dma_reg_map {
- /* 0-15 (0x000-0x078) */
- DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */
-
- /* 16-31 (0x080-0x0f8) */
- DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */
-
- /* 32/33 (0x100/0x108) */
- V32 reserved_32;
- V32 pad_32;
- V32 reserved_33;
- V32 pad_33;
-
- /* 34 (0x110) */
- DMA_RXTX_ENABLE rxtx_enable;
- V32 pad_34;
-
- /* 35 (0x118) */
- DMA_RX_DELETE rx_delete;
- V32 pad_35;
-
- /* 36-38 (0x120-0x130) */
- DMA_INT_STATUS status;
- V32 pad_36;
- DMA_INT_STATUS last_status;
- V32 pad_37;
- DMA_INT_MASK int_mask;
- V32 pad_38;
-
- /* 39/40 (0x138/0x140) */
- union {
- /* NOTE!! 4 dwords */
- struct {
- V32 channel_3:8;
- V32 channel_2:8;
- V32 channel_1:8;
- V32 channel_0:8;
- V32 pad1;
- V32 channel_7:8;
- V32 channel_6:8;
- V32 channel_5:8;
- V32 channel_4:8;
- V32 pad3;
- } _be_s_bits;
- struct {
- V32 channel_0:8;
- V32 channel_1:8;
- V32 channel_2:8;
- V32 channel_3:8;
- V32 pad1;
- V32 channel_4:8;
- V32 channel_5:8;
- V32 channel_6:8;
- V32 channel_7:8;
- V32 pad3;
- } _be_bits, _le_bits;
- V8 byte[16];
- V32 word[4];
- } rx_size;
-
- /* 41/42 (0x148/0x150) */
- V32 reserved_41;
- V32 pad_41;
- V32 reserved_42;
- V32 pad_42;
-
- /* 43/44 (0x158/0x160) */
- DMA_RX_LEVEL_STATUS rx_level_status;
- V32 pad_43;
- DMA_RX_LEVEL_INT_MASK rx_level_int_mask;
- V32 pad_44;
-
- /* 45 (0x168) */
- DMA_RX_TIMER rx_timer;
- V32 pad_45;
-
- /* 46 (0x170) */
- V32 reserved_46;
- V32 pad_46;
-
- /* 47 (0x178) */
- V32 mbox_status;
- V32 pad_47;
-
- /* 48/49 (0x180/0x188) */
- V32 mbox_out;
- V32 pad_48;
- V32 mbox_in;
- V32 pad_49;
-
- /* 50 (0x190) */
- V32 config;
- V32 pad_50;
-
- /* 51/52 (0x198/0x1a0) */
- V32 c2a_ctr;
- V32 pad_51;
- V32 a2c_ctr;
- V32 pad_52;
-
- /* 53 (0x1a8) */
- union {
- struct {
- V32 rev_major:8; /* bits 31-24 */
- V32 rev_minor:8; /* bits 23-16 */
- V32 reserved:16; /* bits 15-0 */
- } _be_s_bits;
- struct {
- V32 s_reserved:16; /* bits 7-0, 15-8 */
- V32 rev_minor:8; /* bits 23-16 */
- V32 rev_major:8; /* bits 31-24 */
- } _be_bits;
- struct {
- V32 reserved:16; /* bits 0-15 */
- V32 rev_minor:8; /* bits 16-23 */
- V32 rev_major:8; /* bits 24-31 */
- } _le_bits;
- V8 byte[4];
- V32 word;
- } version;
- V32 pad_53;
-
- /* 54-59 (0x1b0-0x1d8) */
- V32 debug_54;
- V32 pad_54;
- V32 debug_55;
- V32 pad_55;
- V32 debug_56;
- V32 pad_56;
- V32 debug_57;
- V32 pad_57;
- V32 debug_58;
- V32 pad_58;
- V32 debug_59;
- V32 pad_59;
-
- /* 60 (0x1e0) */
- V32 timestamp;
- V32 pad_60;
-
- /* 61-63 (0x1e8-0x1f8) */
- V32 debug_61;
- V32 pad_61;
- V32 debug_62;
- V32 pad_62;
- V32 debug_63;
- V32 pad_63;
-
- /* 64-71 (0x200 - 0x238) */
- DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */
-
- /* 72-98 (0x240 - 0x2f8) */
- /* reserved */
-
- /* 96-127 (0x300 - 0x3f8) */
- /* mirrors (0x100 - 0x1f8) */
-
-} PBB_DMA_REG_MAP;
-
-
-#endif /* ZUMA_PBB_H */
diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c
deleted file mode 100644
index 621c64c..0000000
--- a/board/evb64260/zuma_pbb_mbox.c
+++ /dev/null
@@ -1,208 +0,0 @@
-#include <common.h>
-#include <galileo/pci.h>
-#include <net.h>
-#include <pci.h>
-
-#include "zuma_pbb.h"
-#include "zuma_pbb_mbox.h"
-
-
-struct _zuma_mbox_dev zuma_mbox_dev;
-
-
-static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data)
-{
- unsigned int status, count = 0, i;
-
- status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
-
- while ((status & OUT_PENDING) && count < 1000) {
- count++;
- for (i = 0; i < 1000; i++)
- ;
- status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
- }
- if (count < 1000) {
- /* if SET it means msg pending */
- /* printf("mbox real write %08x\n",data); */
- dev->sip->mbox_out = cpu_to_le32(data);
- return 4;
- }
-
- printf("mbox tx timeout\n");
- return 0;
-}
-
-static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data)
-{
- unsigned int status, count = 0, i;
-
- status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
-
- while (!(status & IN_VALID) && count < 1000) {
- count++;
- for (i = 0; i < 1000; i++)
- ;
- status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
- }
- if (count < 1000) {
- /* if SET it means msg pending */
- *data = le32_to_cpu(dev->sip->mbox_in);
- /*printf("mbox real read %08x\n", *data); */
- return 4;
- }
- printf("mbox rx timeout\n");
- return 0;
-}
-
-static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in)
-{
- int ret;
-
- ret = zuma_mbox_write(&zuma_mbox_dev, out);
- /*printf("write 0x%08x (%d bytes)\n", out, ret); */
- if (ret != 4)
- return -1;
- ret = zuma_mbox_read(&zuma_mbox_dev, in);
- /*printf("read 0x%08x (%d bytes)\n", *in, ret); */
- if (ret != 4)
- return -1;
- return 0;
-}
-
-
-#define RET_IF_FAILED(x) if ((x) == -1) return -1
-
-static int zuma_mbox_do_all_mailbox(void)
-{
- unsigned int data_in;
- unsigned short sdata_in;
-
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in));
-
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in));
- memcpy(zuma_acc_mac + 2, &data_in, 4);
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in));
- sdata_in = data_in & 0xffff;
- memcpy(zuma_acc_mac, &sdata_in, 2);
-
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in));
- zuma_ip = data_in;
-
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in));
- zuma_slot_bac = data_in >> 3;
-
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in));
- zuma_console_baud = data_in & 0xffff;
- zuma_debug_baud = data_in >> 16;
-
- RET_IF_FAILED(zuma_mbox_do_one_mailbox
- (ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in));
- memcpy(zuma_prv_mac + 2, &data_in, 4);
- RET_IF_FAILED(zuma_mbox_do_one_mailbox
- (ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in));
- sdata_in = data_in & 0xffff;
- memcpy(zuma_prv_mac, &sdata_in, 2);
-
- RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in));
-
- return 0;
-}
-
-
-static void zuma_mbox_dump(void)
-{
- unsigned short s;
- unsigned int i;
-
- memcpy(&s, &zuma_acc_mac, sizeof(s));
- memcpy(&i, &zuma_acc_mac[2], sizeof(i));
- printf("ACC MAC=%04x%08x\n", s, i);
-
- memcpy(&s, &zuma_prv_mac, sizeof(s));
- memcpy(&s, &zuma_prv_mac[2], sizeof(i));
- printf("PRV MAC=%04x%08x\n", s, i);
-
- printf("slot:bac=%d:%d\n",
- (zuma_slot_bac >> 2) & 0xf,
- zuma_slot_bac & 0x3);
-
- printf("BAUD1=%d BAUD2=%d\n",
- zuma_console_baud,
- zuma_debug_baud);
-}
-
-
-static void zuma_mbox_setenv(void)
-{
- char *data, buf[32];
- unsigned char save = 0;
-
- data = getenv("baudrate");
-
- if (!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) {
- sprintf(buf, "%6d", zuma_console_baud);
- setenv("baudrate", buf);
- save = 1;
- printf("baudrate doesn't match from mbox\n");
- }
-
- ip_to_string(zuma_ip, buf);
- setenv("ipaddr", buf);
-
- sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
- zuma_prv_mac[0],
- zuma_prv_mac[1],
- zuma_prv_mac[2],
- zuma_prv_mac[3], zuma_prv_mac[4], zuma_prv_mac[5]);
- setenv("ethaddr", buf);
-
- sprintf(buf, "%02x", zuma_slot_bac);
- setenv("bacslot", buf);
-
- if (save)
- saveenv();
-}
-
-/**
- * zuma_mbox_init:
- */
-
-int zuma_mbox_init(void)
-{
- unsigned int iobase;
-
- memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev));
-
- zuma_mbox_dev.dev =
- pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
-
- if (zuma_mbox_dev.dev == -1) {
- printf("no zuma pbb\n");
- return -1;
- }
-
- pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase);
-
- iobase &= PCI_BASE_ADDRESS_MEM_MASK;
-
- zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) iobase;
-
- zuma_mbox_dev.sip->int_mask.word = 0;
-
- printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip,
- zuma_mbox_dev.sip->version.pci_bits.rev_major,
- zuma_mbox_dev.sip->version.pci_bits.rev_minor,
- zuma_mbox_dev.sip->timestamp);
-
- if (zuma_mbox_do_all_mailbox() == -1) {
- printf("mailbox failed.. no ACC?\n");
- return -1;
- }
-
- zuma_mbox_dump();
-
- zuma_mbox_setenv();
-
- return 0;
-}
diff --git a/board/evb64260/zuma_pbb_mbox.h b/board/evb64260/zuma_pbb_mbox.h
deleted file mode 100644
index b4a4c0c..0000000
--- a/board/evb64260/zuma_pbb_mbox.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#define IN_VALID 1
-#define OUT_PENDING 2
-
-enum {
- ZUMA_MBOXMSG_DONE,
- ZUMA_MBOXMSG_MACL,
- ZUMA_MBOXMSG_MACH,
- ZUMA_MBOXMSG_IP,
- ZUMA_MBOXMSG_SLOT,
- ZUMA_MBOXMSG_RESET,
- ZUMA_MBOXMSG_BAUD,
- ZUMA_MBOXMSG_START,
- ZUMA_MBOXMSG_ENG_PRV_MACL,
- ZUMA_MBOXMSG_ENG_PRV_MACH,
-
- MBOXMSG_LAST
-};
-
-struct zuma_mailbox_info {
- unsigned char acc_mac[6];
- unsigned char prv_mac[6];
- unsigned int ip;
- unsigned int slot_bac;
- unsigned int console_baud;
- unsigned int debug_baud;
-};
-
-struct _zuma_mbox_dev {
- pci_dev_t dev;
- PBB_DMA_REG_MAP *sip;
- struct zuma_mailbox_info mailbox;
-};
-
-#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac
-#define zuma_acc_mac zuma_mbox_dev.mailbox.acc_mac
-#define zuma_ip zuma_mbox_dev.mailbox.ip
-#define zuma_slot_bac zuma_mbox_dev.mailbox.slot_bac
-#define zuma_console_baud zuma_mbox_dev.mailbox.console_baud
-#define zuma_debug_baud zuma_mbox_dev.mailbox.debug_baud
-
-
-extern struct _zuma_mbox_dev zuma_mbox_dev;
-extern int zuma_mbox_init (void);
diff --git a/board/freescale/c29xpcie/MAINTAINERS b/board/freescale/c29xpcie/MAINTAINERS
index db2e5e3..3308839 100644
--- a/board/freescale/c29xpcie/MAINTAINERS
+++ b/board/freescale/c29xpcie/MAINTAINERS
@@ -6,3 +6,5 @@
F: configs/C29XPCIE_defconfig
F: configs/C29XPCIE_NAND_defconfig
F: configs/C29XPCIE_SPIFLASH_defconfig
+F: configs/C29XPCIE_NOR_SECBOOT_defconfig
+F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index 5f7a67d..1eb3786 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -63,7 +63,7 @@
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS)
+#if defined(CONFIG_MPC8569MDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, &val8, 1);
i2c_write(0x20, 0x7, 1, &val8, 1);
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index c8ca674..745847c 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -27,3 +27,4 @@
F: configs/P5040DS_NAND_defconfig
F: configs/P5040DS_SDCARD_defconfig
F: configs/P5040DS_SPIFLASH_defconfig
+F: configs/P5040DS_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
index 638833d..661526b 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -6,6 +6,7 @@
F: configs/ls1021aqds_nor_defconfig
F: configs/ls1021aqds_ddr4_nor_defconfig
F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+F: configs/ls1021aqds_nor_lpuart_defconfig
F: configs/ls1021aqds_sdcard_defconfig
F: configs/ls1021aqds_qspi_defconfig
F: configs/ls1021aqds_nand_defconfig
diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
index 3b6903c..ab02344 100644
--- a/board/freescale/ls1021aqds/Makefile
+++ b/board/freescale/ls1021aqds/Makefile
@@ -7,3 +7,4 @@
obj-y += ls1021aqds.o
obj-y += ddr.o
obj-y += eth.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
new file mode 100644
index 0000000..90f5bc0
--- /dev/null
+++ b/board/freescale/ls1021aqds/dcu.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <i2c.h>
+#include "div64.h"
+#include "../common/diu_ch7301.h"
+#include "ls1021aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long long div;
+
+ div = (unsigned long long)(gd->bus_clk / 1000);
+ div *= (unsigned long long)pixclock;
+ do_div(div, 1000000000);
+
+ return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
+{
+ const char *name;
+ unsigned int pixel_format;
+ int ret;
+ u8 ch;
+
+ /* Mux I2C3+I2C4 as HSYNC+VSYNC */
+ ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+ 1, &ch, 1);
+ if (ret) {
+ printf("Error: failed to read I2C @%02x\n",
+ CONFIG_SYS_I2C_QIXIS_ADDR);
+ return ret;
+ }
+ ch &= 0x1F;
+ ch |= 0xA0;
+ ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+ 1, &ch, 1);
+ if (ret) {
+ printf("Error: failed to write I2C @%02x\n",
+ CONFIG_SYS_I2C_QIXIS_ADDR);
+ return ret;
+ }
+
+ if (strncmp(port, "hdmi", 4) == 0) {
+ unsigned long pixval;
+
+ name = "HDMI";
+
+ pixval = 1000000000 / dcu_fb_videomode->pixclock;
+ pixval *= 1000;
+
+ i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+ select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
+ diu_set_dvi_encoder(pixval);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ } else {
+ return 0;
+ }
+
+ printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+ pixel_format = 32;
+ fsl_dcu_init(xres, yres, pixel_format);
+
+ return 0;
+}
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index a539ff9..6435bf9 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -149,6 +150,17 @@
}
#endif
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -159,6 +171,11 @@
#else
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index f08e54f..20eade4 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -20,6 +20,7 @@
#include <fsl_sec.h>
#include <spl.h>
+#include "../common/sleep.h"
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
#ifdef CONFIG_U_QE
@@ -48,6 +49,12 @@
MUX_TYPE_SD_PC_SG_SG,
};
+enum {
+ GE0_CLK125,
+ GE2_CLK125,
+ GE1_CLK125,
+};
+
int checkboard(void)
{
#ifndef CONFIG_QSPI_BOOT
@@ -177,7 +184,6 @@
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
- out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
#ifdef CONFIG_FSL_IFC
@@ -188,6 +194,24 @@
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+#ifdef CONFIG_FSL_DCU_FB
+ out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A7 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
* instruction. Set CCI-400 control override register to
@@ -195,6 +219,11 @@
* allow barrier transaction to DDR again */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
return 0;
}
@@ -219,9 +248,6 @@
pinctl);
#endif
- /* Set global data pointer */
- gd = &gdata;
-
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -231,6 +257,11 @@
get_clocks();
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
@@ -244,6 +275,32 @@
}
#endif
+void config_etseccm_source(int etsec_gtx_125_mux)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ switch (etsec_gtx_125_mux) {
+ case GE0_CLK125:
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
+ debug("etseccm set to GE0_CLK125\n");
+ break;
+
+ case GE2_CLK125:
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+ debug("etseccm set to GE2_CLK125\n");
+ break;
+
+ case GE1_CLK125:
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
+ debug("etseccm set to GE1_CLK125\n");
+ break;
+
+ default:
+ printf("Error! trying to set etseccm to invalid value\n");
+ break;
+ }
+}
+
int config_board_mux(int ctrl_type)
{
u8 reg12, reg14;
@@ -253,6 +310,7 @@
switch (ctrl_type) {
case MUX_TYPE_CAN:
+ config_etseccm_source(GE2_CLK125);
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
break;
case MUX_TYPE_IIC2:
@@ -262,6 +320,7 @@
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
break;
case MUX_TYPE_SAI:
+ config_etseccm_source(GE2_CLK125);
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
break;
case MUX_TYPE_SDHC:
@@ -474,13 +533,6 @@
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
- /*
- * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -503,6 +555,21 @@
return 0;
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+ struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to
+ * enable barrier transaction */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+}
+#endif
+
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
index 09b3be2..8e482eb 100644
--- a/board/freescale/ls1021aqds/ls1021aqds_qixis.h
+++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
@@ -32,4 +32,6 @@
#define QIXIS_SRDS1CLK_100 0x0
+#define QIXIS_DCU_BRDCFG5 0x55
+
#endif
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
index 9176706..e9f6f0a 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -5,5 +5,6 @@
F: include/configs/ls1021atwr.h
F: configs/ls1021atwr_nor_defconfig
F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+F: configs/ls1021atwr_nor_lpuart_defconfig
F: configs/ls1021atwr_sdcard_defconfig
F: configs/ls1021atwr_qspi_defconfig
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 8ab229d..bc8b006 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -263,6 +263,7 @@
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
@@ -281,15 +282,26 @@
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A7 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
return 0;
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
- /* Set global data pointer */
- gd = &gdata;
-
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -408,16 +420,6 @@
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
- /*
- * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
#ifndef CONFIG_QSPI_BOOT
diff --git a/board/freescale/mpc7448hpc2/Kconfig b/board/freescale/mpc7448hpc2/Kconfig
deleted file mode 100644
index 3e7f6e8..0000000
--- a/board/freescale/mpc7448hpc2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC7448HPC2
-
-config SYS_BOARD
- default "mpc7448hpc2"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "mpc7448hpc2"
-
-endif
diff --git a/board/freescale/mpc7448hpc2/MAINTAINERS b/board/freescale/mpc7448hpc2/MAINTAINERS
deleted file mode 100644
index 9966b55..0000000
--- a/board/freescale/mpc7448hpc2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC7448HPC2 BOARD
-M: Roy Zang <tie-fei.zang@freescale.com>
-S: Maintained
-F: board/freescale/mpc7448hpc2/
-F: include/configs/mpc7448hpc2.h
-F: configs/mpc7448hpc2_defconfig
diff --git a/board/freescale/mpc7448hpc2/Makefile b/board/freescale/mpc7448hpc2/Makefile
deleted file mode 100644
index 2cc211b..0000000
--- a/board/freescale/mpc7448hpc2/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mpc7448hpc2.o tsi108_init.o
-obj-y += asm_init.o
diff --git a/board/freescale/mpc7448hpc2/README b/board/freescale/mpc7448hpc2/README
deleted file mode 100644
index cbb043e..0000000
--- a/board/freescale/mpc7448hpc2/README
+++ /dev/null
@@ -1,184 +0,0 @@
-Freescale MPC7448hpc2 (Taiga) board
-===================================
-
-Created 08/11/2006 Roy Zang
---------------------------
-MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference
-design, which is optimized for high speed throughput between the processor and
-the memory, disk drive and Ethernet port subsystems.
-
-MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be
-used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX
-chassis.
-
-Building U-Boot
-------------------
-The mpc7448hpc2 code base is known to compile using:
- Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
-
- $ make mpc7448hpc2_config
- Configuring for mpc7448hpc2 board...
-
- $ make
-
-Memory Map
-----------
-
-The memory map is setup for Linux to operate properly.
-
-The mapping is:
-
- Range Start Range End Definition Size
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0xe000_0000 0xe7ff_ffff PCI Memory 128M
- 0xfa00_0000 0xfaff_ffff PCI IO 16M
- 0xfb00_0000 0xfbff_ffff PCI Config 16M
- 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M
- 0xfe00_0000 0xfeff_ffff PromJet 16M
- 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
- 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
-
-Using Flash
------------
-
-The MPC7448hpc2 board has two "banks" of flash, each 8MB in size
-(2^23 = 0x00800000).
-
-Note: the "bank" here refers to half of the flash. In fact, there is only one
-bank of flash, which is divided into low and high half. Each is controlled by
-the most significant bit of the address bus. The so called "bank" is only for
-convenience.
-
-There is a switch which allows the "bank" to be selected. The switch
-settings for updating flash are given below.
-
-The u-boot commands for copying the boot-bank into the secondary bank are
-as follows:
-
- erase ff800000 ff880000
- cp.b ff000000 ff800000 80000
-
-U-boot commands for downloading an image via tftp and flashing
-it into the secondary bank:
-
- tftp 10000 <u-boot.bin.image>
- erase ff000000 ff080000
- cp.b 10000 ff000000 80000
-
-After copying the image into the second bank of flash, be sure to toggle
-SW3[4] on board before resetting the board in order to set the
-secondary bank as the boot-bank.
-
-Board Switches
-----------------------
-
-Most switches on the board should not be changed. The most frequent
-user-settable switches on the board are used to configure
-the flash banks and determining the PCI frequency.
-
-SW1[1-5]: Processor core voltage
-
- 12345 Core Voltage
- -----
- SW1=01111 1.000V.
- SW1=01101 1.100V.
- SW1=01011 1.200V.
- SW1=01001 1.300V only for MPC7447A.
-
-
-SW2[1-6]: CPU core frequency
-
- CPU Core Frequency (MHz)
- Bus Frequency
- 123456 100 133 167 200 Ratio
-
- ------
- SW2=101100 500 667 833 1000 5x
- SW2=100100 550 733 917 1100 5.5x
- SW2=110100 600 800 1000 1200 6x
- SW2=010100 650 866 1083 1300 6.5x
- SW2=001000 700 930 1167 1400 7x
- SW2=000100 750 1000 1250 1500 7.5x
- SW2=110000 800 1066 1333 1600 8x
- SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A
- SW2=011110 900 1200 1500 1800 9x
-
-This table shows only a subset of available frequency options; see the CPU
-hardware specifications for more information.
-
-SW2[7-8]: Bus Protocol and CPU Reset Option
-
- 7
- -
- SW2=0 System bus uses MPX bus protocol
- SW2=1 System bus uses 60x bus protocol
-
- 8
- -
- SW2=0 TSI108 can cause CPU reset
- SW2=1 TSI108 can not cause CPU reset
-
-SW3[1-8] system options
-
- 123
- ---
- SW3=xxx Connected to GPIO[0:2] on TSI108
-
- 4
- -
- SW3=0 CPU boots from low half of flash
- SW3=1 CPU boots from high half of flash
-
- 5
- -
- SW3=0 SATA and slot2 connected to PCI bus
- SW3=1 Only slot1 connected to PCI bus
-
- 6
- -
- SW3=0 USB connected to PCI bus
- SW3=1 USB disconnected from PCI bus
-
- 7
- -
- SW3=0 Flash is write protected
- SW3=1 Flash is NOT write protected
-
- 8
- -
- SW3=0 CPU will boot from flash
- SW3=1 CPU will boot from PromJet
-
-SW4[1-3]: System bus frequency
-
- Bus Frequency (MHz)
- ---
- SW4=010 183
- SW4=011 100
- SW4=100 133
- SW4=101 166 only for MPC7447A
- SW4=110 200 only for MPC7448
- others reserved
-
-SW4[4-6]: DDR2 SDRAM frequency
-
- Bus Frequency (MHz)
- ---
- SW4=000 external clock
- SW4=011 system clock
- SW4=100 133
- SW4=101 166
- SW4=110 200
- others reserved
-
-SW4[7-8]: PCI/PCI-X frequency control
- 7
- -
- SW4=0 PCI/PCI-X bus operates normally
- SW4=1 PCI bus forced to PCI-33 mode
-
- 8
- -
- SW4=0 PCI-X mode at 133 MHz allowed
- SW4=1 PCI-X mode limited to 100 MHz
diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S
deleted file mode 100644
index 70315c3..0000000
--- a/board/freescale/mpc7448hpc2/asm_init.S
+++ /dev/null
@@ -1,905 +0,0 @@
-/*
- * (C) Copyright 2004-05; Tundra Semiconductor Corp.
- *
- * Added automatic detect of SDC settings
- * Copyright (c) 2005 Freescale Semiconductor, Inc.
- * Maintainer tie-fei.zang@freescale.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * FILENAME: asm_init.s
- *
- * Originator: Alex Bounine
- *
- * DESCRIPTION:
- * Initialization code for the Tundra Tsi108 bridge chip
- *
- */
-
-#include <config.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/processor.h>
-
-#include <tsi108.h>
-
-/*
- * Build Configuration Options
- */
-
-/* #define DISABLE_PBM disables usage of PB Master */
-/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
-/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
-
-/*
- * Hardcoded SDC settings
- */
-
-#ifdef SDC_HARDCODED_INIT
-
-/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
-
-#define VAL_SD_REFRESH (0x61A)
-#define VAL_SD_TIMING (0x0308336b)
-#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */
-#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */
-#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */
-#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */
-
-#endif /* SDC_HARDCODED_INIT */
-
-/*
- CPU Configuration:
-
- CPU Address and Data Parity enables.
-
-#define CPU_AP
-#define CPU_DP
-*/
-
-/*
- * Macros
- * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
- * expected to work correctly for the CSR space within 32KB range.
- *
- * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
- * These macros are absolutely identical except their names. This difference
- * is provided intentionally for better readable code.
- */
-
-#define LOAD_PTR(reg,const32) \
- addis reg,r0,const32@h; ori reg,reg,const32@l
-
-#define LOAD_U32(reg,const32) \
- addis reg,r0,const32@h; ori reg,reg,const32@l
-
-/* LOADMEM initializes a register with the contents of a specified 32-bit
- * memory location, usually a CSR value.
- */
-
-#define LOAD_MEM(reg,addr32) \
- addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
-
-#ifndef SDC_HARDCODED_INIT
-sdc_clk_sync:
- /* MHz: 0,0,183,100,133,167,200,233 */
- .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
-#endif
-
-/*
- * board_asm_init() - early initialization function. Coded to be portable to
- * dual-CPU configuration.
- * Checks CPU number and performs board HW initialization if called for CPU0.
- * Registers used: r3,r4,r5,r6,r19,r29
- *
- * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
- * and the rest of the board. Current implementation demonstrates two
- * possible ways to identify CPU number:
- * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
- * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
- */
-
- .globl board_asm_init
-board_asm_init:
- mflr r19 /* Save LR to be able return later. */
- bl icache_enable /* Enable icache to reduce reads from flash. */
-
-/* Initialize pointer to Tsi108 register space */
-
- LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
- ori r4,r29,TSI108_PB_REG_OFFSET
-
-/* Check Processor Version Number */
-
- mfspr r3, PVR
- rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
-
- cmpli 0,0,r3,0x8000 /* MPC74xx */
- bne cont_brd_init
-
- /*
- * For MPC744x/5x enable extended BATs[4-7]
- * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
- * to disable prefetch
- */
-
- mfspr r5, HID0
- oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */
- ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */
- mtspr HID0, r5
- isync
- sync
-
- /* Adding code to disable external interventions in MPX bus mode */
- mfspr r3, 1014
- oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */
- mtspr 1014, r3
- isync
- sync
-
- /* Sri: code to enable FP unit */
- mfmsr r3
- ori r3, r3, 0x2000
- mtmsr r3
- isync
- sync
-
- /* def CONFIG_DUAL_CPU
- * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
- */
-#if(1)
- mfspr r3,1014 /* read MSSCR0 */
- rlwinm. r3,r3,27,31,31 /* get processor ID number */
- mtspr SPRN_PIR,r3 /* Save CPU ID */
- sync
- bne init_done
- b do_tsi108_init
-
-cont_brd_init:
-
- /* An alternative method of checking the processor number (in addition
- * to configuration using MSSCR0[ID] bit on MPC74xx).
- * Good for IBM PPC750FX/GX.
- */
-
- lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
- rlwinm. r3,r3,24,31,31 /* get processor ID number */
- bne init_done
-#else
-
-cont_brd_init:
-
-#endif /* CONFIG_DUAL_CPU */
-
- /* Initialize Tsi108 chip */
-
-do_tsi108_init:
-
- /*
- * Adjust HLP/Flash parameters. By default after reset the HLP port is
- * set to support slow devices. Better performance can be achived when
- * an optimal parameters are used for specific EPROM device.
- * NOTE: This should be performed ASAP for the emulation platform
- * because it has 5MHz HLP clocking.
- */
-
-#ifdef CONFIG_TSI108EMU
- ori r4,r29,TSI108_HLP_REG_OFFSET
- LOAD_U32(r5,0x434422c0)
- stw r5,0x08(r4) /* set HLP B0_CTRL0 */
- sync
- LOAD_U32(r5,0xd0012000)
- stw r5,0x0c(r4) /* set HLP B0_CTRL1 */
- sync
-#endif
-
- /* Initialize PB interface. */
-
- ori r4,r29,TSI108_PB_REG_OFFSET
-
-#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE)
- /* Relocate (if required) Tsi108 registers. Set new value for
- * PB_REG_BAR:
- * Note we are in the 32-bit address mode.
- */
- LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
- stw r5,PB_REG_BAR(r4)
- andis. r29,r5,0xFFFF
- sync
- ori r4,r29,TSI108_PB_REG_OFFSET
-#endif
-
- /* Set PB Slave configuration register */
-
- LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
- lwz r3, PB_RSR(r4) /* get PB bus mode */
- xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
- rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
- stw r5,PB_SCR(r4)
- sync
-
- /* Configure PB Arbiter */
-
- lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
- li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */
-#ifdef DISABLE_PBM
- ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
-#endif
- andc r5,r5,r3 /* Clear the masked bit fields */
- ori r5,r5,0x0001 /* Set pipeline depth */
- stw r5,PB_ARB_CTRL(r4)
-
-#if (0) /* currently using the default settings for PBM after reset */
- LOAD_U32(r5,0x) /* value for PB_MCR */
- stw r5,PB_MCR(r4)
- sync
-
- LOAD_U32(r5,0x) /* value for PB_MCMD */
- stw r5,PB_MCMD(r4)
- sync
-#endif
-
- /* Disable or enable PVT based on processor bus frequency
- * 1. Read CG_PWRUP_STATUS register field bits 18,17,16
- * 2. See if the value is < or > 133mhz (18:16 = 100)
- * 3. If > enable PVT
- */
-
- LOAD_U32(r3,0xC0002234)
- lwz r3,0(r3)
- rlwinm r3,r3,16,29,31
-
- cmpi 0,0,r3,0x0004
- bgt sdc_init
-
-#ifndef CONFIG_TSI108EMU
- /* FIXME: Disable PB calibration control for any real Tsi108 board */
- li r5,0x0101 /* disable calibration control */
- stw r5,PB_PVT_CTRL2(r4)
- sync
-#endif
-
- /* Initialize SDRAM controller. */
-
-sdc_init:
-
-#ifndef SDC_HARDCODED_INIT
- /* get SDC clock prior doing sdram controller autoconfig */
- ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */
- lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */
- rlwinm r3,r3,12,29,31 /* r3 - SD clk */
- lis r5,sdc_clk_sync@h
- ori r5,r5,sdc_clk_sync@l
- /* Sri: At this point check if r3 = 001. If yes,
- * the memory frequency should be same as the
- * MPX bus frequency
- */
- cmpi 0,0,r3,0x0001
- bne get_nsec
- lwz r6, CG_PWRUP_STATUS(r4)
- rlwinm r6,r6,16,29,31
- mr r3,r6
-
-get_nsec:
- rlwinm r3,r3,2,0,31
- lwzx r9,r5,r3 /* get SD clk rate in nSec */
- /* ATTN: r9 will be used by SPD routine */
-#endif /* !SDC_HARDCODED_INIT */
-
- ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
-
- /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
-
- LOAD_U32(r5,0x00)
- stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
-#ifdef ENABLE_SDRAM_ECC
- li r5, 0x01
-#endif /* ENABLE_SDRAM_ECC */
- stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */
- sync
-
-#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
-
- /* First read the CG_PWRUP_STATUS register to get the
- * memory speed from bits 22,21,20
- */
-
- LOAD_U32(r3,0xC0002234)
- lwz r3,0(r3)
- rlwinm r3,r3,12,29,31
-
- /* Now first check for 166, then 200, or default */
-
- cmpi 0,0,r3,0x0005
- bne check_for_200mhz
-
- /* set values for 166 Mhz memory speed
- * Set refresh rate and timing parameters
- */
- LOAD_U32(r5,0x00000515)
- stw r5,SD_REFRESH(r4)
- LOAD_U32(r5,0x03073368)
- stw r5,SD_TIMING(r4)
- sync
-
- /* Initialize DIMM0 control and BAR registers */
- LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D0_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D0_BAR)
- stw r5,SD_D0_BAR(r4)
- sync
-
- /* Initialize DIMM1 control and BAR registers
- * (same as dimm 0, next 512MB, disabled)
- */
- LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D1_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D1_BAR)
- stw r5,SD_D1_BAR(r4)
- sync
-
- b sdc_init_done
-
-check_for_200mhz:
-
- cmpi 0,0,r3,0x0006
- bne set_default_values
-
- /* set values for 200Mhz memory speed
- * Set refresh rate and timing parameters
- */
- LOAD_U32(r5,0x0000061a)
- stw r5,SD_REFRESH(r4)
- LOAD_U32(r5,0x03083348)
- stw r5,SD_TIMING(r4)
- sync
-
- /* Initialize DIMM0 control and BAR registers */
- LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D0_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D0_BAR)
- stw r5,SD_D0_BAR(r4)
- sync
-
- /* Initialize DIMM1 control and BAR registers
- * (same as dimm 0, next 512MB, disabled)
- */
- LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D1_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D1_BAR)
- stw r5,SD_D1_BAR(r4)
- sync
-
- b sdc_init_done
-
-set_default_values:
-
- /* Set refresh rate and timing parameters */
- LOAD_U32(r5,VAL_SD_REFRESH)
- stw r5,SD_REFRESH(r4)
- LOAD_U32(r5,VAL_SD_TIMING)
- stw r5,SD_TIMING(r4)
- sync
-
- /* Initialize DIMM0 control and BAR registers */
- LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D0_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D0_BAR)
- stw r5,SD_D0_BAR(r4)
- sync
-
- /* Initialize DIMM1 control and BAR registers
- * (same as dimm 0, next 512MB, disabled)
- */
- LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D1_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D1_BAR)
- stw r5,SD_D1_BAR(r4)
- sync
-#else /* !SDC_HARDCODED_INIT */
- bl tsi108_sdram_spd /* automatically detect SDC settings */
-#endif /* SDC_HARDCODED_INIT */
-
-sdc_init_done:
-
-#ifdef DISABLE_PBM
- LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */
-#else
- LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */
-#endif /* DISABLE_PBM */
-
-#ifdef CONFIG_TSI108EMU
- oris r5,r5,0x0010 /* set EMULATION_MODE bit */
-#endif
-
- stw r5,SD_CTRL(r4)
- eieio
- sync
-
- /* Enable SDRAM access */
-
- oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */
- stw r5,SD_CTRL(r4)
- sync
-
-wait_init_complete:
- lwz r5,SD_STATUS(r4)
- andi. r5,r5,0x0001
- /* wait until SDRAM initialization is complete */
- beq wait_init_complete
-
- /* Map SDRAM into the processor bus address space */
-
- ori r4,r29,TSI108_PB_REG_OFFSET
-
- /* Setup BARs associated with direct path PB<->SDRAM */
-
- /* PB_SDRAM_BAR1:
- * provides a direct path to the main system memory (cacheable SDRAM)
- */
-
- /* BA=0,Size=512MB, ENable, No Addr.Translation */
- LOAD_U32(r5, 0x00000011)
- stw r5,PB_SDRAM_BAR1(r4)
- sync
-
- /* Make sure that PB_SDRAM_BAR1 decoder is set
- * (to allow following immediate read from SDRAM)
- */
- lwz r5,PB_SDRAM_BAR1(r4)
- sync
-
- /* PB_SDRAM_BAR2:
- * provides non-cacheable alias (via the direct path) to main
- * system memory.
- * Size = 512MB, ENable, Addr.Translation - ON,
- * BA = 0x0_40000000, TA = 0x0_00000000
- */
-
- LOAD_U32(r5, 0x40010011)
- stw r5,PB_SDRAM_BAR2(r4)
- sync
-
- /* Make sure that PB_SDRAM_BAR2 decoder is set
- * (to allow following immediate read from SDRAM)
- */
- lwz r5,PB_SDRAM_BAR2(r4)
- sync
-
-init_done:
-
- /* All done. Restore LR and return. */
- mtlr r19
- blr
-
-#if (0)
- /*
- * init_cpu1
- * This routine enables CPU1 on the dual-processor system.
- * Now there is only one processor in the system
- */
-
- .global enable_cpu1
-enable_cpu1:
-
- lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */
- addi r3,r3,Tsi108_Base@l
- lwz r3,0(r3) /* R3 = CSR Base Addr */
- ori r4,r3,TSI108_PB_REG_OFFSET
- lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
- ori r3,r3,0x0200 /* Set M1_EN bit */
- stw r3,PB_ARB_CTRL(r4)
-
- blr
-#endif
-
- /*
- * enable_EI
- * Enable CPU core external interrupt
- */
-
- .global enable_EI
-enable_EI:
- mfmsr r3
- ori r3,r3,0x8000 /* set EE bit */
- mtmsr r3
- blr
-
- /*
- * disable_EI
- * Disable CPU core external interrupt
- */
-
- .global disable_EI
-disable_EI:
- mfmsr r3
- li r4,-32768 /* aka "li r4,0x8000" */
- andc r3,r3,r4 /* clear EE bit */
- mtmsr r3
- blr
-
-#ifdef ENABLE_SDRAM_ECC
- /* enables SDRAM ECC */
-
- .global enable_ECC
-enable_ECC:
- ori r4,r29,TSI108_SD_REG_OFFSET
- lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */
- ori r3,r3,0x0001 /* Set ECC_EN bit */
- stw r3,SD_ECC_CTRL(r4)
- blr
-
- /*
- * clear_ECC_err
- * Clears all pending SDRAM ECC errors
- * (normally after SDRAM scrubbing/initialization)
- */
-
- .global clear_ECC_err
-clear_ECC_err:
- ori r4,r29,TSI108_SD_REG_OFFSET
- ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
- stw r3,SD_INT_STATUS(r4)
- blr
-
-#endif /* ENABLE_SDRAM_ECC */
-
-#ifndef SDC_HARDCODED_INIT
-
- /* SDRAM SPD Support */
-#define SD_I2C_CTRL1 (0x400)
-#define SD_I2C_CTRL2 (0x404)
-#define SD_I2C_RD_DATA (0x408)
-#define SD_I2C_WR_DATA (0x40C)
-
- /*
- * SDRAM SPD Support Macros
- */
-
-#define SPD_DIMM0 (0x00000100)
-#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */
-
-#define SPD_RDIMM (0x01)
-#define SPD_UDIMM (0x02)
-
-#define SPD_CAS_3 0x8
-#define SPD_CAS_4 0x10
-#define SPD_CAS_5 0x20
-
-#define ERR_NO_DIMM_FOUND (0xdb0)
-#define ERR_TRAS_FAIL (0xdb1)
-#define ERR_TRCD_FAIL (0xdb2)
-#define ERR_TRP_FAIL (0xdb3)
-#define ERR_TWR_FAIL (0xdb4)
-#define ERR_UNKNOWN_PART (0xdb5)
-#define ERR_NRANK_INVALID (0xdb6)
-#define ERR_DIMM_SIZE (0xdb7)
-#define ERR_ADDR_MODE (0xdb8)
-#define ERR_RFRSH_RATE (0xdb9)
-#define ERR_DIMM_TYPE (0xdba)
-#define ERR_CL_VALUE (0xdbb)
-#define ERR_TRFC_FAIL (0xdbc)
-
-/* READ_SPD requirements:
- * byte - byte address in SPD device (0 - 255)
- * r3 = will return data read from I2C Byte location
- * r4 - unchanged (SDC base addr)
- * r5 - clobbered in routine (I2C status)
- * r10 - number of DDR slot where first SPD device is detected
- */
-
-#define READ_SPD(byte_num) \
- addis r3, 0, byte_num@l; \
- or r3, r3, r10; \
- ori r3, r3, 0x0A; \
- stw r3, SD_I2C_CTRL1(r4); \
- li r3, I2C_CNTRL2_START; \
- stw r3, SD_I2C_CTRL2(r4); \
- eieio; \
- sync; \
- li r3, 0x100; \
-1:; \
- addic. r3, r3, -1; \
- bne 1b; \
-2:; \
- lwz r5, SD_I2C_CTRL2(r4); \
- rlwinm. r3,r5,0,23,23; \
- bne 2b; \
- rlwinm. r3,r5,0,3,3; \
- lwz r3,SD_I2C_RD_DATA(r4)
-
-#define SPD_MIN_RFRSH (0x80)
-#define SPD_MAX_RFRSH (0x85)
-
-refresh_rates: /* in nSec */
- .long 15625 /* Normal (0x80) */
- .long 3900 /* Reduced 0.25x (0x81) */
- .long 7800 /* Reduced 0.5x (0x82) */
- .long 31300 /* Extended 2x (0x83) */
- .long 62500 /* Extended 4x (0x84) */
- .long 125000 /* Extended 8x (0x85) */
-
-/*
- * tsi108_sdram_spd
- *
- * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
- * Uses registers: r4 - SDC base address (not changed)
- * r9 - SDC clocking period in nSec
- * Changes registers: r3,r5,r6,r7,r8,r10,r11
- */
-
-tsi108_sdram_spd:
-
- li r10,SPD_DIMM0
- xor r11,r11,r11 /* DIMM Base Address: starts from 0 */
-
-do_first_dimm:
-
- /* Program Refresh Rate Register */
-
- READ_SPD(12) /* get Refresh Rate */
- beq check_next_slot
- li r5, ERR_RFRSH_RATE
- cmpi 0,0,r3,SPD_MIN_RFRSH
- ble spd_fail
- cmpi 0,0,r3,SPD_MAX_RFRSH
- bgt spd_fail
- addi r3,r3,-SPD_MIN_RFRSH
- rlwinm r3,r3,2,0,31
- lis r5,refresh_rates@h
- ori r5,r5,refresh_rates@l
- lwzx r5,r5,r3 /* get refresh rate in nSec */
- divwu r5,r5,r9 /* calculate # of SDC clocks */
- stw r5,SD_REFRESH(r4) /* Set refresh rate */
- sync
-
- /* Program SD Timing Register */
-
- li r7, 0 /* clear r7 prior parameter collection */
-
- READ_SPD(20) /* get DIMM type: Registered or Unbuffered */
- beq spd_read_fail
- li r5, ERR_DIMM_TYPE
- cmpi 0,0,r3,SPD_UDIMM
- beq do_cl
- cmpi 0,0,r3,SPD_RDIMM
- bne spd_fail
- oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */
-
-do_cl:
- READ_SPD(18) /* Get CAS Latency */
- beq spd_read_fail
- li r5,ERR_CL_VALUE
- andi. r6,r3,SPD_CAS_3
- beq cl_4
- li r6,3
- b set_cl
-cl_4:
- andi. r6,r3,SPD_CAS_4
- beq cl_5
- li r6,4
- b set_cl
-cl_5:
- andi. r6,r3,SPD_CAS_5
- beq spd_fail
- li r6,5
-set_cl:
- rlwimi r7,r6,24,5,7
-
- READ_SPD(30) /* Get tRAS */
- beq spd_read_fail
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_tras
- addi r6,r6,1
-set_tras:
- li r5,ERR_TRAS_FAIL
- cmpi 0,0,r6,0x0F /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,16,12,15
-
- READ_SPD(29) /* Get tRCD */
- beq spd_read_fail
- /* right shift tRCD by 2 bits as per DDR2 spec */
- rlwinm r3,r3,30,2,31
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_trcd
- addi r6,r6,1
-set_trcd:
- li r5,ERR_TRCD_FAIL
- cmpi 0,0,r6,0x07 /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,12,17,19
-
- READ_SPD(27) /* Get tRP value */
- beq spd_read_fail
- rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_trp
- addi r6,r6,1
-set_trp:
- li r5,ERR_TRP_FAIL
- cmpi 0,0,r6,0x07 /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,8,21,23
-
- READ_SPD(36) /* Get tWR value */
- beq spd_read_fail
- rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_twr
- addi r6,r6,1
-set_twr:
- addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */
- li r5,ERR_TWR_FAIL
- cmpi 0,0,r6,0x07 /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,5,24,26
-
- READ_SPD(42) /* Get tRFC */
- beq spd_read_fail
- li r5, ERR_TRFC_FAIL
- /* Tsi108 spec: tRFC=(tRFC + 1)/2 */
- addi r3,r3,1
- rlwinm. r3,r3,31,1,31 /* divide by 2 */
- beq spd_fail
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_trfc
- addi r6,r6,1
-set_trfc:
- cmpi 0,0,r6,0x1F /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,0,27,31
-
- stw r7,SD_TIMING(r4)
- sync
-
- /*
- * The following two registers are set on per-DIMM basis.
- * The SD_REFRESH and SD_TIMING settings are common for both DIMMS
- */
-
-do_each_dimm:
-
- /* Program SDRAM DIMM Control Register */
-
- li r7, 0 /* clear r7 prior parameter collection */
-
- READ_SPD(13) /* Get Primary SDRAM Width */
- beq spd_read_fail
- cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */
- beq do_nbank
- oris r7,r7,0x0010 /* Set MEM_WIDTH bit */
-
-do_nbank:
- READ_SPD(17) /* Get Number of banks on SDRAM device */
- beq spd_read_fail
- /* Grendel only distinguish betw. 4 or 8-bank memory parts */
- li r5,ERR_UNKNOWN_PART /* non-supported memory part */
- cmpi 0,0,r3,4
- beq do_nrank
- cmpi 0,0,r3,8
- bne spd_fail
- ori r7,r7,0x1000
-
-do_nrank:
- READ_SPD(5) /* Get # of Ranks */
- beq spd_read_fail
- li r5,ERR_NRANK_INVALID
- andi. r6,r3,0x7 /* Use bits [2..0] only */
- beq do_addr_mode
- cmpi 0,0,r6,1
- bgt spd_fail
- rlwimi r7,r6,8,23,23
-
-do_addr_mode:
- READ_SPD(4) /* Get # of Column Addresses */
- beq spd_read_fail
- li r5, ERR_ADDR_MODE
- andi. r3,r3,0x0f /* cut off reserved bits */
- cmpi 0,0,r3,8
- ble spd_fail
- cmpi 0,0,r3,15
- bgt spd_fail
- addi r6,r3,-8 /* calculate ADDR_MODE parameter */
- rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */
-
-set_dimm_ctrl:
-#ifdef SDC_AUTOPRECH_EN
- oris r7,r7,0x0001 /* set auto precharge EN bit */
-#endif
- ori r7,r7,1 /* set ENABLE bit */
- cmpi 0,0,r10,SPD_DIMM0
- bne 1f
- stw r7,SD_D0_CTRL(r4)
- sync
- b set_dimm_bar
-1:
- stw r7,SD_D1_CTRL(r4)
- sync
-
-
- /* Program SDRAM DIMMx Base Address Register */
-
-set_dimm_bar:
- READ_SPD(5) /* get # of Ranks */
- beq spd_read_fail
- andi. r7,r3,0x7
- addi r7,r7,1
- READ_SPD(31) /* Read DIMM rank density */
- beq spd_read_fail
- rlwinm r5,r3,27,29,31
- rlwinm r6,r3,3,24,28
- or r5,r6,r5 /* r5 = Normalized Rank Density byte */
- lis r8, 0x0080 /* 128MB >> 4 */
- mullw r8,r8,r5 /* r8 = (rank_size >> 4) */
- mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */
- neg r7,r8
- rlwinm r7,r7,28,4,31
- or r7,r7,r11 /* set ADDR field */
- rlwinm r8,r8,12,20,31
- add r11,r11,r8 /* set Base Addr for next DIMM */
-
- cmpi 0,0,r10,SPD_DIMM0
- bne set_dimm1_size
- stw r7,SD_D0_BAR(r4)
- sync
- li r10,SPD_DIMM1
- READ_SPD(0)
- bne do_each_dimm
- b spd_done
-
-set_dimm1_size:
- stw r7,SD_D1_BAR(r4)
- sync
-spd_done:
- blr
-
-check_next_slot:
- cmpi 0,0,r10,SPD_DIMM1
- beq spd_read_fail
- li r10,SPD_DIMM1
- b do_first_dimm
-spd_read_fail:
- ori r3,r0,0xdead
- b err_hung
-spd_fail:
- li r3,0x0bad
- sync
-err_hung: /* hang here for debugging */
- nop
- nop
- b err_hung
-
-#endif /* !SDC_HARDCODED_INIT */
diff --git a/board/freescale/mpc7448hpc2/config.mk b/board/freescale/mpc7448hpc2/config.mk
deleted file mode 100644
index b2d6f76..0000000
--- a/board/freescale/mpc7448hpc2/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2005 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float
diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
deleted file mode 100644
index 11747ca..0000000
--- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2005 Freescale Semiconductor, Inc.
- *
- * Roy Zang <tie-fei.zang@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * modifications for the Tsi108 Emul Board by avb@Tundra
- */
-
-/*
- * board support/init functions for the
- * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform).
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include <fdt_support.h>
-#include <netdev.h>
-
-#undef DEBUG
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void tsi108_init_f (void);
-
-int display_mem_map (void);
-
-void after_reloc (ulong dest_addr)
-{
- /*
- * Jump to the main U-Boot board init code
- */
- board_init_r ((gd_t *) gd, dest_addr);
- /* NOTREACHED */
-}
-
-/*
- * Check Board Identity:
- * report board type
- */
-
-int checkboard (void)
-{
- int l_type = 0;
-
- printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
- return (l_type);
-}
-
-/*
- * Read Processor ID:
- *
- * report calling processor number
- */
-
-int read_pid (void)
-{
- return 0; /* we are on single CPU platform for a while */
-}
-
-long int dram_size (int board_type)
-{
- return 0x20000000; /* 256M bytes */
-}
-
-phys_size_t initdram (int board_type)
-{
- return dram_size (board_type);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-
- return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#if defined(CONFIG_TSI108_ETH)
- rc = tsi108_eth_initialize(bis);
-#endif
- return rc;
-}
diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c
deleted file mode 100644
index 9a1e407..0000000
--- a/board/freescale/mpc7448hpc2/tsi108_init.c
+++ /dev/null
@@ -1,652 +0,0 @@
-/*****************************************************************************
- * (C) Copyright 2003; Tundra Semiconductor Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *****************************************************************************/
-
-/*----------------------------------------------------------------------------
- * FILENAME: tsi108_init.c
- *
- * Originator: Alex Bounine
- *
- * DESCRIPTION:
- * Initialization code for the Tundra Tsi108 bridge chip
- *---------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include <config.h>
-#include <version.h>
-#include <asm/processor.h>
-#include <tsi108.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void mpicInit (int verbose);
-
-/*
- * Configuration Options
- */
-
-typedef struct {
- ulong upper;
- ulong lower;
-} PB2OCN_LUT_ENTRY;
-
-PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
- /* 0 - 7 */
- {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
-
- /* 8 - 15 */
- {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
-
- /* 16 - 23 */
- {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
- /* 24 - 31 */
- {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap + Translate) */
- {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
-
- {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
- {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
- {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
- {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
-};
-
-#ifdef CONFIG_SYS_CLK_SPREAD
-typedef struct {
- ulong ctrl0;
- ulong ctrl1;
-} PLL_CTRL_SET;
-
-/*
- * Clock Generator SPLL0 initialization values
- * PLL0 configuration table for various PB_CLKO freq.
- * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
- * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
- */
-
-static PLL_CTRL_SET pll0_config[8] = {
- {0x00000000, 0x00000000}, /* 0: bypass */
- {0x00000000, 0x00000000}, /* 1: reserved */
- {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
- {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
- {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
- {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
- {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
- {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
-};
-#endif /* CONFIG_SYS_CLK_SPREAD */
-
-/*
- * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
- * (based on recommended Tsi108 reference clock 33MHz)
- */
-static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
-
-/*
- * get_board_bus_clk ()
- *
- * returns the bus clock in Hz.
- */
-unsigned long get_board_bus_clk (void)
-{
- ulong i;
-
- /* Detect PB clock freq. */
- i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
- i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
-
- return pb_clk_sel[i] * 1000000;
-}
-
-/*
- * board_early_init_f ()
- *
- * board-specific initialization executed from flash
- */
-
-int board_early_init_f (void)
-{
- ulong i;
-
- gd->mem_clk = 0;
- i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
- CG_PWRUP_STATUS);
- i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
- switch (i) {
- case 0: /* external clock */
- printf ("Using external clock\n");
- break;
- case 1: /* system clock */
- gd->mem_clk = gd->bus_clk;
- break;
- case 4: /* 133 MHz */
- case 5: /* 166 MHz */
- case 6: /* 200 MHz */
- gd->mem_clk = pb_clk_sel[i] * 1000000;
- break;
- default:
- printf ("Invalid DDR2 clock setting\n");
- return -1;
- }
- printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
- printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
- return 0;
-}
-
-/*
- * board_early_init_r() - Tsi108 initialization function executed right after
- * relocation. Contains code that cannot be executed from flash.
- */
-
-int board_early_init_r (void)
-{
- ulong temp, i;
- ulong reg_val;
- volatile ulong *reg_ptr;
-
- reg_ptr =
- (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = 0x00000201; /* SWAP ENABLED */
- *reg_ptr++ = 0x00;
- }
-
- __asm__ __volatile__ ("eieio");
- __asm__ __volatile__ ("sync");
-
- /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
- 0x80000001);
- __asm__ __volatile__ ("sync");
-
- /* Make sure that OCN_BAR2 decoder is set (to allow following immediate
- * read from SDRAM)
- */
-
- temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
- __asm__ __volatile__ ("sync");
-
- /*
- * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
- * processor bus address space. Immediately after reset LUT and address
- * translation are disabled for this BAR. Now we have to initialize LUT
- * and switch from the BOOT mode to the normal operation mode.
- *
- * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
- * and covers 512MB of address space. To allow larger aperture we also
- * have to relocate register window of Tsi108
- *
- * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
- * mode.
- *
- * initialize pointer to LUT associated with PB_OCN_BAR1
- */
- reg_ptr =
- (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = pb2ocn_lut1[i].lower;
- *reg_ptr++ = pb2ocn_lut1[i].upper;
- }
-
- __asm__ __volatile__ ("sync");
-
- /* Base addresses for CS0, CS1, CS2, CS3 */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
- 0x00000000);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
- 0x00100000);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
- 0x00200000);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
- 0x00300000);
- __asm__ __volatile__ ("sync");
-
- /* Masks for HLP banks */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
- 0xFFF00000);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
- 0xFFF00000);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
- 0xFFF00000);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
- 0xFFF00000);
- __asm__ __volatile__ ("sync");
-
- /* Set CTRL0 values for banks */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
- 0x7FFC44C2);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
- 0x7FFC44C0);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
- 0x7FFC44C0);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
- 0x7FFC44C2);
- __asm__ __volatile__ ("sync");
-
- /* Set banks to latched mode, enabled, and other default settings */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
- 0x7C0F2000);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
- 0x7C0F2000);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
- 0x7C0F2000);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
- 0x7C0F2000);
- __asm__ __volatile__ ("sync");
-
- /*
- * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
- * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
- */
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
- 0xE0000011);
- __asm__ __volatile__ ("sync");
-
- /* Make sure that OCN_BAR2 decoder is set (to allow following
- * immediate read from SDRAM)
- */
-
- temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
- __asm__ __volatile__ ("sync");
-
- /*
- * SRI: At this point we have enabled the HLP banks. That means we can
- * now read from the NVRAM and initialize the environment variables.
- * We will over-ride the env_init called in board_init_f
- * This is really a work-around because, the HLP bank 1
- * where NVRAM resides is not visible during board_init_f
- * (arch/powerpc/lib/board.c)
- * Alternatively, we could use the I2C EEPROM at start-up to configure
- * and enable all HLP banks and not just HLP 0 as is being done for
- * Taiga Rev. 2.
- */
-
- env_init ();
-
-#ifndef DISABLE_PBM
-
- /*
- * For IBM processors we have to set Address-Only commands generated
- * by PBM that are different from ones set after reset.
- */
-
- temp = get_cpu_type ();
-
- if ((CPU_750FX == temp) || (CPU_750GX == temp))
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
- 0x00009955);
-#endif /* DISABLE_PBM */
-
-#ifdef CONFIG_PCI
- /*
- * Initialize PCI/X block
- */
-
- /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
- PCI_PFAB_BAR0_UPPER, 0);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
- 0xFB000001);
- __asm__ __volatile__ ("sync");
-
- /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
-
- temp = in32(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
-
- temp &= ~0xFF00; /* Clear the BUS_NUM field */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
- temp);
-
- /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
- 0);
- __asm__ __volatile__ ("sync");
-
- /* This register is on the PCI side to interpret the address it receives
- * and maps it as a IO address.
- */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
- 0x00000001);
- __asm__ __volatile__ ("sync");
-
- /*
- * Map PCI/X Memory Space
- *
- * Transactions directed from OCM to PCI Memory Space are directed
- * from PB to PCI
- * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
- * If address remapping is required the corresponding PCI_PFAB_MEM32
- * and PCI_PFAB_PFMx register groups have to be configured.
- *
- * Map the path from the PCI/X bus into the system memory
- *
- * The memory mapped window assotiated with PCI P2O_BAR2 provides
- * access to the system memory without address remapping.
- * All system memory is opened for accesses initiated by PCI/X bus
- * masters.
- *
- * Initialize LUT associated with PCI P2O_BAR2
- *
- * set pointer to LUT associated with PCI P2O_BAR2
- */
-
- reg_ptr =
- (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
-
-#ifdef DISABLE_PBM
-
- /* In case when PBM is disabled (no HW supported cache snoopng on PB)
- * P2O_BAR2 is directly mapped into the system memory without address
- * translation.
- */
-
- reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
- *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
- }
-
- /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
- reg_val = 0x00007500;
-#else
-
- reg_val = 0x00000002; /* Destination port = PBM */
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
-/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
- *reg_ptr++ = 0x40000000;
-/* offset = 16MB, address translation is enabled to allow byte swapping */
- reg_val += 0x01000000;
- }
-
-/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
- reg_val = 0x00007100;
-#endif
-
- __asm__ __volatile__ ("eieio");
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
- reg_val);
- __asm__ __volatile__ ("sync");
-
- /* Set 64-bit PCI bus address for system memory
- * ( 0 is the best choice for easy mapping)
- */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
- 0x00000000);
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
- 0x00000000);
- __asm__ __volatile__ ("sync");
-
-#ifndef DISABLE_PBM
- /*
- * The memory mapped window assotiated with PCI P2O_BAR3 provides
- * access to the system memory using SDRAM OCN port and address
- * translation. This is alternative way to access SDRAM from PCI
- * required for Tsi108 emulation testing.
- * All system memory is opened for accesses initiated by
- * PCI/X bus masters.
- *
- * Initialize LUT associated with PCI P2O_BAR3
- *
- * set pointer to LUT associated with PCI P2O_BAR3
- */
- reg_ptr =
- (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
-
- reg_val = 0x00000004; /* Destination port = SDC */
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
-
-/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
- *reg_ptr++ = 0;
-
-/* offset = 16MB, address translation is enabled to allow byte swapping */
- reg_val += 0x01000000;
- }
-
- __asm__ __volatile__ ("eieio");
- __asm__ __volatile__ ("sync");
-
- /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
-
- reg_val =
- in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
- PCI_P2O_PAGE_SIZES);
- reg_val &= ~0x00FF;
- reg_val |= 0x0071;
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
- reg_val);
- __asm__ __volatile__ ("sync");
-
- /* Set 64-bit base PCI bus address for window (0x20000000) */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
- 0x00000000);
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
- 0x20000000);
- __asm__ __volatile__ ("sync");
-
-#endif /* !DISABLE_PBM */
-
-#ifdef ENABLE_PCI_CSR_BAR
- /* open if required access to Tsi108 CSRs from the PCI/X bus */
- /* enable BAR0 on the PCI/X bus */
- reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
- reg_val |= 0x02;
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
- reg_val);
- __asm__ __volatile__ ("sync");
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
- 0x00000000);
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
- CONFIG_SYS_TSI108_CSR_BASE);
- __asm__ __volatile__ ("sync");
-
-#endif
-
- /*
- * Finally enable PCI/X Bus Master and Memory Space access
- */
-
- reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
- reg_val |= 0x06;
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
- __asm__ __volatile__ ("sync");
-
-#endif /* CONFIG_PCI */
-
- /*
- * Initialize MPIC outputs (interrupt pins):
- * Interrupt routing on the Grendel Emul. Board:
- * PB_INT[0] -> INT (CPU0)
- * PB_INT[1] -> INT (CPU1)
- * PB_INT[2] -> MCP (CPU0)
- * PB_INT[3] -> MCP (CPU1)
- * Set interrupt controller outputs as Level_Sensitive/Active_Low
- */
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
- __asm__ __volatile__ ("sync");
-
- /*
- * Ensure that Machine Check exception is enabled
- * We need it to support PCI Bus probing (configuration reads)
- */
-
- reg_val = mfmsr ();
- mtmsr(reg_val | MSR_ME);
-
- return 0;
-}
-
-/*
- * Needed to print out L2 cache info
- * used in the misc_init_r function
- */
-
-unsigned long get_l2cr (void)
-{
- unsigned long l2controlreg;
- asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
- return l2controlreg;
-}
-
-/*
- * misc_init_r()
- *
- * various things to do after relocation
- *
- */
-
-int misc_init_r (void)
-{
-#ifdef CONFIG_SYS_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
- ulong i;
-
- /* Ensure that Spread-Spectrum is disabled */
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
-
- /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
- * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
- */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
- 0x002e0044); /* D = 0.25% */
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
- 0x00000039); /* BWADJ */
-
- /* Initialize PLL0: CG_PB_CLKO */
- /* Detect PB clock freq. */
- i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
- i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
-
- out32 (CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
- out32 (CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
-
- /* Wait and set SSEN for both PLL0 and 1 */
- udelay (1000);
- out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
- 0x802e0044); /* D=0.25% */
- out32 (CONFIG_SYS_TSI108_CSR_BASE +
- TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
- 0x80000000 | pll0_config[i].ctrl0);
-#endif /* CONFIG_SYS_CLK_SPREAD */
-
-#ifdef CONFIG_SYS_L2
- l2cache_enable ();
-#endif
- printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000);
- printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
-
- /*
- * All the information needed to print the cache details is avaiblable
- * at this point i.e. above call to l2cache_enable is the very last
- * thing done with regards to enabling diabling the cache.
- * So this seems like a good place to print all this information
- */
-
- printf ("CACHE: ");
- switch (get_cpu_type()) {
- case CPU_7447A:
- printf ("L1 Instruction cache - 32KB 8-way");
- (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("L1 Data cache - 32KB 8-way");
- (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("Unified L2 cache - 512KB 8-way");
- (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("\n");
- break;
-
- case CPU_7448:
- printf ("L1 Instruction cache - 32KB 8-way");
- (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("L1 Data cache - 32KB 8-way");
- (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("Unified L2 cache - 1MB 8-way");
- (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- break;
- default:
- break;
- }
- return 0;
-}
diff --git a/board/freescale/mpc8360emds/Kconfig b/board/freescale/mpc8360emds/Kconfig
deleted file mode 100644
index 3f4f95c..0000000
--- a/board/freescale/mpc8360emds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8360EMDS
-
-config SYS_BOARD
- default "mpc8360emds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8360EMDS"
-
-endif
diff --git a/board/freescale/mpc8360emds/MAINTAINERS b/board/freescale/mpc8360emds/MAINTAINERS
deleted file mode 100644
index 91ff2ef..0000000
--- a/board/freescale/mpc8360emds/MAINTAINERS
+++ /dev/null
@@ -1,15 +0,0 @@
-MPC8360EMDS BOARD
-M: Dave Liu <daveliu@freescale.com>
-S: Maintained
-F: board/freescale/mpc8360emds/
-F: include/configs/MPC8360EMDS.h
-F: configs/MPC8360EMDS_33_defconfig
-F: configs/MPC8360EMDS_33_ATM_defconfig
-F: configs/MPC8360EMDS_33_HOST_33_defconfig
-F: configs/MPC8360EMDS_33_HOST_66_defconfig
-F: configs/MPC8360EMDS_33_SLAVE_defconfig
-F: configs/MPC8360EMDS_66_defconfig
-F: configs/MPC8360EMDS_66_ATM_defconfig
-F: configs/MPC8360EMDS_66_HOST_33_defconfig
-F: configs/MPC8360EMDS_66_HOST_66_defconfig
-F: configs/MPC8360EMDS_66_SLAVE_defconfig
diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile
deleted file mode 100644
index e8332ce..0000000
--- a/board/freescale/mpc8360emds/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc8360emds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8360emds/README b/board/freescale/mpc8360emds/README
deleted file mode 100644
index 6afa753..0000000
--- a/board/freescale/mpc8360emds/README
+++ /dev/null
@@ -1,155 +0,0 @@
-Freescale MPC8360EMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
- For some reason, the HW designers describe the switch settings
- in terms of 0 and 1, and then map that to physical switches where
- the label "On" refers to logic 0 and "Off" is logic 1.
-
- Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
- bits may contribute to signals that are numbered based at 0,
- and some of those signals may be high-bit-number-0 too. Heed
- well the names and labels and do not get confused.
-
- "Off" == 1
- "On" == 0
-
- SW18 is switch 18 as silk-screened onto the board.
- SW4[8] is the bit labeled 8 on Switch 4.
- SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
- SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
- SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
- and bits labeled 8 is set as "Off".
-
-1.1 There are three type boards for MPC8360E silicon up to now, They are
-
- * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE)
- * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT)
- * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE)
-
-1.2 For all the MPC8360EMDS Board
-
- First, make sure the board default setting is consistent with the
- document shipped with your board. Then apply the following setting:
- SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus)
- SW4[1-8]= 0011_0000 (Flash boot on local bus)
- SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH)
- SW10[1-8]= 0000_1000 (core PLL setting)
- SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
- JP6 1-2
- on board Oscillator: 66M
-
-1.3 Since different board/chip rev. combinations have AC timing issues,
- u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default
- by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers).
-
- When the rev2.x silicon mount on these boards, and if you are using
- u-boot version after this patch, to make the ethernet interfaces usable,
- and to enable RGMII-ID on your board, you have to setup the jumpers
- correctly.
-
- * MPC8360E-MDS-PB PROTO
- nothing to do
- * MPC8360E-MDS-PB PILOT
- JP9 and JP8 should be ON
- * MPC8360EA-MDS-PB PROTO
- JP2 and JP3 should be ON
-
-2. Memory Map
-
-2.1. The memory map should look pretty much like this:
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
- 0xc000_0000 0xdfff_ffff Empty 512M
- 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
- 0xe020_0000 0xe02f_ffff Empty 1M
- 0xe030_0000 0xe03f_ffff PCI IO 1M
- 0xe040_0000 0xefff_ffff Empty 252M
- 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M
- 0xf400_0000 0xf7ff_ffff Empty 64M
- 0xf800_0000 0xf800_7fff BCSR on CS1 32K
- 0xf800_8000 0xf800_ffff PIB CS4 32K
- 0xf801_0000 0xf801_7fff PIB CS5 32K
- 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC8360EMDS.h
-
- CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
- CONFIG_MPC8360 MPC8360 specific
- CONFIG_MPC8360EMDS MPC8360EMDS board specific
-
-4. Compilation
-
- MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip).
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC8360EMDS_XX_config
- make
-
- MPC8360EMDS support ATM, PCI in host and slave mode.
-
- To make u-boot support ATM :
- 1) Make MPC8360EMDS_XX_ATM_config
-
- To make u-boot support PCI host 66M :
- 1) DIP SW support PCI mode as described in Section 1.1.
- 2) Make MPC8360EMDS_XX_HOST_66_config
-
- To make u-boot support PCI host 33M :
- 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
- 2) Make MPC8360EMDS_XX_HOST_33_config
-
- To make u-boot support PCI slave 66M :
- 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
- 2) Make MPC8360EMDS_XX_SLAVE_config
-
- (where XX is:
- 33 - 33.33MHz oscillator
- 66 - 66MHz oscillator)
-
-5. Downloading and Flashing Images
-
-5.0 Download over serial line using Kermit:
-
- loadb
- [Drop to kermit:
- ^\c
- send <u-boot-bin-image>
- c
- ]
-
-
- Or via tftp:
-
- tftp 10000 u-boot.bin
-
-5.1 Reflash U-boot Image using U-boot
-
- tftp 20000 u-boot.bin
- protect off fef00000 fef3ffff
- erase fef00000 fef3ffff
-
- cp.b 20000 fef00000 xxxx
-
- or
-
- cp.b 20000 fef00000 3ffff
-
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-Maybe 3ffff will work too, that corresponds to the erased sectors.
-
-
-6. Notes
- 1) The console baudrate for MPC8360EMDS is 115200bps.
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
deleted file mode 100644
index f0a55f8..0000000
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_mdio.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <spd_sdram.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#include <hwconfig.h>
-#include <fdt_support.h>
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-#include "../../../drivers/qe/uec.h"
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* GETH1 */
- {0, 3, 1, 0, 1}, /* TxD0 */
- {0, 4, 1, 0, 1}, /* TxD1 */
- {0, 5, 1, 0, 1}, /* TxD2 */
- {0, 6, 1, 0, 1}, /* TxD3 */
- {1, 6, 1, 0, 3}, /* TxD4 */
- {1, 7, 1, 0, 1}, /* TxD5 */
- {1, 9, 1, 0, 2}, /* TxD6 */
- {1, 10, 1, 0, 2}, /* TxD7 */
- {0, 9, 2, 0, 1}, /* RxD0 */
- {0, 10, 2, 0, 1}, /* RxD1 */
- {0, 11, 2, 0, 1}, /* RxD2 */
- {0, 12, 2, 0, 1}, /* RxD3 */
- {0, 13, 2, 0, 1}, /* RxD4 */
- {1, 1, 2, 0, 2}, /* RxD5 */
- {1, 0, 2, 0, 2}, /* RxD6 */
- {1, 4, 2, 0, 2}, /* RxD7 */
- {0, 7, 1, 0, 1}, /* TX_EN */
- {0, 8, 1, 0, 1}, /* TX_ER */
- {0, 15, 2, 0, 1}, /* RX_DV */
- {0, 16, 2, 0, 1}, /* RX_ER */
- {0, 0, 2, 0, 1}, /* RX_CLK */
- {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
- {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
- /* GETH2 */
- {0, 17, 1, 0, 1}, /* TxD0 */
- {0, 18, 1, 0, 1}, /* TxD1 */
- {0, 19, 1, 0, 1}, /* TxD2 */
- {0, 20, 1, 0, 1}, /* TxD3 */
- {1, 2, 1, 0, 1}, /* TxD4 */
- {1, 3, 1, 0, 2}, /* TxD5 */
- {1, 5, 1, 0, 3}, /* TxD6 */
- {1, 8, 1, 0, 3}, /* TxD7 */
- {0, 23, 2, 0, 1}, /* RxD0 */
- {0, 24, 2, 0, 1}, /* RxD1 */
- {0, 25, 2, 0, 1}, /* RxD2 */
- {0, 26, 2, 0, 1}, /* RxD3 */
- {0, 27, 2, 0, 1}, /* RxD4 */
- {1, 12, 2, 0, 2}, /* RxD5 */
- {1, 13, 2, 0, 3}, /* RxD6 */
- {1, 11, 2, 0, 2}, /* RxD7 */
- {0, 21, 1, 0, 1}, /* TX_EN */
- {0, 22, 1, 0, 1}, /* TX_ER */
- {0, 29, 2, 0, 1}, /* RX_DV */
- {0, 30, 2, 0, 1}, /* RX_ER */
- {0, 31, 2, 0, 1}, /* RX_CLK */
- {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
- {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
-
- {0, 1, 3, 0, 2}, /* MDIO */
- {0, 2, 1, 0, 1}, /* MDC */
-
- {5, 0, 1, 0, 2}, /* UART2_SOUT */
- {5, 1, 2, 0, 3}, /* UART2_CTS */
- {5, 2, 1, 0, 1}, /* UART2_RTS */
- {5, 3, 2, 0, 2}, /* UART2_SIN */
-
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
-static int board_handle_erratum2(void)
-{
- const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
- REVID_MINOR(immr->sysconf.spridr) == 1;
-}
-
-int board_early_init_f(void)
-{
- const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
-
- /* Enable flash write */
- bcsr[0xa] &= ~0x04;
-
- /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
- if (REVID_MAJOR(immr->sysconf.spridr) == 2)
- bcsr[0xe] = 0x30;
-
- /* Enable second UART */
- bcsr[0x9] &= ~0x01;
-
- if (board_handle_erratum2()) {
- void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
-
- /*
- * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
- * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
- */
- setbits_be32(immap, 0x0c003000);
-
- /*
- * IMMR + 0x14AC[20:27] = 10101010
- * (data delay for both UCC's)
- */
- clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
- }
- return 0;
-}
-
-int board_early_init_r(void)
-{
- gd_t *gd;
-#ifdef CONFIG_PQ_MDS_PIB
- pib_init();
-#endif
- /*
- * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
- * So re-setup PCI MEM space used BAT5 after relocated to DDR
- */
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
- if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
- write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
- write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
- }
-
- return 0;
-}
-
-#ifdef CONFIG_UEC_ETH
-static uec_info_t uec_info[] = {
-#ifdef CONFIG_UEC_ETH1
- STD_UEC_INFO(1),
-#endif
-#ifdef CONFIG_UEC_ETH2
- STD_UEC_INFO(2),
-#endif
-};
-
-int board_eth_init(bd_t *bd)
-{
- if (board_handle_erratum2()) {
- int i;
-
- for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
- uec_info[i].enet_interface_type =
- PHY_INTERFACE_MODE_RGMII_RXID;
- uec_info[i].speed = SPEED_1000;
- }
- }
- return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
-}
-#endif /* CONFIG_UEC_ETH */
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-int fixed_sdram(void);
-static int sdram_init(unsigned int base);
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 lbc_sdram_size;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
- msize = spd_sdram();
-#else
- msize = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize DDR ECC byte
- */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
- /*
- * Initialize SDRAM if it is on local bus.
- */
- lbc_sdram_size = sdram_init(msize * 1024 * 1024);
- if (!msize)
- msize = lbc_sdram_size;
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE;
- u32 ddr_size = msize << 20;
- u32 ddr_size_log2 = __ilog2(ddr_size);
- u32 half_ddr_size = ddr_size >> 1;
-
- im->sysconf.ddrlaw[0].bar =
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currenly any ddr size other than 256 is not supported
-#endif
-#ifdef CONFIG_DDR_II
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
- im->ddr.csbnds[1].csbnds =
- (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
- CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
-
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
-
- im->ddr.cs_config[2] = 0;
- im->ddr.cs_config[3] = 0;
-
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
- udelay(200);
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- return msize;
-}
-#endif /*!CONFIG_SYS_SPD_EEPROM */
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC8360EMDS\n");
- return 0;
-}
-
-/*
- * if MPC8360EMDS is soldered with SDRAM
- */
-#ifdef CONFIG_SYS_LB_SDRAM
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-static int sdram_init(unsigned int base)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- fsl_lbc_t *lbc = LBC_BASE_ADDR;
- const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
- int rem = base % sdram_size;
- uint *sdram_addr;
-
- /* window base address should be aligned to the window size */
- if (rem)
- base = base - rem + sdram_size;
-
- /*
- * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
- * After relocated to DDR, reuse BAT5 for PCI MEM space
- */
- if (base > CONFIG_MAX_MEM_MAPPED) {
- unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
- unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
-
- /* Setup the BAT6 for SDRAM */
- write_bat(DBAT6, batu, batl);
- write_bat(IBAT6, batu, batl);
- }
-
- sdram_addr = (uint *)base;
- /*
- * Setup SDRAM Base and Option Registers
- */
- set_lbc_br(2, base | CONFIG_SYS_BR2);
- set_lbc_or(2, CONFIG_SYS_OR2);
- immap->sysconf.lblaw[2].bar = base;
- immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
-
- /*setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- asm("sync");
-
- /*
- * Configure the SDRAM controller Machine Mode Register.
- */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /*
- * We need do 8 times auto refresh operation.
- */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
- asm("sync");
- *sdram_addr = 0xff; /* 1 times */
- udelay(100);
- *sdram_addr = 0xff; /* 2 times */
- udelay(100);
- *sdram_addr = 0xff; /* 3 times */
- udelay(100);
- *sdram_addr = 0xff; /* 4 times */
- udelay(100);
- *sdram_addr = 0xff; /* 5 times */
- udelay(100);
- *sdram_addr = 0xff; /* 6 times */
- udelay(100);
- *sdram_addr = 0xff; /* 7 times */
- udelay(100);
- *sdram_addr = 0xff; /* 8 times */
- udelay(100);
-
- /* Mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
- asm("sync");
- *(sdram_addr + 0xcc) = 0xff;
- udelay(100);
-
- /* Normal operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /*
- * In non-aligned case we don't [normally] use that memory because
- * there is a hole.
- */
- if (rem)
- return 0;
- return CONFIG_SYS_LBC_SDRAM_SIZE;
-}
-#else
-static int sdram_init(unsigned int base) { return 0; }
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
-{
- if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
- return;
-
- do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
- "peripheral", sizeof("peripheral"), 1);
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_board_fixup_qe_usb(blob, bd);
- /*
- * mpc8360ea pb mds errata 2: RGMII timing
- * if on mpc8360ea rev. 2.1,
- * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
- */
- if (board_handle_erratum2()) {
- int nodeoffset;
- const char *prop;
- int path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
-#if defined(CONFIG_HAS_ETH0)
- /* fixup UCC 1 if using rgmii-id mode */
- prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
- if (prop) {
- path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path,
- "phy-connection-type", 0);
- if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_fixup_phy_connection(blob, path,
- PHY_INTERFACE_MODE_RGMII_RXID);
- }
-#endif
-#if defined(CONFIG_HAS_ETH1)
- /* fixup UCC 2 if using rgmii-id mode */
- prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
- if (prop) {
- path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path,
- "phy-connection-type", 0);
- if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_fixup_phy_connection(blob, path,
- PHY_INTERFACE_MODE_RGMII_RXID);
- }
-#endif
- }
- }
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
deleted file mode 100644
index 71244df..0000000
--- a/board/freescale/mpc8360emds/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * PCI Configuration space access support for MPC83xx PCI Bridge
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include "../common/pq-mds-pib.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI2_MEM_BASE,
- phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
- size: CONFIG_SYS_PCI2_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI2_IO_BASE,
- phys_start: CONFIG_SYS_PCI2_IO_PHYS,
- size: CONFIG_SYS_PCI2_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
- size: CONFIG_SYS_PCI2_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-#endif
-
-void pci_init_board(void)
-#ifdef CONFIG_PCISLAVE
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
- struct pci_region *reg[] = { pci1_regions };
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
- mpc83xx_pci_init(1, reg);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar0 = 0x0;
- pci_ctrl[0].pibar0 = 0x0;
- pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-
- pci_ctrl[0].pitar2 = 0x0;
- pci_ctrl[0].pibar2 = 0x0;
- pci_ctrl[0].piebar2 = 0x0;
- pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-
- /* Unlock the configuration bit */
- mpc83xx_pcislave_unlock(0);
- printf("PCI: Agent mode enabled\n");
-}
-#else
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
- struct pci_region *reg[] = { pci1_regions };
-#else
- struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
- /* initialize the PCA9555PW IO expander on the PIB board */
- pib_init();
-
-#if defined(CONFIG_PCI_66M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#elif defined(CONFIG_PCI_33M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
- OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
- printf("PCI clock is 33MHz\n");
-#else
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#endif
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
- udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
- mpc83xx_pci_init(1, reg);
-#else
- mpc83xx_pci_init(2, reg);
-#endif
-}
-#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8360erdk/Kconfig b/board/freescale/mpc8360erdk/Kconfig
deleted file mode 100644
index 5c9be7c..0000000
--- a/board/freescale/mpc8360erdk/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8360ERDK
-
-config SYS_BOARD
- default "mpc8360erdk"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8360ERDK"
-
-endif
diff --git a/board/freescale/mpc8360erdk/MAINTAINERS b/board/freescale/mpc8360erdk/MAINTAINERS
deleted file mode 100644
index e5b5995..0000000
--- a/board/freescale/mpc8360erdk/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8360ERDK BOARD
-#M: Anton Vorontsov <avorontsov@ru.mvista.com>
-S: Orphan (since 2014-03)
-F: board/freescale/mpc8360erdk/
-F: include/configs/MPC8360ERDK.h
-F: configs/MPC8360ERDK_defconfig
-F: configs/MPC8360ERDK_33_defconfig
diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile
deleted file mode 100644
index e2235c2..0000000
--- a/board/freescale/mpc8360erdk/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc8360erdk.o
-obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c
deleted file mode 100644
index 478f820..0000000
--- a/board/freescale/mpc8360erdk/mpc8360erdk.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <pci.h>
-#include <libfdt.h>
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* MDIO */
- {0, 1, 3, 0, 2}, /* MDIO */
- {0, 2, 1, 0, 1}, /* MDC */
-
- /* UCC1 - UEC (Gigabit) */
- {0, 3, 1, 0, 1}, /* TxD0 */
- {0, 4, 1, 0, 1}, /* TxD1 */
- {0, 5, 1, 0, 1}, /* TxD2 */
- {0, 6, 1, 0, 1}, /* TxD3 */
- {0, 9, 2, 0, 1}, /* RxD0 */
- {0, 10, 2, 0, 1}, /* RxD1 */
- {0, 11, 2, 0, 1}, /* RxD2 */
- {0, 12, 2, 0, 1}, /* RxD3 */
- {0, 7, 1, 0, 1}, /* TX_EN */
- {0, 8, 1, 0, 1}, /* TX_ER */
- {0, 15, 2, 0, 1}, /* RX_DV */
- {0, 0, 2, 0, 1}, /* RX_CLK */
- {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
- {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
-
- /* UCC2 - UEC (Gigabit) */
- {0, 17, 1, 0, 1}, /* TxD0 */
- {0, 18, 1, 0, 1}, /* TxD1 */
- {0, 19, 1, 0, 1}, /* TxD2 */
- {0, 20, 1, 0, 1}, /* TxD3 */
- {0, 23, 2, 0, 1}, /* RxD0 */
- {0, 24, 2, 0, 1}, /* RxD1 */
- {0, 25, 2, 0, 1}, /* RxD2 */
- {0, 26, 2, 0, 1}, /* RxD3 */
- {0, 21, 1, 0, 1}, /* TX_EN */
- {0, 22, 1, 0, 1}, /* TX_ER */
- {0, 29, 2, 0, 1}, /* RX_DV */
- {0, 31, 2, 0, 1}, /* RX_CLK */
- {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */
- {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
-
- /* UCC7 - UEC */
- {4, 0, 1, 0, 1}, /* TxD0 */
- {4, 1, 1, 0, 1}, /* TxD1 */
- {4, 2, 1, 0, 1}, /* TxD2 */
- {4, 3, 1, 0, 1}, /* TxD3 */
- {4, 6, 2, 0, 1}, /* RxD0 */
- {4, 7, 2, 0, 1}, /* RxD1 */
- {4, 8, 2, 0, 1}, /* RxD2 */
- {4, 9, 2, 0, 1}, /* RxD3 */
- {4, 4, 1, 0, 1}, /* TX_EN */
- {4, 5, 1, 0, 1}, /* TX_ER */
- {4, 12, 2, 0, 1}, /* RX_DV */
- {4, 13, 2, 0, 1}, /* RX_ER */
- {4, 10, 2, 0, 1}, /* COL */
- {4, 11, 2, 0, 1}, /* CRS */
- {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
- {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
-
- /* UCC4 - UEC */
- {1, 14, 1, 0, 1}, /* TxD0 */
- {1, 15, 1, 0, 1}, /* TxD1 */
- {1, 16, 1, 0, 1}, /* TxD2 */
- {1, 17, 1, 0, 1}, /* TxD3 */
- {1, 20, 2, 0, 1}, /* RxD0 */
- {1, 21, 2, 0, 1}, /* RxD1 */
- {1, 22, 2, 0, 1}, /* RxD2 */
- {1, 23, 2, 0, 1}, /* RxD3 */
- {1, 18, 1, 0, 1}, /* TX_EN */
- {1, 19, 1, 0, 2}, /* TX_ER */
- {1, 26, 2, 0, 1}, /* RX_DV */
- {1, 27, 2, 0, 1}, /* RX_ER */
- {1, 24, 2, 0, 1}, /* COL */
- {1, 25, 2, 0, 1}, /* CRS */
- {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */
- {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */
-
- /* PCI1 */
- {5, 4, 2, 0, 3}, /* PCI_M66EN */
- {5, 5, 1, 0, 3}, /* PCI_INTA */
- {5, 6, 1, 0, 3}, /* PCI_RSTO */
- {5, 7, 3, 0, 3}, /* PCI_C_BE0 */
- {5, 8, 3, 0, 3}, /* PCI_C_BE1 */
- {5, 9, 3, 0, 3}, /* PCI_C_BE2 */
- {5, 10, 3, 0, 3}, /* PCI_C_BE3 */
- {5, 11, 3, 0, 3}, /* PCI_PAR */
- {5, 12, 3, 0, 3}, /* PCI_FRAME */
- {5, 13, 3, 0, 3}, /* PCI_TRDY */
- {5, 14, 3, 0, 3}, /* PCI_IRDY */
- {5, 15, 3, 0, 3}, /* PCI_STOP */
- {5, 16, 3, 0, 3}, /* PCI_DEVSEL */
- {5, 17, 0, 0, 0}, /* PCI_IDSEL */
- {5, 18, 3, 0, 3}, /* PCI_SERR */
- {5, 19, 3, 0, 3}, /* PCI_PERR */
- {5, 20, 3, 0, 3}, /* PCI_REQ0 */
- {5, 21, 2, 0, 3}, /* PCI_REQ1 */
- {5, 22, 2, 0, 3}, /* PCI_GNT2 */
- {5, 23, 3, 0, 3}, /* PCI_GNT0 */
- {5, 24, 1, 0, 3}, /* PCI_GNT1 */
- {5, 25, 1, 0, 3}, /* PCI_GNT2 */
- {5, 26, 0, 0, 0}, /* PCI_CLK0 */
- {5, 27, 0, 0, 0}, /* PCI_CLK1 */
- {5, 28, 0, 0, 0}, /* PCI_CLK2 */
- {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
- {6, 0, 3, 0, 3}, /* PCI_AD0 */
- {6, 1, 3, 0, 3}, /* PCI_AD1 */
- {6, 2, 3, 0, 3}, /* PCI_AD2 */
- {6, 3, 3, 0, 3}, /* PCI_AD3 */
- {6, 4, 3, 0, 3}, /* PCI_AD4 */
- {6, 5, 3, 0, 3}, /* PCI_AD5 */
- {6, 6, 3, 0, 3}, /* PCI_AD6 */
- {6, 7, 3, 0, 3}, /* PCI_AD7 */
- {6, 8, 3, 0, 3}, /* PCI_AD8 */
- {6, 9, 3, 0, 3}, /* PCI_AD9 */
- {6, 10, 3, 0, 3}, /* PCI_AD10 */
- {6, 11, 3, 0, 3}, /* PCI_AD11 */
- {6, 12, 3, 0, 3}, /* PCI_AD12 */
- {6, 13, 3, 0, 3}, /* PCI_AD13 */
- {6, 14, 3, 0, 3}, /* PCI_AD14 */
- {6, 15, 3, 0, 3}, /* PCI_AD15 */
- {6, 16, 3, 0, 3}, /* PCI_AD16 */
- {6, 17, 3, 0, 3}, /* PCI_AD17 */
- {6, 18, 3, 0, 3}, /* PCI_AD18 */
- {6, 19, 3, 0, 3}, /* PCI_AD19 */
- {6, 20, 3, 0, 3}, /* PCI_AD20 */
- {6, 21, 3, 0, 3}, /* PCI_AD21 */
- {6, 22, 3, 0, 3}, /* PCI_AD22 */
- {6, 23, 3, 0, 3}, /* PCI_AD23 */
- {6, 24, 3, 0, 3}, /* PCI_AD24 */
- {6, 25, 3, 0, 3}, /* PCI_AD25 */
- {6, 26, 3, 0, 3}, /* PCI_AD26 */
- {6, 27, 3, 0, 3}, /* PCI_AD27 */
- {6, 28, 3, 0, 3}, /* PCI_AD28 */
- {6, 29, 3, 0, 3}, /* PCI_AD29 */
- {6, 30, 3, 0, 3}, /* PCI_AD30 */
- {6, 31, 3, 0, 3}, /* PCI_AD31 */
-
- /* NAND */
- {4, 18, 2, 0, 0}, /* NAND_RYnBY */
-
- /* DUART - UART2 */
- {5, 0, 1, 0, 2}, /* UART2_SOUT */
- {5, 2, 1, 0, 1}, /* UART2_RTS */
- {5, 3, 2, 0, 2}, /* UART2_SIN */
- {5, 1, 2, 0, 3}, /* UART2_CTS */
-
- /* UCC5 - UART3 */
- {3, 0, 1, 0, 1}, /* UART3_TX */
- {3, 4, 1, 0, 1}, /* UART3_RTS */
- {3, 6, 2, 0, 1}, /* UART3_RX */
- {3, 12, 2, 0, 0}, /* UART3_CTS */
- {3, 13, 2, 0, 0}, /* UCC5_CD */
-
- /* UCC6 - UART4 */
- {3, 14, 1, 0, 1}, /* UART4_TX */
- {3, 18, 1, 0, 1}, /* UART4_RTS */
- {3, 20, 2, 0, 1}, /* UART4_RX */
- {3, 26, 2, 0, 0}, /* UART4_CTS */
- {3, 27, 2, 0, 0}, /* UCC6_CD */
-
- /* Fujitsu MB86277 (MINT) graphics controller */
- {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
- {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */
- {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */
- {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
-
- /* AD7843 ADC/Touchscreen controller */
- {4, 14, 1, 0, 0}, /* SPI_nCS0 */
- {4, 28, 3, 0, 3}, /* SPI_MOSI */
- {4, 29, 3, 0, 3}, /* SPI_MISO */
- {4, 30, 3, 0, 3}, /* SPI_CLK */
-
- /* Freescale QUICC Engine USB Host Controller (FHCI) */
- {1, 2, 1, 0, 3}, /* USBOE */
- {1, 3, 1, 0, 3}, /* USBTP */
- {1, 8, 1, 0, 1}, /* USBTN */
- {1, 9, 2, 1, 3}, /* USBRP */
- {1, 10, 2, 0, 3}, /* USBRXD */
- {1, 11, 2, 1, 3}, /* USBRN */
- {2, 20, 2, 0, 1}, /* CLK21 */
- {4, 20, 1, 0, 0}, /* SPEED */
- {4, 21, 1, 0, 0}, /* SUSPND */
-
- /* END of table */
- {0, 0, 0, 0, QE_IOP_TAB_END},
-};
-
-int board_early_init_r(void)
-{
- void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
- u32 val;
-
- /*
- * Because of errata in the UCCs, we have to write to the reserved
- * registers to slow the clocks down.
- */
- val = in_be32(reg);
- /* UCC1 */
- val |= 0x00003000;
- /* UCC2 */
- val |= 0x0c000000;
- out_be32(reg, val);
-
- return 0;
-}
-
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1)
- return -1;
- }
-
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- udelay(200);
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- return msize;
-}
-
-phys_size_t initdram(int board_type)
-{
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
- msize = fixed_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize DDR ECC byte
- */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale/Logic MPC8360ERDK\n");
- return 0;
-}
-
-static struct pci_region pci_regions[] = {
- {
- .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
- .size = CONFIG_SYS_PCI1_MEM_SIZE,
- .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
- },
- {
- .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
- .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
- .size = CONFIG_SYS_PCI1_MMIO_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCI1_IO_BASE,
- .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
- .size = CONFIG_SYS_PCI1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions, };
-
-#if defined(CONFIG_PCI_33M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
- OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
- printf("PCI clock is 33MHz\n");
-#else
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#endif
-
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
- ft_pci_setup(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c
deleted file mode 100644
index 237c0c4..0000000
--- a/board/freescale/mpc8360erdk/nand.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * MPC8360E-RDK support for the NAND on FSL UPM
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/immap_83xx.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/fsl_upm.h>
-#include <nand.h>
-
-static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
-
-static const u32 upm_array[] = {
- 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */
- 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */
- 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */
- 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */
- 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */
- 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */
- 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */
- 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */
- 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */
- 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */
- 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */
- 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */
- 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */
-};
-
-static void upm_setup(struct fsl_upm *upm)
-{
- int i;
-
- /* write upm array */
- out_be32(upm->mxmr, MxMR_OP_WARR);
-
- for (i = 0; i < 64; i++) {
- out_be32(upm->mdr, upm_array[i]);
- out_8(upm->io_addr, 0x0);
- }
-
- /* normal operation */
- out_be32(upm->mxmr, MxMR_OP_NORM);
- while (in_be32(upm->mxmr) != MxMR_OP_NORM)
- eieio();
-}
-
-static int dev_ready(int chip_nr)
-{
- if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
- debug("nand ready\n");
- return 1;
- }
-
- debug("nand busy\n");
- return 0;
-}
-
-static struct fsl_upm_nand fun = {
- .upm = {
- .io_addr = (void *)CONFIG_SYS_NAND_BASE,
- },
- .width = 8,
- .upm_cmd_offset = 8,
- .upm_addr_offset = 16,
- .dev_ready = dev_ready,
- .wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
- .chip_delay = 50,
-};
-
-int board_nand_init(struct nand_chip *nand)
-{
- fun.upm.mxmr = &im->im_lbc.mamr;
- fun.upm.mdr = &im->im_lbc.mdr;
- fun.upm.mar = &im->im_lbc.mar;
-
- upm_setup(&fun.upm);
-
- return fsl_upm_nand_init(nand, &fun);
-}
diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS
index 8592a2c..81b4eed 100644
--- a/board/freescale/mpc837xerdb/MAINTAINERS
+++ b/board/freescale/mpc837xerdb/MAINTAINERS
@@ -1,6 +1,6 @@
MPC837XERDB BOARD
-#M: Joe D'Abbraccio <ljd015@freescale.com>
-S: Orphan (since 2014-06)
+M: Sinan Akman <sinan@writeme.com>
+S: Maintained
F: board/freescale/mpc837xerdb/
F: include/configs/MPC837XERDB.h
F: configs/MPC837XERDB_defconfig
diff --git a/board/freescale/p1_p2_rdb/Kconfig b/board/freescale/p1_p2_rdb/Kconfig
deleted file mode 100644
index d7ad35d..0000000
--- a/board/freescale/p1_p2_rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1_P2_RDB
-
-config SYS_BOARD
- default "p1_p2_rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P1_P2_RDB"
-
-endif
diff --git a/board/freescale/p1_p2_rdb/MAINTAINERS b/board/freescale/p1_p2_rdb/MAINTAINERS
deleted file mode 100644
index aabf587..0000000
--- a/board/freescale/p1_p2_rdb/MAINTAINERS
+++ /dev/null
@@ -1,37 +0,0 @@
-P1_P2_RDB BOARD
-#M: -
-S: Maintained
-F: board/freescale/p1_p2_rdb/
-F: include/configs/P1_P2_RDB.h
-F: configs/P1011RDB_defconfig
-F: configs/P1011RDB_36BIT_defconfig
-F: configs/P1011RDB_36BIT_SDCARD_defconfig
-F: configs/P1011RDB_36BIT_SPIFLASH_defconfig
-F: configs/P1011RDB_NAND_defconfig
-F: configs/P1011RDB_SDCARD_defconfig
-F: configs/P1011RDB_SPIFLASH_defconfig
-F: configs/P1020RDB_defconfig
-F: configs/P1020RDB_36BIT_defconfig
-F: configs/P1020RDB_36BIT_SDCARD_defconfig
-F: configs/P1020RDB_36BIT_SPIFLASH_defconfig
-F: configs/P1020RDB_NAND_defconfig
-F: configs/P1020RDB_SDCARD_defconfig
-F: configs/P1020RDB_SPIFLASH_defconfig
-F: configs/P2010RDB_defconfig
-F: configs/P2010RDB_36BIT_defconfig
-F: configs/P2010RDB_36BIT_SDCARD_defconfig
-F: configs/P2010RDB_36BIT_SPIFLASH_defconfig
-F: configs/P2010RDB_NAND_defconfig
-F: configs/P2010RDB_SDCARD_defconfig
-F: configs/P2010RDB_SPIFLASH_defconfig
-F: configs/P2020RDB_36BIT_defconfig
-F: configs/P2020RDB_36BIT_SDCARD_defconfig
-F: configs/P2020RDB_36BIT_SPIFLASH_defconfig
-F: configs/P2020RDB_NAND_defconfig
-F: configs/P2020RDB_SDCARD_defconfig
-F: configs/P2020RDB_SPIFLASH_defconfig
-
-P2020RDB BOARD
-M: Poonam Aggrwal <poonam.aggrwal@freescale.com>
-S: Maintained
-F: configs/P2020RDB_defconfig
diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
deleted file mode 100644
index a97bf45..0000000
--- a/board/freescale/p1_p2_rdb/Makefile
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += p1_p2_rdb.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-
-endif
diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README
deleted file mode 100644
index cd66e58..0000000
--- a/board/freescale/p1_p2_rdb/README
+++ /dev/null
@@ -1,145 +0,0 @@
-Overview
---------
-P2020RDB is a Low End Dual core platform supporting the P2020 processor
-of QorIQ series. P2020 is an e500 based dual core SOC.
-
-Building U-boot
------------
-To build the u-boot for P2020RDB:
- make P2020RDB_config
- make
-
-NOR Flash Banks
------------
-RDB board for P2020 has two flash banks. They are both present on boot.
-
-Booting by default is always from the boot bank at 0xef00_0000.
-
-Memory Map
-----------
-0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
-0xe800_0000 - 0xefff_ffff Boot bank 8MB
-
-0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB
-0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB
-
-Switch settings to boot from the NOR flash banks
-------------------------------------------------
-SW4[8]=0 default NOR Flash bank
-SW4[8]=1 Alternate NOR Flash bank
-
-Flashing Images
----------------
-To place a new u-boot image in the alternate flash bank and then boot
-with that new image temporarily, use this:
- tftp 1000000 u-boot.bin
- erase ef740000 ef7fffff
- cp.b 1000000 ef740000 c0000
-
-Now to boot from the alternate bank change the SW4[8] from 0 to 1.
-
-To program the image in the boot flash bank:
- tftp 1000000 u-boot.bin
- protect off all
- erase eff40000 ffffffff
- cp.b 1000000 eff40000 c0000
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
- tftp 1000000 uImage.p2020rdb
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp c00000 p2020rdb.dtb
- bootm 1000000 2000000 c00000
-
-Implementing AMP(Asymmetric MultiProcessing)
----------------------------------------------
-1. Build kernel image for core0:
-
- a. $ make 85xx/p1_p2_rdb_defconfig
-
- b. $ make menuconfig
- - un-select "Processor support"->
- "Symetric multi-processing support"
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
-
-2. Build kernel image for core1:
-
- a. $ make 85xx/p1_p2_rdb_defconfig
-
- b. $ make menuconfig
- - Un-select "Processor support"->
- "Symetric multi-processing support"
- - Select "Advanced setup" ->
- "Prompt for advanced kernel configuration options"
- - Select
- "Set physical address where the kernel is loaded"
- and set it to 0x20000000, assuming core1 will
- start from 512MB.
- - Select "Set custom page offset address"
- - Select "Set custom kernel base address"
- - Select "Set maximum low memory"
- - "Exit" and save the selection.
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
-
-3. Create dtb for core0:
-
- $ dtc -I dts -O dtb -f -b 0
- arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
- /tftpboot/p2020rdb_camp_core0.dtb
-
-4. Create dtb for core1:
-
- $ dtc -I dts -O dtb -f -b 1
- arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
- /tftpboot/p2020rdb_camp_core1.dtb
-
-5. Bring up two cores separately:
-
- a. Power on the board, under u-boot prompt:
- => setenv <serverip>
- => setenv <ipaddr>
- => setenv bootargs root=/dev/ram rw console=ttyS0,115200
- b. Bring up core1's kernel first:
- => setenv bootm_low 0x20000000
- => setenv bootm_size 0x10000000
- => tftp 21000000 uImage.core1
- => tftp 22000000 ramdiskfile
- => tftp 20c00000 p2020rdb_camp_core1.dtb
- => interrupts off
- => bootm start 21000000 22000000 20c00000
- => bootm loados
- => bootm ramdisk
- => bootm fdt
- => fdt boardsetup
- => fdt chosen $initrd_start $initrd_end
- => bootm prep
- => cpu 1 release $bootm_low - $fdtaddr -
- c. Bring up core0's kernel(on the same u-boot console):
- => setenv bootm_low 0
- => setenv bootm_size 0x20000000
- => tftp 1000000 uImage.core0
- => tftp 2000000 ramdiskfile
- => tftp c00000 p2020rdb_camp_core0.dtb
- => bootm 1000000 2000000 c00000
-
-Please note only core0 will run u-boot, core1 starts kernel directly
-after "cpu release" command is issued.
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
deleted file mode 100644
index 98ee5f1..0000000
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright 2009, 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
-#define CONFIG_SYS_DDR_TIMING_4 0x00000000
-#define CONFIG_SYS_DDR_TIMING_5 0x00000000
-
-#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
-#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
-#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
-#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_400 0x00480432
-#define CONFIG_SYS_DDR_MODE_2_400 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
-
-#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
-#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
-#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_533 0x00040642
-#define CONFIG_SYS_DDR_MODE_2_533 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
-
-#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
-#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
-#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
-#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
-#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
-#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
-#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- size_t ddr_size;
- struct cpu_type *cpu;
- ulong ddr_freq, ddr_freq_mhz;
-
- cpu = gd->arch.cpu;
-
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
-#if defined(CONFIG_SYS_RAMBOOT)
- return ddr_size;
-#endif
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
-
- if(ddr_freq_mhz <= 400)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
- else if(ddr_freq_mhz <= 533)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
- else if(ddr_freq_mhz <= 667)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
- else if(ddr_freq_mhz <= 800)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
- else
- panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
-
- /* P1020 and it's derivatives support max 32bit DDR width */
- if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
- ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
- ddr_cfg_regs.cs[0].bnds = 0x0000001F;
- }
-
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
- return ddr_size;
-}
diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c
deleted file mode 100644
index b60a27f..0000000
--- a/board/freescale/p1_p2_rdb/law.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
deleted file mode 100644
index 61ed466..0000000
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <vsc7385.h>
-#include <netdev.h>
-#include <rtc.h>
-#include <i2c.h>
-#include <hwconfig.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define VSC7385_RST_SET 0x00080000
-#define SLIC_RST_SET 0x00040000
-#define SGMII_PHY_RST_SET 0x00020000
-#define PCIE_RST_SET 0x00010000
-#define RGMII_PHY_RST_SET 0x02000000
-
-#define USB_RST_CLR 0x04000000
-#define USB2_PORT_OUT_EN 0x01000000
-
-#define GPIO_DIR 0x060f0000
-
-#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \
- SGMII_PHY_RST_SET | PCIE_RST_SET | \
- RGMII_PHY_RST_SET
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-#define BOARDREV_C 0x00100000
-#define BOARDREV_D 0x00000000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val_gpdat, sysclk_gpio;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- sysclk_gpio = val_gpdat & SYSCLK_MASK;
-
- if(sysclk_gpio == 0)
- return SYSCLK_66;
- else
- return SYSCLK_100;
-
- return 0;
-}
-
-#ifdef CONFIG_MMC
-int board_early_init_f (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
- return 0;
-}
-#endif
-
-int checkboard (void)
-{
- u32 val_gpdat, board_rev_gpio;
- volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- char board_rev = 0;
- struct cpu_type *cpu;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- board_rev_gpio = val_gpdat & BOARDREV_MASK;
- if (board_rev_gpio == BOARDREV_C)
- board_rev = 'C';
- else if (board_rev_gpio == BOARDREV_D)
- board_rev = 'D';
- else
- panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
-
- cpu = gd->arch.cpu;
- printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
-
- setbits_be32(&pgpio->gpdir, GPIO_DIR);
-
-/*
- * Bringing the following peripherals out of reset via GPIOs
- * 0 = reset and 1 = out of reset
- * GPIO12 - Reset to Ethernet Switch
- * GPIO13 - Reset to SLIC/SLAC devices
- * GPIO14 - Reset to SGMII_PHY_N
- * GPIO15 - Reset to PCIe slots
- * GPIO6 - Reset to RGMII PHY
- * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
- */
- clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR;
-
- setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
- setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
-#endif
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- unsigned int orig_bus = i2c_get_bus_num();
- u8 i2c_data;
-
- i2c_set_bus_num(1);
- if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
- 1, &i2c_data, sizeof(i2c_data)) == 0) {
- if (i2c_data & 0x2)
- puts("NOR Flash Bank : Secondary\n");
- else
- puts("NOR Flash Bank : Primary\n");
-
- if (i2c_data & 0x1) {
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
- puts("SD/MMC : 8-bit Mode\n");
- puts("eSPI : Disabled\n");
- } else {
- puts("SD/MMC : 4-bit Mode\n");
- puts("eSPI : Enabled\n");
- }
- } else {
- puts("Failed reading I2C Chip 0x18 on bus 1\n");
- }
- i2c_set_bus_num(orig_bus);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_16M, 1);
- rtc_reset();
- return 0;
-}
-
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
- char *tmp;
- unsigned int vscfw_addr;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-#ifdef CONFIG_VSC7385_ENET
-/* If a VSC7385 microcode image is present, then upload it. */
- if ((tmp = getenv ("vscfw_addr")) != NULL) {
- vscfw_addr = simple_strtoul (tmp, NULL, 16);
- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
- if (vsc7385_upload_firmware((void *) vscfw_addr,
- CONFIG_VSC7385_IMAGE_SIZE))
- puts("Failure uploading VSC7385 microcode.\n");
- } else
- puts("No address specified for VSC7385 microcode.\n");
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-extern void ft_pci_board_setup(void *blob);
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- const char *soc_usb_compat = "fsl-usb2-dr";
- int err, usb1_off, usb2_off;
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
-#if defined(CONFIG_PCI)
- ft_pci_board_setup(blob);
-#endif /* #if defined(CONFIG_PCI) */
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- /* Delete eLBC node as it is muxed with USB2 controller */
- if (hwconfig("usb2")) {
- const char *soc_elbc_compat = "fsl,p1020-elbc";
- int off = fdt_node_offset_by_compatible(blob, -1,
- soc_elbc_compat);
- if (off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_elbc_compat);
- return off;
- }
- err = fdt_del_node(blob, off);
- if (err < 0) {
- printf("WARNING: could not remove %s\n",
- soc_elbc_compat);
- return err;
- }
- return 0;
- }
-#endif
- /* Delete USB2 node as it is muxed with eLBC */
- usb1_off = fdt_node_offset_by_compatible(blob, -1,
- soc_usb_compat);
- if (usb1_off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_usb_compat);
- return usb1_off;
- }
- usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
- soc_usb_compat);
- if (usb2_off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_usb_compat);
- return usb2_off;
- }
- err = fdt_del_node(blob, usb2_off);
- if (err < 0) {
- printf("WARNING: could not remove %s\n", soc_usb_compat);
- return err;
- }
-
- return 0;
-}
-
-#endif
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
deleted file mode 100644
index 745ebb1..0000000
--- a/board/freescale/p1_p2_rdb/pci.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <asm/fsl_pci.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void ft_pci_board_setup(void *blob)
-{
- FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/p1_p2_rdb/spl.c b/board/freescale/p1_p2_rdb/spl.c
deleted file mode 100644
index f30c5fe..0000000
--- a/board/freescale/p1_p2_rdb/spl.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val_gpdat, sysclk_gpio;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- sysclk_gpio = val_gpdat & SYSCLK_MASK;
-
- if (sysclk_gpio == 0)
- return SYSCLK_66;
- else
- return SYSCLK_100;
-
- return 0;
-}
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
-#ifdef CONFIG_SPL_SPI_BOOT
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- gd->bus_clk = bus_clk;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
- probecpu();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
- gd->env_valid = 1;
-
- gd->ram_size = initdram(0);
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("Tertiary program loader running in sram...");
-#else
- puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/p1_p2_rdb/spl_minimal.c b/board/freescale/p1_p2_rdb/spl_minimal.c
deleted file mode 100644
index 96a4d1c..0000000
--- a/board/freescale/p1_p2_rdb/spl_minimal.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val_gpdat, sysclk_gpio;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- sysclk_gpio = val_gpdat & SYSCLK_MASK;
-
- if (sysclk_gpio == 0)
- return SYSCLK_66;
- else
- return SYSCLK_100;
-
- return 0;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
deleted file mode 100644
index 73f5729..0000000
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_16M, 1),
-
-#if defined(CONFIG_PCI)
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
-#endif /* #if defined(CONFIG_PCI) */
-#endif
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-
- /* *I*G - VSC7385 Switch */
- SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_1M, 1),
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#if CONFIG_SYS_L2_SIZE >= (256 << 10)
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_256K, 1),
-#endif
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_1G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2020come/Kconfig b/board/freescale/p2020come/Kconfig
deleted file mode 100644
index 8ce5cf1..0000000
--- a/board/freescale/p2020come/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P2020COME
-
-config SYS_BOARD
- default "p2020come"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P2020COME"
-
-endif
diff --git a/board/freescale/p2020come/MAINTAINERS b/board/freescale/p2020come/MAINTAINERS
deleted file mode 100644
index ab3ef94..0000000
--- a/board/freescale/p2020come/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-P2020COME BOARD
-M: Ira W. Snyder <iws@ovro.caltech.edu>
-S: Maintained
-F: board/freescale/p2020come/
-F: include/configs/P2020COME.h
-F: configs/P2020COME_SDCARD_defconfig
-F: configs/P2020COME_SPIFLASH_defconfig
diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile
deleted file mode 100644
index 4857136..0000000
--- a/board/freescale/p2020come/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += p2020come.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
deleted file mode 100644
index b642e12..0000000
--- a/board/freescale/p2020come/ddr.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2009, 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
-
- if (!pdimm->n_ranks)
- return;
-
- /*
- * Set DDR_SDRAM_CLK_CNTL = 0x02800000
- *
- * Clock is launched 5/8 applied cycle after address/command
- */
- popts->clk_adjust = 5;
-}
diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
deleted file mode 100644
index 7048a08..0000000
--- a/board/freescale/p2020come/law.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Create a dummy LAW entry for the DDR SDRAM which will be replaced when
- * the DDR SPD setup code runs.
- *
- * This table would be empty, except that it is used before the BSS section is
- * initialized, and therefore must have at least one entry to push it into
- * the DATA section.
- */
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
deleted file mode 100644
index 1db37e3..0000000
--- a/board/freescale/p2020come/p2020come.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * Copyright 2009,2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/mpc85xx_gpio.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <vsc7385.h>
-#include <netdev.h>
-#include <mmc.h>
-#include <malloc.h>
-#include <i2c.h>
-
-#if defined(CONFIG_PCI)
-#include <asm/fsl_pci.h>
-#include <pci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void ft_pci_board_setup(void *blob)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
-
-#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
- SGMII_PHY_RST_SET | PCIE_RST_SET | \
- RGMII_PHY_RST_SET)
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-#define BOARDREV_B 0x10100000
-#define BOARDREV_C 0x00100000
-#define BOARDREV_D 0x00000000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_50 50000000
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-
- ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- switch (ddr_ratio) {
- case 0x0C:
- return SYSCLK_66;
- case 0x0A:
- case 0x08:
- return SYSCLK_100;
- default:
- puts("ERROR: unknown DDR ratio\n");
- return SYSCLK_100;
- }
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-
- ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- switch (ddr_ratio) {
- case 0x0C:
- case 0x0A:
- return SYSCLK_66;
- case 0x08:
- return SYSCLK_100;
- default:
- puts("ERROR: unknown DDR ratio\n");
- return SYSCLK_100;
- }
-}
-
-#ifdef CONFIG_MMC
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
-
- /* All the device are enable except for SRIO12 */
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
- return 0;
-}
-#endif
-
-#define GPIO_DIR 0x0f3a0000
-#define GPIO_ODR 0x00000000
-#define GPIO_DAT 0x001a0000
-
-int checkboard(void)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
-
- /*
- * GPIO
- * 0 - 3: CarryBoard Input;
- * 4 - 7: CarryBoard Output;
- * 8 : Mux as SDHC_CD (card detection)
- * 9 : Mux as SDHC_WP
- * 10 : Clear Watchdog timer
- * 11 : LED Input
- * 12 : Output to 1
- * 13 : Open Drain
- * 14 : LED Output
- * 15 : Switch Input
- *
- * Set GPIOs 11, 12, 14 to 1.
- */
- out_be32(&pgpio->gpodr, GPIO_ODR);
- mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT);
-
- puts("Board: Freescale COM Express P2020\n");
- return 0;
-}
-
-#define M41ST85W_I2C_BUS 1
-#define M41ST85W_I2C_ADDR 0x68
-#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
-
-static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
-{
- u8 data;
-
- if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
- M41ST85W_ERROR("unable to read %s bit\n", name);
- return;
- }
-
- if (data & mask) {
- data &= ~mask;
- if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
- M41ST85W_ERROR("unable to clear %s bit\n", name);
- return;
- }
- }
-}
-
-#define M41ST85W_REG_SEC2 0x01
-#define M41ST85W_REG_SEC2_ST 0x80
-
-#define M41ST85W_REG_ALHOUR 0x0c
-#define M41ST85W_REG_ALHOUR_HT 0x40
-
-/*
- * The P2020COME board has a STMicro M41ST85W RTC/watchdog
- * at i2c bus 1 address 0x68.
- */
-static void start_rtc(void)
-{
- unsigned int bus = i2c_get_bus_num();
-
- if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
- M41ST85W_ERROR("unable to set i2c bus\n");
- goto out;
- }
-
- /* ensure ST (stop) and HT (halt update) bits are cleared */
- m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
- m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
-
-out:
- /* reset the i2c bus */
- i2c_set_bus_num(bus);
-}
-
-int board_early_init_r(void)
-{
- start_rtc();
- return 0;
-}
-
-#define M41ST85W_REG_WATCHDOG 0x09
-#define M41ST85W_REG_WATCHDOG_WDS 0x80
-#define M41ST85W_REG_WATCHDOG_BMB0 0x04
-
-void board_reset(void)
-{
- u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0;
-
- /* set the hardware watchdog timeout to 1/16 second, then hang */
- i2c_set_bus_num(M41ST85W_I2C_BUS);
- i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1);
-
- while (1)
- /* hang */;
-}
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
-#if defined(CONFIG_PCI)
- ft_pci_board_setup(blob);
-#endif
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
deleted file mode 100644
index 08a1e34..0000000
--- a/board/freescale/p2020come/tlb.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_PCI)
- /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * *I*G* - PCI I/O
- *
- * PCI3 => 0xFFC10000
- * PCI2 => 0xFFC2,0000
- * PCI1 => 0xFFC3,0000
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
-#endif /* #if defined(CONFIG_PCI) */
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2020ds/Kconfig b/board/freescale/p2020ds/Kconfig
deleted file mode 100644
index e527ec9..0000000
--- a/board/freescale/p2020ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P2020DS
-
-config SYS_BOARD
- default "p2020ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P2020DS"
-
-endif
diff --git a/board/freescale/p2020ds/MAINTAINERS b/board/freescale/p2020ds/MAINTAINERS
deleted file mode 100644
index cb61fc5..0000000
--- a/board/freescale/p2020ds/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-P2020DS BOARD
-#M: -
-S: Maintained
-F: board/freescale/p2020ds/
-F: include/configs/P2020DS.h
-F: configs/P2020DS_defconfig
-F: configs/P2020DS_36BIT_defconfig
-F: configs/P2020DS_DDR2_defconfig
-F: configs/P2020DS_SDCARD_defconfig
-F: configs/P2020DS_SPIFLASH_defconfig
diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile
deleted file mode 100644
index ee00806..0000000
--- a/board/freescale/p2020ds/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright 2007-2009 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += p2020ds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
deleted file mode 100644
index debe70b..0000000
--- a/board/freescale/p2020ds/ddr.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- *
- * ranges for parameters:
- * wr_data_delay = 0-6
- * clk adjust = 0-8
- * cpo 2-0x1E (30)
- */
-static const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
-#ifdef CONFIG_SYS_FSL_DDR2
- {2, 549, 4, 0x1f, 2, 0},
- {2, 680, 4, 0x1f, 3, 0},
- {2, 850, 4, 0x1f, 4, 0},
- {1, 549, 4, 0x1f, 2, 0},
- {1, 680, 4, 0x1f, 3, 0},
- {1, 850, 4, 0x1f, 4, 0},
-#else
- {2, 850, 6, 0x1f, 4, 0},
- {1, 850, 4, 0x1f, 4, 0},
-#endif
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- int i;
-
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
- * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
- * there are two dimms in the controller, set odt_rd_cfg to 3 and
- * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
- */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 1;
- }
-
- pbsp = dimm0;
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- popts->wrlvl_en = 1;
- /* Write leveling override */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xa;
- popts->wrlvl_start = 0x8;
- /* Rtt and Rtt_WR override */
- popts->rtt_override = 1;
- popts->rtt_override_value = DDR3_RTT_120_OHM;
- popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
-}
diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
deleted file mode 100644
index 9cd4da9..0000000
--- a/board/freescale/p2020ds/law.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
deleted file mode 100644
index 5d18e8d..0000000
--- a/board/freescale/p2020ds/p2020ds.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Copyright 2007-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <asm/fsl_law.h>
-#include <netdev.h>
-
-#include "../common/ngpixis.h"
-#include "../common/sgmii_riser.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_MMC
- ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- u8 sw;
-
- printf("Board: P2020DS Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
-
- sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
- sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- /* The lower two bits are the actual vbank number */
- printf("vBank: %d\n", sw & 3);
- else
- puts("Promjet\n");
-
- return 0;
-}
-
-#if !defined(CONFIG_DDR_SPD)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- uint d_init;
-
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
- ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
- ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
- ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
- ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
- ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
-
- if (!strcmp("performance", getenv("perf_mode"))) {
- /* Performance Mode Values */
-
- ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
- ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
-
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
- } else {
- /* Stable Mode Values */
-
- ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
- /* ECC will be assumed in stable mode */
- ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
- ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
- ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
- }
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
- udelay(1000);
- debug("DDR: memory initialized\n\n");
- asm("sync; isync");
- udelay(500);
-#endif
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
- LAW_TRGT_IF_DDR) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- return 0;
-}
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
-}
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
-
- return 0;
- }
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_init(tsec_info, num);
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c
deleted file mode 100644
index 02da6e8..0000000
--- a/board/freescale/p2020ds/tlb.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-
- SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 46fc64e..2d4d10f 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -152,6 +153,19 @@
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -166,5 +180,10 @@
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
index f3141b5..708afca 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -19,10 +19,10 @@
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
-#include <asm/mpc85xx_gpio.h>
#include "../common/qixis.h"
#include "t102xqds.h"
#include "t102xqds_qixis.h"
+#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -242,6 +242,16 @@
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
}
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
@@ -395,14 +405,3 @@
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
}
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h
index 5a3100f..db50f81 100644
--- a/board/freescale/t102xrdb/cpld.h
+++ b/board/freescale/t102xrdb/cpld.h
@@ -43,3 +43,7 @@
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
+
+#define CPLD_PCIE_SGMII_MUX 0x80
+#define CPLD_OVERRIDE_BOOT_EN 0x01
+#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index a20330b..a2a8f4c 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -136,6 +137,19 @@
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(cpld_base + 0x17, 0x40);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -150,5 +164,10 @@
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 2e400c4..f611ff0 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -21,6 +21,7 @@
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
+#include "../common/fman.h"
int board_eth_init(bd_t *bis)
{
@@ -51,15 +52,22 @@
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+ /* Set the on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
case 0x95:
- /* 10G XFI with Aquantia PHY */
+ /* set the on-board RGMII2 PHY */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+
+ /* set 10G XFI with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
+ case 0x77:
+ case 0x135:
+ /* set the on-board 2.5G SGMII AQR105 PHY */
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
+ break;
default:
printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
srds_s1);
@@ -73,6 +81,10 @@
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
default:
break;
}
@@ -95,6 +107,18 @@
return pci_eth_init(bis);
}
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
+ (port == FM1_DTSEC3)) {
+ fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
+ fdt_setprop(fdt, offset, "phy-connection-type",
+ "sgmii-2500", 10);
+ fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
+ }
+}
+
void fdt_fixup_board_enet(void *fdt)
{
}
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index dd2dec4..1a3a996 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -11,6 +11,7 @@
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,12 @@
console_init_f();
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index f5c438d..e196f12 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -16,10 +16,10 @@
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
-#include <asm/mpc85xx_gpio.h>
#include <fm_eth.h>
#include "t102xrdb.h"
#include "cpld.h"
+#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -27,6 +27,11 @@
{
struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
@@ -50,7 +55,40 @@
#endif
puts("SERDES Reference Clocks:\n");
- printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+ if (srds_s1 == 0x95)
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+ else
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
+
+ return 0;
+}
+
+static void board_mux_lane(void)
+{
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1;
+ u8 reg = CPLD_READ(misc_ctl_status);
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ if (srds_prtcl_s1 == 0x95) {
+ /* Route Lane B to PCIE */
+ CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
+ } else {
+ /* Route Lane B to SGMII */
+ CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
+ }
+ CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
+}
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
return 0;
}
@@ -86,6 +124,7 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
+ board_mux_lane();
return 0;
}
@@ -131,14 +170,3 @@
return 0;
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 43f952f..8240240 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -100,6 +101,19 @@
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -112,5 +126,10 @@
dram_size *= 0x100000;
puts(" DDR: ");
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 06d9086..8c82934 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -18,6 +18,7 @@
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/fsl_dtsec.h>
+#include <vsc9953.h>
#include "../common/fman.h"
#include "../common/qixis.h"
@@ -216,6 +217,7 @@
lane_to_slot[1] = 7;
lane_to_slot[2] = 7;
lane_to_slot[3] = 7;
+ lane_to_slot[6] = 7;
lane_to_slot[7] = 7;
break;
case 0x8d:
@@ -438,6 +440,12 @@
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
unsigned int i;
+#ifdef CONFIG_VSC9953
+ int lane;
+ int phy_addr;
+ phy_interface_t phy_int;
+ struct mii_dev *bus;
+#endif
printf("Initializing Fman\n");
set_brdcfg9_for_gtx_clk();
@@ -477,6 +485,7 @@
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
+ fm_info_set_mdio(i, NULL);
break;
case PHY_INTERFACE_MODE_SGMII:
t1040_handle_phy_interface_sgmii(i);
@@ -491,6 +500,90 @@
}
}
+#ifdef CONFIG_VSC9953
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ lane = -1;
+ phy_addr = 0;
+ phy_int = PHY_INTERFACE_MODE_NONE;
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
+ /* PHYs connected over QSGMII */
+ if (lane >= 0) {
+ phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
+ i;
+ phy_int = PHY_INTERFACE_MODE_QSGMII;
+ break;
+ }
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_SW1_MAC1 + i);
+
+ if (lane < 0)
+ break;
+
+ /* PHYs connected over QSGMII */
+ if (i != 3 || lane_to_slot[lane] == 7)
+ phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ + i;
+ else
+ phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
+ phy_int = PHY_INTERFACE_MODE_SGMII;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
+ /* PHYs connected over QSGMII */
+ if (lane >= 0) {
+ phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
+ i - 4;
+ phy_int = PHY_INTERFACE_MODE_QSGMII;
+ break;
+ }
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_SW1_MAC1 + i);
+ /* PHYs connected over SGMII */
+ if (lane >= 0) {
+ phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ + i - 3;
+ phy_int = PHY_INTERFACE_MODE_SGMII;
+ }
+ break;
+ case 8:
+ if (serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1) < 0)
+ /* FM1@DTSEC1 is connected to SW1@PORT8 */
+ vsc9953_port_enable(i);
+ break;
+ case 9:
+ if (serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC2) < 0) {
+ /* Enable L2 On MAC2 using SCFG */
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+ CONFIG_SYS_MPC85xx_SCFG;
+
+ out_be32(&scfg->esgmiiselcr,
+ in_be32(&scfg->esgmiiselcr) |
+ (0x80000000));
+ vsc9953_port_enable(i);
+ }
+ break;
+ }
+
+ if (lane >= 0) {
+ bus = mii_dev_for_muxval(lane_to_slot[lane]);
+ vsc9953_port_info_set_mdio(i, bus);
+ vsc9953_port_enable(i);
+ }
+ vsc9953_port_info_set_phy_address(i, phy_addr);
+ vsc9953_port_info_set_phy_int(i, phy_int);
+ }
+
+#endif
cpu_eth_init(bis);
#endif
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 13285be..eaca57f 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -19,8 +19,8 @@
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
-#include <asm/mpc85xx_gpio.h>
+#include "../common/sleep.h"
#include "../common/qixis.h"
#include "t1040qds.h"
#include "t1040qds_qixis.h"
@@ -115,6 +115,16 @@
}
}
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
@@ -281,14 +291,3 @@
{
return 1;
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index b61e1c0..13d9be9 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -21,3 +21,4 @@
M: Aneesh Bansal <aneesh.bansal@freescale.com>
S: Maintained
F: configs/T1040RDB_SECURE_BOOT_defconfig
+F: configs/T1042RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index c8b6c67..7581a4cd 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -6,11 +6,13 @@
#include <common.h>
#include <netdev.h>
+#include <asm/fsl_serdes.h>
#include <asm/immap_85xx.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/fsl_dtsec.h>
+#include <vsc9953.h>
#include "../common/fman.h"
@@ -20,6 +22,11 @@
struct memac_mdio_info memac_mdio_info;
unsigned int i;
int phy_addr = 0;
+#ifdef CONFIG_VSC9953
+ phy_interface_t phy_int;
+ struct mii_dev *bus;
+#endif
+
printf("Initializing Fman\n");
memac_mdio_info.regs =
@@ -72,10 +79,58 @@
fm_info_set_phy_address(i, 0);
break;
}
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
+ fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
+ fm_info_set_mdio(i, NULL);
+ else
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(
+ DEFAULT_FM_MDIO_NAME));
}
+#ifdef CONFIG_VSC9953
+ /* SerDes configured for QSGMII */
+ if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
+ for (i = 0; i < 4; i++) {
+ bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+ phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+ vsc9953_port_info_set_mdio(i, bus);
+ vsc9953_port_info_set_phy_address(i, phy_addr);
+ vsc9953_port_info_set_phy_int(i, phy_int);
+ vsc9953_port_enable(i);
+ }
+ }
+ if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
+ for (i = 4; i < 8; i++) {
+ bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+ phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+ vsc9953_port_info_set_mdio(i, bus);
+ vsc9953_port_info_set_phy_address(i, phy_addr);
+ vsc9953_port_info_set_phy_int(i, phy_int);
+ vsc9953_port_enable(i);
+ }
+ }
+
+ /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
+ if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
+ vsc9953_port_enable(8);
+
+ /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
+ if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
+ /* Enable L2 On MAC2 using SCFG */
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+ CONFIG_SYS_MPC85xx_SCFG;
+
+ out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
+ (0x80000000));
+ vsc9953_port_enable(9);
+ }
+#endif
+
cpu_eth_init(bis);
#endif
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 142c6a8..879bd1a 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -101,7 +101,7 @@
}
#if (CONFIG_SYS_NUM_FMAN == 2)
- if (srds_prtcl_s2 == 56) {
+ if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
/* SGMII && XFI */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index fdbbe5e..e46c7b2 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 27_56_1_9
+#serdes protocol 27_55_1_9
16070019 18101916 00000000 00000000
-6c700848 00448c00 6c020000 f5000000
+6c6e0848 00448c00 6c020000 f5000000
00000000 ee0000ee 00000000 000287fc
00000000 50000000 00000000 00000028
diff --git a/board/g2000/Kconfig b/board/g2000/Kconfig
deleted file mode 100644
index 031fae9..0000000
--- a/board/g2000/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_G2000
-
-config SYS_BOARD
- default "g2000"
-
-config SYS_CONFIG_NAME
- default "G2000"
-
-endif
diff --git a/board/g2000/MAINTAINERS b/board/g2000/MAINTAINERS
deleted file mode 100644
index 8171b10..0000000
--- a/board/g2000/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-G2000 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/g2000/
-F: include/configs/G2000.h
-F: configs/G2000_defconfig
diff --git a/board/g2000/Makefile b/board/g2000/Makefile
deleted file mode 100644
index 74c8053..0000000
--- a/board/g2000/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = g2000.o strataflash.o
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
deleted file mode 100644
index a64f946..0000000
--- a/board/g2000/g2000.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-
-#define MEM_MCOPT1_INIT_VAL 0x00800000
-#define MEM_RTR_INIT_VAL 0x04070000
-#define MEM_PMIT_INIT_VAL 0x07c00000
-#define MEM_MB0CF_INIT_VAL 0x00082001
-#define MEM_MB1CF_INIT_VAL 0x04082000
-#define MEM_SDTR1_INIT_VAL 0x00854005
-#define SDRAM0_CFG_ENABLE 0x80000000
-
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
-
-int board_early_init_f (void)
-{
-#if 0 /* test-only */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr (UIC0ER, 0x00000000); /* disable all ints */
- mtdcr (UIC0CR, 0x00000010);
- mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */
- mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */
- mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
-#else
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-#endif
-
-#if 1 /* test-only */
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-#endif
-
- return 0;
-}
-
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
-int misc_init_r (void)
-{
-#if defined(CONFIG_CMD_NAND)
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);
-#endif
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming G2000");
- } else {
- puts(str);
- }
-
- putc ('\n');
-
- return 0;
-}
-
-
-/* -------------------------------------------------------------------------
- G2000 rev B is an embeded design. we don't read for spd of this version.
- Doing static SDRAM controller configuration in the following section.
- ------------------------------------------------------------------------- */
-
-long int init_sdram_static_settings(void)
-{
- /* disable memcontroller so updates work */
- mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL);
- mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL);
- mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL);
- mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL);
- mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL);
- mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL);
-
- /* SDRAM have a power on delay, 500 micro should do */
- udelay(500);
- mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE);
-
- return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
- }
-
-
-phys_size_t initdram (int board_type)
-{
- long int ret;
-
-/* flzt, we can still turn this on in the future */
-/* #ifdef CONFIG_SPD_EEPROM
- ret = spd_sdram ();
-#else
- ret = init_sdram_static_settings();
-#endif
-*/
-
- ret = init_sdram_static_settings();
-
- return ret;
-}
-
-#if 0 /* test-only !!! */
-int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong ap, cr;
-
- printf("\nEBC registers for PPC405GP:\n");
- mfebc(PB0AP, ap); mfebc(PB0CR, cr);
- printf("0: AP=%08lx CP=%08lx\n", ap, cr);
- mfebc(PB1AP, ap); mfebc(PB1CR, cr);
- printf("1: AP=%08lx CP=%08lx\n", ap, cr);
- mfebc(PB2AP, ap); mfebc(PB2CR, cr);
- printf("2: AP=%08lx CP=%08lx\n", ap, cr);
- mfebc(PB3AP, ap); mfebc(PB3CR, cr);
- printf("3: AP=%08lx CP=%08lx\n", ap, cr);
- mfebc(PB4AP, ap); mfebc(PB4CR, cr);
- printf("4: AP=%08lx CP=%08lx\n", ap, cr);
- printf("\n");
-
- return 0;
-}
-U_BOOT_CMD(
- dumpebc, 1, 1, do_dumpebc,
- "Dump all EBC registers",
- ""
-);
-
-
-int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
-
- printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
- for (i=0; i<=0x1e0; i++) {
- if (!(i % 0x8)) {
- printf("\n%04x ", i);
- }
- printf("%08lx ", get_dcr(i));
- }
- printf("\n");
-
- return 0;
-}
-U_BOOT_CMD(
- dumpdcr, 1, 1, do_dumpdcr,
- "Dump all DCR registers",
- ""
-);
-
-
-int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
- printf("\n%04x %08x ", 947, mfspr(947));
- printf("\n%04x %08x ", 9, mfspr(9));
- printf("\n%04x %08x ", 1014, mfspr(1014));
- printf("\n%04x %08x ", 1015, mfspr(1015));
- printf("\n%04x %08x ", 1010, mfspr(1010));
- printf("\n%04x %08x ", 957, mfspr(957));
- printf("\n%04x %08x ", 1008, mfspr(1008));
- printf("\n%04x %08x ", 1018, mfspr(1018));
- printf("\n%04x %08x ", 954, mfspr(954));
- printf("\n%04x %08x ", 950, mfspr(950));
- printf("\n%04x %08x ", 951, mfspr(951));
- printf("\n%04x %08x ", 981, mfspr(981));
- printf("\n%04x %08x ", 980, mfspr(980));
- printf("\n%04x %08x ", 982, mfspr(982));
- printf("\n%04x %08x ", 1012, mfspr(1012));
- printf("\n%04x %08x ", 1013, mfspr(1013));
- printf("\n%04x %08x ", 948, mfspr(948));
- printf("\n%04x %08x ", 949, mfspr(949));
- printf("\n%04x %08x ", 1019, mfspr(1019));
- printf("\n%04x %08x ", 979, mfspr(979));
- printf("\n%04x %08x ", 8, mfspr(8));
- printf("\n%04x %08x ", 945, mfspr(945));
- printf("\n%04x %08x ", 987, mfspr(987));
- printf("\n%04x %08x ", 287, mfspr(287));
- printf("\n%04x %08x ", 953, mfspr(953));
- printf("\n%04x %08x ", 955, mfspr(955));
- printf("\n%04x %08x ", 272, mfspr(272));
- printf("\n%04x %08x ", 273, mfspr(273));
- printf("\n%04x %08x ", 274, mfspr(274));
- printf("\n%04x %08x ", 275, mfspr(275));
- printf("\n%04x %08x ", 260, mfspr(260));
- printf("\n%04x %08x ", 276, mfspr(276));
- printf("\n%04x %08x ", 261, mfspr(261));
- printf("\n%04x %08x ", 277, mfspr(277));
- printf("\n%04x %08x ", 262, mfspr(262));
- printf("\n%04x %08x ", 278, mfspr(278));
- printf("\n%04x %08x ", 263, mfspr(263));
- printf("\n%04x %08x ", 279, mfspr(279));
- printf("\n%04x %08x ", 26, mfspr(26));
- printf("\n%04x %08x ", 27, mfspr(27));
- printf("\n%04x %08x ", 990, mfspr(990));
- printf("\n%04x %08x ", 991, mfspr(991));
- printf("\n%04x %08x ", 956, mfspr(956));
- printf("\n%04x %08x ", 284, mfspr(284));
- printf("\n%04x %08x ", 285, mfspr(285));
- printf("\n%04x %08x ", 986, mfspr(986));
- printf("\n%04x %08x ", 984, mfspr(984));
- printf("\n%04x %08x ", 256, mfspr(256));
- printf("\n%04x %08x ", 1, mfspr(1));
- printf("\n%04x %08x ", 944, mfspr(944));
- printf("\n");
-
- return 0;
-}
-U_BOOT_CMD(
- dumpspr, 1, 1, do_dumpspr,
- "Dump all SPR registers",
- ""
-);
-#endif
diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c
deleted file mode 100644
index 1d29eb4..0000000
--- a/board/g2000/strataflash.c
+++ /dev/null
@@ -1,774 +0,0 @@
-/*
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-#undef DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for ppcboot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI 0x98
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xD0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xD0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
-
-#define FLASH_STATUS_DONE 0x80
-#define FLASH_STATUS_ESS 0x40
-#define FLASH_STATUS_ECLBS 0x20
-#define FLASH_STATUS_PSLBS 0x10
-#define FLASH_STATUS_VPENS 0x08
-#define FLASH_STATUS_PSS 0x04
-#define FLASH_STATUS_DPS 0x02
-#define FLASH_STATUS_R 0x01
-#define FLASH_STATUS_PROTECT 0x01
-
-#define FLASH_OFFSET_CFI 0x55
-#define FLASH_OFFSET_CFI_RESP 0x10
-#define FLASH_OFFSET_WTOUT 0x1F
-#define FLASH_OFFSET_WBTOUT 0x20
-#define FLASH_OFFSET_ETOUT 0x21
-#define FLASH_OFFSET_CETOUT 0x22
-#define FLASH_OFFSET_WMAX_TOUT 0x23
-#define FLASH_OFFSET_WBMAX_TOUT 0x24
-#define FLASH_OFFSET_EMAX_TOUT 0x25
-#define FLASH_OFFSET_CEMAX_TOUT 0x26
-#define FLASH_OFFSET_SIZE 0x27
-#define FLASH_OFFSET_INTERFACE 0x28
-#define FLASH_OFFSET_BUFFER_SIZE 0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
-#define FLASH_OFFSET_ERASE_REGIONS 0x2D
-#define FLASH_OFFSET_PROTECT 0x02
-#define FLASH_OFFSET_USER_PROTECTION 0x85
-#define FLASH_OFFSET_INTEL_PROTECTION 0x81
-
-#define FLASH_MAN_CFI 0x01000000
-
-typedef union {
- unsigned char c;
- unsigned short w;
- unsigned long l;
-} cfiword_t;
-
-typedef union {
- unsigned char * cp;
- unsigned short *wp;
- unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
-{
- return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
-}
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
-{
- uchar *cp;
- cp = flash_make_addr(info, 0, offset);
- return (cp[info->portwidth - 1]);
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
-{
- uchar * addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
-{
- uchar * addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
- (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size;
- int i;
- unsigned long address;
-
-
- /* The flash is positioned back to back, with the demultiplexing of the chip
- * based on the A24 address line.
- *
- */
-
- address = CONFIG_SYS_FLASH_BASE;
- size = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- size += flash_info[i].size = flash_get_size(address, i);
- address += CONFIG_SYS_FLASH_INCREMENT;
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
- flash_info[0].size, flash_info[i].size<<20);
- }
- }
-
-#if 0 /* test-only */
- /* Monitor protection ON by default */
-#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
- for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
- (void)flash_real_protect(&flash_info[0], i, 1);
-#endif
-#else
- /* monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- - CONFIG_SYS_MONITOR_LEN,
- - 1, &flash_info[1]);
-#endif
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int rcode = 0;
- int prot;
- int sect;
-
- if( info->flash_id != FLASH_MAN_CFI) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
- if ((s_first < 0) || (s_first > s_last)) {
- printf ("- no sectors to erase\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
-
- if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
- rcode = 1;
- } else
- printf(".");
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- printf("CFI conformant FLASH (%d x %d)",
- (info->portwidth << 3 ), (info->chipwidth << 3 ));
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
- info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- /* print empty and read-only info */
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
-#else
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
-#endif
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong wp;
- ulong cp;
- int aln;
- cfiword_t cword;
- int i, rc;
-
- /* get lower aligned address */
- wp = (addr & ~(info->portwidth - 1));
-
- /* handle unaligned start */
- if((aln = addr - wp) != 0) {
- cword.l = 0;
- cp = wp;
- for(i=0;i<aln; ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
-
- for(; (i< info->portwidth) && (cnt > 0) ; i++) {
- flash_add_byte(info, &cword, *src++);
- cnt--;
- cp++;
- }
- for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp = cp;
- }
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- while(cnt >= info->portwidth) {
- i = info->buffer_size > cnt? cnt: info->buffer_size;
- if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
- return rc;
- wp += i;
- src += i;
- cnt -=i;
- }
-#else
- /* handle the aligned part */
- while(cnt >= info->portwidth) {
- cword.l = 0;
- for(i = 0; i < info->portwidth; i++) {
- flash_add_byte(info, &cword, *src++);
- }
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp += info->portwidth;
- cnt -= info->portwidth;
- }
-#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- cword.l = 0;
- for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
- flash_add_byte(info, &cword, *src++);
- --cnt;
- }
- for (; i<info->portwidth; ++i, ++cp) {
- flash_add_byte(info, & cword, (*(uchar *)cp));
- }
-
- return flash_write_cfiword(info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- int retcode = 0;
-
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
- if(prot)
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
- if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
- prot?"protect":"unprotect")) == 0) {
-
- info->protect[sector] = prot;
- /* Intel's unprotect unprotects all locking */
- if(prot == 0) {
- int i;
- for(i = 0 ; i<info->sector_count; i++) {
- if(info->protect[i])
- flash_real_protect(info, i, 1);
- }
- }
- }
-
- return retcode;
-}
-/*-----------------------------------------------------------------------
- * wait for XSR.7 to be set. Time out with an error if it does not.
- * This routine does not set the flash to read-array mode.
- */
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
- ulong start;
-
- /* Wait for command completion */
- start = get_timer (0);
- while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
- if (get_timer(start) > info->erase_blk_tout) {
- printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return ERR_TIMOUT;
- }
- }
- return ERR_OK;
-}
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
- int retcode;
- retcode = flash_status_check(info, sector, tout, prompt);
- if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
- printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
- if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
- printf("Command Sequence Error.\n");
- } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
- printf("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
- } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
- printf("Locking Error\n");
- }
- if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
- printf("Block locked.\n");
- retcode = ERR_PROTECTED;
- }
- if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
- printf("Vpp Low Error.\n");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return retcode;
-}
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
-{
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cword->c = c;
- break;
- case FLASH_CFI_16BIT:
- cword->w = (cword->w << 8) | c;
- break;
- case FLASH_CFI_32BIT:
- cword->l = (cword->l << 8) | c;
- }
-}
-
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
-{
- int i;
- uchar *cp = (uchar *)cmdbuf;
- for(i=0; i< info->portwidth; i++)
- *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-
- volatile cfiptr_t addr;
- cfiword_t cword;
- addr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- *addr.cp = cword.c;
- break;
- case FLASH_CFI_16BIT:
- *addr.wp = cword.w;
- break;
- case FLASH_CFI_32BIT:
- *addr.lp = cword.l;
- break;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = (cptr.cp[0] == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = (cptr.wp[0] == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = (cptr.lp[0] == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-/*-----------------------------------------------------------------------
- */
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
-*/
-static int flash_detect_cfi(flash_info_t * info)
-{
-
- for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
- info->portwidth <<= 1) {
- for(info->chipwidth =FLASH_CFI_BY8;
- info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
- if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
- return 1;
- }
- }
- return 0;
-}
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size (ulong base, int banknum)
-{
- flash_info_t * info = &flash_info[banknum];
- int i, j;
- int sect_cnt;
- unsigned long sector;
- unsigned long tmp;
- int size_ratio;
- uchar num_erase_regions;
- int erase_region_size;
- int erase_region_count;
-
- info->start[0] = base;
-
- if(flash_detect_cfi(info)){
-#ifdef DEBUG_FLASH
- printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
- size_ratio = info->portwidth / info->chipwidth;
- num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-#ifdef DEBUG_FLASH
- printf("found %d erase regions\n", num_erase_regions);
-#endif
- sect_cnt = 0;
- sector = base;
- for(i = 0 ; i < num_erase_regions; i++) {
- if(i > NUM_ERASE_REGIONS) {
- printf("%d erase regions found, only %d used\n",
- num_erase_regions, NUM_ERASE_REGIONS);
- break;
- }
- tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
- erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
- tmp >>= 16;
- erase_region_count = (tmp & 0xffff) +1;
- for(j = 0; j< erase_region_count; j++) {
- info->start[sect_cnt] = sector;
- sector += (erase_region_size * size_ratio);
- info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
- sect_cnt++;
- }
- }
-
- info->sector_count = sect_cnt;
- /* multiply the size by the number of chips */
- info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
- info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
- info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
- info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
- info->flash_id = FLASH_MAN_CFI;
- }
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- return(info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
-{
-
- cfiptr_t cptr;
- int flag;
-
- cptr.cp = (uchar *)dest;
-
- /* Check if Flash is (sufficiently) erased */
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- flag = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- flag = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- return 2;
- }
- if(!flag)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
-
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cptr.cp[0] = cword.c;
- break;
- case FLASH_CFI_16BIT:
- cptr.wp[0] = cword.w;
- break;
- case FLASH_CFI_32BIT:
- cptr.lp[0] = cword.l;
- break;
- }
-
- /* re-enable interrupts if necessary */
- if(flag)
- enable_interrupts();
-
- return flash_full_status_check(info, 0, info->write_tout, "write");
-}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector(flash_info_t *info, ulong addr)
-{
- int sector;
- for(sector = info->sector_count - 1; sector >= 0; sector--) {
- if(addr >= info->start[sector])
- break;
- }
- return sector;
-}
-
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
-{
-
- int sector;
- int cnt;
- int retcode;
- volatile cfiptr_t src;
- volatile cfiptr_t dst;
-
- src.cp = cp;
- dst.cp = (uchar *)dest;
- sector = find_sector(info, dest);
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- if (len & 0x1) { /* test-only: unaligned size */
- puts("\nUnalgined size!!!\n"); /* test-only */
- cnt++;
- }
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- flash_write_cmd(info, sector, 0, (uchar)cnt-1);
- while(cnt-- > 0) {
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- *dst.lp++ = *src.lp++;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
- "buffer write");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- return retcode;
-}
-#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 7f79fd2..33a31f3 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -14,6 +14,7 @@
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
+ select X86_RESET_VECTOR
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
@@ -29,4 +30,12 @@
bool "Enable early post to Chrome OS EC"
default y
+config SYS_CAR_ADDR
+ hex
+ default 0xff7e0000
+
+config SYS_CAR_SIZE
+ hex
+ default 0x20000
+
endif
diff --git a/board/icecube/Kconfig b/board/icecube/Kconfig
deleted file mode 100644
index e5b2153..0000000
--- a/board/icecube/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_ICECUBE
-
-config SYS_BOARD
- default "icecube"
-
-config SYS_CONFIG_NAME
- default "IceCube"
-
-endif
diff --git a/board/icecube/MAINTAINERS b/board/icecube/MAINTAINERS
deleted file mode 100644
index 8a24eb4..0000000
--- a/board/icecube/MAINTAINERS
+++ /dev/null
@@ -1,21 +0,0 @@
-ICECUBE BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/icecube/
-F: include/configs/IceCube.h
-F: configs/icecube_5200_defconfig
-
-ICECUBE_5200_DDR BOARD
-#M: -
-S: Maintained
-F: configs/icecube_5200_DDR_defconfig
-F: configs/icecube_5200_DDR_LOWBOOT_defconfig
-F: configs/icecube_5200_DDR_LOWBOOT08_defconfig
-F: configs/icecube_5200_LOWBOOT_defconfig
-F: configs/icecube_5200_LOWBOOT08_defconfig
-F: configs/Lite5200_defconfig
-F: configs/Lite5200_LOWBOOT_defconfig
-F: configs/Lite5200_LOWBOOT08_defconfig
-F: configs/lite5200b_defconfig
-F: configs/lite5200b_LOWBOOT_defconfig
-F: configs/lite5200b_PM_defconfig
diff --git a/board/icecube/Makefile b/board/icecube/Makefile
deleted file mode 100644
index c3c2cd1..0000000
--- a/board/icecube/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := icecube.o flash.o
diff --git a/board/icecube/README b/board/icecube/README
deleted file mode 100644
index 5252bc9..0000000
--- a/board/icecube/README
+++ /dev/null
@@ -1,13 +0,0 @@
----------------------------------------------------------------------------
-Build target Flash address | BDI "go" command | Reset Vector
----------------------------------------------------------------------------
-Lite5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100
-Lite5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100
-Lite5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
-icecube_5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100
-icecube_5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100
-icecube_5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
-icecube_5200_DDR 0xFFF00000 | 0xFFF00100 | 0xFFF00100
-icecube_5200_DDR_LOWBOOT 0xFF800000 | 0xFF800100 | 0x00000100
-icecube_5200_DDR_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
----------------------------------------------------------------------------
diff --git a/board/icecube/README.Lite5200B_low_power b/board/icecube/README.Lite5200B_low_power
deleted file mode 100644
index 5b04fbb..0000000
--- a/board/icecube/README.Lite5200B_low_power
+++ /dev/null
@@ -1,22 +0,0 @@
-Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM)
-----------------------------------------------------------
-
-Low-power mode as described in Lite5200B User's Manual, means that
-with support of MC68HLC908QT1 microcontroller (refered to as QT),
-everything but the SDRAM can be powered down. This brings
-maximum power saving, while one can still restore previous state
-quickly.
-
-Quick overview where U-Boot comes into the picture:
-- OS saves device states
-- OS saves wakeup handler address to physical 0x0, puts SDRAM into
- self-refresh and signals to QT, it should power down the board
-- / board is sleeping here /
-- someone presses SW4 (connected to QT)
-- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up,
- so get SDRAM out of self-refresh and transfer control to OS
- wakeup handler
-- OS restores device states
-
-This was tested on Linux with USB and Ethernet in use. Adding
-support for other devices is an OS issue.
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
deleted file mode 100644
index a044e8f..0000000
--- a/board/icecube/flash.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#ifndef CONFIG_FLASH_CFI_DRIVER
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
- * has nothing to do with the flash chip being 8-bit or 16-bit.
- */
-#ifdef CONFIG_FLASH_16BIT
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-#define FLASH_ID_MASK 0xFFFF
-#else
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-#define FLASH_ID_MASK 0xFF
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-#define FLASH_CYCLE1 0x0555
-#define FLASH_CYCLE2 0x02aa
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- unsigned long size = 0;
- int i;
- extern void flash_preinit(void);
- extern void flash_afterinit(ulong);
- ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
- flash_preinit();
-
- /* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- memset(&flash_info[i], 0, sizeof(flash_info_t));
-
- flash_info[i].size =
- flash_get_size((FPW *)flashbase, &flash_info[i]);
-
- size += flash_info[i].size;
- flashbase += 0x800000;
- }
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
- flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-
- flash_afterinit(size);
- return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
- FPWV *base = (FPWV *)(info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
- *base = (FPW)0x00FF00FF; /* Intel Read Mode */
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- *base = (FPW)0x00F000F0; /* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
- int i;
- flash_info_t * info;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
- info = & flash_info[i];
- if (info->size &&
- info->start[0] <= base && base <= info->start[0] + info->size - 1)
- break;
- }
-
- return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- uchar *boottype;
- uchar *bootletter;
- char *fmt;
- uchar botbootletter[] = "B";
- uchar topbootletter[] = "T";
- uchar botboottype[] = "bottom boot sector";
- uchar topboottype[] = "top boot sector";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- /* check for top or bottom boot, if it applies */
- if (info->flash_id & FLASH_BTYPE) {
- boottype = botboottype;
- bootletter = botbootletter;
- }
- else {
- boottype = topboottype;
- bootletter = topbootletter;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDLV065D:
- fmt = "29LV065 (64 Mbit, uniform sectors)\n";
- break;
- default:
- fmt = "Unknown Chip Type\n";
- break;
- }
-
- printf (fmt, bootletter, boottype);
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
-
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
- int i;
- FPWV* addr2;
-
- /* Write auto select command: read Manufacturer ID */
- /* Write auto select command sequence and test FLASH answer */
- addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte.
- * This works for any bus width and any FLASH device width.
- */
- udelay(100);
- switch (addr[0] & 0xff) {
-
- case (uchar)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case (uchar)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
-
- case (FPW)AMD_ID_LV065D:
- info->flash_id += FLASH_AMDLV065D;
- info->sector_count = 128;
- info->size = 0x00800000;
- for( i = 0; i < info->sector_count; i++ )
- info->start[i] = (ulong)addr + (i * 0x10000);
- break; /* => 8 or 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* => no or unknown flash */
- }
-
- /* test for real flash at bank 1 */
- addr2 = (FPW *)((ulong)addr | 0x800000);
- if (addr2 != addr &&
- ((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
- /* Seems 2 banks are the same space (8Mb chip is installed,
- * J24 in default position (CS0)). Disable this (first) bank.
- */
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- }
- /* Put FLASH back in read mode */
- flash_reset(info);
-
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- FPWV *addr;
- int flag, prot, sect;
- int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDLV065D:
- break;
- case FLASH_UNKNOWN:
- default:
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- last = get_timer(0);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
- if (info->protect[sect] != 0) /* protected, skip it */
- continue;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr = (FPWV *)(info->start[sect]);
- if (intel) {
- *addr = (FPW)0x00500050; /* clear status register */
- *addr = (FPW)0x00200020; /* erase setup */
- *addr = (FPW)0x00D000D0; /* erase confirm */
- }
- else {
- /* must be AMD style if not Intel */
- FPWV *base; /* first address in bank */
-
- base = (FPWV *)(info->start[0]);
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- *addr = (FPW)0x00300030; /* erase sector */
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer(0);
-
- /* wait at least 50us for AMD, 80us for Intel.
- * Let's wait 1 ms.
- */
- udelay (1000);
-
- while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
-
- if (intel) {
- /* suspend erase */
- *addr = (FPW)0x00B000B0;
- }
-
- flash_reset(info); /* reset to read mode */
- rcode = 1; /* failed */
- break;
- }
-
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
- putc ('.');
- last = get_timer(0);
- }
- }
-
- /* show that we're waiting */
- if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
- putc ('.');
- last = get_timer(0);
- }
-
- flash_reset(info); /* reset to read mode */
- }
-
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
- int bytes; /* number of bytes to program in current word */
- int left; /* number of bytes left to program */
- int i, res;
-
- for (left = cnt, res = 0;
- left > 0 && res == 0;
- addr += sizeof(data), left -= sizeof(data) - bytes) {
-
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
-
- /* combine source and destination data so can program
- * an entire word of 16 or 32 bits
- */
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left )
- data += *((uchar *)addr + i);
- else
- data += *src++;
- }
-
- /* write one word to the flash */
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- res = write_word_amd(info, (FPWV *)addr, data);
- break;
- default:
- /* unknown flash type, error! */
- printf ("missing or unknown FLASH type\n");
- res = 1; /* not really a timeout, but gives error */
- break;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
-
- base = (FPWV *)(info->start[0]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- /* data polling for D7 */
- while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00F000F0; /* reset bank */
- res = 1;
- }
- }
-
- return (res);
-}
-#endif /*CONFIG_FLASH_CFI_DRIVER*/
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
deleted file mode 100644
index f0af24a..0000000
--- a/board/icecube/icecube.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <libfdt.h>
-#include <netdev.h>
-
-#if defined(CONFIG_LITE5200B)
-#include "mt46v32m16.h"
-#else
-# if defined(CONFIG_MPC5200_DDR)
-# include "mt46v16m16-75.h"
-# else
-#include "mt48lc16m16a2-75.h"
-# endif
-#endif
-
-#ifdef CONFIG_LITE5200B_PM
-/* u-boot part of low-power mode implementation */
-#define SAVED_ADDR (*(void **)0x00000000)
-#define PSC2_4 0x02
-
-void lite5200b_wakeup(void)
-{
- unsigned char wakeup_pin;
- void (*linux_wakeup)(void);
-
- /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
- * from low power mode */
- *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
- __asm__ volatile ("sync");
-
- wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
- if (wakeup_pin & PSC2_4)
- return;
-
- /* acknowledge to "QT"
- * by holding pin at 1 for 10 uS */
- *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
- __asm__ volatile ("sync");
- *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
- __asm__ volatile ("sync");
- udelay(10);
-
- /* put ram out of self-refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
- __asm__ volatile ("sync");
- *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
- __asm__ volatile ("sync");
- *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
- __asm__ volatile ("sync");
- udelay(10); /* wait a bit */
-
- /* jump back to linux kernel code */
- linux_wakeup = SAVED_ADDR;
- printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
- (unsigned long)linux_wakeup);
- linux_wakeup();
-}
-#else
-#define lite5200b_wakeup()
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
- uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
- /* find RAM size using SDRAM CS1 only */
- if (!dramsize)
- sdram_start(0);
- test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- if (!dramsize) {
- sdram_start(1);
- test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- }
- if (test1 > test2) {
- sdram_start(0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
- | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
- * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
- *
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
- * parameters."
- */
- svr = get_svr();
- pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) &&
- (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
- *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
- __asm__ volatile ("sync");
- }
-
- lite5200b_wakeup();
-
- return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-#if defined (CONFIG_LITE5200B)
- puts ("Board: Freescale Lite5200B\n");
-#else
- puts ("Board: Motorola MPC5200 (IceCube)\n");
-#endif
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong size)
-{
- if (size == 0x800000) { /* adjust mapping */
- *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
- START_REG(CONFIG_SYS_BOOTCS_START | size);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
- STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
- }
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
- /* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
- /* Deassert reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
- /* Make a delay. MPC5200 spec says 25 usec min */
- udelay(500000);
- } else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
- }
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in FEC comes first */
- return pci_eth_init(bis);
-}
diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h
deleted file mode 100644
index 919876f..0000000
--- a/board/icecube/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x705f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h
deleted file mode 100644
index a200bc7..0000000
--- a/board/icecube/mt46v32m16.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x704f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa..0000000
--- a/board/icecube/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig
index 4709f9b..762663a 100644
--- a/board/intel/crownbay/Kconfig
+++ b/board/intel/crownbay/Kconfig
@@ -14,6 +14,7 @@
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
+ select X86_RESET_VECTOR
select INTEL_QUEENSBAY
select BOARD_ROMSIZE_KB_1024
diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg
index 3c63a03..f4260fa 100644
--- a/board/iomega/iconnect/kwbimage.cfg
+++ b/board/iomega/iconnect/kwbimage.cfg
@@ -20,7 +20,7 @@
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xffd100e0 0x1b1b1b9b
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+# Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xffd01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
# bit23-14: 0x0,
@@ -87,7 +87,7 @@
# bit6-4: 0x4, CL=5
# bit7: 0x0, TestMode=0 normal
# bit8: 0x0, DLL reset=0 normal
-# bit11-9: 0x6, auto-precharge write recovery ????????????
+# bit11-9: 0x6, auto-precharge write recovery
# bit12: 0x0, PD must be zero
# bit31-13: 0x0, required
diff --git a/board/pm520/Kconfig b/board/pm520/Kconfig
deleted file mode 100644
index 3f0a258..0000000
--- a/board/pm520/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PM520
-
-config SYS_BOARD
- default "pm520"
-
-config SYS_CONFIG_NAME
- default "PM520"
-
-endif
diff --git a/board/pm520/MAINTAINERS b/board/pm520/MAINTAINERS
deleted file mode 100644
index 7b255bc..0000000
--- a/board/pm520/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-PM520 BOARD
-M: Josef Wagner <Wagner@Microsys.de>
-S: Maintained
-F: board/pm520/
-F: include/configs/PM520.h
-F: configs/PM520_defconfig
-F: configs/PM520_DDR_defconfig
-F: configs/PM520_ROMBOOT_defconfig
-F: configs/PM520_ROMBOOT_DDR_defconfig
diff --git a/board/pm520/Makefile b/board/pm520/Makefile
deleted file mode 100644
index 8b5a7eb..0000000
--- a/board/pm520/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := pm520.o flash.o
diff --git a/board/pm520/flash.c b/board/pm520/flash.c
deleted file mode 100644
index 89c9f02..0000000
--- a/board/pm520/flash.c
+++ /dev/null
@@ -1,659 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x) (x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) (x)
-#endif
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT 0x00890089
-#define INTEL_ALT 0x00B000B0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x00100010
-#define INTEL_ERASE 0x00200020
-#define INTEL_CLEAR 0x00500050
-#define INTEL_LOCKBIT 0x00600060
-#define INTEL_PROTECT 0x00010001
-#define INTEL_STATUS 0x00700070
-#define INTEL_READID 0x00900090
-#define INTEL_CONFIRM 0x00D000D0
-#define INTEL_RESET 0xFFFFFFFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x00800080
-#define INTEL_OK 0x00800080
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-void inline spin_wheel (void);
-static void flash_sync_real_protect (flash_info_t * info);
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
- extern void flash_preinit(void);
- extern void flash_afterinit(ulong, ulong);
- ulong flashbase = CONFIG_SYS_FLASH_BASE;
-
- flash_preinit();
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- memset(&flash_info[i], 0, sizeof(flash_info_t));
- flash_get_size ((FPW *) flashbase, &flash_info[i]);
- flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
- break;
- default:
- panic ("configured to many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
-
- /* get the h/w and s/w protection status in sync */
- flash_sync_real_protect(&flash_info[i]);
- }
-
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#ifndef CONFIG_BOOT_ROM
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0] );
-#endif
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
-#endif
-
- flash_afterinit(flash_info[0].start[0], flash_info[0].size);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F256J3A:
- printf ("28F256J3A\n");
- break;
-
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
-
- case FLASH_28F640J3A:
- printf ("28F640J3A\n");
- break;
-
- case FLASH_28F320J3A:
- printf ("28F320J3A\n");
- break;
-
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info)
-{
- volatile FPW value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- mb ();
- udelay(100);
-
- value = addr[0];
-
- switch (value) {
-
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[1]; /* device ID */
-
- switch (value) {
-
- case (FPW) INTEL_ID_28F256J3A:
- info->flash_id += FLASH_28F256J3A;
- /* In U-Boot we support only 32 MB (no bank-switching) */
- info->sector_count = 256 / 2;
- info->size = 0x04000000 / 2;
- info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
- break; /* => 32 MB */
-
- case (FPW) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x02000000;
- info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
- break; /* => 32 MB */
-
- case (FPW) INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x01000000;
- info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03000000;
- break; /* => 16 MB */
-
- case (FPW) INTEL_ID_28F320J3A:
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x800000;
- info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03800000;
- break; /* => 8 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*
- * This function gets the u-boot flash sector protection status
- * (flash_info_t.protect[]) in sync with the sector protection
- * status stored in hardware.
- */
-static void flash_sync_real_protect (flash_info_t * info)
-{
- int i;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
-
- case FLASH_28F256J3A:
- case FLASH_28F128J3A:
- case FLASH_28F640J3A:
- case FLASH_28F320J3A:
- for (i = 0; i < info->sector_count; ++i) {
- info->protect[i] = intel_sector_protected(info, i);
- }
- break;
- default:
- /* no h/w protect support */
- break;
- }
-}
-
-
-/*
- * checks if "sector" in bank "info" is protected. Should work on intel
- * strata flash chips 28FxxxJ3x in 8-bit mode.
- * Returns 1 if sector is protected (or timed-out while trying to read
- * protection status), 0 if it is not.
- */
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
-{
- FPWV *addr;
- FPWV *lock_conf_addr;
- ulong start;
- unsigned char ret;
-
- /*
- * first, wait for the WSM to be finished. The rationale for
- * waiting for the WSM to become idle for at most
- * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
- * because of: (1) erase, (2) program or (3) lock bit
- * configuration. So we just wait for the longest timeout of
- * the (1)-(3), i.e. the erase timeout.
- */
-
- /* wait at least 35ns (W12) before issuing Read Status Register */
- udelay(1);
- addr = (FPWV *) info->start[sector];
- *addr = (FPW) INTEL_STATUS;
-
- start = get_timer (0);
- while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
- if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- *addr = (FPW) INTEL_RESET; /* restore read mode */
- printf("WSM busy too long, can't get prot status\n");
- return 1;
- }
- }
-
- /* issue the Read Identifier Codes command */
- *addr = (FPW) INTEL_READID;
-
- /* wait at least 35ns (W12) before reading */
- udelay(1);
-
- /* Intel example code uses offset of 2 for 16 bit flash */
- lock_conf_addr = (FPWV *) info->start[sector] + 2;
- ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
-
- /* put flash back in read mode */
- *addr = (FPW) INTEL_RESET;
-
- return ret;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = (FPW) 0x00B000B0; /* suspend erase */
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- rcode = 1;
- break;
- }
- }
-
- *addr = 0x00500050; /* clear status register cmd. */
- *addr = 0x00FF00FF; /* resest to read mode */
-
- printf (" done\n");
- }
- }
-
- if (flag)
- enable_interrupts();
-
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- ulong start;
- int flag;
- int rcode = 0;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- rcode = 1;
- break;
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
-
- if (flag)
- enable_interrupts();
-
- return rcode;
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect (flash_info_t *info, long sector, int prot)
-{
- ulong start;
- int i;
- int rc = 0;
- vu_long *addr = (vu_long *)(info->start[sector]);
- int flag = disable_interrupts();
-
- *addr = INTEL_CLEAR; /* Clear status register */
- if (prot) { /* Set sector lock bit */
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- }
- else { /* Clear sector lock bit */
- *addr = INTEL_LOCKBIT; /* All sectors lock bits */
- *addr = INTEL_CONFIRM; /* clear */
- }
-
- start = get_timer(0);
-
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
- printf("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- if (!rc)
- info->protect[sector] = prot;
-
- /*
- * Clear lock bit command clears all sectors lock bits, so
- * we have to restore lock bits of protected sectors.
- * WARNING: code below re-locks sectors only for one bank (info).
- * This causes problems on boards where several banks share
- * the same chip, as sectors in othere banks will be unlocked
- * but not re-locked. It works fine on pm520 though, as there
- * is only one chip and one bank.
- */
- if (!prot)
- {
- for (i = 0; i < info->sector_count; i++)
- {
- if (info->protect[i])
- {
- start = get_timer(0);
- addr = (vu_long *)(info->start[i]);
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
- {
- if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT)
- {
- printf("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
- }
- }
- /*
- * get the s/w sector protection status in sync with the h/w,
- * in case something went wrong during the re-locking.
- */
- flash_sync_real_protect(info); /* resets flash to read mode */
- }
-
- if (flag)
- enable_interrupts();
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h
deleted file mode 100644
index 9068fbf..0000000
--- a/board/pm520/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x714f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa..0000000
--- a/board/pm520/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c
deleted file mode 100644
index 4ec4505..0000000
--- a/board/pm520/pm520.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m16a2-75.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
- /* find RAM size using SDRAM CS1 only */
- if (!dramsize)
- sdram_start(0);
- test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- if (!dramsize) {
- sdram_start(1);
- test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- }
- if (test1 > test2) {
- sdram_start(0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
- | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
- puts ("Board: MicroSys PM520 \n");
- return 0;
-}
-
-void flash_preinit(void)
-{
- /*
- * Now, when we are in RAM, enable flash write
- * access for detection process.
- * Note that CS_BOOT cannot be cleared when
- * executing in flash.
- */
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-void flash_afterinit(ulong start, ulong size)
-{
-#if defined(CONFIG_BOOT_ROM)
- /* adjust mapping */
- *(vu_long *)MPC5XXX_CS1_START =
- START_REG(start);
- *(vu_long *)MPC5XXX_CS1_STOP =
- STOP_REG(start, size);
-#else
- /* adjust mapping */
- *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
- START_REG(start);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
- STOP_REG(start, size);
-#endif
-}
-
-
-extern flash_info_t flash_info[]; /* info for FLASH chips */
-
-int misc_init_r (void)
-{
- /* adjust flash start */
- gd->bd->bi_flashstart = flash_info[0].start[0];
- return (0);
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
-}
-#endif
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in FEC comes first */
- return pci_eth_init(bis);
-}
diff --git a/board/ppmc7xx/Kconfig b/board/ppmc7xx/Kconfig
deleted file mode 100644
index f101940..0000000
--- a/board/ppmc7xx/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PPMC7XX
-
-config SYS_BOARD
- default "ppmc7xx"
-
-config SYS_CONFIG_NAME
- default "ppmc7xx"
-
-endif
diff --git a/board/ppmc7xx/MAINTAINERS b/board/ppmc7xx/MAINTAINERS
deleted file mode 100644
index a0c1f44..0000000
--- a/board/ppmc7xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PPMC7XX BOARD
-#M: -
-S: Maintained
-F: board/ppmc7xx/
-F: include/configs/ppmc7xx.h
-F: configs/ppmc7xx_defconfig
diff --git a/board/ppmc7xx/Makefile b/board/ppmc7xx/Makefile
deleted file mode 100644
index f8957f3..0000000
--- a/board/ppmc7xx/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := init.o
-obj-y += ppmc7xx.o pci.o flash.o
diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c
deleted file mode 100644
index e724227..0000000
--- a/board/ppmc7xx/flash.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/*
- * flash.c
- * -------
- *
- * Flash programming routines for the Wind River PPMC 74xx/7xx
- * based on flash.c from the TQM8260 board.
- *
- * By Richard Danter (richard.danter@windriver.com)
- * Copyright (C) 2005 Wind River Systems
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <74xx_7xx.h>
-
-#define DWORD unsigned long long
-
-/* Local function prototypes */
-static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
-static void write_via_fpu (volatile DWORD* addr, DWORD* data);
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- */
-void flash_reset (void)
-{
- unsigned long msr;
- DWORD cmd_reset = 0x00F000F000F000F0LL;
-
- if (flash_info[0].flash_id != FLASH_UNKNOWN) {
- msr = get_msr ();
- set_msr (msr | MSR_FP);
-
- write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
-
- set_msr (msr);
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_get_size (ulong baseaddr, flash_info_t * info)
-{
- int i;
- unsigned long msr;
- DWORD flashtest;
- DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
- 0x0090009000900090LL };
-
- /* Enable FPU */
- msr = get_msr ();
- set_msr (msr | MSR_FP);
-
- /* Write auto-select command sequence */
- write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
- write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
- write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
-
- /* Restore FPU */
- set_msr (msr);
-
- /* Read manufacturer ID */
- flashtest = *(volatile DWORD*)baseaddr;
- switch ((int)flashtest) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- /* No, faulty or unknown flash */
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0);
- }
-
- /* Read device ID */
- flashtest = *(volatile DWORD*)(baseaddr + 8);
- switch ((long)flashtest) {
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00400000;
- break;
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00400000;
- break;
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00800000;
- break;
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00800000;
- break;
- case AMD_ID_DL322T:
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x01000000;
- break;
- case AMD_ID_DL322B:
- info->flash_id += FLASH_AMDL322B;
- info->sector_count = 71;
- info->size = 0x01000000;
- break;
- case AMD_ID_DL323T:
- info->flash_id += FLASH_AMDL323T;
- info->sector_count = 71;
- info->size = 0x01000000;
- break;
- case AMD_ID_DL323B:
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x01000000;
- break;
- case AMD_ID_LV640U:
- info->flash_id += FLASH_AM640U;
- info->sector_count = 128;
- info->size = 0x02000000;
- break;
- default:
- /* Unknown flash type */
- info->flash_id = FLASH_UNKNOWN;
- return (0);
- }
-
- if ((long)flashtest == AMD_ID_LV640U) {
- /* set up sector start adress table (uniform sector type) */
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = baseaddr + (i * 0x00040000);
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set up sector start adress table (bottom sector type) */
- info->start[0] = baseaddr + 0x00000000;
- info->start[1] = baseaddr + 0x00010000;
- info->start[2] = baseaddr + 0x00018000;
- info->start[3] = baseaddr + 0x00020000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
- }
- } else {
- /* set up sector start adress table (top sector type) */
- i = info->sector_count - 1;
- info->start[i--] = baseaddr + info->size - 0x00010000;
- info->start[i--] = baseaddr + info->size - 0x00018000;
- info->start[i--] = baseaddr + info->size - 0x00020000;
- for (; i >= 0; i--) {
- info->start[i] = baseaddr + i * 0x00040000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
- info->protect[i] = 1; /* D0 = 1 if protected */
- } else {
- info->protect[i] = 0;
- }
- }
-
- flash_reset ();
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size_b0 = 0;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here (only one bank) */
- size_b0 = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 >> 20);
- }
-
- /*
- * protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf ("FUJITSU ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM800T:
- printf ("29LV800T (8 M, top sector)\n");
- break;
- case FLASH_AM800B:
- printf ("29LV800T (8 M, bottom sector)\n");
- break;
- case FLASH_AM160T:
- printf ("29LV160T (16 M, top sector)\n");
- break;
- case FLASH_AM160B:
- printf ("29LV160B (16 M, bottom sector)\n");
- break;
- case FLASH_AMDL322T:
- printf ("29DL322T (32 M, top sector)\n");
- break;
- case FLASH_AMDL322B:
- printf ("29DL322B (32 M, bottom sector)\n");
- break;
- case FLASH_AMDL323T:
- printf ("29DL323T (32 M, top sector)\n");
- break;
- case FLASH_AMDL323B:
- printf ("29DL323B (32 M, bottom sector)\n");
- break;
- case FLASH_AM640U:
- printf ("29LV640D (64 M, uniform sector)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- unsigned long msr;
- DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
- 0x0080008000800080LL, 0x00AA00AA00AA00AALL,
- 0x0055005500550055LL, 0x0030003000300030LL };
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Enable FPU */
- msr = get_msr();
- set_msr ( msr | MSR_FP );
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
- write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
- write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
- write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
- write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
- udelay (1000);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* Restore FPU */
- set_msr (msr);
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
- != 0x0080008000800080LL )
- {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- flash_reset ();
-
- printf (" done\n");
- return 0;
-}
-
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong dp;
- static unsigned char bb[8];
- int i, l, rc, cc = cnt;
-
- dp = (addr & ~7); /* get lower dword aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - dp) != 0) {
- for (i = 0; i < 8; i++)
- bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
- if ((rc = write_dword (info, dp, bb)) != 0) {
- return (rc);
- }
- dp += 8;
- cc -= 8 - l;
- }
-
- /*
- * handle word aligned part
- */
- while (cc >= 8) {
- if ((rc = write_dword (info, dp, src)) != 0) {
- return (rc);
- }
- dp += 8;
- src += 8;
- cc -= 8;
- }
-
- if (cc <= 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- for (i = 0; i < 8; i++) {
- bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
- }
- return (write_dword (info, dp, bb));
-}
-
-/*-----------------------------------------------------------------------
- * Write a dword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
-{
- ulong start;
- unsigned long msr;
- int flag, i;
- DWORD data;
- DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
- 0x00A000A000A000A0LL };
-
- for (data = 0, i = 0; i < 8; i++)
- data = (data << 8) + *pdata++;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*(DWORD*)dest & data) != data) {
- return (2);
- }
-
- /* Enable FPU */
- msr = get_msr();
- set_msr( msr | MSR_FP );
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
- write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
- write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
- write_via_fpu ((DWORD*)dest, &data );
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* Restore FPU */
- set_msr(msr);
-
- /* data polling for D7 */
- start = get_timer (0);
- while (*(volatile DWORD*)dest != data ) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void write_via_fpu (volatile DWORD* addr, DWORD* data)
-{
- __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
- __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
- __asm__ __volatile__ ("eieio");
-}
diff --git a/board/ppmc7xx/init.S b/board/ppmc7xx/init.S
deleted file mode 100644
index 99a818a..0000000
--- a/board/ppmc7xx/init.S
+++ /dev/null
@@ -1,336 +0,0 @@
-/*
- * init.S
- * ------
- *
- * Wind River PPMC 7xx/74xx init code.
- *
- * By Richard Danter (richard.danter@windriver.com)
- * Copyright (C) 2005 Wind River Systems
- *
- * NOTE: The following code was generated automatically by Workbench
- * from the ppmc7400_107.reg register file.
- */
-
-#include <ppc_asm.tmpl>
-
-
-.globl board_asm_init
-board_asm_init:
-
- lis r4,0xFEC0
- ori r4,r4,0x0000
- lis r5,0xFEE0
- ori r5,r5,0x0000
- lis r3,0x8000 # ADDR_00
- ori r3,r3,0x0000
- stwbrx r3,0,r4
- li r3,0x1057 # VENDOR
- li r8, 0x0
- sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_02
- ori r3,r3,0x0002
- stwbrx r3,0,r4
- li r3,0x0004 # ID
- li r8, 0x2
- sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_04
- ori r3,r3,0x0004
- stwbrx r3,0,r4
- li r3,0x0006 # PCICMD
- li r8, 0x0
- sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_06
- ori r3,r3,0x0006
- stwbrx r3,0,r4
- li r3,0x00A0 # PCISTAT
- li r8, 0x2
- sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_08
- ori r3,r3,0x0008
- stwbrx r3,0,r4
- li r3,0x10 # REVID
- stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_09
- ori r3,r3,0x0009
- stwbrx r3,0,r4
- li r3,0x00 # PROGIR
- stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_0A
- ori r3,r3,0x000A
- stwbrx r3,0,r4
- li r3,0x00 # SUBCCODE
- stb r3,0x2(r5)
- lis r3,0x8000 # ADDR_0B
- ori r3,r3,0x000B
- stwbrx r3,0,r4
- li r3,0x06 # PBCCR
- stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_0C
- ori r3,r3,0x000C
- stwbrx r3,0,r4
- li r3,0x08 # PCLSR
- stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_0D
- ori r3,r3,0x000D
- stwbrx r3,0,r4
- li r3,0x00 # PLTR
- stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_0E
- ori r3,r3,0x000E
- stwbrx r3,0,r4
- li r3,0x00 # HEADTYPE
- stb r3,0x2(r5)
- lis r3,0x8000 # ADDR_0F
- ori r3,r3,0x000F
- stwbrx r3,0,r4
- li r3,0x00 # BISTCTRL
- stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_10
- ori r3,r3,0x0010
- stwbrx r3,0,r4
- lis r3,0x0000 # LMBAR
- ori r3,r3,0x0008
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_14
- ori r3,r3,0x0014
- stwbrx r3,0,r4
- lis r3,0xF000 # PCSRBAR
- ori r3,r3,0x0000
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_3C
- ori r3,r3,0x003C
- stwbrx r3,0,r4
- li r3,0x00 # ILR
- stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_3D
- ori r3,r3,0x003D
- stwbrx r3,0,r4
- li r3,0x01 # INTPIN
- stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_3E
- ori r3,r3,0x003E
- stwbrx r3,0,r4
- li r3,0x00 # MIN_GNT
- stb r3,0x2(r5)
- lis r3,0x8000 # ADDR_3F
- ori r3,r3,0x003F
- stwbrx r3,0,r4
- li r3,0x00 # MAX_LAT
- stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_40
- ori r3,r3,0x0040
- stwbrx r3,0,r4
- li r3,0x00 # BUSNB
- stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_41
- ori r3,r3,0x0041
- stwbrx r3,0,r4
- li r3,0x00 # SBUSNB
- stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_46
- ori r3,r3,0x0046
- stwbrx r3,0,r4
-# li r3,0xE080 # PCIARB
- li r3,-0x1F80 # PCIARB
- li r8, 0x2
- sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_70
- ori r3,r3,0x0070
- stwbrx r3,0,r4
- li r3,0x0000 # PMCR1
- li r8, 0x0
- sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_72
- ori r3,r3,0x0072
- stwbrx r3,0,r4
- li r3,0xC0 # PMCR2
- stb r3,0x2(r5)
- lis r3,0x8000 # ADDR_73
- ori r3,r3,0x0073
- stwbrx r3,0,r4
- li r3,0xEF # ODCR
- stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_74
- ori r3,r3,0x0074
- stwbrx r3,0,r4
- li r3,0x7D00 # CLKDCR
- li r8, 0x0
- sthbrx r3,r8,r5
- lis r3,0x8000 # ADDR_76
- ori r3,r3,0x0076
- stwbrx r3,0,r4
- li r3,0x00 # MDCR
- stb r3,0x2(r5)
- lis r6,0xFCE0
- ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
- lis r3,0x8000 # ADDR_78
- ori r3,r3,0x0078
- stwbrx r3,0,r4
- lis r3,0xFCE0 # EUMBBAR
- ori r3,r3,0x0000
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_80
- ori r3,r3,0x0080
- stwbrx r3,0,r4
- lis r3,0xFFFF # MSADDR1
- ori r3,r3,0x4000
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_84
- ori r3,r3,0x0084
- stwbrx r3,0,r4
- lis r3,0xFFFF # MSADDR2
- ori r3,r3,0xFFFF
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_88
- ori r3,r3,0x0088
- stwbrx r3,0,r4
- lis r3,0x0303 # EMSADDR1
- ori r3,r3,0x0000
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_8C
- ori r3,r3,0x008C
- stwbrx r3,0,r4
- lis r3,0x0303 # EMSADDR2
- ori r3,r3,0x0303
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_90
- ori r3,r3,0x0090
- stwbrx r3,0,r4
- lis r3,0xFFFF # EMEADDR1
- ori r3,r3,0x7F3F
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_94
- ori r3,r3,0x0094
- stwbrx r3,0,r4
- lis r3,0xFFFF # EMEADDR2
- ori r3,r3,0xFFFF
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_98
- ori r3,r3,0x0098
- stwbrx r3,0,r4
- lis r3,0x0303 # EXTEMEM1
- ori r3,r3,0x0000
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_9C
- ori r3,r3,0x009C
- stwbrx r3,0,r4
- lis r3,0x0303 # EXTEMEM2
- ori r3,r3,0x0303
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_A0
- ori r3,r3,0x00A0
- stwbrx r3,0,r4
- li r3,0x03 # MEMBNKEN
- stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_A3
- ori r3,r3,0x00A3
- stwbrx r3,0,r4
- li r3,0x00 # MEMPMODE
- stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_B8
- ori r3,r3,0x00B8
- stwbrx r3,0,r4
- li r3,0x00 # ECCCNT
- stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_B9
- ori r3,r3,0x00B9
- stwbrx r3,0,r4
- li r3,0x00 # ECCTRG
- stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_C0
- ori r3,r3,0x00C0
- stwbrx r3,0,r4
- li r3,0xFF # ERRENR1
- stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_C1
- ori r3,r3,0x00C1
- stwbrx r3,0,r4
- li r3,0x00 # ERRDR1
- stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_C3
- ori r3,r3,0x00C3
- stwbrx r3,0,r4
- li r3,0x50 # IPBESR
- stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_C4
- ori r3,r3,0x00C4
- stwbrx r3,0,r4
- li r3,0xBF # ERRENR2
- stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_C5
- ori r3,r3,0x00C5
- stwbrx r3,0,r4
- li r3,0x00 # ERRDR2
- stb r3,0x1(r5)
- lis r3,0x8000 # ADDR_C7
- ori r3,r3,0x00C7
- stwbrx r3,0,r4
- li r3,0x00 # PCIBESR
- stb r3,0x3(r5)
- lis r3,0x8000 # ADDR_C8
- ori r3,r3,0x00C8
- stwbrx r3,0,r4
- lis r3,0x0000 # BERRADDR
- ori r3,r3,0xE0FE
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_E0
- ori r3,r3,0x00E0
- stwbrx r3,0,r4
- li r3,0xC0 # AMBOR
- stb r3,0x0(r5)
- lis r3,0x8000 # ADDR_F4
- ori r3,r3,0x00F4
- stwbrx r3,0,r4
- lis r3,0x0000 # MCCR2
- ori r3,r3,0x020C
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_F8
- ori r3,r3,0x00F8
- stwbrx r3,0,r4
- lis r3,0x0230 # MCCR3
- ori r3,r3,0x0000
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_FC
- ori r3,r3,0x00FC
- stwbrx r3,0,r4
- lis r3,0x2532 # MCCR4
- ori r3,r3,0x2220
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_F0
- ori r3,r3,0x00F0
- stwbrx r3,0,r4
- lis r3,0xFFC8 # MCCR1
- ori r3,r3,0x0000
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_A8
- ori r3,r3,0x00A8
- stwbrx r3,0,r4
- lis r3,0xFF14 # PICR1
- ori r3,r3,0x1CC8
- li r8, 0x0
- stwbrx r3,r8,r5
- lis r3,0x8000 # ADDR_AC
- ori r3,r3,0x00AC
- stwbrx r3,0,r4
- lis r3,0x0000 # PICR2
- ori r3,r3,0x0000
- li r8, 0x0
- stwbrx r3,r8,r5
-
- blr
diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c
deleted file mode 100644
index d81a41a..0000000
--- a/board/ppmc7xx/pci.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * PCI initialisation for the MPC10x.
- */
-
-#include <common.h>
-#include <pci.h>
-#include <mpc106.h>
-
-#ifdef CONFIG_PCI
-
-struct pci_controller local_hose;
-
-void pci_init_board(void)
-{
- struct pci_controller* hose = (struct pci_controller *)&local_hose;
- u16 reg16;
-
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI_MEM_BUS,
- CONFIG_SYS_PCI_MEM_PHYS,
- CONFIG_SYS_PCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* ISA/PCI memory space */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_ISA_MEM_BUS,
- CONFIG_SYS_ISA_MEM_PHYS,
- CONFIG_SYS_ISA_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + 3,
- CONFIG_SYS_PCI_IO_BUS,
- CONFIG_SYS_PCI_IO_PHYS,
- CONFIG_SYS_PCI_IO_SIZE,
- PCI_REGION_IO);
-
- /* ISA/PCI I/O space */
- pci_set_region(hose->regions + 4,
- CONFIG_SYS_ISA_IO_BUS,
- CONFIG_SYS_ISA_IO_PHYS,
- CONFIG_SYS_ISA_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 5;
-
- pci_setup_indirect(hose,
- MPC106_REG_ADDR,
- MPC106_REG_DATA);
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-
- /* Initialises the MPC10x PCI Configuration regs. */
- pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
- /* Clear non-reserved bits in status register */
- pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
-}
-
-#endif /* CONFIG_PCI */
diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c
deleted file mode 100644
index 432d366..0000000
--- a/board/ppmc7xx/ppmc7xx.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * ppmc7xx.c
- * ---------
- *
- * Main board-specific routines for Wind River PPMC 7xx/74xx board.
- *
- * By Richard Danter (richard.danter@windriver.com)
- * Copyright (C) 2005 Wind River Systems
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-
-
-/* Define some MPC107 (memory controller) registers */
-#define MPC107_EUMB_GCR 0xfce41020
-#define MPC107_EUMB_IACKR 0xfce600a0
-
-
-/* Function prototypes */
-extern void _start(void);
-
-
-/*
- * initdram()
- *
- * This function normally initialises the (S)DRAM of the system. For this board
- * the SDRAM was already initialised by board_asm_init (see init.S) so we just
- * return the size of RAM.
- */
-phys_size_t initdram( int board_type )
-{
- return CONFIG_SYS_SDRAM_SIZE;
-}
-
-
-/*
- * after_reloc()
- *
- * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
- * us an opportunity to do some additional setup before the rest of the system
- * is initialised. We don't need to do anything, so we just call board_init_r()
- * which should never return.
- */
-void after_reloc( ulong dest_addr, gd_t* gd )
-{
- /* Jump to the main U-Boot board init code */
- board_init_r( gd, dest_addr );
-}
-
-
-/*
- * checkboard()
- *
- * We could do some board level checks here, such as working out what version
- * it is, but for this board we simply display it's name (on the console).
- */
-int checkboard( void )
-{
- puts( "Board: Wind River PPMC 7xx/74xx\n" );
- return 0;
-}
-
-
-/*
- * misc_init_r
- *
- * Used for other setup which needs to be done late in the bring-up phase.
- */
-int misc_init_r( void )
-{
- /* Reset the EPIC and clear pending interrupts */
- out32r(MPC107_EUMB_GCR, 0xa0000000);
- while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
- out32r( MPC107_EUMB_GCR, 0x20000000 );
- while( in32r( MPC107_EUMB_IACKR ) != 0xff );
-
- /* Enable the I-Cache */
- icache_enable();
-
- return 0;
-}
-
-
-/*
- * do_reset()
- *
- * Shell command to reset the board.
- */
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf( "Resetting...\n" );
-
- /* Disabe and invalidate cache */
- icache_disable();
- dcache_disable();
-
- /* Jump to cold reset point (in RAM) */
- _start();
-
- /* Should never get here */
- while(1)
- ;
-
- return 1;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
index 596071f..ec00c15 100644
--- a/board/raidsonic/ib62x0/kwbimage.cfg
+++ b/board/raidsonic/ib62x0/kwbimage.cfg
@@ -11,7 +11,7 @@
#
# Boot Media configurations
-BOOT_FROM nand # change from nand to uart if building UART image
+BOOT_FROM nand
NAND_ECC_MODE default
NAND_PAGE_SIZE 0x0800
@@ -21,12 +21,12 @@
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xffd100e0 0x1b1b1b9b
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+# Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xffd01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
# bit23-14: 0x0,
-# bit24: 0x1, enable exit self refresh mode on DDR access
-# bit25: 0x1, required
+# bit24: 0x1, enable exit self refresh mode on DDR access
+# bit25: 0x1, required
# bit29-26: 0x0,
# bit31-30: 0x1,
@@ -64,10 +64,10 @@
# bit3-2: 11, Cs0size (1Gb)
# bit5-4: 00, Cs1width (x8)
# bit7-6: 11, Cs1size (1Gb)
-# bit9-8: 00, Cs2width (nonexistent
-# bit11-10: 00, Cs2size (nonexistent
-# bit13-12: 00, Cs3width (nonexistent
-# bit15-14: 00, Cs3size (nonexistent
+# bit9-8: 00, Cs2width (nonexistent)
+# bit11-10: 00, Cs2size (nonexistent)
+# bit13-12: 00, Cs3width (nonexistent)
+# bit15-14: 00, Cs3size (nonexistent)
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
@@ -88,7 +88,7 @@
# bit6-4: 0x4, CL=5
# bit7: 0x0, TestMode=0 normal
# bit8: 0x0, DLL reset=0 normal
-# bit11-9: 0x6, auto-precharge write recovery ????????????
+# bit11-9: 0x6, auto-precharge write recovery
# bit12: 0x0, PD must be zero
# bit31-13: 0x0, required
@@ -148,8 +148,8 @@
DATA 0xffd01480 0x00000001 # DDR Initialization Control
# bit0: 0x1, enable DDR init upon this register write
-DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
-DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register
+DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register
# End of Header extension
DATA 0x0 0x0
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5ae491d..738b55e 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -29,9 +29,37 @@
config MACH_SUN8I
bool "sun8i (Allwinner A23)"
select CPU_V7
+ select SUPPORT_SPL
endchoice
+config DRAM_CLK
+ int "sunxi dram clock speed"
+ default 312 if MACH_SUN6I || MACH_SUN8I
+ default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+ ---help---
+ Set the dram clock speed, valid range 240 - 480, must be a multiple
+ of 24. Note on sun4i / sun5i / sun7i this is only used by boards
+ which use dram autoconfig.
+
+config DRAM_ZQ
+ int "sunxi dram zq value"
+ default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
+ default 127 if MACH_SUN7I
+ ---help---
+ Set the dram zq value. Note on sun4i / sun5i / sun7i this is only
+ used by boards which use dram autoconfig.
+
+if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+config DRAM_EMR1
+ int "sunxi dram emr1 value"
+ default 0 if MACH_SUN4I
+ default 4 if MACH_SUN5I || MACH_SUN7I
+ ---help---
+ Set the dram controller emr1 value. Note this is only used by boards
+ which use dram autoconfig.
+endif
+
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
default "sun5i" if MACH_SUN5I
@@ -42,10 +70,6 @@
choice
prompt "Board"
-config TARGET_A10_OLINUXINO_L
- bool "A10_OLINUXINO_L"
- depends on MACH_SUN4I
-
config TARGET_A10S_OLINUXINO_M
bool "A10S_OLINUXINO_M"
depends on MACH_SUN5I
@@ -78,66 +102,47 @@
bool "BANANAPI"
depends on MACH_SUN7I
-config TARGET_COLOMBUS
- bool "COLOMBUS"
- depends on MACH_SUN6I
+config TARGET_BANANAPRO
+ bool "BANANAPRO"
+ depends on MACH_SUN7I
config TARGET_CUBIEBOARD2
bool "CUBIEBOARD2"
depends on MACH_SUN7I
-config TARGET_CUBIEBOARD
- bool "CUBIEBOARD"
- depends on MACH_SUN4I
-
config TARGET_CUBIETRUCK
bool "CUBIETRUCK"
depends on MACH_SUN7I
-config TARGET_IPPO_Q8H_V5
- bool "IPPO_Q8H_V5"
- depends on MACH_SUN8I
-
config TARGET_PCDUINO3
bool "PCDUINO3"
depends on MACH_SUN7I
-config TARGET_MELE_A1000G
- bool "MELE_A1000G"
- depends on MACH_SUN4I
-
-config TARGET_MELE_A1000
- bool "MELE_A1000"
- depends on MACH_SUN4I
-
config TARGET_MELE_M3
bool "MELE_M3"
depends on MACH_SUN7I
-config TARGET_MELE_M9
- bool "MELE_M9"
- depends on MACH_SUN6I
+config TARGET_MK802_A10S
+ bool "MK802_A10S"
+ depends on MACH_SUN5I
-config TARGET_MINI_X_1GB
- bool "MINI_X_1GB"
- depends on MACH_SUN4I
-
-config TARGET_MINI_X
- bool "MINI_X"
- depends on MACH_SUN4I
-
-config TARGET_BA10_TV_BOX
- bool "BA10_TV_BOX"
- depends on MACH_SUN4I
+config TARGET_MSI_PRIMO73
+ bool "MSI Primo73 (7\" tablet)"
+ depends on MACH_SUN7I
+ ---help---
+ The MSI Primo73 is an A20 based tablet, with 1G RAM, 16G NAND,
+ 1024x600 TN LCD display, mono speaker, 0.3 MP front camera, 2.0 MP
+ rear camera, 3000 mAh battery, gt911 touchscreen, mma8452 accelerometer
+ and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons
+ (both volume buttons are also connected to the UBOOT_SEL pin). The
+ external connectors are represented by MicroSD slot, MiniHDMI, MicroUSB
+ OTG and 3.5mm headphone jack. More details are available at
+ http://linux-sunxi.org/MSI_Primo73
config TARGET_I12_TVBOX
bool "I12_TVBOX"
depends on MACH_SUN7I
-config TARGET_QT840A
- bool "QT840A"
- depends on MACH_SUN7I
-
config TARGET_R7DONGLE
bool "R7DONGLE"
depends on MACH_SUN5I
@@ -155,6 +160,18 @@
depends on SPL
default n
+config UART0_PORT_F
+ bool "UART0 on MicroSD breakout board"
+ depends on SPL_FEL
+ default n
+ ---help---
+ Repurpose the SD card slot for getting access to the UART0 serial
+ console. Primarily useful only for low level u-boot debugging on
+ tablets, where normal UART0 is difficult to access and requires
+ device disassembly and/or soldering. As the SD card can't be used
+ at the same time, the system can be only booted in the FEL mode.
+ Only enable this if you really know what you are doing.
+
config FDTFILE
string "Default fdtfile env setting for this board"
@@ -199,6 +216,13 @@
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
+config USB0_VBUS_PIN
+ string "Vbus enable pin for usb0 (otg)"
+ default ""
+ ---help---
+ Set the Vbus enable pin for usb0 (otg). This takes a string in the
+ format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+
config USB1_VBUS_PIN
string "Vbus enable pin for usb1 (ehci0)"
default "PH6" if MACH_SUN4I || MACH_SUN7I
@@ -216,17 +240,147 @@
See USB1_VBUS_PIN help text.
config VIDEO
- boolean "Enable graphical uboot console on HDMI"
+ boolean "Enable graphical uboot console on HDMI, LCD or VGA"
default y
---help---
- Say Y here to add support for using a cfb console on the HDMI output
- found on most sunxi devices.
+ Say Y here to add support for using a cfb console on the HDMI, LCD
+ or VGA output found on most sunxi devices. See doc/README.video for
+ info on how to select the video output and mode.
+
+config VIDEO_HDMI
+ boolean "HDMI output support"
+ depends on VIDEO && !MACH_SUN8I
+ default y
+ ---help---
+ Say Y here to add support for outputting video over HDMI.
+
+config VIDEO_VGA
+ boolean "VGA output support"
+ depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
+ default n
+ ---help---
+ Say Y here to add support for outputting video over VGA.
+
+config VIDEO_VGA_VIA_LCD
+ boolean "VGA via LCD controller support"
+ depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
+ default n
+ ---help---
+ Say Y here to add support for external DACs connected to the parallel
+ LCD interface driving a VGA connector, such as found on the
+ Olimex A13 boards.
+
+config VIDEO_VGA_EXTERNAL_DAC_EN
+ string "LCD panel power enable pin"
+ depends on VIDEO_VGA_VIA_LCD
+ default ""
+ ---help---
+ Set the enable pin for the external VGA DAC. This takes a string in the
+ format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+
+config VIDEO_LCD_MODE
+ string "LCD panel timing details"
+ depends on VIDEO
+ default ""
+ ---help---
+ LCD panel timing details string, leave empty if there is no LCD panel.
+ This is in drivers/video/videomodes.c: video_get_params() format, e.g.
+ x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
+
+config VIDEO_LCD_DCLK_PHASE
+ int "LCD panel display clock phase"
+ depends on VIDEO
+ default 1
+ ---help---
+ Select LCD panel display clock phase shift, range 0-3.
+
+config VIDEO_LCD_POWER
+ string "LCD panel power enable pin"
+ depends on VIDEO
+ default ""
+ ---help---
+ Set the power enable pin for the LCD panel. This takes a string in the
+ format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+
+config VIDEO_LCD_BL_EN
+ string "LCD panel backlight enable pin"
+ depends on VIDEO
+ default ""
+ ---help---
+ Set the backlight enable pin for the LCD panel. This takes a string in the
+ the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
+ port H.
+
+config VIDEO_LCD_BL_PWM
+ string "LCD panel backlight pwm pin"
+ depends on VIDEO
+ default ""
+ ---help---
+ Set the backlight pwm pin for the LCD panel. This takes a string in the
+ format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+
+config VIDEO_LCD_BL_PWM_ACTIVE_LOW
+ bool "LCD panel backlight pwm is inverted"
+ depends on VIDEO
+ default y
+ ---help---
+ Set this if the backlight pwm output is active low.
+
+
+# Note only one of these may be selected at a time! But hidden choices are
+# not supported by Kconfig
+config VIDEO_LCD_IF_PARALLEL
+ bool
+
+config VIDEO_LCD_IF_LVDS
+ bool
+
+
+choice
+ prompt "LCD panel support"
+ depends on VIDEO
+ ---help---
+ Select which type of LCD panel to support.
+
+config VIDEO_LCD_PANEL_PARALLEL
+ bool "Generic parallel interface LCD panel"
+ select VIDEO_LCD_IF_PARALLEL
+
+config VIDEO_LCD_PANEL_LVDS
+ bool "Generic lvds interface LCD panel"
+ select VIDEO_LCD_IF_LVDS
+
+config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
+ bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
+ select VIDEO_LCD_SSD2828
+ select VIDEO_LCD_IF_PARALLEL
+ ---help---
+ 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
+
+config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
+ bool "Hitachi tx18d42vm LCD panel"
+ select VIDEO_LCD_HITACHI_TX18D42VM
+ select VIDEO_LCD_IF_LVDS
+ ---help---
+ 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
+
+endchoice
+
+
+config USB_MUSB_SUNXI
+ bool "Enable sunxi OTG / DRC USB controller in host mode"
+ default n
+ ---help---
+ Say y here to enable support for the sunxi OTG / DRC USB controller
+ used on almost all sunxi boards. Note currently u-boot can only have
+ one usb host controller enabled at a time, so enabling this on boards
+ which also use the ehci host controller will result in build errors.
config USB_KEYBOARD
boolean "Enable USB keyboard support"
default y
---help---
Say Y here to add support for using a USB keyboard (typically used
- in combination with a graphical console on HDMI).
+ in combination with a graphical console).
endif
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index ca03002..743e7f5 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -5,26 +5,34 @@
F: include/configs/sun4i.h
F: configs/A10-OLinuXino-Lime_defconfig
F: configs/ba10_tv_box_defconfig
+F: configs/Chuwi_V7_CW0825_defconfig
F: configs/Cubieboard_defconfig
+F: configs/Hyundai_A7HD_defconfig
F: configs/Mele_A1000_defconfig
-F: configs/Mele_A1000G_defconfig
F: configs/Mele_M3_defconfig
-F: configs/Mele_M9_defconfig
F: configs/Mini-X_defconfig
-F: configs/Mini-X-1Gb_defconfig
+F: configs/mk802_defconfig
+F: configs/mk802ii_defconfig
F: include/configs/sun5i.h
F: configs/A10s-OLinuXino-M_defconfig
F: configs/A13-OLinuXino_defconfig
F: configs/A13-OLinuXinoM_defconfig
F: configs/Auxtek-T004_defconfig
+F: configs/mk802_a10s_defconfig
F: configs/r7-tv-dongle_defconfig
+F: include/configs/sun6i.h
+F: configs/CSQ_CS908_defconfig
+F: configs/Mele_M9_defconfig
F: include/configs/sun7i.h
F: configs/A20-OLinuXino_MICRO_defconfig
F: configs/Bananapi_defconfig
+F: configs/Bananapro_defconfig
F: configs/i12-tvbox_defconfig
F: configs/Linksprite_pcDuino3_defconfig
F: configs/Linksprite_pcDuino3_fdt_defconfig
F: configs/qt840a_defconfig
+F: include/configs/sun8i.h
+F: configs/Ippo_q8h_v1_2_defconfig
CUBIEBOARD2 BOARD
M: Ian Campbell <ijc@hellion.org.uk>
@@ -53,7 +61,42 @@
S: Maintained
F: configs/Colombus_defconfig
+GEMEI-G9 TABLET
+M: Priit Laes <plaes@plaes.org>
+S: Maintained
+F: configs/sunxi_Gemei_G9_defconfig
+
+HUMMINIGBIRD-A31 BOARD
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/Hummingbird_A31_defconfig
+
IPPO-Q8H-V5 BOARD
M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
F: configs/Ippo_q8h_v5_defconfig
+
+MSI-PRIMO73 BOARD
+M: Siarhei Siamashka <siarhei.siamashka@gmail.com>
+S: Maintained
+F: configs/MSI_Primo73_defconfig
+
+MSI-PRIMO81 BOARD
+M: Siarhei Siamashka <siarhei.siamashka@gmail.com>
+S: Maintained
+F: configs/MSI_Primo81_defconfig
+
+LINKSPRITE-PCDUINO BOARD
+M: Zoltan Herpai <wigyori@uid0.hu>
+S: Maintained
+F: configs/Linksprite_pcDuino_defconfig
+
+MARSBOARD-A10 BOARD
+M: Aleksei Mamlin <mamlinav@gmail.com>
+S: Maintained
+F: configs/Marsboard_A10_defconfig
+
+MELE M5 BOARD
+M: Ian Campbell <ijc@hellion.org.uk>
+S: Maintained
+F: configs/Mele_M5_defconfig
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index b84ff9b..71edb83 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -11,26 +11,12 @@
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
obj-$(CONFIG_SUNXI_AHCI) += ahci.o
-obj-$(CONFIG_TARGET_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o
+obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o
+obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o
obj-$(CONFIG_TARGET_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o
obj-$(CONFIG_TARGET_A13_OLINUXINO) += dram_a13_olinuxino.o
obj-$(CONFIG_TARGET_A13_OLINUXINOM) += dram_a13_oli_micro.o
-obj-$(CONFIG_TARGET_A20_OLINUXINO_L) += dram_a20_olinuxino_l.o
-obj-$(CONFIG_TARGET_A20_OLINUXINO_L2) += dram_a20_olinuxino_l2.o
-obj-$(CONFIG_TARGET_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o
# This is not a typo, uses the same mem settings as the a10s-olinuxino-m
obj-$(CONFIG_TARGET_AUXTEK_T004) += dram_a10s_olinuxino_m.o
-obj-$(CONFIG_TARGET_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o
-obj-$(CONFIG_TARGET_BANANAPI) += dram_bananapi.o
-obj-$(CONFIG_TARGET_CUBIEBOARD) += dram_cubieboard.o
-obj-$(CONFIG_TARGET_CUBIEBOARD2) += dram_cubieboard2.o
-obj-$(CONFIG_TARGET_CUBIETRUCK) += dram_cubietruck.o
-obj-$(CONFIG_TARGET_I12_TVBOX) += dram_sun7i_384_1024_iow16.o
-obj-$(CONFIG_TARGET_MELE_A1000) += dram_sun4i_360_512.o
-obj-$(CONFIG_TARGET_MELE_A1000G) += dram_sun4i_360_1024_iow8.o
-obj-$(CONFIG_TARGET_MELE_M3) += dram_sun7i_384_1024_iow16.o
-obj-$(CONFIG_TARGET_MINI_X) += dram_sun4i_360_512.o
-obj-$(CONFIG_TARGET_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o
-obj-$(CONFIG_TARGET_PCDUINO3) += dram_linksprite_pcduino3.o
-obj-$(CONFIG_TARGET_QT840A) += dram_sun7i_384_512_busw16_iow16.o
+obj-$(CONFIG_TARGET_MK802_A10S) += dram_sun5i_auto.o
obj-$(CONFIG_TARGET_R7DONGLE) += dram_r7dongle.o
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 4c1c69a..b70e00c 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -28,7 +28,9 @@
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/usbc.h>
#include <asm/io.h>
+#include <linux/usb/musb.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -175,26 +177,21 @@
#endif
#ifdef CONFIG_AXP221_POWER
power_failed = axp221_init();
- power_failed |= axp221_set_dcdc1(3000);
- power_failed |= axp221_set_dcdc2(1200);
- power_failed |= axp221_set_dcdc3(1200);
- power_failed |= axp221_set_dcdc4(1200);
- power_failed |= axp221_set_dcdc5(1500);
-#if CONFIG_AXP221_DLDO1_VOLT != -1
+ power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT);
+ power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */
+ power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */
+#ifdef CONFIG_MACH_SUN6I
+ power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */
+#else
+ power_failed |= axp221_set_dcdc4(0); /* A23:unused */
+#endif
+ power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */
power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
-#endif
-#if CONFIG_AXP221_DLDO4_VOLT != -1
power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
-#endif
-#if CONFIG_AXP221_ALDO1_VOLT != -1
power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
-#endif
-#if CONFIG_AXP221_ALDO2_VOLT != -1
power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
-#endif
-#if CONFIG_AXP221_ALDO3_VOLT != -1
power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
-#endif
+ power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT);
#endif
printf("DRAM:");
@@ -214,27 +211,48 @@
}
#endif
+#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 6,
+ .ram_bits = 11,
+};
+
+static struct musb_hdrc_platform_data musb_plat = {
+#if defined(CONFIG_MUSB_HOST)
+ .mode = MUSB_HOST,
+#else
+ .mode = MUSB_PERIPHERAL,
+#endif
+ .config = &musb_config,
+ .power = 250,
+ .platform_ops = &sunxi_musb_ops,
+};
+#endif
+
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
- if (!getenv("ethaddr")) {
- uint32_t reg_val = readl(SUNXI_SID_BASE);
+ unsigned int sid[4];
- if (reg_val) {
- uint8_t mac_addr[6];
+ if (!getenv("ethaddr") && sunxi_get_sid(sid) == 0 &&
+ sid[0] != 0 && sid[3] != 0) {
+ uint8_t mac_addr[6];
- mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
- mac_addr[1] = (reg_val >> 0) & 0xff;
- reg_val = readl(SUNXI_SID_BASE + 0x0c);
- mac_addr[2] = (reg_val >> 24) & 0xff;
- mac_addr[3] = (reg_val >> 16) & 0xff;
- mac_addr[4] = (reg_val >> 8) & 0xff;
- mac_addr[5] = (reg_val >> 0) & 0xff;
+ mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
+ mac_addr[1] = (sid[0] >> 0) & 0xff;
+ mac_addr[2] = (sid[3] >> 24) & 0xff;
+ mac_addr[3] = (sid[3] >> 16) & 0xff;
+ mac_addr[4] = (sid[3] >> 8) & 0xff;
+ mac_addr[5] = (sid[3] >> 0) & 0xff;
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
+ eth_setenv_enetaddr("ethaddr", mac_addr);
}
+#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
+ musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
+#endif
return 0;
}
#endif
diff --git a/board/sunxi/dram_a10_olinuxino_l.c b/board/sunxi/dram_a10_olinuxino_l.c
deleted file mode 100644
index 24a1bd9..0000000
--- a/board/sunxi/dram_a10_olinuxino_l.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 480,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 16,
- .bus_width = 16,
- .cas = 6,
- .zq = 123,
- .odt_en = 0,
- .size = 512,
- .tpr0 = 0x30926692,
- .tpr1 = 0x1090,
- .tpr2 = 0x1a0c8,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0x4,
- .emr2 = 0,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_a20_olinuxino_l.c b/board/sunxi/dram_a20_olinuxino_l.c
deleted file mode 100644
index 2c74999..0000000
--- a/board/sunxi/dram_a20_olinuxino_l.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include "common.h"
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 480,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 16,
- .bus_width = 16,
- .cas = 9,
- .zq = 0x7f,
- .odt_en = 0,
- .size = 512,
- .tpr0 = 0x42d899b7,
- .tpr1 = 0xa090,
- .tpr2 = 0x22a00,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0x4,
- .emr2 = 0x10,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_a20_olinuxino_l2.c b/board/sunxi/dram_a20_olinuxino_l2.c
deleted file mode 100644
index 2115d37..0000000
--- a/board/sunxi/dram_a20_olinuxino_l2.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 480,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 16,
- .bus_width = 32,
- .cas = 9,
- .zq = 0x7f,
- .odt_en = 0,
- .size = 1024,
- .tpr0 = 0x42d899b7,
- .tpr1 = 0xa090,
- .tpr2 = 0x22a00,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0x4,
- .emr2 = 0x10,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_cubieboard.c b/board/sunxi/dram_cubieboard.c
deleted file mode 100644
index 399028c..0000000
--- a/board/sunxi/dram_cubieboard.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 480,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 16,
- .bus_width = 32,
- .cas = 6,
- .zq = 123,
- .odt_en = 0,
- .size = 1024,
- .tpr0 = 0x30926692,
- .tpr1 = 0x1090,
- .tpr2 = 0x1a0c8,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0,
- .emr2 = 0,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_cubieboard2.c b/board/sunxi/dram_cubieboard2.c
deleted file mode 100644
index 9e75367..0000000
--- a/board/sunxi/dram_cubieboard2.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 480,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 16,
- .bus_width = 32,
- .cas = 9,
- .zq = 0x7f,
- .odt_en = 0,
- .size = 1024,
- .tpr0 = 0x42d899b7,
- .tpr1 = 0xa090,
- .tpr2 = 0x22a00,
- .tpr3 = 0x0,
- .tpr4 = 0x1,
- .tpr5 = 0x0,
- .emr1 = 0x4,
- .emr2 = 0x10,
- .emr3 = 0x0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_cubietruck.c b/board/sunxi/dram_cubietruck.c
deleted file mode 100644
index fbcd687..0000000
--- a/board/sunxi/dram_cubietruck.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 432,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 8,
- .bus_width = 32,
- .cas = 9,
- .zq = 0x7f,
- .odt_en = 0,
- .size = 2048,
- .tpr0 = 0x42d899b7,
- .tpr1 = 0xa090,
- .tpr2 = 0x22a00,
- .tpr3 = 0x0,
- .tpr4 = 0x1,
- .tpr5 = 0x0,
- .emr1 = 0x4,
- .emr2 = 0x10,
- .emr3 = 0x0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_linksprite_pcduino3.c b/board/sunxi/dram_linksprite_pcduino3.c
deleted file mode 100644
index 9cc6e19..0000000
--- a/board/sunxi/dram_linksprite_pcduino3.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 480,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 16,
- .bus_width = 32,
- .cas = 9,
- .zq = 0x7a,
- .odt_en = 0,
- .size = 1024,
- .tpr0 = 0x42d899b7,
- .tpr1 = 0xa090,
- .tpr2 = 0x22a00,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0x4,
- .emr2 = 0x10,
- .emr3 = 0x0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_sun4i_360_1024_iow16.c b/board/sunxi/dram_sun4i_360_1024_iow16.c
deleted file mode 100644
index 3763713..0000000
--- a/board/sunxi/dram_sun4i_360_1024_iow16.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 360,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 16,
- .bus_width = 32,
- .cas = 6,
- .zq = 123,
- .odt_en = 0,
- .size = 1024,
- .tpr0 = 0x30926692,
- .tpr1 = 0x1090,
- .tpr2 = 0x1a0c8,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0,
- .emr2 = 0,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_sun4i_360_1024_iow8.c b/board/sunxi/dram_sun4i_360_1024_iow8.c
deleted file mode 100644
index 2a5c9ed..0000000
--- a/board/sunxi/dram_sun4i_360_1024_iow8.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 360,
- .type = 3,
- .rank_num = 1,
- .density = 2048,
- .io_width = 8,
- .bus_width = 32,
- .cas = 6,
- .zq = 123,
- .odt_en = 0,
- .size = 1024,
- .tpr0 = 0x30926692,
- .tpr1 = 0x1090,
- .tpr2 = 0x1a0c8,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0,
- .emr2 = 0,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_sun4i_360_512.c b/board/sunxi/dram_sun4i_360_512.c
deleted file mode 100644
index 48aa6e2..0000000
--- a/board/sunxi/dram_sun4i_360_512.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 360,
- .type = 3,
- .rank_num = 1,
- .density = 2048,
- .io_width = 16,
- .bus_width = 32,
- .cas = 6,
- .zq = 123,
- .odt_en = 0,
- .size = 512,
- .tpr0 = 0x30926692,
- .tpr1 = 0x1090,
- .tpr2 = 0x1a0c8,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0,
- .emr2 = 0,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_sun4i_384_1024_iow8.c b/board/sunxi/dram_sun4i_384_1024_iow8.c
deleted file mode 100644
index b0fcc55..0000000
--- a/board/sunxi/dram_sun4i_384_1024_iow8.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include <common.h>
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 384,
- .type = 3,
- .rank_num = 1,
- .density = 2048,
- .io_width = 8,
- .bus_width = 32,
- .cas = 6,
- .zq = 123,
- .odt_en = 0,
- .size = 1024,
- .tpr0 = 0x30926692,
- .tpr1 = 0x1090,
- .tpr2 = 0x1a0c8,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0x4,
- .emr2 = 0,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c
new file mode 100644
index 0000000..826bacf
--- /dev/null
+++ b/board/sunxi/dram_sun4i_auto.c
@@ -0,0 +1,29 @@
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = CONFIG_DRAM_CLK,
+ .type = 3,
+ .rank_num = 1,
+ .density = 0,
+ .io_width = 0,
+ .bus_width = 0,
+ .cas = 6,
+ .zq = CONFIG_DRAM_ZQ,
+ .odt_en = 0,
+ .size = 0,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = CONFIG_DRAM_EMR1,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c
new file mode 100644
index 0000000..e86b08e
--- /dev/null
+++ b/board/sunxi/dram_sun5i_auto.c
@@ -0,0 +1,31 @@
+/* DRAM parameters for auto dram configuration on sun5i and sun7i */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = CONFIG_DRAM_CLK,
+ .type = 3,
+ .rank_num = 1,
+ .density = 0,
+ .io_width = 0,
+ .bus_width = 0,
+ .cas = 9,
+ .zq = CONFIG_DRAM_ZQ,
+ .odt_en = 0,
+ .size = 0,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = CONFIG_DRAM_EMR1,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_sun7i_384_1024_iow16.c b/board/sunxi/dram_sun7i_384_1024_iow16.c
deleted file mode 100644
index 04e4b1e..0000000
--- a/board/sunxi/dram_sun7i_384_1024_iow16.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include "common.h"
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 384,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 16,
- .bus_width = 32,
- .cas = 9,
- .zq = 0x7f,
- .odt_en = 0,
- .size = 1024,
- .tpr0 = 0x42d899b7,
- .tpr1 = 0xa090,
- .tpr2 = 0x22a00,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0x4,
- .emr2 = 0x10,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/dram_sun7i_384_512_busw16_iow16.c b/board/sunxi/dram_sun7i_384_512_busw16_iow16.c
deleted file mode 100644
index 2e36011..0000000
--- a/board/sunxi/dram_sun7i_384_512_busw16_iow16.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* this file is generated, don't edit it yourself */
-
-#include "common.h"
-#include <asm/arch/dram.h>
-
-static struct dram_para dram_para = {
- .clock = 384,
- .type = 3,
- .rank_num = 1,
- .density = 4096,
- .io_width = 16,
- .bus_width = 16,
- .cas = 9,
- .zq = 0x7f,
- .odt_en = 0,
- .size = 512,
- .tpr0 = 0x42d899b7,
- .tpr1 = 0xa090,
- .tpr2 = 0x22a00,
- .tpr3 = 0,
- .tpr4 = 0,
- .tpr5 = 0,
- .emr1 = 0x4,
- .emr2 = 0x10,
- .emr3 = 0,
-};
-
-unsigned long sunxi_dram_init(void)
-{
- return dramc_init(&dram_para);
-}
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 571bc9e..4e4615e 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -34,7 +34,7 @@
* need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
* of the GMAC clk register to 3.
*/
-#ifdef CONFIG_TARGET_BANANAPI
+#if defined CONFIG_TARGET_BANANAPI || defined CONFIG_TARGET_BANANAPRO
setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
#endif
diff --git a/board/synopsys/Kconfig b/board/synopsys/Kconfig
index a54d3df..f614f88 100644
--- a/board/synopsys/Kconfig
+++ b/board/synopsys/Kconfig
@@ -1,8 +1,5 @@
if TARGET_ARCANGEL4
-config SYS_CPU
- default "arc700"
-
config SYS_VENDOR
default "synopsys"
@@ -13,9 +10,6 @@
if TARGET_ARCANGEL4_BE
-config SYS_CPU
- default "arc700"
-
config SYS_VENDOR
default "synopsys"
diff --git a/board/synopsys/axs101/Kconfig b/board/synopsys/axs101/Kconfig
index 8448265..79e5400 100644
--- a/board/synopsys/axs101/Kconfig
+++ b/board/synopsys/axs101/Kconfig
@@ -1,8 +1,5 @@
if TARGET_AXS101
-config SYS_CPU
- default "arc700"
-
config SYS_BOARD
default "axs101"
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index a1c3c17..6703670 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -21,6 +21,7 @@
#include "board.h"
#include <power/pmic.h>
#include <power/tps65218.h>
+#include <power/tps62362.h>
#include <miiphy.h>
#include <cpsw.h>
@@ -81,12 +82,12 @@
const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
{ /* 19.2 MHz */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
+ {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
- {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
+ {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
+ {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
+ {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
+ {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 24 MHz */
{300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
@@ -115,24 +116,32 @@
};
const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
- {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
{1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
{1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
{1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
};
const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
- {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
- {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
- {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
+ {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
+ {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
+ {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
};
-const struct dpll_params epos_evm_dpll_ddr = {
- 266, 24, 1, -1, 1, -1, -1};
+const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
+ {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
+ {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
+ {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
+ {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
+};
const struct dpll_params gp_evm_dpll_ddr = {
- 400, 23, 1, -1, 1, -1, -1};
+ 50, 2, 1, -1, 2, -1, -1};
+
+static const struct dpll_params idk_dpll_ddr = {
+ 400, 23, 1, -1, 2, -1, -1
+};
const struct ctrl_ioregs ioregs_lpddr2 = {
.cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
@@ -157,7 +166,7 @@
.emif_rd_wr_lvl_rmp_win = 0x0,
.emif_rd_wr_lvl_rmp_ctl = 0x0,
.emif_rd_wr_lvl_ctl = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E084006,
+ .emif_ddr_phy_ctlr_1 = 0x0E284006,
.emif_rd_wr_exec_thresh = 0x80000405,
.emif_ddr_ext_phy_ctrl_1 = 0x04010040,
.emif_ddr_ext_phy_ctrl_2 = 0x00500050,
@@ -170,29 +179,6 @@
.emif_cos_config = 0x000FFFFF
};
-const u32 ext_phy_ctrl_const_base_lpddr2[] = {
- 0x00500050,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40001000,
- 0x08102040
-};
-
const struct ctrl_ioregs ioregs_ddr3 = {
.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
@@ -201,7 +187,7 @@
.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
- .emif_sdram_config_ext = 0x0143,
+ .emif_sdram_config_ext = 0xc163,
};
const struct emif_regs ddr3_emif_regs_400Mhz = {
@@ -301,150 +287,32 @@
.emif_cos_config = 0x000FFFFF
};
-const u32 ext_phy_ctrl_const_base_ddr3[] = {
- 0x00400040,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00340034,
- 0x00340034,
- 0x00340034,
- 0x00340034,
- 0x00340034,
- 0x0,
- 0x0,
- 0x40000000,
- 0x08102040
+static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
+ .sdram_config = 0x61a11b32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00000c30,
+ .sdram_tim1 = 0xeaaad4db,
+ .sdram_tim2 = 0x266b7fda,
+ .sdram_tim3 = 0x107f8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074be4,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1 = 0x00008009,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
+ .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000405,
+ .emif_prio_class_serv_map = 0x00000000,
+ .emif_connect_id_serv_1_map = 0x00000000,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x00ffffff
};
-const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
- 0x00000000,
- 0x00000045,
- 0x00000046,
- 0x00000048,
- 0x00000047,
- 0x00000000,
- 0x0000004C,
- 0x00000070,
- 0x00000085,
- 0x000000A3,
- 0x00000000,
- 0x0000000C,
- 0x00000030,
- 0x00000045,
- 0x00000063,
- 0x00000000,
- 0x0,
- 0x0,
- 0x40000000,
- 0x08102040
-};
-
-const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
- 0x00000000,
- 0x00000044,
- 0x00000044,
- 0x00000046,
- 0x00000046,
- 0x00000000,
- 0x00000059,
- 0x00000077,
- 0x00000093,
- 0x000000A8,
- 0x00000000,
- 0x00000019,
- 0x00000037,
- 0x00000053,
- 0x00000068,
- 0x00000000,
- 0x0,
- 0x0,
- 0x40000000,
- 0x08102040
-};
-
-static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
- /* first 5 are taken care by emif_regs */
- 0x00700070,
-
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
-
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-
- 0x00150015,
- 0x00150015,
- 0x00150015,
- 0x00150015,
- 0x00150015,
-
- 0x00800080,
- 0x00800080,
-
- 0x40000000,
-
- 0x08102040,
-
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
-{
- if (board_is_eposevm()) {
- *regs = ext_phy_ctrl_const_base_lpddr2;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
- } else if (board_is_evm_14_or_later()) {
- *regs = ext_phy_ctrl_const_base_ddr3_production;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
- } else if (board_is_evm_12_or_later()) {
- *regs = ext_phy_ctrl_const_base_ddr3_beta;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
- } else if (board_is_gpevm()) {
- *regs = ext_phy_ctrl_const_base_ddr3;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
- } else if (board_is_sk()) {
- *regs = ext_phy_ctrl_const_base_ddr3_sk;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
- }
-
- return;
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- if (board_is_eposevm())
- return &epos_evm_dpll_ddr;
- else if (board_is_gpevm() || board_is_sk())
- return &gp_evm_dpll_ddr;
-
- printf(" Board '%s' not supported\n", am43xx_board_name);
- return NULL;
-}
-
/*
* get_sys_clk_index : returns the index of the sys_clk read from
* ctrl status register. This value is either
@@ -464,6 +332,22 @@
CTRL_SYSBOOT_15_14_SHIFT);
}
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ int ind = get_sys_clk_index();
+
+ if (board_is_eposevm())
+ return &epos_evm_dpll_ddr[ind];
+ else if (board_is_gpevm() || board_is_sk())
+ return &gp_evm_dpll_ddr;
+ else if (board_is_idk())
+ return &idk_dpll_ddr;
+
+ printf(" Board '%s' not supported\n", am43xx_board_name);
+ return NULL;
+}
+
+
/*
* get_opp_offset:
* Returns the index for safest OPP of the device to boot.
@@ -513,10 +397,86 @@
return &dpll_per[ind];
}
+void scale_vcores_generic(u32 m)
+{
+ int mpu_vdd;
+
+ if (i2c_probe(TPS65218_CHIP_PM))
+ return;
+
+ switch (m) {
+ case 1000:
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+ break;
+ case 800:
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
+ break;
+ case 720:
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
+ break;
+ case 600:
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+ break;
+ case 300:
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
+ break;
+ default:
+ puts("Unknown MPU clock, not scaling\n");
+ return;
+ }
+
+ /* Set DCDC1 (CORE) voltage to 1.1V */
+ if (tps65218_voltage_update(TPS65218_DCDC1,
+ TPS65218_DCDC_VOLT_SEL_1100MV)) {
+ printf("%s failure\n", __func__);
+ return;
+ }
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+ printf("%s failure\n", __func__);
+ return;
+ }
+}
+
+void scale_vcores_idk(u32 m)
+{
+ int mpu_vdd;
+
+ if (i2c_probe(TPS62362_I2C_ADDR))
+ return;
+
+ switch (m) {
+ case 1000:
+ mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
+ break;
+ case 800:
+ mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
+ break;
+ case 720:
+ mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
+ break;
+ case 600:
+ mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
+ break;
+ case 300:
+ mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
+ break;
+ default:
+ puts("Unknown MPU clock, not scaling\n");
+ return;
+ }
+
+ /* Set VDD_MPU voltage */
+ if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
+ printf("%s failure\n", __func__);
+ return;
+ }
+}
+
void scale_vcores(void)
{
const struct dpll_params *mpu_params;
- int mpu_vdd;
struct am43xx_board_id header;
enable_i2c0_pin_mux();
@@ -527,30 +487,10 @@
/* Get the frequency */
mpu_params = get_dpll_mpu_params();
- if (i2c_probe(TPS65218_CHIP_PM))
- return;
-
- if (mpu_params->m == 1000) {
- mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
- } else if (mpu_params->m == 600) {
- mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
- } else {
- puts("Unknown MPU clock, not scaling\n");
- return;
- }
-
- /* Set DCDC1 (CORE) voltage to 1.1V */
- if (tps65218_voltage_update(TPS65218_DCDC1,
- TPS65218_DCDC_VOLT_SEL_1100MV)) {
- puts("tps65218_voltage_update failure\n");
- return;
- }
-
- /* Set DCDC2 (MPU) voltage */
- if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
- puts("tps65218_voltage_update failure\n");
- return;
- }
+ if (board_is_idk())
+ scale_vcores_idk(mpu_params->m);
+ else
+ scale_vcores_generic(mpu_params->m);
}
void set_uart_mux_conf(void)
@@ -602,6 +542,9 @@
} else if (board_is_sk()) {
config_ddr(400, &ioregs_ddr3, NULL, NULL,
&ddr3_sk_emif_regs_400Mhz, 0);
+ } else if (board_is_idk()) {
+ config_ddr(400, &ioregs_ddr3, NULL, NULL,
+ &ddr3_idk_emif_regs_400Mhz, 0);
}
}
#endif
@@ -611,10 +554,17 @@
{
struct pmic *p;
- power_tps65218_init(I2C_PMIC);
- p = pmic_get("TPS65218_PMIC");
- if (p && !pmic_probe(p))
- puts("PMIC: TPS65218\n");
+ if (board_is_idk()) {
+ power_tps62362_init(I2C_PMIC);
+ p = pmic_get("TPS62362");
+ if (p && !pmic_probe(p))
+ puts("PMIC: TPS62362\n");
+ } else {
+ power_tps65218_init(I2C_PMIC);
+ p = pmic_get("TPS65218_PMIC");
+ if (p && !pmic_probe(p))
+ puts("PMIC: TPS65218\n");
+ }
return 0;
}
@@ -771,6 +721,10 @@
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
cpsw_slaves[0].phy_addr = 4;
cpsw_slaves[1].phy_addr = 5;
+ } else if (board_is_idk()) {
+ writel(RGMII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+ cpsw_slaves[0].phy_addr = 0;
} else {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 8e12191..eb9493e 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -53,6 +53,11 @@
return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN);
}
+static inline int board_is_idk(void)
+{
+ return !strncmp(am43xx_board_name, "AM43_IDK", HDR_NAME_LEN);
+}
+
static inline int board_is_evm_14_or_later(void)
{
return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0);
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index a670b0b..510477d 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -131,7 +131,7 @@
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
#endif
- } else if (board_is_sk()) {
+ } else if (board_is_sk() || board_is_idk()) {
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
printf("Error: NAND flash not present on this board\n");
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index b978044..4d07313 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -17,6 +17,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
@@ -43,6 +45,17 @@
0
};
+static const struct ns16550_platdata devkit8000_serial = {
+ OMAP34XX_UART3,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(devkit8000_uart) = {
+ "serial_omap",
+ &devkit8000_serial
+};
+
/*
* Routine: board_init
* Description: Early hardware init.
diff --git a/board/total5200/Kconfig b/board/total5200/Kconfig
deleted file mode 100644
index ffa9516..0000000
--- a/board/total5200/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_TOTAL5200
-
-config SYS_BOARD
- default "total5200"
-
-config SYS_CONFIG_NAME
- default "Total5200"
-
-endif
diff --git a/board/total5200/MAINTAINERS b/board/total5200/MAINTAINERS
deleted file mode 100644
index afb0058..0000000
--- a/board/total5200/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-TOTAL5200 BOARD
-#M: -
-S: Maintained
-F: board/total5200/
-F: include/configs/Total5200.h
-F: configs/Total5200_defconfig
-F: configs/Total5200_lowboot_defconfig
-F: configs/Total5200_Rev2_defconfig
-F: configs/Total5200_Rev2_lowboot_defconfig
diff --git a/board/total5200/Makefile b/board/total5200/Makefile
deleted file mode 100644
index 527557c..0000000
--- a/board/total5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := total5200.o sdram.o
diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h
deleted file mode 100644
index 068a9a6..0000000
--- a/board/total5200/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h
deleted file mode 100644
index 0377417..0000000
--- a/board/total5200/mt48lc32m16a2-75.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Micron MT48LC32M16A2-75 is compatible to:
- * - Infineon HYB39S512160AT-75
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x514F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c
deleted file mode 100644
index dbe3587..0000000
--- a/board/total5200/sdram.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-
-#include "sdram.h"
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- if (sdram_conf->ddr) {
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000;
- __asm__ volatile ("sync");
- }
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit;
- __asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
- __asm__ volatile ("sync");
-
- if (sdram_conf->ddr) {
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay;
- __asm__ volatile ("sync");
- }
-
- /* find RAM size using SDRAM CS0 only */
- mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- mpc5xxx_sdram_start(sdram_conf, 0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
- /* find RAM size using SDRAM CS1 only */
- mpc5xxx_sdram_start(sdram_conf, 0);
- test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- mpc5xxx_sdram_start(sdram_conf, 1);
- test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- if (test1 > test2) {
- mpc5xxx_sdram_start(sdram_conf, 0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
- | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- return dramsize + dramsize2;
-}
diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h
deleted file mode 100644
index 3758f5c9..0000000
--- a/board/total5200/sdram.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-typedef struct {
- ulong ddr;
- ulong mode;
- ulong emode;
- ulong control;
- ulong config1;
- ulong config2;
- ulong tapdelay;
-} sdram_conf_t;
-
-long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c
deleted file mode 100644
index 345a186..0000000
--- a/board/total5200/total5200.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-
-#include "sdram.h"
-
-#if CONFIG_TOTAL5200_REV==2
-#include "mt48lc32m16a2-75.h"
-#else
-#include "mt48lc16m16a2-75.h"
-#endif
-
-phys_size_t initdram (int board_type)
-{
- sdram_conf_t sdram_conf;
-
- sdram_conf.ddr = SDRAM_DDR;
- sdram_conf.mode = SDRAM_MODE;
- sdram_conf.emode = 0;
- sdram_conf.control = SDRAM_CONTROL;
- sdram_conf.config1 = SDRAM_CONFIG1;
- sdram_conf.config2 = SDRAM_CONFIG2;
- sdram_conf.tapdelay = 0;
- return mpc5xxx_sdram_init (&sdram_conf);
-}
-
-int checkboard (void)
-{
-#if CONFIG_TOTAL5200_REV==2
- puts ("Board: Total5200 Rev.2 ");
-#else
- puts ("Board: Total5200 ");
-#endif
-
- /*
- * Retrieve FPGA Revision.
- */
- printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400));
-
- /*
- * Take all peripherals in power-up mode.
- */
-#if CONFIG_TOTAL5200_REV==2
- *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70;
-#else
- *(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70;
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-/* IRDA_1 aka PSC6_3 (pin C13) */
-#define GPIO_IRDA_1 0x20000000UL
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
- /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
- *(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1;
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
- if (idereset) {
- *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1;
- } else {
- *(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1;
- }
-}
-#endif
-
-#ifdef CONFIG_VIDEO_SED13806
-#include <sed13806.h>
-
-#define DISPLAY_WIDTH 640
-#define DISPLAY_HEIGHT 480
-
-#ifdef CONFIG_VIDEO_SED13806_8BPP
-#error CONFIG_VIDEO_SED13806_8BPP not supported.
-#endif /* CONFIG_VIDEO_SED13806_8BPP */
-
-#ifdef CONFIG_VIDEO_SED13806_16BPP
-static const S1D_REGS init_regs [] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x00}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0x00}, /* General IO Pins Control Register 0 */
- {0x0009,0x00}, /* General IO Pins Control Register 1 */
- {0x0010,0x02}, /* Memory Clock Configuration Register */
- {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x03}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x25}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x01}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x05}, /* LCD Display Mode Register */
- {0x0041,0x00}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x10}, /* TV Output Control Register */
- {0x0060,0x05}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01E4,0x00}, /* Look-Up Table Data Register */
- {0x01F0,0x00}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
- {0, 0}
-};
-#endif /* CONFIG_VIDEO_SED13806_16BPP */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/* Return text to be printed besides the logo. */
-void video_get_info_str (int line_number, char *info)
-{
- if (line_number == 1) {
-#if CONFIG_TOTAL5200_REV==1
- strcpy (info, " Total5200");
-#elif CONFIG_TOTAL5200_REV==2
- strcpy (info, " Total5200 Rev.2");
-#else
-#error CONFIG_TOTAL5200_REV must be 1 or 2.
-#endif
- } else {
- info [0] = '\0';
- }
-}
-#endif
-
-/* Returns SED13806 base address. First thing called in the driver. */
-unsigned int board_video_init (void)
-{
- return CONFIG_SYS_LCD_BASE;
-}
-
-/* Called after initializing the SED13806 and before clearing the screen. */
-void board_validate_screen (unsigned int base)
-{
-}
-
-/* Return a pointer to the initialization sequence. */
-const S1D_REGS *board_get_regs (void)
-{
- return init_regs;
-}
-
-int board_get_width (void)
-{
- return DISPLAY_WIDTH;
-}
-
-int board_get_height (void)
-{
- return DISPLAY_HEIGHT;
-}
-
-#endif /* CONFIG_VIDEO_SED13806 */
-
-int board_eth_init(bd_t *bis)
-{
- cpu_eth_init(bis); /* Built in FEC comes first */
- return pci_eth_init(bis);
-}
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
index 2744514..3da61a4 100644
--- a/board/woodburn/woodburn.c
+++ b/board/woodburn/woodburn.c
@@ -137,9 +137,6 @@
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
- /* Set global data pointer. */
- gd = &gdata;
-
preloader_console_init();
timer_init();
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 47f85c7..738c31c 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -24,6 +24,7 @@
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif
@@ -49,6 +50,9 @@
case XILINX_ZYNQ_7030:
fpga = fpga030;
break;
+ case XILINX_ZYNQ_7035:
+ fpga = fpga035;
+ break;
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;
diff --git a/common/Makefile b/common/Makefile
index c668a2f..94554f2 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -196,7 +196,7 @@
obj-$(CONFIG_I2C_EDID) += edid.o
obj-$(CONFIG_KALLSYMS) += kallsyms.o
obj-y += splash.o
-obj-$(CONFIG_LCD) += lcd.o
+obj-$(CONFIG_LCD) += lcd.o lcd_console.o
obj-$(CONFIG_LYNXKDI) += lynxkdi.o
obj-$(CONFIG_MENU) += menu.o
obj-$(CONFIG_MODEM_SUPPORT) += modem.o
diff --git a/common/board_f.c b/common/board_f.c
index cfd77f8..3a4b32c 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -985,6 +985,11 @@
INIT_FUNC_WATCHDOG_RESET
reloc_fdt,
setup_reloc,
+#ifdef CONFIG_X86
+ copy_uboot_to_ram,
+ clear_bss,
+ do_elf_reloc_fixups,
+#endif
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
jump_to_copy,
#endif
@@ -1044,9 +1049,6 @@
*/
static init_fnc_t init_sequence_f_r[] = {
init_cache_f_r,
- copy_uboot_to_ram,
- clear_bss,
- do_elf_reloc_fixups,
NULL,
};
diff --git a/common/bootm.c b/common/bootm.c
index 6b3ea8c..e2dc164 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -264,103 +264,122 @@
return 0;
}
-#endif /* USE_HOSTCC */
+#endif /* USE_HOSTC */
/**
- * decomp_image() - decompress the operating system
+ * print_decomp_msg() - Print a suitable decompression/loading message
*
- * @comp: Compression algorithm that is used (IH_COMP_...)
- * @load: Destination load address in U-Boot memory
- * @image_start Image start address (where we are decompressing from)
* @type: OS type (IH_OS_...)
- * @load_bug: Place to decompress to
- * @image_buf: Address to decompress from
- * @return 0 if OK, -ve on error (BOOTM_ERR_...)
+ * @comp_type: Compression type being used (IH_COMP_...)
+ * @is_xip: true if the load address matches the image start
*/
-static int decomp_image(int comp, ulong load, ulong image_start, int type,
- void *load_buf, void *image_buf, ulong image_len,
- ulong *load_end)
+static void print_decomp_msg(int comp_type, int type, bool is_xip)
{
- const char *type_name = genimg_get_type_name(type);
- __attribute__((unused)) uint unc_len = CONFIG_SYS_BOOTM_LEN;
+ const char *name = genimg_get_type_name(type);
+
+ if (comp_type == IH_COMP_NONE)
+ printf(" %s %s ... ", is_xip ? "XIP" : "Loading", name);
+ else
+ printf(" Uncompressing %s ... ", name);
+}
+
+/**
+ * handle_decomp_error() - display a decompression error
+ *
+ * This function tries to produce a useful message. In the case where the
+ * uncompressed size is the same as the available space, we can assume that
+ * the image is too large for the buffer.
+ *
+ * @comp_type: Compression type being used (IH_COMP_...)
+ * @uncomp_size: Number of bytes uncompressed
+ * @unc_len: Amount of space available for decompression
+ * @ret: Error code to report
+ * @return BOOTM_ERR_RESET, indicating that the board must be reset
+ */
+static int handle_decomp_error(int comp_type, size_t uncomp_size,
+ size_t unc_len, int ret)
+{
+ const char *name = genimg_get_comp_name(comp_type);
+
+ if (uncomp_size >= unc_len)
+ printf("Image too large: increase CONFIG_SYS_BOOTM_LEN\n");
+ else
+ printf("%s: uncompress error %d\n", name, ret);
+
+ /*
+ * The decompression routines are now safe, so will not write beyond
+ * their bounds. Probably it is not necessary to reset, but maintain
+ * the current behaviour for now.
+ */
+ printf("Must RESET board to recover\n");
+#ifndef USE_HOSTCC
+ bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
+#endif
+
+ return BOOTM_ERR_RESET;
+}
+
+int bootm_decomp_image(int comp, ulong load, ulong image_start, int type,
+ void *load_buf, void *image_buf, ulong image_len,
+ uint unc_len, ulong *load_end)
+{
+ int ret = 0;
*load_end = load;
+ print_decomp_msg(comp, type, load == image_start);
+
+ /*
+ * Load the image to the right place, decompressing if needed. After
+ * this, image_len will be set to the number of uncompressed bytes
+ * loaded, ret will be non-zero on error.
+ */
switch (comp) {
case IH_COMP_NONE:
- if (load == image_start) {
- printf(" XIP %s ... ", type_name);
- } else {
- printf(" Loading %s ... ", type_name);
+ if (load == image_start)
+ break;
+ if (image_len <= unc_len)
memmove_wd(load_buf, image_buf, image_len, CHUNKSZ);
- }
- *load_end = load + image_len;
+ else
+ ret = 1;
break;
#ifdef CONFIG_GZIP
- case IH_COMP_GZIP:
- printf(" Uncompressing %s ... ", type_name);
- if (gunzip(load_buf, unc_len, image_buf, &image_len) != 0) {
- puts("GUNZIP: uncompress, out-of-mem or overwrite error - must RESET board to recover\n");
- return BOOTM_ERR_RESET;
- }
-
- *load_end = load + image_len;
+ case IH_COMP_GZIP: {
+ ret = gunzip(load_buf, unc_len, image_buf, &image_len);
break;
+ }
#endif /* CONFIG_GZIP */
#ifdef CONFIG_BZIP2
- case IH_COMP_BZIP2:
- printf(" Uncompressing %s ... ", type_name);
+ case IH_COMP_BZIP2: {
+ uint size = unc_len;
+
/*
* If we've got less than 4 MB of malloc() space,
* use slower decompression algorithm which requires
* at most 2300 KB of memory.
*/
- int i = BZ2_bzBuffToBuffDecompress(load_buf, &unc_len,
+ ret = BZ2_bzBuffToBuffDecompress(load_buf, &size,
image_buf, image_len,
CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
- if (i != BZ_OK) {
- printf("BUNZIP2: uncompress or overwrite error %d - must RESET board to recover\n",
- i);
- return BOOTM_ERR_RESET;
- }
-
- *load_end = load + unc_len;
+ image_len = size;
break;
+ }
#endif /* CONFIG_BZIP2 */
#ifdef CONFIG_LZMA
case IH_COMP_LZMA: {
SizeT lzma_len = unc_len;
- int ret;
-
- printf(" Uncompressing %s ... ", type_name);
ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
image_buf, image_len);
- unc_len = lzma_len;
- if (ret != SZ_OK) {
- printf("LZMA: uncompress or overwrite error %d - must RESET board to recover\n",
- ret);
- bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
- return BOOTM_ERR_RESET;
- }
- *load_end = load + unc_len;
+ image_len = lzma_len;
break;
}
#endif /* CONFIG_LZMA */
#ifdef CONFIG_LZO
case IH_COMP_LZO: {
size_t size = unc_len;
- int ret;
-
- printf(" Uncompressing %s ... ", type_name);
ret = lzop_decompress(image_buf, image_len, load_buf, &size);
- if (ret != LZO_E_OK) {
- printf("LZO: uncompress or overwrite error %d - must RESET board to recover\n",
- ret);
- return BOOTM_ERR_RESET;
- }
-
- *load_end = load + size;
+ image_len = size;
break;
}
#endif /* CONFIG_LZO */
@@ -369,6 +388,10 @@
return BOOTM_ERR_UNIMPLEMENTED;
}
+ if (ret)
+ return handle_decomp_error(comp, image_len, unc_len, ret);
+ *load_end = load + image_len;
+
puts("OK\n");
return 0;
@@ -390,8 +413,9 @@
load_buf = map_sysmem(load, 0);
image_buf = map_sysmem(os.image_start, image_len);
- err = decomp_image(os.comp, load, os.image_start, os.type, load_buf,
- image_buf, image_len, load_end);
+ err = bootm_decomp_image(os.comp, load, os.image_start, os.type,
+ load_buf, image_buf, image_len,
+ CONFIG_SYS_BOOTM_LEN, load_end);
if (err) {
bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
return err;
@@ -882,9 +906,11 @@
/* Allow the image to expand by a factor of 4, should be safe */
load_buf = malloc((1 << 20) + len * 4);
- ret = decomp_image(imape_comp, 0, data, image_type, load_buf,
- (void *)data, len, &load_end);
+ ret = bootm_decomp_image(imape_comp, 0, data, image_type, load_buf,
+ (void *)data, len, CONFIG_SYS_BOOTM_LEN,
+ &load_end);
free(load_buf);
+
if (ret && ret != BOOTM_ERR_UNIMPLEMENTED)
return ret;
diff --git a/common/bootm_os.c b/common/bootm_os.c
index 5be4467..72477f0 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -404,6 +404,32 @@
}
#endif
+#ifdef CONFIG_BOOTM_OPENRTOS
+static int do_bootm_openrtos(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ void (*entry_point)(void);
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+ entry_point = (void (*)(void))images->ep;
+
+ printf("## Transferring control to OpenRTOS (at address %08lx) ...\n",
+ (ulong)entry_point);
+
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+ /*
+ * OpenRTOS Parameters:
+ * None
+ */
+ (*entry_point)();
+
+ return 1;
+}
+#endif
+
static boot_os_fn *boot_os[] = {
[IH_OS_U_BOOT] = do_bootm_standalone,
#ifdef CONFIG_BOOTM_LINUX
@@ -434,6 +460,9 @@
#ifdef CONFIG_INTEGRITY
[IH_OS_INTEGRITY] = do_bootm_integrity,
#endif
+#ifdef CONFIG_BOOTM_OPENRTOS
+ [IH_OS_OPENRTOS] = do_bootm_openrtos,
+#endif
};
/* Allow for arch specific config before we boot */
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 8c5bf44..484a6c6 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -211,6 +211,7 @@
comp = image_get_comp(hdr);
if (comp == IH_COMP_GZIP) {
+#if defined(CONFIG_GZIP)
ulong image_buf = image_get_data(hdr);
data = image_get_load(hdr);
ulong image_size = ~0UL;
@@ -222,6 +223,10 @@
return 1;
}
data_size = image_size;
+#else
+ puts("Gunzip image is not supported\n");
+ return 1;
+#endif
} else {
data = (ulong)image_get_data(hdr);
data_size = image_get_data_size(hdr);
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 96478e4..4e28c9d 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -73,6 +73,8 @@
static void print_mmcinfo(struct mmc *mmc)
{
+ int i;
+
printf("Device: %s\n", mmc->cfg->name);
printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24);
printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff);
@@ -92,6 +94,48 @@
printf("Bus Width: %d-bit%s\n", mmc->bus_width,
mmc->ddr_mode ? " DDR" : "");
+
+ puts("Erase Group Size: ");
+ print_size(((u64)mmc->erase_grp_size) << 9, "\n");
+
+ if (!IS_SD(mmc) && mmc->version >= MMC_VERSION_4_41) {
+ bool has_enh = (mmc->part_support & ENHNCD_SUPPORT) != 0;
+ bool usr_enh = has_enh && (mmc->part_attr & EXT_CSD_ENH_USR);
+
+ puts("HC WP Group Size: ");
+ print_size(((u64)mmc->hc_wp_grp_size) << 9, "\n");
+
+ puts("User Capacity: ");
+ print_size(mmc->capacity_user, usr_enh ? " ENH" : "");
+ if (mmc->wr_rel_set & EXT_CSD_WR_DATA_REL_USR)
+ puts(" WRREL\n");
+ else
+ putc('\n');
+ if (usr_enh) {
+ puts("User Enhanced Start: ");
+ print_size(mmc->enh_user_start, "\n");
+ puts("User Enhanced Size: ");
+ print_size(mmc->enh_user_size, "\n");
+ }
+ puts("Boot Capacity: ");
+ print_size(mmc->capacity_boot, has_enh ? " ENH\n" : "\n");
+ puts("RPMB Capacity: ");
+ print_size(mmc->capacity_rpmb, has_enh ? " ENH\n" : "\n");
+
+ for (i = 0; i < ARRAY_SIZE(mmc->capacity_gp); i++) {
+ bool is_enh = has_enh &&
+ (mmc->part_attr & EXT_CSD_ENH_GP(i));
+ if (mmc->capacity_gp[i]) {
+ printf("GP%i Capacity: ", i+1);
+ print_size(mmc->capacity_gp[i],
+ is_enh ? " ENH" : "");
+ if (mmc->wr_rel_set & EXT_CSD_WR_DATA_REL_GP(i))
+ puts(" WRREL\n");
+ else
+ putc('\n');
+ }
+ }
+ }
}
static struct mmc *init_mmc_device(int dev, bool force_init)
{
@@ -444,6 +488,157 @@
print_mmc_devices('\n');
return CMD_RET_SUCCESS;
}
+
+static int parse_hwpart_user(struct mmc_hwpart_conf *pconf,
+ int argc, char * const argv[])
+{
+ int i = 0;
+
+ memset(&pconf->user, 0, sizeof(pconf->user));
+
+ while (i < argc) {
+ if (!strcmp(argv[i], "enh")) {
+ if (i + 2 >= argc)
+ return -1;
+ pconf->user.enh_start =
+ simple_strtoul(argv[i+1], NULL, 10);
+ pconf->user.enh_size =
+ simple_strtoul(argv[i+2], NULL, 10);
+ i += 3;
+ } else if (!strcmp(argv[i], "wrrel")) {
+ if (i + 1 >= argc)
+ return -1;
+ pconf->user.wr_rel_change = 1;
+ if (!strcmp(argv[i+1], "on"))
+ pconf->user.wr_rel_set = 1;
+ else if (!strcmp(argv[i+1], "off"))
+ pconf->user.wr_rel_set = 0;
+ else
+ return -1;
+ i += 2;
+ } else {
+ break;
+ }
+ }
+ return i;
+}
+
+static int parse_hwpart_gp(struct mmc_hwpart_conf *pconf, int pidx,
+ int argc, char * const argv[])
+{
+ int i;
+
+ memset(&pconf->gp_part[pidx], 0, sizeof(pconf->gp_part[pidx]));
+
+ if (1 >= argc)
+ return -1;
+ pconf->gp_part[pidx].size = simple_strtoul(argv[0], NULL, 10);
+
+ i = 1;
+ while (i < argc) {
+ if (!strcmp(argv[i], "enh")) {
+ pconf->gp_part[pidx].enhanced = 1;
+ i += 1;
+ } else if (!strcmp(argv[i], "wrrel")) {
+ if (i + 1 >= argc)
+ return -1;
+ pconf->gp_part[pidx].wr_rel_change = 1;
+ if (!strcmp(argv[i+1], "on"))
+ pconf->gp_part[pidx].wr_rel_set = 1;
+ else if (!strcmp(argv[i+1], "off"))
+ pconf->gp_part[pidx].wr_rel_set = 0;
+ else
+ return -1;
+ i += 2;
+ } else {
+ break;
+ }
+ }
+ return i;
+}
+
+static int do_mmc_hwpartition(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct mmc *mmc;
+ struct mmc_hwpart_conf pconf = { };
+ enum mmc_hwpart_conf_mode mode = MMC_HWPART_CONF_CHECK;
+ int i, r, pidx;
+
+ mmc = init_mmc_device(curr_device, false);
+ if (!mmc)
+ return CMD_RET_FAILURE;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+ i = 1;
+ while (i < argc) {
+ if (!strcmp(argv[i], "user")) {
+ i++;
+ r = parse_hwpart_user(&pconf, argc-i, &argv[i]);
+ if (r < 0)
+ return CMD_RET_USAGE;
+ i += r;
+ } else if (!strncmp(argv[i], "gp", 2) &&
+ strlen(argv[i]) == 3 &&
+ argv[i][2] >= '1' && argv[i][2] <= '4') {
+ pidx = argv[i][2] - '1';
+ i++;
+ r = parse_hwpart_gp(&pconf, pidx, argc-i, &argv[i]);
+ if (r < 0)
+ return CMD_RET_USAGE;
+ i += r;
+ } else if (!strcmp(argv[i], "check")) {
+ mode = MMC_HWPART_CONF_CHECK;
+ i++;
+ } else if (!strcmp(argv[i], "set")) {
+ mode = MMC_HWPART_CONF_SET;
+ i++;
+ } else if (!strcmp(argv[i], "complete")) {
+ mode = MMC_HWPART_CONF_COMPLETE;
+ i++;
+ } else {
+ return CMD_RET_USAGE;
+ }
+ }
+
+ puts("Partition configuration:\n");
+ if (pconf.user.enh_size) {
+ puts("\tUser Enhanced Start: ");
+ print_size(((u64)pconf.user.enh_start) << 9, "\n");
+ puts("\tUser Enhanced Size: ");
+ print_size(((u64)pconf.user.enh_size) << 9, "\n");
+ } else {
+ puts("\tNo enhanced user data area\n");
+ }
+ if (pconf.user.wr_rel_change)
+ printf("\tUser partition write reliability: %s\n",
+ pconf.user.wr_rel_set ? "on" : "off");
+ for (pidx = 0; pidx < 4; pidx++) {
+ if (pconf.gp_part[pidx].size) {
+ printf("\tGP%i Capacity: ", pidx+1);
+ print_size(((u64)pconf.gp_part[pidx].size) << 9,
+ pconf.gp_part[pidx].enhanced ?
+ " ENH\n" : "\n");
+ } else {
+ printf("\tNo GP%i partition\n", pidx+1);
+ }
+ if (pconf.gp_part[pidx].wr_rel_change)
+ printf("\tGP%i write reliability: %s\n", pidx+1,
+ pconf.gp_part[pidx].wr_rel_set ? "on" : "off");
+ }
+
+ if (!mmc_hwpart_config(mmc, &pconf, mode)) {
+ if (mode == MMC_HWPART_CONF_COMPLETE)
+ puts("Partitioning successful, "
+ "power-cycle to make effective\n");
+ return CMD_RET_SUCCESS;
+ } else {
+ puts("Failed!\n");
+ return CMD_RET_FAILURE;
+ }
+}
+
#ifdef CONFIG_SUPPORT_EMMC_BOOT
static int do_mmc_bootbus(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
@@ -601,6 +796,7 @@
U_BOOT_CMD_MKENT(part, 1, 1, do_mmc_part, "", ""),
U_BOOT_CMD_MKENT(dev, 3, 0, do_mmc_dev, "", ""),
U_BOOT_CMD_MKENT(list, 1, 1, do_mmc_list, "", ""),
+ U_BOOT_CMD_MKENT(hwpartition, 28, 0, do_mmc_hwpartition, "", ""),
#ifdef CONFIG_SUPPORT_EMMC_BOOT
U_BOOT_CMD_MKENT(bootbus, 5, 0, do_mmc_bootbus, "", ""),
U_BOOT_CMD_MKENT(bootpart-resize, 4, 0, do_mmc_boot_resize, "", ""),
@@ -640,7 +836,7 @@
}
U_BOOT_CMD(
- mmc, 7, 1, do_mmcops,
+ mmc, 29, 1, do_mmcops,
"MMC sub system",
"info - display info of the current MMC device\n"
"mmc read addr blk# cnt\n"
@@ -650,6 +846,13 @@
"mmc part - lists available partition on current mmc device\n"
"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
"mmc list - lists available devices\n"
+ "mmc hwpartition [args...] - does hardware partitioning\n"
+ " arguments (sizes in 512-byte blocks):\n"
+ " [user [enh start cnt] [wrrel {on|off}]] - sets user data area attributes\n"
+ " [gp1|gp2|gp3|gp4 cnt [enh] [wrrel {on|off}]] - general purpose partition\n"
+ " [check|set|complete] - mode, complete set partitioning completed\n"
+ " WARNING: Partitioning is a write-once setting once it is set to complete.\n"
+ " Power cycling is required to initialize partitions after set to complete.\n"
#ifdef CONFIG_SUPPORT_EMMC_BOOT
"mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n"
" - Set the BOOT_BUS_WIDTH field of the specified device\n"
diff --git a/common/cmd_sandbox.c b/common/cmd_sandbox.c
index 3d9fce7..4286969 100644
--- a/common/cmd_sandbox.c
+++ b/common/cmd_sandbox.c
@@ -117,7 +117,7 @@
"load hostfs - <addr> <filename> [<bytes> <offset>] - "
"load a file from host\n"
"sb ls hostfs - <filename> - list files on host\n"
- "sb save hostfs - <filename> <addr> <bytes> [<offset>] - "
+ "sb save hostfs - <addr> <filename> <bytes> [<offset>] - "
"save a file to host\n"
"sb bind <dev> [<filename>] - bind \"host\" device to file\n"
"sb info [<dev>] - show device binding & info\n"
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index c192498..27813f0 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -441,6 +441,26 @@
return 0;
}
+static void do_usb_start(void)
+{
+ bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start");
+
+ if (usb_init() < 0)
+ return;
+
+#ifdef CONFIG_USB_STORAGE
+ /* try to recognize storage devices immediately */
+ usb_stor_curr_dev = usb_stor_scan(1);
+#endif
+#ifdef CONFIG_USB_HOST_ETHER
+ /* try to recognize ethernet devices immediately */
+ usb_ether_curr_dev = usb_host_eth_scan(1);
+#endif
+#ifdef CONFIG_USB_KEYBOARD
+ drv_usb_kbd_init();
+#endif
+}
+
/******************************************************************************
* usb command intepreter
*/
@@ -457,26 +477,20 @@
if (argc < 2)
return CMD_RET_USAGE;
- if ((strncmp(argv[1], "reset", 5) == 0) ||
- (strncmp(argv[1], "start", 5) == 0)) {
- bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start");
+ if (strncmp(argv[1], "start", 5) == 0) {
+ if (usb_started)
+ return 0; /* Already started */
+ printf("starting USB...\n");
+ do_usb_start();
+ return 0;
+ }
+
+ if (strncmp(argv[1], "reset", 5) == 0) {
+ printf("resetting USB...\n");
if (do_usb_stop_keyboard(1) != 0)
return 1;
usb_stop();
- printf("(Re)start USB...\n");
- if (usb_init() >= 0) {
-#ifdef CONFIG_USB_STORAGE
- /* try to recognize storage devices immediately */
- usb_stor_curr_dev = usb_stor_scan(1);
-#endif
-#ifdef CONFIG_USB_HOST_ETHER
- /* try to recognize ethernet devices immediately */
- usb_ether_curr_dev = usb_host_eth_scan(1);
-#endif
-#ifdef CONFIG_USB_KEYBOARD
- drv_usb_kbd_init();
-#endif
- }
+ do_usb_start();
return 0;
}
if (strncmp(argv[1], "stop", 4) == 0) {
diff --git a/common/console.c b/common/console.c
index 29560c3..fc1963b 100644
--- a/common/console.c
+++ b/common/console.c
@@ -199,6 +199,20 @@
}
}
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+static void console_putc_noserial(int file, const char c)
+{
+ int i;
+ struct stdio_dev *dev;
+
+ for (i = 0; i < cd_count[file]; i++) {
+ dev = console_devices[file][i];
+ if (dev->putc != NULL && strcmp(dev->name, "serial") != 0)
+ dev->putc(dev, c);
+ }
+}
+#endif
+
static void console_puts(int file, const char *s)
{
int i;
@@ -236,6 +250,14 @@
stdio_devices[file]->putc(stdio_devices[file], c);
}
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+static inline void console_putc_noserial(int file, const char c)
+{
+ if (strcmp(stdio_devices[file]->name, "serial") != 0)
+ stdio_devices[file]->putc(stdio_devices[file], c);
+}
+#endif
+
static inline void console_puts(int file, const char *s)
{
stdio_devices[file]->puts(stdio_devices[file], s);
@@ -382,6 +404,9 @@
return serial_tstc();
}
+#define PRE_CONSOLE_FLUSHPOINT1_SERIAL 0
+#define PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL 1
+
#ifdef CONFIG_PRE_CONSOLE_BUFFER
#define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)CONFIG_PRE_CON_BUF_SZ)
@@ -398,7 +423,7 @@
pre_console_putc(*s++);
}
-static void print_pre_console_buffer(void)
+static void print_pre_console_buffer(int flushpoint)
{
unsigned long i = 0;
char *buffer = (char *)CONFIG_PRE_CON_BUF_ADDR;
@@ -407,12 +432,20 @@
i = gd->precon_buf_idx - CONFIG_PRE_CON_BUF_SZ;
while (i < gd->precon_buf_idx)
- putc(buffer[CIRC_BUF_IDX(i++)]);
+ switch (flushpoint) {
+ case PRE_CONSOLE_FLUSHPOINT1_SERIAL:
+ putc(buffer[CIRC_BUF_IDX(i++)]);
+ break;
+ case PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL:
+ console_putc_noserial(stdout,
+ buffer[CIRC_BUF_IDX(i++)]);
+ break;
+ }
}
#else
static inline void pre_console_putc(const char c) {}
static inline void pre_console_puts(const char *s) {}
-static inline void print_pre_console_buffer(void) {}
+static inline void print_pre_console_buffer(int flushpoint) {}
#endif
void putc(const char c)
@@ -441,6 +474,7 @@
fputc(stdout, c);
} else {
/* Send directly to the handler */
+ pre_console_putc(c);
serial_putc(c);
}
}
@@ -472,6 +506,7 @@
fputs(stdout, s);
} else {
/* Send directly to the handler */
+ pre_console_puts(s);
serial_puts(s);
}
}
@@ -679,7 +714,7 @@
gd->flags |= GD_FLG_SILENT;
#endif
- print_pre_console_buffer();
+ print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT1_SERIAL);
return 0;
}
@@ -794,6 +829,7 @@
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
return 0;
#endif
+ print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL);
return 0;
}
@@ -869,7 +905,7 @@
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
return 0;
#endif
-
+ print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL);
return 0;
}
diff --git a/common/edid.c b/common/edid.c
index e66108f..df797fc 100644
--- a/common/edid.c
+++ b/common/edid.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <edid.h>
+#include <errno.h>
#include <linux/ctype.h>
#include <linux/string.h>
@@ -29,6 +30,17 @@
return 0;
}
+int edid_check_checksum(u8 *edid_block)
+{
+ u8 checksum = 0;
+ int i;
+
+ for (i = 0; i < 128; i++)
+ checksum += edid_block[i];
+
+ return (checksum == 0) ? 0 : -EINVAL;
+}
+
int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin,
unsigned int *hmax, unsigned int *vmin,
unsigned int *vmax)
diff --git a/common/image-fit.c b/common/image-fit.c
index 4ffc5aa..1589ee3 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1518,6 +1518,7 @@
size_t size;
int type_ok, os_ok;
ulong load, data, len;
+ uint8_t os;
const char *prop_name;
int ret;
@@ -1612,10 +1613,15 @@
(image_type == IH_TYPE_KERNEL &&
fit_image_check_type(fit, noffset,
IH_TYPE_KERNEL_NOLOAD));
+
os_ok = image_type == IH_TYPE_FLATDT ||
- fit_image_check_os(fit, noffset, IH_OS_LINUX);
+ fit_image_check_os(fit, noffset, IH_OS_LINUX) ||
+ fit_image_check_os(fit, noffset, IH_OS_OPENRTOS);
if (!type_ok || !os_ok) {
- printf("No Linux %s %s Image\n", genimg_get_arch_name(arch),
+ fit_image_get_os(fit, noffset, &os);
+ printf("No %s %s %s Image\n",
+ genimg_get_os_name(os),
+ genimg_get_arch_name(arch),
genimg_get_type_name(image_type));
bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL);
return -EIO;
diff --git a/common/image.c b/common/image.c
index e691a51..ad7a46d 100644
--- a/common/image.c
+++ b/common/image.c
@@ -120,6 +120,10 @@
{ IH_OS_SOLARIS, "solaris", "Solaris", },
{ IH_OS_SVR4, "svr4", "SVR4", },
#endif
+#if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC)
+ { IH_OS_OPENRTOS, "openrtos", "OpenRTOS", },
+#endif
+
{ -1, "", "", },
};
diff --git a/common/lcd.c b/common/lcd.c
index 3ed504d..cc34b8a 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -73,45 +73,13 @@
#define CONFIG_LCD_ALIGNMENT PAGE_SIZE
#endif
-/* By default we scroll by a single line */
-#ifndef CONFIG_CONSOLE_SCROLL_LINES
-#define CONFIG_CONSOLE_SCROLL_LINES 1
-#endif
-
-/************************************************************************/
-/* ** CONSOLE DEFINITIONS & FUNCTIONS */
-/************************************************************************/
-#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
-# define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \
- / VIDEO_FONT_HEIGHT)
-#else
-# define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT)
-#endif
-
-#define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH)
-#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length)
-#define CONSOLE_ROW_FIRST lcd_console_address
-#define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE)
-#define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \
- - CONSOLE_ROW_SIZE)
-#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS)
-#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE)
-
-#if LCD_BPP == LCD_MONOCHROME
-# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
- (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
-#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || \
- (LCD_BPP == LCD_COLOR32)
-# define COLOR_MASK(c) (c)
-#else
+#if (LCD_BPP != LCD_COLOR8) && (LCD_BPP != LCD_COLOR16) && \
+ (LCD_BPP != LCD_COLOR32)
# error Unsupported LCD BPP.
#endif
DECLARE_GLOBAL_DATA_PTR;
-static void lcd_drawchars(ushort x, ushort y, uchar *str, int count);
-static inline void lcd_putc_xy(ushort x, ushort y, uchar c);
-
static int lcd_init(void *lcdbase);
static void *lcd_logo(void);
@@ -125,10 +93,6 @@
char lcd_is_enabled = 0;
-static short console_col;
-static short console_row;
-
-static void *lcd_console_address;
static void *lcd_base; /* Start of framebuffer memory */
static char lcd_flush_dcache; /* 1 to flush dcache after each lcd update */
@@ -166,217 +130,16 @@
/*----------------------------------------------------------------------*/
-static void console_scrollup(void)
-{
- const int rows = CONFIG_CONSOLE_SCROLL_LINES;
-
- /* Copy up rows ignoring those that will be overwritten */
- memcpy(CONSOLE_ROW_FIRST,
- lcd_console_address + CONSOLE_ROW_SIZE * rows,
- CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows);
-
- /* Clear the last rows */
-#if (LCD_BPP != LCD_COLOR32)
- memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows,
- COLOR_MASK(lcd_color_bg),
- CONSOLE_ROW_SIZE * rows);
-#else
- u32 *ppix = lcd_console_address +
- CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows;
- u32 i;
- for (i = 0;
- i < (CONSOLE_ROW_SIZE * rows) / NBYTES(panel_info.vl_bpix);
- i++) {
- *ppix++ = COLOR_MASK(lcd_color_bg);
- }
-#endif
- lcd_sync();
- console_row -= rows;
-}
-
-/*----------------------------------------------------------------------*/
-
-static inline void console_back(void)
-{
- if (--console_col < 0) {
- console_col = CONSOLE_COLS-1 ;
- if (--console_row < 0)
- console_row = 0;
- }
-
- lcd_putc_xy(console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT, ' ');
-}
-
-/*----------------------------------------------------------------------*/
-
-static inline void console_newline(void)
-{
- console_col = 0;
-
- /* Check if we need to scroll the terminal */
- if (++console_row >= CONSOLE_ROWS)
- console_scrollup();
- else
- lcd_sync();
-}
-
-/*----------------------------------------------------------------------*/
-
static void lcd_stub_putc(struct stdio_dev *dev, const char c)
{
lcd_putc(c);
}
-void lcd_putc(const char c)
-{
- if (!lcd_is_enabled) {
- serial_putc(c);
-
- return;
- }
-
- switch (c) {
- case '\r':
- console_col = 0;
-
- return;
- case '\n':
- console_newline();
-
- return;
- case '\t': /* Tab (8 chars alignment) */
- console_col += 8;
- console_col &= ~7;
-
- if (console_col >= CONSOLE_COLS)
- console_newline();
-
- return;
- case '\b':
- console_back();
-
- return;
- default:
- lcd_putc_xy(console_col * VIDEO_FONT_WIDTH,
- console_row * VIDEO_FONT_HEIGHT, c);
- if (++console_col >= CONSOLE_COLS)
- console_newline();
- }
-}
-
-/*----------------------------------------------------------------------*/
-
static void lcd_stub_puts(struct stdio_dev *dev, const char *s)
{
lcd_puts(s);
}
-void lcd_puts(const char *s)
-{
- if (!lcd_is_enabled) {
- serial_puts(s);
-
- return;
- }
-
- while (*s)
- lcd_putc(*s++);
-
- lcd_sync();
-}
-
-/*----------------------------------------------------------------------*/
-
-void lcd_printf(const char *fmt, ...)
-{
- va_list args;
- char buf[CONFIG_SYS_PBSIZE];
-
- va_start(args, fmt);
- vsprintf(buf, fmt, args);
- va_end(args);
-
- lcd_puts(buf);
-}
-
-/************************************************************************/
-/* ** Low-Level Graphics Routines */
-/************************************************************************/
-
-static void lcd_drawchars(ushort x, ushort y, uchar *str, int count)
-{
- uchar *dest;
- ushort row;
-
-#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
- y += BMP_LOGO_HEIGHT;
-#endif
-
-#if LCD_BPP == LCD_MONOCHROME
- ushort off = x * (1 << LCD_BPP) % 8;
-#endif
-
- dest = (uchar *)(lcd_base + y * lcd_line_length + x * NBITS(LCD_BPP)/8);
-
- for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) {
- uchar *s = str;
- int i;
-#if LCD_BPP == LCD_COLOR16
- ushort *d = (ushort *)dest;
-#elif LCD_BPP == LCD_COLOR32
- u32 *d = (u32 *)dest;
-#else
- uchar *d = dest;
-#endif
-
-#if LCD_BPP == LCD_MONOCHROME
- uchar rest = *d & -(1 << (8 - off));
- uchar sym;
-#endif
- for (i = 0; i < count; ++i) {
- uchar c, bits;
-
- c = *s++;
- bits = video_fontdata[c * VIDEO_FONT_HEIGHT + row];
-
-#if LCD_BPP == LCD_MONOCHROME
- sym = (COLOR_MASK(lcd_color_fg) & bits) |
- (COLOR_MASK(lcd_color_bg) & ~bits);
-
- *d++ = rest | (sym >> off);
- rest = sym << (8-off);
-#elif LCD_BPP == LCD_COLOR8
- for (c = 0; c < 8; ++c) {
- *d++ = (bits & 0x80) ?
- lcd_color_fg : lcd_color_bg;
- bits <<= 1;
- }
-#elif LCD_BPP == LCD_COLOR16
- for (c = 0; c < 8; ++c) {
- *d++ = (bits & 0x80) ?
- lcd_color_fg : lcd_color_bg;
- bits <<= 1;
- }
-#elif LCD_BPP == LCD_COLOR32
- for (c = 0; c < 8; ++c) {
- *d++ = (bits & 0x80) ?
- lcd_color_fg : lcd_color_bg;
- bits <<= 1;
- }
-#endif
- }
-#if LCD_BPP == LCD_MONOCHROME
- *d = rest | (*d & ((1 << (8 - off)) - 1));
-#endif
- }
-}
-
-static inline void lcd_putc_xy(ushort x, ushort y, uchar c)
-{
- lcd_drawchars(x, y, &c, 1);
-}
-
/************************************************************************/
/** Small utility to check that you got the colours right */
/************************************************************************/
@@ -455,11 +218,9 @@
/*----------------------------------------------------------------------*/
void lcd_clear(void)
{
-#if LCD_BPP == LCD_MONOCHROME
- /* Setting the palette */
- lcd_initcolregs();
-
-#elif LCD_BPP == LCD_COLOR8
+ short console_rows, console_cols;
+ int bg_color;
+#if LCD_BPP == LCD_COLOR8
/* Setting the palette */
lcd_setcolreg(CONSOLE_COLOR_BLACK, 0, 0, 0);
lcd_setcolreg(CONSOLE_COLOR_RED, 0xFF, 0, 0);
@@ -475,9 +236,11 @@
#ifndef CONFIG_SYS_WHITE_ON_BLACK
lcd_setfgcolor(CONSOLE_COLOR_BLACK);
lcd_setbgcolor(CONSOLE_COLOR_WHITE);
+ bg_color = CONSOLE_COLOR_WHITE;
#else
lcd_setfgcolor(CONSOLE_COLOR_WHITE);
lcd_setbgcolor(CONSOLE_COLOR_BLACK);
+ bg_color = CONSOLE_COLOR_BLACK;
#endif /* CONFIG_SYS_WHITE_ON_BLACK */
#ifdef LCD_TEST_PATTERN
@@ -485,25 +248,27 @@
#else
/* set framebuffer to background color */
#if (LCD_BPP != LCD_COLOR32)
- memset((char *)lcd_base,
- COLOR_MASK(lcd_color_bg),
- lcd_line_length * panel_info.vl_row);
+ memset((char *)lcd_base, bg_color, lcd_line_length * panel_info.vl_row);
#else
u32 *ppix = lcd_base;
u32 i;
for (i = 0;
i < (lcd_line_length * panel_info.vl_row)/NBYTES(panel_info.vl_bpix);
i++) {
- *ppix++ = COLOR_MASK(lcd_color_bg);
+ *ppix++ = bg_color;
}
#endif
#endif
/* Paint the logo and retrieve LCD base address */
debug("[LCD] Drawing the logo...\n");
- lcd_console_address = lcd_logo();
-
- console_col = 0;
- console_row = 0;
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
+ console_rows = (panel_info.vl_row - BMP_LOGO_HEIGHT);
+ console_rows /= VIDEO_FONT_HEIGHT;
+#else
+ console_rows = panel_info.vl_row / VIDEO_FONT_HEIGHT;
+#endif
+ console_cols = panel_info.vl_col / VIDEO_FONT_WIDTH;
+ lcd_init_console(lcd_logo(), console_rows, console_cols);
lcd_sync();
}
@@ -546,11 +311,11 @@
lcd_enable();
/* Initialize the console */
- console_col = 0;
+ lcd_set_col(0);
#ifdef CONFIG_LCD_INFO_BELOW_LOGO
- console_row = 7 + BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT;
+ lcd_set_row(7 + BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT);
#else
- console_row = 1; /* leave 1 blank line below logo */
+ lcd_set_row(1); /* leave 1 blank line below logo */
#endif
return 0;
@@ -597,6 +362,11 @@
lcd_color_fg = color;
}
+int lcd_getfgcolor(void)
+{
+ return lcd_color_fg;
+}
+
/*----------------------------------------------------------------------*/
static void lcd_setbgcolor(int color)
@@ -604,6 +374,11 @@
lcd_color_bg = color;
}
+int lcd_getbgcolor(void)
+{
+ return lcd_color_bg;
+}
+
/************************************************************************/
/* ** Chipset depending Bitmap / Logo stuff... */
/************************************************************************/
@@ -685,11 +460,7 @@
*(cmap + BMP_LOGO_OFFSET) = lut_entry;
cmap++;
#else /* !CONFIG_ATMEL_LCD */
-#ifdef CONFIG_SYS_INVERT_COLORS
- *cmap++ = 0xffff - colreg;
-#else
*cmap++ = colreg;
-#endif
#endif /* CONFIG_ATMEL_LCD */
}
@@ -967,11 +738,7 @@
( ((cte.red) << 8) & 0xf800) |
( ((cte.green) << 3) & 0x07e0) |
( ((cte.blue) >> 3) & 0x001f) ;
-#ifdef CONFIG_SYS_INVERT_COLORS
- *cmap = 0xffff - colreg;
-#else
*cmap = colreg;
-#endif
#if defined(CONFIG_MPC823)
cmap--;
#else
@@ -1108,8 +875,8 @@
bitmap_plot(0, 0);
#ifdef CONFIG_LCD_INFO
- console_col = LCD_INFO_X / VIDEO_FONT_WIDTH;
- console_row = LCD_INFO_Y / VIDEO_FONT_HEIGHT;
+ lcd_set_col(LCD_INFO_X / VIDEO_FONT_WIDTH);
+ lcd_set_row(LCD_INFO_Y / VIDEO_FONT_HEIGHT);
lcd_show_board_info();
#endif /* CONFIG_LCD_INFO */
@@ -1144,12 +911,6 @@
U_BOOT_ENV_CALLBACK(splashimage, on_splashimage);
#endif
-void lcd_position_cursor(unsigned col, unsigned row)
-{
- console_col = min_t(short, col, CONSOLE_COLS - 1);
- console_row = min_t(short, row, CONSOLE_ROWS - 1);
-}
-
int lcd_get_pixel_width(void)
{
return panel_info.vl_col;
@@ -1160,16 +921,6 @@
return panel_info.vl_row;
}
-int lcd_get_screen_rows(void)
-{
- return CONSOLE_ROWS;
-}
-
-int lcd_get_screen_columns(void)
-{
- return CONSOLE_COLS;
-}
-
#if defined(CONFIG_LCD_DT_SIMPLEFB)
static int lcd_dt_simplefb_configure_node(void *blob, int off)
{
diff --git a/common/lcd_console.c b/common/lcd_console.c
new file mode 100644
index 0000000..74c388a
--- /dev/null
+++ b/common/lcd_console.c
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2001-2014
+ * DENX Software Engineering -- wd@denx.de
+ * Compulab Ltd - http://compulab.co.il/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <video_font.h> /* Get font data, width and height */
+
+#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length)
+#define CONSOLE_ROW_FIRST lcd_console_address
+#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * console_rows)
+
+static short console_curr_col;
+static short console_curr_row;
+static short console_cols;
+static short console_rows;
+static void *lcd_console_address;
+
+void lcd_init_console(void *address, int rows, int cols)
+{
+ console_curr_col = 0;
+ console_curr_row = 0;
+ console_cols = cols;
+ console_rows = rows;
+ lcd_console_address = address;
+}
+
+void lcd_set_col(short col)
+{
+ console_curr_col = col;
+}
+
+void lcd_set_row(short row)
+{
+ console_curr_row = row;
+}
+
+void lcd_position_cursor(unsigned col, unsigned row)
+{
+ console_curr_col = min_t(short, col, console_cols - 1);
+ console_curr_row = min_t(short, row, console_rows - 1);
+}
+
+int lcd_get_screen_rows(void)
+{
+ return console_rows;
+}
+
+int lcd_get_screen_columns(void)
+{
+ return console_cols;
+}
+
+static void lcd_drawchars(ushort x, ushort y, uchar *str, int count)
+{
+ uchar *dest;
+ ushort row;
+ int fg_color, bg_color;
+
+ dest = (uchar *)(lcd_console_address +
+ y * lcd_line_length + x * NBITS(LCD_BPP) / 8);
+
+ for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) {
+ uchar *s = str;
+ int i;
+#if LCD_BPP == LCD_COLOR16
+ ushort *d = (ushort *)dest;
+#elif LCD_BPP == LCD_COLOR32
+ u32 *d = (u32 *)dest;
+#else
+ uchar *d = dest;
+#endif
+
+ fg_color = lcd_getfgcolor();
+ bg_color = lcd_getbgcolor();
+ for (i = 0; i < count; ++i) {
+ uchar c, bits;
+
+ c = *s++;
+ bits = video_fontdata[c * VIDEO_FONT_HEIGHT + row];
+
+ for (c = 0; c < 8; ++c) {
+ *d++ = (bits & 0x80) ? fg_color : bg_color;
+ bits <<= 1;
+ }
+ }
+ }
+}
+
+static inline void lcd_putc_xy(ushort x, ushort y, uchar c)
+{
+ lcd_drawchars(x, y, &c, 1);
+}
+
+static void console_scrollup(void)
+{
+ const int rows = CONFIG_CONSOLE_SCROLL_LINES;
+ int bg_color = lcd_getbgcolor();
+
+ /* Copy up rows ignoring those that will be overwritten */
+ memcpy(CONSOLE_ROW_FIRST,
+ lcd_console_address + CONSOLE_ROW_SIZE * rows,
+ CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows);
+
+ /* Clear the last rows */
+#if (LCD_BPP != LCD_COLOR32)
+ memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows,
+ bg_color, CONSOLE_ROW_SIZE * rows);
+#else
+ u32 *ppix = lcd_console_address +
+ CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows;
+ u32 i;
+ for (i = 0;
+ i < (CONSOLE_ROW_SIZE * rows) / NBYTES(panel_info.vl_bpix);
+ i++) {
+ *ppix++ = bg_color;
+ }
+#endif
+ lcd_sync();
+ console_curr_row -= rows;
+}
+
+static inline void console_back(void)
+{
+ if (--console_curr_col < 0) {
+ console_curr_col = console_cols - 1;
+ if (--console_curr_row < 0)
+ console_curr_row = 0;
+ }
+
+ lcd_putc_xy(console_curr_col * VIDEO_FONT_WIDTH,
+ console_curr_row * VIDEO_FONT_HEIGHT, ' ');
+}
+
+static inline void console_newline(void)
+{
+ console_curr_col = 0;
+
+ /* Check if we need to scroll the terminal */
+ if (++console_curr_row >= console_rows)
+ console_scrollup();
+ else
+ lcd_sync();
+}
+
+void lcd_putc(const char c)
+{
+ if (!lcd_is_enabled) {
+ serial_putc(c);
+
+ return;
+ }
+
+ switch (c) {
+ case '\r':
+ console_curr_col = 0;
+
+ return;
+ case '\n':
+ console_newline();
+
+ return;
+ case '\t': /* Tab (8 chars alignment) */
+ console_curr_col += 8;
+ console_curr_col &= ~7;
+
+ if (console_curr_col >= console_cols)
+ console_newline();
+
+ return;
+ case '\b':
+ console_back();
+
+ return;
+ default:
+ lcd_putc_xy(console_curr_col * VIDEO_FONT_WIDTH,
+ console_curr_row * VIDEO_FONT_HEIGHT, c);
+ if (++console_curr_col >= console_cols)
+ console_newline();
+ }
+}
+
+void lcd_puts(const char *s)
+{
+ if (!lcd_is_enabled) {
+ serial_puts(s);
+
+ return;
+ }
+
+ while (*s)
+ lcd_putc(*s++);
+
+ lcd_sync();
+}
+
+void lcd_printf(const char *fmt, ...)
+{
+ va_list args;
+ char buf[CONFIG_SYS_PBSIZE];
+
+ va_start(args, fmt);
+ vsprintf(buf, fmt, args);
+ va_end(args);
+
+ lcd_puts(buf);
+}
diff --git a/common/memsize.c b/common/memsize.c
index 589400d..0fb9ba5 100644
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -33,43 +33,46 @@
long size;
int i = 0;
- for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
+ for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
- sync ();
+ sync();
save[i++] = *addr;
- sync ();
+ sync();
*addr = ~cnt;
}
addr = base;
- sync ();
+ sync();
save[i] = *addr;
- sync ();
+ sync();
*addr = 0;
- sync ();
+ sync();
if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function.
- */
- sync ();
+ /* Restore the original data before leaving the function. */
+ sync();
*addr = save[i];
for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
addr = base + cnt;
- sync ();
+ sync();
*addr = save[--i];
}
return (0);
}
- for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
+ for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
- size = cnt * sizeof (long);
- /* Restore the original data before leaving the function.
+ size = cnt * sizeof(long);
+ /*
+ * Restore the original data
+ * before leaving the function.
*/
- for (cnt <<= 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
+ for (cnt <<= 1;
+ cnt < maxsize / sizeof(long);
+ cnt <<= 1) {
addr = base + cnt;
*addr = save[--i];
}
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index b444a3e..2c0e8e0 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -15,37 +15,51 @@
*/
spl_image.flags |= SPL_COPY_PAYLOAD_ONLY;
- if (spl_start_uboot()) {
- /*
- * Load real U-Boot from its location in NOR flash to its
- * defined location in SDRAM
- */
- spl_parse_image_header(
- (const struct image_header *)CONFIG_SYS_UBOOT_BASE);
+#ifdef CONFIG_SPL_OS_BOOT
+ if (!spl_start_uboot()) {
+ struct image_header *header;
- memcpy((void *)spl_image.load_addr,
- (void *)(CONFIG_SYS_UBOOT_BASE +
- sizeof(struct image_header)),
- spl_image.size);
- } else {
/*
* Load Linux from its location in NOR flash to its defined
* location in SDRAM
*/
- spl_parse_image_header(
- (const struct image_header *)CONFIG_SYS_OS_BASE);
+ header = (const struct image_header *)CONFIG_SYS_OS_BASE;
- memcpy((void *)spl_image.load_addr,
- (void *)(CONFIG_SYS_OS_BASE +
- sizeof(struct image_header)),
- spl_image.size);
+ if (image_get_os(header) == IH_OS_LINUX) {
+ /* happy - was a Linux */
- /*
- * Copy DT blob (fdt) to SDRAM. Passing pointer to flash
- * doesn't work (16 KiB should be enough for DT)
- */
- memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR,
- (void *)(CONFIG_SYS_FDT_BASE),
- (16 << 10));
+ spl_parse_image_header(header);
+
+ memcpy((void *)spl_image.load_addr,
+ (void *)(CONFIG_SYS_OS_BASE +
+ sizeof(struct image_header)),
+ spl_image.size);
+
+ /*
+ * Copy DT blob (fdt) to SDRAM. Passing pointer to
+ * flash doesn't work (16 KiB should be enough for DT)
+ */
+ memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR,
+ (void *)(CONFIG_SYS_FDT_BASE),
+ (16 << 10));
+
+ return;
+ } else {
+ puts("The Expected Linux image was not found.\n"
+ "Please check your NOR configuration.\n"
+ "Trying to start u-boot now...\n");
+ }
}
+#endif
+
+ /*
+ * Load real U-Boot from its location in NOR flash to its
+ * defined location in SDRAM
+ */
+ spl_parse_image_header(
+ (const struct image_header *)CONFIG_SYS_UBOOT_BASE);
+
+ memcpy((void *)spl_image.load_addr,
+ (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)),
+ spl_image.size);
}
diff --git a/common/usb.c b/common/usb.c
index 736cd9f..32e15cd 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -59,6 +59,7 @@
void *ctrl;
struct usb_device *dev;
int i, start_index = 0;
+ int controllers_initialized = 0;
int ret;
dev_index = 0;
@@ -78,6 +79,7 @@
ret = usb_lowlevel_init(i, USB_INIT_HOST, &ctrl);
if (ret == -ENODEV) { /* No such device. */
puts("Port not available.\n");
+ controllers_initialized++;
continue;
}
@@ -89,6 +91,7 @@
* lowlevel init is OK, now scan the bus for devices
* i.e. search HUBs and configure them
*/
+ controllers_initialized++;
start_index = dev_index;
printf("scanning bus %d for devices... ", i);
dev = usb_alloc_new_device(ctrl);
@@ -110,12 +113,10 @@
debug("scan end\n");
/* if we were not able to find at least one working bus, bail out */
- if (!usb_started) {
+ if (controllers_initialized == 0)
puts("USB error: all controllers failed lowlevel init\n");
- return -1;
- }
- return 0;
+ return usb_started ? 0 : -1;
}
/******************************************************************************
@@ -969,6 +970,8 @@
printf("\n Couldn't reset port %i\n", dev->portnr);
return 1;
}
+ } else {
+ usb_reset_root_port();
}
#endif
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index bc7145e..ecc3085 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -332,7 +332,8 @@
/* We've consumed all queued int packets, create new */
destroy_int_queue(dev, data->intq);
data->intq = create_int_queue(dev, data->intpipe, 1,
- USB_KBD_BOOT_REPORT_SIZE, data->new);
+ USB_KBD_BOOT_REPORT_SIZE, data->new,
+ data->intinterval);
}
#endif
}
@@ -453,7 +454,8 @@
debug("USB KBD: enable interrupt pipe...\n");
#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
data->intq = create_int_queue(dev, data->intpipe, 1,
- USB_KBD_BOOT_REPORT_SIZE, data->new);
+ USB_KBD_BOOT_REPORT_SIZE, data->new,
+ data->intinterval);
if (!data->intq) {
#else
if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize,
@@ -542,6 +544,10 @@
data = usb_kbd_dev->privptr;
if (stdio_deregister_dev(dev, force) != 0)
return 1;
+#ifdef CONFIG_CONSOLE_MUX
+ if (iomux_doenv(stdin, getenv("stdin")) != 0)
+ return 1;
+#endif
#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
destroy_int_queue(usb_kbd_dev, data->intq);
#endif
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index f0cbf21..8fa1a33 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -4,4 +4,6 @@
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_TARGET_A10_OLINUXINO_L=y
++S:CONFIG_DRAM_CLK=480
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index be8652b..1a99418 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -2,8 +2,13 @@
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI"
CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb"
CONFIG_USB1_VBUS_PIN="PG11"
-CONFIG_VIDEO=n
-CONFIG_USB_KEYBOARD=n
+CONFIG_VIDEO_HDMI=n
+CONFIG_VIDEO_VGA_VIA_LCD=y
+# For use with the Olimex 7" LCD module, adjust timings for other displays
+# Set video-mode=sunxi:800x600-24@60,monitor=lcd in the env. to enable
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="PB10"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN5I=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 654e12a..7df6951 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -2,8 +2,13 @@
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb"
CONFIG_USB1_VBUS_PIN="PG11"
-CONFIG_VIDEO=n
-CONFIG_USB_KEYBOARD=n
+CONFIG_VIDEO_HDMI=n
+CONFIG_VIDEO_VGA_VIA_LCD=y
+# For use with the Olimex 7" LCD module, adjust timings for other displays
+# Set video-mode=sunxi:800x600-24@60,monitor=lcd in the env. to enable
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="AXP0-0"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN5I=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index f80b98a..17fd19d 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -5,3 +5,6 @@
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_A20_OLINUXINO_L2=y
++S:CONFIG_DRAM_CLK=480
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index d9e66b7..c8243a4 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -5,3 +5,6 @@
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_A20_OLINUXINO_L=y
++S:CONFIG_DRAM_CLK=480
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 1b9668d..ac94c79 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -2,9 +2,13 @@
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-micro.dtb"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+CONFIG_VIDEO_VGA=y
+S:CONFIG_MMC0_CD_PIN="PH1"
+S:CONFIG_MMC3_CD_PIN="PH11"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_A20_OLINUXINO_M=y
++S:CONFIG_DRAM_CLK=384
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/APC405_defconfig b/configs/APC405_defconfig
deleted file mode 100644
index d9da49b..0000000
--- a/configs/APC405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_APC405=y
diff --git a/configs/AR405_defconfig b/configs/AR405_defconfig
deleted file mode 100644
index be65ab7..0000000
--- a/configs/AR405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_AR405=y
diff --git a/configs/ASH405_defconfig b/configs/ASH405_defconfig
deleted file mode 100644
index ee094cb..0000000
--- a/configs/ASH405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_ASH405=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 196f682..d94e08e 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -5,3 +5,6 @@
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_BANANAPI=y
++S:CONFIG_DRAM_CLK=432
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
new file mode 100644
index 0000000..02e4f3e
--- /dev/null
+++ b/configs/Bananapro_defconfig
@@ -0,0 +1,12 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-bananapro.dtb"
+CONFIG_USB1_VBUS_PIN="PH0"
+CONFIG_USB2_VBUS_PIN="PH1"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_BANANAPRO=y
++S:CONFIG_DRAM_CLK=432
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
new file mode 100644
index 0000000..86751cf
--- /dev/null
+++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_C29XPCIE=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
new file mode 100644
index 0000000..d1a42b2
--- /dev/null
+++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_C29XPCIE=y
diff --git a/configs/CATcenter_25_defconfig b/configs/CATcenter_25_defconfig
deleted file mode 100644
index 1a8903c..0000000
--- a/configs/CATcenter_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CATCENTER=y
diff --git a/configs/CATcenter_33_defconfig b/configs/CATcenter_33_defconfig
deleted file mode 100644
index 4b0eb8d..0000000
--- a/configs/CATcenter_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CATCENTER=y
diff --git a/configs/CATcenter_defconfig b/configs/CATcenter_defconfig
deleted file mode 100644
index 53e00ad..0000000
--- a/configs/CATcenter_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CATCENTER=y
diff --git a/configs/CMS700_defconfig b/configs/CMS700_defconfig
deleted file mode 100644
index dd21223..0000000
--- a/configs/CMS700_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CMS700=y
diff --git a/configs/CPCI405AB_defconfig b/configs/CPCI405AB_defconfig
deleted file mode 100644
index 6550fd1..0000000
--- a/configs/CPCI405AB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CPCI405AB=y
diff --git a/configs/CPCI405DT_defconfig b/configs/CPCI405DT_defconfig
deleted file mode 100644
index b61f65c..0000000
--- a/configs/CPCI405DT_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CPCI405DT=y
diff --git a/configs/CPCI405_defconfig b/configs/CPCI405_defconfig
deleted file mode 100644
index 1638e2b..0000000
--- a/configs/CPCI405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CPCI405=y
diff --git a/configs/CPCIISER4_defconfig b/configs/CPCIISER4_defconfig
deleted file mode 100644
index 2a7566d..0000000
--- a/configs/CPCIISER4_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CPCIISER4=y
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
new file mode 100644
index 0000000..4040bee
--- /dev/null
+++ b/configs/CSQ_CS908_defconfig
@@ -0,0 +1,15 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
+CONFIG_FDTFILE="sun6i-a31s-cs908.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN6I=y
++S:CONFIG_DRAM_CLK=432
++S:CONFIG_DRAM_ZQ=123
+# Ethernet phy power
++S:CONFIG_AXP221_DLDO1_VOLT=3300
+# Wifi power
++S:CONFIG_AXP221_ALDO1_VOLT=3300
+# No Vbus gpio for either usb
++S:CONFIG_USB1_VBUS_PIN=""
++S:CONFIG_USB2_VBUS_PIN=""
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
new file mode 100644
index 0000000..680b631
--- /dev/null
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -0,0 +1,19 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+CONFIG_FDTFILE="sun4i-a10-chuwi-v7-cw0825.dtb"
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_VIDEO_LCD_SPI_CS="PA0"
+CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
+CONFIG_VIDEO_LCD_SPI_MOSI="PA2"
+CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_DRAM_CLK=408
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index de78a01..33edcc4 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -1,7 +1,12 @@
CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
-CONFIG_USB_KEYBOARD=n
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_TARGET_COLOMBUS=y
++S:CONFIG_DRAM_CLK=240
++S:CONFIG_DRAM_ZQ=251
+# Wifi power
++S:CONFIG_AXP221_ALDO1_VOLT=3300
+# No Vbus gpio for usb1
++S:CONFIG_USB1_VBUS_PIN=""
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 7e7a1ca..ef5b43a 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -5,3 +5,6 @@
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_CUBIEBOARD2=y
++S:CONFIG_DRAM_CLK=480
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index 0bc45fd..4efc6e1 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -4,4 +4,6 @@
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_TARGET_CUBIEBOARD=y
++S:CONFIG_DRAM_CLK=480
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=0
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index b1f9f93..f51c491 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -1,7 +1,11 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
+CONFIG_VIDEO_VGA=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_CUBIETRUCK=y
++S:CONFIG_DRAM_CLK=432
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/DP405_defconfig b/configs/DP405_defconfig
deleted file mode 100644
index 4d48276..0000000
--- a/configs/DP405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_DP405=y
diff --git a/configs/DU405_defconfig b/configs/DU405_defconfig
deleted file mode 100644
index fdfe41b..0000000
--- a/configs/DU405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_DU405=y
diff --git a/configs/DU440_defconfig b/configs/DU440_defconfig
deleted file mode 100644
index 59891fe..0000000
--- a/configs/DU440_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_DU440=y
diff --git a/configs/ELPPC_defconfig b/configs/ELPPC_defconfig
deleted file mode 100644
index c4694ef..0000000
--- a/configs/ELPPC_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_ELPPC=y
diff --git a/configs/G2000_defconfig b/configs/G2000_defconfig
deleted file mode 100644
index a01bc0f..0000000
--- a/configs/G2000_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_G2000=y
diff --git a/configs/HH405_defconfig b/configs/HH405_defconfig
deleted file mode 100644
index 1571f32..0000000
--- a/configs/HH405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_HH405=y
diff --git a/configs/HUB405_defconfig b/configs/HUB405_defconfig
deleted file mode 100644
index a39712e..0000000
--- a/configs/HUB405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_HUB405=y
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
new file mode 100644
index 0000000..0275463
--- /dev/null
+++ b/configs/Hummingbird_A31_defconfig
@@ -0,0 +1,16 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
+CONFIG_FDTFILE="sun6i-a31-hummingbird.dtb"
+CONFIG_VIDEO_VGA_VIA_LCD=y
+CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN6I=y
++S:CONFIG_DRAM_CLK=312
++S:CONFIG_DRAM_ZQ=251
+# Wifi power
++S:CONFIG_AXP221_ALDO1_VOLT=3300
+# Vbus gpio for usb1
++S:CONFIG_USB1_VBUS_PIN="PH24"
+# No Vbus gpio for usb2
++S:CONFIG_USB2_VBUS_PIN=""
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
new file mode 100644
index 0000000..60eb03e
--- /dev/null
+++ b/configs/Hyundai_A7HD_defconfig
@@ -0,0 +1,22 @@
+# The Hyundai A7HD is a 7" 16:9 A10 powered tablet featuring 1G RAM, 8G
+# nand, 1024x600 IPS screen, a mini hdmi port, mini usb receptacle and a
+# headphones port for details see: http://linux-sunxi.org/Hyundai_A7HD
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+CONFIG_FDTFILE="sun4i-a10-hyundai-a7hd.dtb"
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB0_VBUS_PIN="PB09"
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=1
+CONFIG_VIDEO_LCD_POWER="PH2"
+CONFIG_VIDEO_LCD_BL_EN="PH9"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW=n
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_DRAM_CLK=360
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig
new file mode 100644
index 0000000..192a461
--- /dev/null
+++ b/configs/Ippo_q8h_v1_2_defconfig
@@ -0,0 +1,20 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v1.2.dtb"
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB0_VBUS_PIN="axp_drivebus"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN8I=y
++S:CONFIG_DRAM_CLK=432
+# zq = 0xf74a
++S:CONFIG_DRAM_ZQ=63306
+# Wifi power
++S:CONFIG_AXP221_DLDO1_VOLT=3300
+# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP
++S:CONFIG_AXP221_ALDO1_VOLT=3000
diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig
index 50c2f93..c894948 100644
--- a/configs/Ippo_q8h_v5_defconfig
+++ b/configs/Ippo_q8h_v5_defconfig
@@ -1,8 +1,21 @@
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_ARM=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN8I=y
-CONFIG_TARGET_IPPO_Q8H_V5=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
-CONFIG_VIDEO=n
-CONFIG_USB_KEYBOARD=n
+CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v5.dtb"
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB0_VBUS_PIN="axp_drivebus"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN8I=y
++S:CONFIG_TARGET_IPPO_Q8H_V5=y
++S:CONFIG_DRAM_CLK=480
+# zq = 0xf777
++S:CONFIG_DRAM_ZQ=63351
+# Wifi power
++S:CONFIG_AXP221_DLDO1_VOLT=3300
+# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP
++S:CONFIG_AXP221_ALDO1_VOLT=3000
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index a26ff0a..64e01c8 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -5,3 +5,6 @@
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_PCDUINO3=y
++S:CONFIG_DRAM_CLK=480
++S:CONFIG_DRAM_ZQ=122
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig
index a33f3a7..49718c7 100644
--- a/configs/Linksprite_pcDuino3_fdt_defconfig
+++ b/configs/Linksprite_pcDuino3_fdt_defconfig
@@ -9,3 +9,6 @@
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_PCDUINO3=y
++S:CONFIG_DRAM_CLK=480
++S:CONFIG_DRAM_ZQ=122
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
new file mode 100644
index 0000000..1ba37bb
--- /dev/null
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -0,0 +1,9 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
+CONFIG_FDTFILE="sun4i-a10-pcduino.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_DRAM_CLK=408
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=0
diff --git a/configs/Lite5200_LOWBOOT08_defconfig b/configs/Lite5200_LOWBOOT08_defconfig
deleted file mode 100644
index 9f0cbd8..0000000
--- a/configs/Lite5200_LOWBOOT08_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/Lite5200_LOWBOOT_defconfig b/configs/Lite5200_LOWBOOT_defconfig
deleted file mode 100644
index ff1552f..0000000
--- a/configs/Lite5200_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/Lite5200_defconfig b/configs/Lite5200_defconfig
deleted file mode 100644
index 49fdb3b..0000000
--- a/configs/Lite5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/MPC8360EMDS_33_ATM_defconfig b/configs/MPC8360EMDS_33_ATM_defconfig
deleted file mode 100644
index dc325b1..0000000
--- a/configs/MPC8360EMDS_33_ATM_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_33_HOST_33_defconfig b/configs/MPC8360EMDS_33_HOST_33_defconfig
deleted file mode 100644
index fba273d..0000000
--- a/configs/MPC8360EMDS_33_HOST_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_33_HOST_66_defconfig b/configs/MPC8360EMDS_33_HOST_66_defconfig
deleted file mode 100644
index e0cf6da..0000000
--- a/configs/MPC8360EMDS_33_HOST_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_33_SLAVE_defconfig b/configs/MPC8360EMDS_33_SLAVE_defconfig
deleted file mode 100644
index c3f74fc..0000000
--- a/configs/MPC8360EMDS_33_SLAVE_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ,PCI,PCISLAVE"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_33_defconfig b/configs/MPC8360EMDS_33_defconfig
deleted file mode 100644
index 60c6ddb..0000000
--- a/configs/MPC8360EMDS_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_ATM_defconfig b/configs/MPC8360EMDS_66_ATM_defconfig
deleted file mode 100644
index 16f12fb..0000000
--- a/configs/MPC8360EMDS_66_ATM_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_HOST_33_defconfig b/configs/MPC8360EMDS_66_HOST_33_defconfig
deleted file mode 100644
index 797a584..0000000
--- a/configs/MPC8360EMDS_66_HOST_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_HOST_66_defconfig b/configs/MPC8360EMDS_66_HOST_66_defconfig
deleted file mode 100644
index a887c29..0000000
--- a/configs/MPC8360EMDS_66_HOST_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_SLAVE_defconfig b/configs/MPC8360EMDS_66_SLAVE_defconfig
deleted file mode 100644
index 4442c61..0000000
--- a/configs/MPC8360EMDS_66_SLAVE_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ,PCI,PCISLAVE"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360EMDS_66_defconfig b/configs/MPC8360EMDS_66_defconfig
deleted file mode 100644
index fce95dd..0000000
--- a/configs/MPC8360EMDS_66_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_66MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360EMDS=y
diff --git a/configs/MPC8360ERDK_33_defconfig b/configs/MPC8360ERDK_33_defconfig
deleted file mode 100644
index 91c47b7..0000000
--- a/configs/MPC8360ERDK_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="CLKIN_33MHZ"
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360ERDK=y
diff --git a/configs/MPC8360ERDK_defconfig b/configs/MPC8360ERDK_defconfig
deleted file mode 100644
index 7e9fa59..0000000
--- a/configs/MPC8360ERDK_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8360ERDK=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
new file mode 100644
index 0000000..6628184
--- /dev/null
+++ b/configs/MSI_Primo73_defconfig
@@ -0,0 +1,16 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+CONFIG_FDTFILE="sun7i-a20-primo73.dtb"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_USB_KEYBOARD=n
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_MSI_PRIMO73=y
++S:CONFIG_DRAM_CLK=384
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
new file mode 100644
index 0000000..6657ad6
--- /dev/null
+++ b/configs/MSI_Primo81_defconfig
@@ -0,0 +1,30 @@
+# The MSI Primo81 is an A31s based tablet, with 1G RAM, 16G NAND,
+# 1024x768 IPS LCD display, mono speaker, 0.3 MP front camera, 2.0 MP
+# rear camera, 3500 mAh battery, gt911 touchscreen, mma8452 accelerometer
+# and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons
+# (both volume buttons are also connected to the UBOOT_SEL pin). The
+# external connectors are represented by MicroSD slot, MiniHDMI, MicroUSB
+# OTG and 3.5mm headphone jack. More details are available at
+# http://linux-sunxi.org/MSI_Primo81
+
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS=""
+CONFIG_FDTFILE="sun6i-a31s-primo81.dtb"
+CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
+CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
+CONFIG_VIDEO_LCD_SSD2828_RESET="PA26"
+CONFIG_VIDEO_LCD_SPI_CS="PH9"
+CONFIG_VIDEO_LCD_SPI_SCLK="PH10"
+CONFIG_VIDEO_LCD_SPI_MOSI="PH11"
+CONFIG_VIDEO_LCD_SPI_MISO="PH12"
+CONFIG_VIDEO_LCD_BL_EN="PA25"
+CONFIG_VIDEO_LCD_BL_PWM="PH13"
+CONFIG_USB_KEYBOARD=n
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN6I=y
++S:CONFIG_DRAM_CLK=360
++S:CONFIG_DRAM_ZQ=122
+# Wifi power
++S:CONFIG_AXP221_DLDO1_VOLT=3300
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
new file mode 100644
index 0000000..653cb01
--- /dev/null
+++ b/configs/Marsboard_A10_defconfig
@@ -0,0 +1,9 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,USB_EHCI"
+CONFIG_FDTFILE="sun4i-a10-marsboard.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_DRAM_CLK=360
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=0
diff --git a/configs/Mele_A1000G_defconfig b/configs/Mele_A1000G_defconfig
deleted file mode 100644
index 2f4bf72..0000000
--- a/configs/Mele_A1000G_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_TARGET_MELE_A1000G=y
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index e2912b0..1a0a025 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -1,7 +1,10 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
+CONFIG_VIDEO_VGA=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_TARGET_MELE_A1000=y
++S:CONFIG_DRAM_CLK=360
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=0
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index fe9ba11..7f1710a 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -1,9 +1,13 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-m3.dtb"
+CONFIG_VIDEO_VGA=y
+S:CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+S:CONFIG_MMC0_CD_PIN="PH1"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_MELE_M3=y
++S:CONFIG_DRAM_CLK=384
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
new file mode 100644
index 0000000..2e1f80d
--- /dev/null
+++ b/configs/Mele_M5_defconfig
@@ -0,0 +1,13 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,USB_EHCI,STATUSLED=234"
+CONFIG_FDTFILE="sun7i-a20-m5.dtb"
+CONFIG_VIDEO_HDMI=y
++S:CONFIG_MMC0_CD_PIN="PH1"
++S:CONFIG_USB1_VBUS_PIN="PH6"
++S:CONFIG_USB2_VBUS_PIN="PH3"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_DRAM_CLK=432
++S:CONFIG_DRAM_ZQ=122
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index ac3cd36..eaf9a7e 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -4,16 +4,16 @@
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_TARGET_MELE_M9=y
++S:CONFIG_DRAM_CLK=312
++S:CONFIG_DRAM_ZQ=120
+# The Mele M9 uses 3.3V for general IO
++S:CONFIG_AXP221_DCDC1_VOLT=3300
# Ethernet phy power
+S:CONFIG_AXP221_DLDO1_VOLT=3300
# USB hub power
+S:CONFIG_AXP221_DLDO4_VOLT=3300
# Wifi power
+S:CONFIG_AXP221_ALDO1_VOLT=3300
-# HDMI power ?
-+S:CONFIG_AXP221_ALDO2_VOLT=1800
-+S:CONFIG_AXP221_ALDO3_VOLT=3000
# Vbus gpio for usb1
+S:CONFIG_USB1_VBUS_PIN="PC27"
# No Vbus gpio for usb2
diff --git a/configs/Mini-X-1Gb_defconfig b/configs/Mini-X-1Gb_defconfig
deleted file mode 100644
index b8fea01..0000000
--- a/configs/Mini-X-1Gb_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_TARGET_MINI_X_1GB=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 0f6bbe0..6aea777 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -4,4 +4,6 @@
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_TARGET_MINI_X=y
++S:CONFIG_DRAM_CLK=360
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=0
diff --git a/configs/OCRTC_defconfig b/configs/OCRTC_defconfig
deleted file mode 100644
index f2fd0c5..0000000
--- a/configs/OCRTC_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_OCRTC=y
diff --git a/configs/P1011RDB_36BIT_SDCARD_defconfig b/configs/P1011RDB_36BIT_SDCARD_defconfig
deleted file mode 100644
index 7205bef..0000000
--- a/configs/P1011RDB_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_36BIT_SPIFLASH_defconfig b/configs/P1011RDB_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index 8b3806e..0000000
--- a/configs/P1011RDB_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_36BIT_defconfig b/configs/P1011RDB_36BIT_defconfig
deleted file mode 100644
index c47f2e2..0000000
--- a/configs/P1011RDB_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_NAND_defconfig b/configs/P1011RDB_NAND_defconfig
deleted file mode 100644
index aac0190..0000000
--- a/configs/P1011RDB_NAND_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_SPL=y
-CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_SDCARD_defconfig b/configs/P1011RDB_SDCARD_defconfig
deleted file mode 100644
index 16e872f..0000000
--- a/configs/P1011RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_SPIFLASH_defconfig b/configs/P1011RDB_SPIFLASH_defconfig
deleted file mode 100644
index d14820f..0000000
--- a/configs/P1011RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1011RDB_defconfig b/configs/P1011RDB_defconfig
deleted file mode 100644
index d14868a..0000000
--- a/configs/P1011RDB_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P1011RDB"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_36BIT_SDCARD_defconfig b/configs/P1020RDB_36BIT_SDCARD_defconfig
deleted file mode 100644
index a18563e..0000000
--- a/configs/P1020RDB_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_36BIT_SPIFLASH_defconfig b/configs/P1020RDB_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index aa145fc..0000000
--- a/configs/P1020RDB_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_36BIT_defconfig b/configs/P1020RDB_36BIT_defconfig
deleted file mode 100644
index 844651f..0000000
--- a/configs/P1020RDB_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_NAND_defconfig b/configs/P1020RDB_NAND_defconfig
deleted file mode 100644
index 441241b..0000000
--- a/configs/P1020RDB_NAND_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_SPL=y
-CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_SDCARD_defconfig b/configs/P1020RDB_SDCARD_defconfig
deleted file mode 100644
index 1349bea..0000000
--- a/configs/P1020RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_SPIFLASH_defconfig b/configs/P1020RDB_SPIFLASH_defconfig
deleted file mode 100644
index 7eb8696..0000000
--- a/configs/P1020RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P1020RDB_defconfig b/configs/P1020RDB_defconfig
deleted file mode 100644
index fc58ac9..0000000
--- a/configs/P1020RDB_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P1020RDB"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_36BIT_SDCARD_defconfig b/configs/P2010RDB_36BIT_SDCARD_defconfig
deleted file mode 100644
index 1381e8e..0000000
--- a/configs/P2010RDB_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_36BIT_SPIFLASH_defconfig b/configs/P2010RDB_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index 53ebca1..0000000
--- a/configs/P2010RDB_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_36BIT_defconfig b/configs/P2010RDB_36BIT_defconfig
deleted file mode 100644
index de29dcb..0000000
--- a/configs/P2010RDB_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_NAND_defconfig b/configs/P2010RDB_NAND_defconfig
deleted file mode 100644
index bc91a67..0000000
--- a/configs/P2010RDB_NAND_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_SPL=y
-CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_SDCARD_defconfig b/configs/P2010RDB_SDCARD_defconfig
deleted file mode 100644
index fd4ade7..0000000
--- a/configs/P2010RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_SPIFLASH_defconfig b/configs/P2010RDB_SPIFLASH_defconfig
deleted file mode 100644
index 9631864..0000000
--- a/configs/P2010RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2010RDB_defconfig b/configs/P2010RDB_defconfig
deleted file mode 100644
index 3b3352a..0000000
--- a/configs/P2010RDB_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P2010RDB"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020COME_SDCARD_defconfig b/configs/P2020COME_SDCARD_defconfig
deleted file mode 100644
index c186fcb..0000000
--- a/configs/P2020COME_SDCARD_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020COME=y
diff --git a/configs/P2020COME_SPIFLASH_defconfig b/configs/P2020COME_SPIFLASH_defconfig
deleted file mode 100644
index 17ce136..0000000
--- a/configs/P2020COME_SPIFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020COME=y
diff --git a/configs/P2020DS_36BIT_defconfig b/configs/P2020DS_36BIT_defconfig
deleted file mode 100644
index 359c446..0000000
--- a/configs/P2020DS_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/configs/P2020DS_DDR2_defconfig b/configs/P2020DS_DDR2_defconfig
deleted file mode 100644
index 00b6731..0000000
--- a/configs/P2020DS_DDR2_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="DDR2"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/configs/P2020DS_SDCARD_defconfig b/configs/P2020DS_SDCARD_defconfig
deleted file mode 100644
index 89aef3a..0000000
--- a/configs/P2020DS_SDCARD_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/configs/P2020DS_SPIFLASH_defconfig b/configs/P2020DS_SPIFLASH_defconfig
deleted file mode 100644
index 503328c..0000000
--- a/configs/P2020DS_SPIFLASH_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/configs/P2020DS_defconfig b/configs/P2020DS_defconfig
deleted file mode 100644
index f2ac6d9..0000000
--- a/configs/P2020DS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2020DS=y
diff --git a/configs/P2020RDB_36BIT_SDCARD_defconfig b/configs/P2020RDB_36BIT_SDCARD_defconfig
deleted file mode 100644
index 43cc2e3..0000000
--- a/configs/P2020RDB_36BIT_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_36BIT_SPIFLASH_defconfig b/configs/P2020RDB_36BIT_SPIFLASH_defconfig
deleted file mode 100644
index f1199b6..0000000
--- a/configs/P2020RDB_36BIT_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_36BIT_defconfig b/configs/P2020RDB_36BIT_defconfig
deleted file mode 100644
index 87490fd..0000000
--- a/configs/P2020RDB_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_NAND_defconfig b/configs/P2020RDB_NAND_defconfig
deleted file mode 100644
index 70ee084..0000000
--- a/configs/P2020RDB_NAND_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_SPL=y
-CONFIG_TPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_SDCARD_defconfig b/configs/P2020RDB_SDCARD_defconfig
deleted file mode 100644
index 2bf5773..0000000
--- a/configs/P2020RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_SPIFLASH_defconfig b/configs/P2020RDB_SPIFLASH_defconfig
deleted file mode 100644
index 290ebd2..0000000
--- a/configs/P2020RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P2020RDB_defconfig b/configs/P2020RDB_defconfig
deleted file mode 100644
index cc39735..0000000
--- a/configs/P2020RDB_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P1_P2_RDB=y
diff --git a/configs/P3G4_defconfig b/configs/P3G4_defconfig
deleted file mode 100644
index 3d219ef..0000000
--- a/configs/P3G4_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_P3G4=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..8e21ca5
--- /dev/null
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P5040DS=y
diff --git a/configs/PCI405_defconfig b/configs/PCI405_defconfig
deleted file mode 100644
index 48f19fe..0000000
--- a/configs/PCI405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PCI405=y
diff --git a/configs/PM520_DDR_defconfig b/configs/PM520_DDR_defconfig
deleted file mode 100644
index 6d6a59d..0000000
--- a/configs/PM520_DDR_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PM520=y
diff --git a/configs/PM520_ROMBOOT_DDR_defconfig b/configs/PM520_ROMBOOT_DDR_defconfig
deleted file mode 100644
index f5a40d9..0000000
--- a/configs/PM520_ROMBOOT_DDR_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,BOOT_ROM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PM520=y
diff --git a/configs/PM520_ROMBOOT_defconfig b/configs/PM520_ROMBOOT_defconfig
deleted file mode 100644
index d9f9ea0..0000000
--- a/configs/PM520_ROMBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ROM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PM520=y
diff --git a/configs/PM520_defconfig b/configs/PM520_defconfig
deleted file mode 100644
index 2737a8c..0000000
--- a/configs/PM520_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PM520=y
diff --git a/configs/PMC405_defconfig b/configs/PMC405_defconfig
deleted file mode 100644
index d82117c..0000000
--- a/configs/PMC405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PMC405=y
diff --git a/configs/PPChameleonEVB_BA_25_defconfig b/configs/PPChameleonEVB_BA_25_defconfig
deleted file mode 100644
index e367299..0000000
--- a/configs/PPChameleonEVB_BA_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_BA_33_defconfig b/configs/PPChameleonEVB_BA_33_defconfig
deleted file mode 100644
index f4041c9..0000000
--- a/configs/PPChameleonEVB_BA_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_HI_25_defconfig b/configs/PPChameleonEVB_HI_25_defconfig
deleted file mode 100644
index a9de221..0000000
--- a/configs/PPChameleonEVB_HI_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_HI_33_defconfig b/configs/PPChameleonEVB_HI_33_defconfig
deleted file mode 100644
index 882262b..0000000
--- a/configs/PPChameleonEVB_HI_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_ME_25_defconfig b/configs/PPChameleonEVB_ME_25_defconfig
deleted file mode 100644
index f9a0440..0000000
--- a/configs/PPChameleonEVB_ME_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_ME_33_defconfig b/configs/PPChameleonEVB_ME_33_defconfig
deleted file mode 100644
index 8ee09b8..0000000
--- a/configs/PPChameleonEVB_ME_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_defconfig b/configs/PPChameleonEVB_defconfig
deleted file mode 100644
index 2d83330..0000000
--- a/configs/PPChameleonEVB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
new file mode 100644
index 0000000..94a76ba
--- /dev/null
+++ b/configs/T1024QDS_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..c8dd5c2
--- /dev/null
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
diff --git a/configs/TASREG_defconfig b/configs/TASREG_defconfig
deleted file mode 100644
index 2bb0421..0000000
--- a/configs/TASREG_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_M68K=y
-CONFIG_TARGET_TASREG=y
diff --git a/configs/Total5200_Rev2_defconfig b/configs/Total5200_Rev2_defconfig
deleted file mode 100644
index 9f27734..0000000
--- a/configs/Total5200_Rev2_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=2"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOTAL5200=y
diff --git a/configs/Total5200_Rev2_lowboot_defconfig b/configs/Total5200_Rev2_lowboot_defconfig
deleted file mode 100644
index 15b27b3..0000000
--- a/configs/Total5200_Rev2_lowboot_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOTAL5200=y
diff --git a/configs/Total5200_defconfig b/configs/Total5200_defconfig
deleted file mode 100644
index 5aaae49..0000000
--- a/configs/Total5200_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=1"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOTAL5200=y
diff --git a/configs/Total5200_lowboot_defconfig b/configs/Total5200_lowboot_defconfig
deleted file mode 100644
index 4c9195e..0000000
--- a/configs/Total5200_lowboot_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_TOTAL5200=y
diff --git a/configs/VOH405_defconfig b/configs/VOH405_defconfig
deleted file mode 100644
index 1fbe91a..0000000
--- a/configs/VOH405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_VOH405=y
diff --git a/configs/WUH405_defconfig b/configs/WUH405_defconfig
deleted file mode 100644
index dadea20..0000000
--- a/configs/WUH405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_WUH405=y
diff --git a/configs/ZUMA_defconfig b/configs/ZUMA_defconfig
deleted file mode 100644
index 536f8bb..0000000
--- a/configs/ZUMA_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_ZUMA=y
diff --git a/configs/arcangel4-be_defconfig b/configs/arcangel4-be_defconfig
index 867fb1f..0c3ab4e 100644
--- a/configs/arcangel4-be_defconfig
+++ b/configs/arcangel4-be_defconfig
@@ -1,2 +1,3 @@
CONFIG_ARC=y
CONFIG_TARGET_ARCANGEL4_BE=y
+CONFIG_SYS_CLK_FREQ=70000000
diff --git a/configs/arcangel4_defconfig b/configs/arcangel4_defconfig
index 82b583e..a63ef21 100644
--- a/configs/arcangel4_defconfig
+++ b/configs/arcangel4_defconfig
@@ -1,2 +1,3 @@
CONFIG_ARC=y
CONFIG_TARGET_ARCANGEL4=y
+CONFIG_SYS_CLK_FREQ=70000000
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index bfa314e..5c0ca11 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -1,2 +1,3 @@
CONFIG_ARC=y
CONFIG_TARGET_AXS101=y
+CONFIG_SYS_CLK_FREQ=750000000
\ No newline at end of file
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index 6ca7c57..400906d 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -1,8 +1,10 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb"
-CONFIG_USB1_VBUS_PIN="PH12"
+CONFIG_USB2_VBUS_PIN="PH12"
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_TARGET_BA10_TV_BOX=y
++S:CONFIG_DRAM_CLK=384
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index b83803e..e956835 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -6,5 +6,6 @@
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_HAVE_MRC=y
CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_VIDEO_X86=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 6249db7..3cc034a 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -2,4 +2,3 @@
CONFIG_X86=y
CONFIG_TARGET_COREBOOT=y
CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="link"
diff --git a/configs/cpci5200_defconfig b/configs/cpci5200_defconfig
deleted file mode 100644
index bdbf4fc..0000000
--- a/configs/cpci5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_CPCI5200=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 5f5037e..65791b7 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -5,3 +5,6 @@
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN7I=y
+S:CONFIG_TARGET_I12_TVBOX=y
++S:CONFIG_DRAM_CLK=384
++S:CONFIG_DRAM_ZQ=127
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/icecube_5200_DDR_LOWBOOT08_defconfig b/configs/icecube_5200_DDR_LOWBOOT08_defconfig
deleted file mode 100644
index 79f8598..0000000
--- a/configs/icecube_5200_DDR_LOWBOOT08_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000,MPC5200_DDR"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_DDR_LOWBOOT_defconfig b/configs/icecube_5200_DDR_LOWBOOT_defconfig
deleted file mode 100644
index 79f8598..0000000
--- a/configs/icecube_5200_DDR_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000,MPC5200_DDR"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_DDR_defconfig b/configs/icecube_5200_DDR_defconfig
deleted file mode 100644
index 19d9637..0000000
--- a/configs/icecube_5200_DDR_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_LOWBOOT08_defconfig b/configs/icecube_5200_LOWBOOT08_defconfig
deleted file mode 100644
index 9f0cbd8..0000000
--- a/configs/icecube_5200_LOWBOOT08_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF800000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_LOWBOOT_defconfig b/configs/icecube_5200_LOWBOOT_defconfig
deleted file mode 100644
index ff1552f..0000000
--- a/configs/icecube_5200_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/icecube_5200_defconfig b/configs/icecube_5200_defconfig
deleted file mode 100644
index 49fdb3b..0000000
--- a/configs/icecube_5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/lite5200b_LOWBOOT_defconfig b/configs/lite5200b_LOWBOOT_defconfig
deleted file mode 100644
index 9ceb834..0000000
--- a/configs/lite5200b_LOWBOOT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/lite5200b_PM_defconfig b/configs/lite5200b_PM_defconfig
deleted file mode 100644
index 35b2aa3..0000000
--- a/configs/lite5200b_PM_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,LITE5200B,LITE5200B_PM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/lite5200b_defconfig b/configs/lite5200b_defconfig
deleted file mode 100644
index c7d4030..0000000
--- a/configs/lite5200b_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MPC5200_DDR,LITE5200B"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_ICECUBE=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
new file mode 100644
index 0000000..29335ee
--- /dev/null
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
new file mode 100644
index 0000000..bdab6d9
--- /dev/null
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021ATWR=y
diff --git a/configs/mecp5200_defconfig b/configs/mecp5200_defconfig
deleted file mode 100644
index a30e224..0000000
--- a/configs/mecp5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MECP5200=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
new file mode 100644
index 0000000..086e1e4
--- /dev/null
+++ b/configs/mk802_a10s_defconfig
@@ -0,0 +1,11 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
+CONFIG_FDTFILE="sun5i-a10s-mk802.dtb"
+CONFIG_USB1_VBUS_PIN="PB10"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_MK802_A10S=y
++S:CONFIG_DRAM_CLK=432
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=0
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
new file mode 100644
index 0000000..d6b51a5
--- /dev/null
+++ b/configs/mk802_defconfig
@@ -0,0 +1,10 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
+CONFIG_FDTFILE="sun4i-a10-mk802.dtb"
+CONFIG_USB2_VBUS_PIN="PH12"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_DRAM_CLK=360
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=0
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
new file mode 100644
index 0000000..500f4df
--- /dev/null
+++ b/configs/mk802ii_defconfig
@@ -0,0 +1,9 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
+CONFIG_FDTFILE="sun4i-a10-mk802ii.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_DRAM_CLK=360
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=0
diff --git a/configs/mpc7448hpc2_defconfig b/configs/mpc7448hpc2_defconfig
deleted file mode 100644
index f2777dc..0000000
--- a/configs/mpc7448hpc2_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_MPC7448HPC2=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
new file mode 100644
index 0000000..5a79c51
--- /dev/null
+++ b/configs/nas220_defconfig
@@ -0,0 +1,3 @@
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_TARGET_NAS220=y
diff --git a/configs/pf5200_defconfig b/configs/pf5200_defconfig
deleted file mode 100644
index fe926a0..0000000
--- a/configs/pf5200_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_PF5200=y
diff --git a/configs/ppmc7xx_defconfig b/configs/ppmc7xx_defconfig
deleted file mode 100644
index feefe49..0000000
--- a/configs/ppmc7xx_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_74xx_7xx=y
-CONFIG_TARGET_PPMC7XX=y
diff --git a/configs/qt840a_defconfig b/configs/qt840a_defconfig
deleted file mode 100644
index 70f8159..0000000
--- a/configs/qt840a_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_TARGET_QT840A=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
new file mode 100644
index 0000000..a85db2a
--- /dev/null
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -0,0 +1,20 @@
+# Gemei G9 is an A10 based tablet, with 1G RAM, 16G NAND,
+# 1024x768 IPS LCD display, stereo speakers, 1.3MP front camera and 5 MP
+# rear camera, 8000mAh battery, GT901 2+1 touchscreen, Bosch BMA250
+# accelerometer and RTL8188CUS USB wifi. It also has MicroSD slot, MiniHDMI,
+# 1 x MicroUSB OTG port and 1 x MicroUSB host port and 3.5mm headphone jack.
+# More details are available at: http://linux-sunxi.org/Gemei_G9
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
+CONFIG_FDTFILE="sun4i-gemei-g9.dtb"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_DRAM_CLK=432
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=4
diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig
index 9669dc0..d2de03b 100644
--- a/configs/tb100_defconfig
+++ b/configs/tb100_defconfig
@@ -1,2 +1,3 @@
CONFIG_ARC=y
CONFIG_TARGET_TB100=y
+CONFIG_SYS_CLK_FREQ=500000000
\ No newline at end of file
diff --git a/doc/README.arm-caches b/doc/README.arm-caches
index f6a52e3..dbb6190 100644
--- a/doc/README.arm-caches
+++ b/doc/README.arm-caches
@@ -47,7 +47,7 @@
- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and
disable MMU and caches.
- The following sequence is advisable while disabling d-cache:
- 1. disable_dcache() - flushes and disables d-cache
+ 1. dcache_disable() - flushes and disables d-cache
2. invalidate_dcache_all() - invalid any entry that came to the cache
in the short period after the cache was flushed but before the
cache got disabled.
diff --git a/doc/README.nand b/doc/README.nand
index e29188f..dee0e00 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -304,6 +304,11 @@
Thus BCH16 can be supported on 4K page NAND.
+ CONFIG_NAND_OMAP_GPMC_PREFETCH
+ On OMAP platforms that use the GPMC controller
+ (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
+ uses the prefetch mode to speed up read operations.
+
NOTE:
=====
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 5d2875c..952ab87 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,54 +12,96 @@
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-A3000 powerpc mpc824x - -
-CPC45 powerpc mpc824x - - Josef Wagner <Wagner@Microsys.de>
-CU824 powerpc mpc824x - - Wolfgang Denk <wd@denx.de>
-eXalion powerpc mpc824x - - Torsten Demke <torsten.demke@fci.com>
-MVBLUE powerpc mpc824x - -
-MUSENKI powerpc mpc824x - - Jim Thompson <jim@musenki.com>
-Sandpoint8240 powerpc mpc824x - - Wolfgang Denk <wd@denx.de>
-Sandpoint8245 powerpc mpc824x - - Jim Thompson <jim@musenki.com>
-utx8245 powerpc mpc824x - - Greg Allen <gallen@arlut.utexas.edu>
-atc powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
-CPU86 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
-CPU87 powerpc mpc8260 - -
-ep82xxm powerpc mpc8260 - -
-gw8260 powerpc mpc8260 - - Oliver Brown <obrown@adventnetworks.com>
-IPHASE4539 powerpc mpc8260 - - Wolfgang Grandegger <wg@denx.de>
-muas3001 powerpc mpc8260 - - Heiko Schocher <hs@denx.de>
-PM825 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
-PM826 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de>
-PM828 powerpc mpc8260 - -
-MPC8266ADS powerpc mpc8260 - - Rune Torgersen <runet@innovsys.com>
-VoVPN-GW powerpc mpc8260 - -
-ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com>
-ppmc8260 powerpc mpc8260 - - Brad Kemp <Brad.Kemp@seranoa.com>
-sacsng powerpc mpc8260 - - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
-cogent_mpc8260 powerpc mpc8260 - - Murray Jensen <Murray.Jensen@csiro.au>
-cogent_8xx powerpc mpc8xx - - Murray Jensen <Murray.Jensen@csiro.au>
-ESTEEM192E powerpc mpc8xx - - Conn Clark <clark@esteem.com>
-IP860 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-IVML24 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-IVMS8 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-lwmon powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-NETVIA powerpc mpc8xx - - Pantelis Antoniou <panto@intracom.gr>
-R360MPI powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-RRvision powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-SPD823TS powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-KUP4K powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
-KUP4X powerpc mpc8xx - - Klaus Heydeck <heydeck@kieback-peter.de>
-ELPT860 powerpc mpc8xx - - The LEOX team <team@leox.org>
-hmi1001 powerpc mpc5xxx - -
-mucmc52 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
-uc101 powerpc mpc5xxx - - Heiko Schocher <hs@denx.de>
-uc100 powerpc mpc8xx - - Stefan Roese <sr@denx.de>
-FPS850L powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-FPS860L powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-NSCU powerpc mpc8xx - -
-SM850 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
-TK885D powerpc mpc8xx - -
-virtlab2 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
+icecube_5200 powerpc mpc5xxx - - Wolfgang Denk <wd@denx.de>
+Lite5200 powerpc mpc5xxx - -
+cpci5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+mecp5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+pf5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+PM520 powerpc mpc5xxx - - Josef Wagner <Wagner@Microsys.de>
+Total5200 powerpc mpc5xxx - -
+CATcenter powerpc ppc4xx - -
+PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+P2020DS powerpc mpc85xx - -
+P2020COME powerpc mpc85xx - - Ira W. Snyder <iws@ovro.caltech.edu>
+P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com>
+P2010RDB powerpc mpc85xx - -
+P1020RDB powerpc mpc85xx - -
+P1011RDB powerpc mpc85xx - -
+MPC8360EMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
+MPC8360ERDK powerpc mpc83xx - - Anton Vorontsov <avorontsov@ru.mvista.com>
+P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk <wd@denx.de>
+ZUMA powerpc 74xx_7xx d928664f 2015-01-16 Nye Liu <nyet@zumanetworks.com>
+ppmc7xx powerpc 74xx_7xx d928664f 2015-01-16
+ELPPC powerpc 74xx_7xx d928664f 2015-01-16
+mpc7448hpc2 powerpc 74xx_7xx d928664f 2015-01-16 Roy Zang <tie-fei.zang@freescale.com>
+CPCI405 ppc4xx 405gp 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+CPCI405DT ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+CPCI405AB ppc4xx 405gpr 5f1459dc 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+G2000 ppc4xx 405ep 5f8f6294 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+WUH405 ppc4xx 405ep fc88a5bf 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+VOH405 ppc4xx 405ep 807db88b 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+PMC405 ppc4xx 405gp d5263304 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+PCI405 ppc4xx 405gp dbe7bb0d 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+OCRTC ppc4xx 405gpr cc6e715f 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+HUB405 ppc4xx 405ep e434d5d7 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+HH405 ppc4xx 405ep 843125da 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+DU440 ppc4xx 440epx 7ac9d47a 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+DU405 ppc4xx 405gpr bc114076 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+DP405 ppc4xx 405ep 9a4018e0 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+CPCIISER4 ppc4xx 405gp 37057260 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+CMS700 ppc4xx 405ep 2404124c 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+ASH405 ppc4xx 405ep b5e7c84f 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+AR405 ppc4xx 405gpr 61b57c4a 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+APC405 ppc4xx 405gpr 2b8a04e5 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+TASREG m68k mcf52x2 cbdc662a 2015-01-13 Matthias Fuchs <matthias.fuchs@esd.eu>
+A3000 powerpc mpc824x d622ac39 2015-01-05
+CPC45 powerpc mpc824x d622ac39 2015-01-05 Josef Wagner <Wagner@Microsys.de>
+CU824 powerpc mpc824x d622ac39 2015-01-05 Wolfgang Denk <wd@denx.de>
+eXalion powerpc mpc824x d622ac39 2015-01-05 Torsten Demke <torsten.demke@fci.com>
+MVBLUE powerpc mpc824x d622ac39 2015-01-05
+MUSENKI powerpc mpc824x d622ac39 2015-01-05 Jim Thompson <jim@musenki.com>
+Sandpoint8240 powerpc mpc824x d622ac39 2015-01-05 Wolfgang Denk <wd@denx.de>
+Sandpoint8245 powerpc mpc824x d622ac39 2015-01-05 Jim Thompson <jim@musenki.com>
+utx8245 powerpc mpc824x d622ac39 2015-01-05 Greg Allen <gallen@arlut.utexas.edu>
+atc powerpc mpc8260 9067b300 2015-01-05 Wolfgang Denk <wd@denx.de>
+CPU86 powerpc mpc8260 f7e1af86 2015-01-05 Wolfgang Denk <wd@denx.de>
+CPU87 powerpc mpc8260 f7e1af86 2015-01-05
+ep82xxm powerpc mpc8260 e2b19629 2015-01-05
+gw8260 powerpc mpc8260 8eecbaf3 2015-01-05 Oliver Brown <obrown@adventnetworks.com>
+IPHASE4539 powerpc mpc8260 87882f57 2015-01-05 Wolfgang Grandegger <wg@denx.de>
+muas3001 powerpc mpc8260 d2fd1d66 2015-01-05 Heiko Schocher <hs@denx.de>
+PM825 powerpc mpc8260 dc0b2fb4 2015-01-05 Wolfgang Denk <wd@denx.de>
+PM826 powerpc mpc8260 dc0b2fb4 2015-01-05 Wolfgang Denk <wd@denx.de>
+PM828 powerpc mpc8260 dc0b2fb4 2015-01-05
+MPC8266ADS powerpc mpc8260 b3a2bbe1 2015-01-05 Rune Torgersen <runet@innovsys.com>
+VoVPN-GW powerpc mpc8260 cc90905f 2015-01-05
+ep8260 powerpc mpc8260 4ad015ba 2015-01-05 Frank Panno <fpanno@delphintech.com>
+ppmc8260 powerpc mpc8260 793116d2 2015-01-05 Brad Kemp <Brad.Kemp@seranoa.com>
+sacsng powerpc mpc8260 b35c0ad6 2015-01-05 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+cogent_mpc8260 powerpc mpc8260 d19f6a60 2015-01-05 Murray Jensen <Murray.Jensen@csiro.au>
+cogent_8xx powerpc mpc8xx d19f6a60 2015-01-05 Murray Jensen <Murray.Jensen@csiro.au>
+ESTEEM192E powerpc mpc8xx af0e3514 2015-01-05 Conn Clark <clark@esteem.com>
+IP860 powerpc mpc8xx 5ec71100 2015-01-05 Wolfgang Denk <wd@denx.de>
+IVML24 powerpc mpc8xx ca620cd1 2015-01-05 Wolfgang Denk <wd@denx.de>
+IVMS8 powerpc mpc8xx ca620cd1 2015-01-05 Wolfgang Denk <wd@denx.de>
+lwmon powerpc mpc8xx acc2372d 2015-01-05 Wolfgang Denk <wd@denx.de>
+NETVIA powerpc mpc8xx f017cd7f 2015-01-05 Pantelis Antoniou <panto@intracom.gr>
+R360MPI powerpc mpc8xx 79cbecb8 2015-01-05 Wolfgang Denk <wd@denx.de>
+RRvision powerpc mpc8xx 8737fc75 2015-01-05 Wolfgang Denk <wd@denx.de>
+SPD823TS powerpc mpc8xx 72ba368f 2015-01-05 Wolfgang Denk <wd@denx.de>
+KUP4K powerpc mpc8xx 4317d070 2015-01-05 Klaus Heydeck <heydeck@kieback-peter.de>
+KUP4X powerpc mpc8xx 4317d070 2015-01-05 Klaus Heydeck <heydeck@kieback-peter.de>
+ELPT860 powerpc mpc8xx 3c5b20f1 2015-01-05 The LEOX team <team@leox.org>
+hmi1001 powerpc mpc5xxx ceaf499b 2015-01-05
+mucmc52 powerpc mpc5xxx ceaf499b 2015-01-05 Heiko Schocher <hs@denx.de>
+uc101 powerpc mpc5xxx ceaf499b 2015-01-05 Heiko Schocher <hs@denx.de>
+uc100 powerpc mpc8xx ceaf499b 2015-01-05 Stefan Roese <sr@denx.de>
+FPS850L powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk <wd@denx.de>
+FPS860L powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk <wd@denx.de>
+NSCU powerpc mpc8xx 5d2a5ef7 2015-01-05
+SM850 powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk <wd@denx.de>
+TK885D powerpc mpc8xx 5d2a5ef7 2015-01-05
+virtlab2 powerpc mpc8xx 5d2a5ef7 2015-01-05 Wolfgang Denk <wd@denx.de>
hermes powerpc mpc8xx 36da51e 2014-12-08 Wolfgang Denk <wd@denx.de>
PRS200 powerpc mpc5200 ecfdcee 2014-11-12
MCC200 powerpc mpc5200 ecfdcee 2014-11-12
diff --git a/doc/README.t1040-l2switch b/doc/README.t1040-l2switch
new file mode 100644
index 0000000..14dbf31
--- /dev/null
+++ b/doc/README.t1040-l2switch
@@ -0,0 +1,48 @@
+This file contains information for VSC9953, a Vitesse L2 Switch IP
+which is integrated in the T1040/T1020 Freescale SoCs.
+
+About Device:
+=============
+VSC9953 is an 8-port Gigabit Ethernet switch supports the following features:
+ - 8192 MAC addresses
+ - Static Address provisioning
+ - Dynamic learning of MAC addresses and aging
+ - 4096 VLANs
+ - Independent and shared VLAN learning (IVL, SVL)
+ - Policing with storm control and MC/BC protection
+ - IPv4 and IPv6 multicast
+ - Jumbo frames (9.6 KB)
+ - Access Control List
+ - VLAN editing, translation and remarking
+ - RMON counters per port
+
+Switch interfaces:
+ - 8 Gigabit switch ports (ports 0 to 7) are external and are connected to external PHYs
+ - 2 switch ports (ports 8 and 9) of 2.5 G are connected (fixed links)
+ to FMan ports (FM1@DTSEC1 and FM1@DTSEC2)
+
+Commands Overview:
+=============
+Commands supported
+ - enable/disable a port
+ - check a port's link speed, duplexity and status.
+
+Commands syntax
+ ethsw port <port_nr> enable|disable - enable/disable an l2 switch port
+ ethsw port <port_nr> show - show an l2 switch port's configuration
+
+ port_nr=0..9; use "all" for all ports
+
+=> ethsw port all show
+ Port Status Link Speed Duplex
+ 0 enabled down 10 half
+ 1 enabled down 10 half
+ 2 enabled down 10 half
+ 3 enabled up 1000 full
+ 4 disabled down - half
+ 5 disabled down - half
+ 6 disabled down - half
+ 7 disabled down - half
+ 8 enabled up 2500 full
+ 9 enabled up 2500 full
+=>
diff --git a/doc/README.video b/doc/README.video
index dadbfcd..d0a3ad6 100644
--- a/doc/README.video
+++ b/doc/README.video
@@ -5,15 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-U-Boot MPC8xx video controller driver
-======================================
-
-The driver has been tested with the following configurations:
-
-- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it
-
"video-mode" environment variable
-===============================
+=================================
The 'video-mode' environment variable can be used to enable and configure
some video drivers. The format matches the video= command-line option used
@@ -28,4 +21,50 @@
<freq> The frequency (in Hz) to use.
<options> A comma-separated list of device-specific options
+
+U-Boot MPC8xx video controller driver
+=====================================
+
+The driver has been tested with the following configurations:
+
+- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it
+
Example: video-mode=fslfb:1280x1024-32@60,monitor=dvi
+
+
+U-boot sunxi video controller driver
+====================================
+
+U-boot supports hdmi and lcd output on Allwinner sunxi SoCs, lcd output
+requires the CONFIG_VIDEO_LCD_MODE Kconfig value to be set.
+
+The sunxi u-boot driver supports the following video-mode options:
+
+- monitor=[none|dvi|hdmi|lcd] - Select the video output to use
+ none: Disable video output.
+ dvi/hdmi: Selects output over the hdmi connector with dvi resp. hdmi output
+ format, if edid is used the format is automatically selected.
+ lcd: Selects video output to a LCD screen.
+ vga: Selects bideo output over the VGA connector.
+ Defaults to monitor=dvi.
+
+- hpd=[0|1] - Enable use of the hdmi HotPlug Detect feature
+ 0: Disabled. Configure dvi/hdmi output even if no cable is detected
+ 1: Enabled. Fallback to the lcd / vga / none in that order (if available)
+ Defaults to hpd=1.
+
+- hpd_delay=<int> - How long to wait for the hdmi HPD signal in milliseconds
+ When the monitor and the board power up at the same time, it may take some
+ time for the monitor to assert the HPD signal. This configures how long to
+ wait for the HPD signal before assuming no cable is connected.
+ Defaults to hpd_delay=500.
+
+- edid=[0|1] - Enable use of DDC + EDID to get monitor info
+ 0: Disabled.
+ 1: Enabled. If valid EDID info was read from the monitor the EDID info will
+ overrides the xres, yres and refresh from the video-mode env. variable.
+ Defaults to edid=1.
+
+For example to always use the hdmi connector, even if no cable is inserted,
+using edid info when available and otherwise initalizing it at 1024x768@60Hz,
+use: "setenv video-mode sunxi:1024x768-24@60,monitor=dvi,hpd=0,edid=1".
diff --git a/doc/README.x86 b/doc/README.x86
index 5fab044..7df8cc5 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -32,6 +32,21 @@
$ make coreboot-x86_defconfig
$ make all
+Note this default configuration will build a U-Boot payload for the Link board.
+To build a coreboot payload against another board, you can change the build
+configuration during the 'make menuconfig' process.
+
+x86 architecture --->
+ ...
+ (chromebook_link) Board configuration file
+ (chromebook_link) Board Device Tree Source (dts) file
+ (0x19200000) Board specific Cache-As-RAM (CAR) address
+ (0x4000) Board specific Cache-As-RAM (CAR) size
+
+Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
+to point to a new board. You can also change the Cache-As-RAM (CAR) related
+settings here if the default values do not fit your new board.
+
Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
little bit tricky, as generally it requires several binary blobs which are not
shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
@@ -88,11 +103,31 @@
Rename the first one to fsp.bin and second one to cmc.bin and put them in the
board directory.
-Now you can build U-Boot and obtaim u-boot.rom
+Now you can build U-Boot and obtain u-boot.rom
$ make crownbay_defconfig
$ make all
+Test with coreboot
+------------------
+For testing U-Boot as the coreboot payload, there are things that need be paid
+attention to. coreboot supports loading an ELF executable and a 32-bit plain
+binary, as well as other supported payloads. With the default configuration,
+U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
+generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
+provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
+this capability yet. The command is as follows:
+
+# in the coreboot root directory
+$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
+ -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
+
+Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
+symbol address of _start (in arch/x86/cpu/start.S).
+
+If you want to use ELF as the coreboot payload, change U-Boot configuration to
+use CONFIG_OF_EMBED.
+
CPU Microcode
-------------
Modern CPU usually requires a special bit stream called microcode [5] to be
@@ -106,13 +141,29 @@
Device Tree
-----------
x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
-be turned on. Not every device on the board is configured via devie tree, but
+be turned on. Not every device on the board is configured via device tree, but
more and more devices will be added as time goes by. Check out the directory
arch/x86/dts/ for these device tree source files.
+Useful Commands
+---------------
+
+In keeping with the U-Boot philosophy of providing functions to check and
+adjust internal settings, there are several x86-specific commands that may be
+useful:
+
+hob - Display information about Firmware Support Package (FSP) Hand-off
+ Block. This is only available on platforms which use FSP, mostly
+ Atom.
+iod - Display I/O memory
+iow - Write I/O memory
+mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
+ tell the CPU whether memory is cacheable and if so the cache write
+ mode to use. U-Boot sets up some reasonable values but you can
+ adjust then with this command.
+
TODO List
---------
-- MTRR support (for performance)
- Audio
- Chrome OS verified boot
- SMI and ACPI support, to provide platform info and facilities to Linux
diff --git a/doc/git-mailrc b/doc/git-mailrc
index d90793a..8ba599c 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -98,8 +98,6 @@
alias mpc85xx uboot, afleming, galak
alias mpc86xx uboot, afleming, galak
alias ppc4xx uboot, stroese
-alias ppc7xx uboot, wd
-alias ppc74xx uboot, wd
alias sandbox sjg
alias sb sandbox
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index cb13d2e..067d0a9 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -6,5 +6,6 @@
# Version 2 as published by the Free Software Foundation.
#
+obj-y += sec.o
obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c
new file mode 100644
index 0000000..443ee96
--- /dev/null
+++ b/drivers/crypto/fsl/sec.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#if CONFIG_SYS_FSL_SEC_COMPAT == 2 || CONFIG_SYS_FSL_SEC_COMPAT >= 4
+#include <fsl_sec.h>
+#endif
+
+/*
+ * update crypto node properties to a specified revision of the SEC
+ * called with sec_rev == 0 if not on an E processor
+ */
+#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
+void fdt_fixup_crypto_node(void *blob, int sec_rev)
+{
+ static const struct sec_rev_prop {
+ u32 sec_rev;
+ u32 num_channels;
+ u32 channel_fifo_len;
+ u32 exec_units_mask;
+ u32 descriptor_types_mask;
+ } sec_rev_prop_list[] = {
+ { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
+ { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
+ { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
+ { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
+ { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
+ { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
+ { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
+ };
+ static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
+ sizeof("fsl,secX.Y")];
+ int crypto_node, sec_idx, err;
+ char *p;
+ u32 val;
+
+ /* locate crypto node based on lowest common compatible */
+ crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
+ if (crypto_node == -FDT_ERR_NOTFOUND)
+ return;
+
+ /* delete it if not on an E-processor */
+ if (crypto_node > 0 && !sec_rev) {
+ fdt_del_node(blob, crypto_node);
+ return;
+ }
+
+ /* else we got called for possible uprev */
+ for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
+ if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
+ break;
+
+ if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
+ puts("warning: unknown SEC revision number\n");
+ return;
+ }
+
+ val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
+ err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+
+ val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
+ err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask",
+ &val, 4);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+
+ val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
+ err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+
+ val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
+ err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+
+ val = 0;
+ while (sec_idx >= 0) {
+ p = compat_strlist + val;
+ val += sprintf(p, "fsl,sec%d.%d",
+ (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
+ sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
+ sec_idx--;
+ }
+ err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist,
+ val);
+ if (err < 0)
+ printf("WARNING: could not set crypto property: %s\n",
+ fdt_strerror(err));
+}
+#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
+static u8 caam_get_era(void)
+{
+ static const struct {
+ u16 ip_id;
+ u8 maj_rev;
+ u8 era;
+ } caam_eras[] = {
+ {0x0A10, 1, 1},
+ {0x0A10, 2, 2},
+ {0x0A12, 1, 3},
+ {0x0A14, 1, 3},
+ {0x0A14, 2, 4},
+ {0x0A16, 1, 4},
+ {0x0A10, 3, 4},
+ {0x0A11, 1, 4},
+ {0x0A18, 1, 4},
+ {0x0A11, 2, 5},
+ {0x0A12, 2, 5},
+ {0x0A13, 1, 5},
+ {0x0A1C, 1, 5}
+ };
+
+ ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ u32 secvid_ms = sec_in32(&sec->secvid_ms);
+ u32 ccbvid = sec_in32(&sec->ccbvid);
+ u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
+ SEC_SECVID_MS_IPID_SHIFT;
+ u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
+ SEC_SECVID_MS_MAJ_REV_SHIFT;
+ u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT;
+
+ int i;
+
+ if (era) /* This is '0' prior to CAAM ERA-6 */
+ return era;
+
+ for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
+ if (caam_eras[i].ip_id == ip_id &&
+ caam_eras[i].maj_rev == maj_rev)
+ return caam_eras[i].era;
+
+ return 0;
+}
+
+static void fdt_fixup_crypto_era(void *blob, u32 era)
+{
+ int err;
+ int crypto_node;
+
+ crypto_node = fdt_path_offset(blob, "crypto");
+ if (crypto_node < 0) {
+ printf("WARNING: Missing crypto node\n");
+ return;
+ }
+
+ err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
+ sizeof(era));
+ if (err < 0) {
+ printf("ERROR: could not set fsl,sec-era property: %s\n",
+ fdt_strerror(err));
+ }
+}
+
+void fdt_fixup_crypto_node(void *blob, int sec_rev)
+{
+ u8 era;
+
+ if (!sec_rev) {
+ fdt_del_node_and_alias(blob, "crypto");
+ return;
+ }
+
+ /* Add SEC ERA information in compatible */
+ era = caam_get_era();
+ if (era) {
+ fdt_fixup_crypto_era(blob, era);
+ } else {
+ printf("WARNING: Unable to get ERA for CAAM rev: %d\n",
+ sec_rev);
+ }
+}
+#endif
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index a3c01e7..4eef047 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -171,6 +171,14 @@
ddr_out32(&ddr->debug[i], regs->debug[i]);
}
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+ /* Erratum applies when accumulated ECC is used, or DBI is enabled */
+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
+ if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+ IS_DBI(regs->ddr_sdram_cfg_3))
+ ddr_setbits32(ddr->debug[28], 0x9 << 20);
+#endif
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 37946d5..d94eb5c 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -38,7 +38,7 @@
/* fpga_get_desc
* map a device number to a descriptor
*/
-static const fpga_desc *const fpga_get_desc(int devnum)
+const fpga_desc *const fpga_get_desc(int devnum)
{
fpga_desc *desc = (fpga_desc *)NULL;
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index adb4b8c..c765a74 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -139,6 +139,11 @@
return FPGA_FAIL;
}
+ if (!desc->operations || !desc->operations->load) {
+ printf("%s: Missing load operation\n", __func__);
+ return FPGA_FAIL;
+ }
+
return desc->operations->load(desc, buf, bsize, bstype);
}
@@ -151,8 +156,10 @@
return FPGA_FAIL;
}
- if (!desc->operations->loadfs)
+ if (!desc->operations || !desc->operations->loadfs) {
+ printf("%s: Missing loadfs operation\n", __func__);
return FPGA_FAIL;
+ }
return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
}
@@ -165,6 +172,11 @@
return FPGA_FAIL;
}
+ if (!desc->operations || !desc->operations->dump) {
+ printf("%s: Missing dump operation\n", __func__);
+ return FPGA_FAIL;
+ }
+
return desc->operations->dump(desc, buf, bsize);
}
@@ -226,12 +238,14 @@
if (desc->name)
printf("Device name: \t%s\n", desc->name);
- if (desc->iface_fns) {
+ if (desc->iface_fns)
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
- desc->operations->info(desc);
- } else
+ else
printf ("No Device Function Table.\n");
+ if (desc->operations && desc->operations->info)
+ desc->operations->info(desc);
+
ret_val = FPGA_SUCCESS;
} else {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 44135e5..6296092 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -18,6 +18,9 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -73,13 +76,22 @@
int gpio_direction_input(unsigned gpio)
{
+#ifdef AXP_GPIO
+ if (gpio >= SUNXI_GPIO_AXP0_START)
+ return axp_gpio_direction_input(gpio - SUNXI_GPIO_AXP0_START);
+#endif
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
- return sunxi_gpio_input(gpio);
+ return 0;
}
int gpio_direction_output(unsigned gpio, int value)
{
+#ifdef AXP_GPIO
+ if (gpio >= SUNXI_GPIO_AXP0_START)
+ return axp_gpio_direction_output(gpio - SUNXI_GPIO_AXP0_START,
+ value);
+#endif
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
return sunxi_gpio_output(gpio, value);
@@ -87,11 +99,19 @@
int gpio_get_value(unsigned gpio)
{
+#ifdef AXP_GPIO
+ if (gpio >= SUNXI_GPIO_AXP0_START)
+ return axp_gpio_get_value(gpio - SUNXI_GPIO_AXP0_START);
+#endif
return sunxi_gpio_input(gpio);
}
int gpio_set_value(unsigned gpio, int value)
{
+#ifdef AXP_GPIO
+ if (gpio >= SUNXI_GPIO_AXP0_START)
+ return axp_gpio_set_value(gpio - SUNXI_GPIO_AXP0_START, value);
+#endif
return sunxi_gpio_output(gpio, value);
}
@@ -101,6 +121,16 @@
int groupsize = 9 * 32;
long pin;
char *eptr;
+
+#ifdef AXP_GPIO
+ if (strncasecmp(name, "AXP0-", 5) == 0) {
+ name += 5;
+ pin = simple_strtol(name, &eptr, 10);
+ if (!*name || *eptr)
+ return -1;
+ return SUNXI_GPIO_AXP0_START + pin;
+ }
+#endif
if (*name == 'P' || *name == 'p')
name++;
if (*name >= 'A') {
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index e69de29..7ba85a2 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -0,0 +1,9 @@
+menu "MMC Host controller Support"
+
+config SH_SDHI
+ bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
+ depends on RMOBILE
+ help
+ Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
+
+endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 461d7d8..4ba5878 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -30,6 +30,7 @@
obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
obj-$(CONFIG_SDHCI) += sdhci.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1eb9c27..b8039cd 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -486,7 +486,7 @@
char cardtype;
int err;
- mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ mmc->card_caps = 0;
if (mmc_host_is_spi(mmc))
return 0;
@@ -495,6 +495,8 @@
if (mmc->version < MMC_VERSION_4)
return 0;
+ mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
+
err = mmc_send_ext_csd(mmc, ext_csd);
if (err)
@@ -605,6 +607,200 @@
return ret;
}
+int mmc_hwpart_config(struct mmc *mmc,
+ const struct mmc_hwpart_conf *conf,
+ enum mmc_hwpart_conf_mode mode)
+{
+ u8 part_attrs = 0;
+ u32 enh_size_mult;
+ u32 enh_start_addr;
+ u32 gp_size_mult[4];
+ u32 max_enh_size_mult;
+ u32 tot_enh_size_mult = 0;
+ u8 wr_rel_set;
+ int i, pidx, err;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+
+ if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
+ return -EINVAL;
+
+ if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
+ printf("eMMC >= 4.4 required for enhanced user data area\n");
+ return -EMEDIUMTYPE;
+ }
+
+ if (!(mmc->part_support & PART_SUPPORT)) {
+ printf("Card does not support partitioning\n");
+ return -EMEDIUMTYPE;
+ }
+
+ if (!mmc->hc_wp_grp_size) {
+ printf("Card does not define HC WP group size\n");
+ return -EMEDIUMTYPE;
+ }
+
+ /* check partition alignment and total enhanced size */
+ if (conf->user.enh_size) {
+ if (conf->user.enh_size % mmc->hc_wp_grp_size ||
+ conf->user.enh_start % mmc->hc_wp_grp_size) {
+ printf("User data enhanced area not HC WP group "
+ "size aligned\n");
+ return -EINVAL;
+ }
+ part_attrs |= EXT_CSD_ENH_USR;
+ enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
+ if (mmc->high_capacity) {
+ enh_start_addr = conf->user.enh_start;
+ } else {
+ enh_start_addr = (conf->user.enh_start << 9);
+ }
+ } else {
+ enh_size_mult = 0;
+ enh_start_addr = 0;
+ }
+ tot_enh_size_mult += enh_size_mult;
+
+ for (pidx = 0; pidx < 4; pidx++) {
+ if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
+ printf("GP%i partition not HC WP group size "
+ "aligned\n", pidx+1);
+ return -EINVAL;
+ }
+ gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
+ if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
+ part_attrs |= EXT_CSD_ENH_GP(pidx);
+ tot_enh_size_mult += gp_size_mult[pidx];
+ }
+ }
+
+ if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
+ printf("Card does not support enhanced attribute\n");
+ return -EMEDIUMTYPE;
+ }
+
+ err = mmc_send_ext_csd(mmc, ext_csd);
+ if (err)
+ return err;
+
+ max_enh_size_mult =
+ (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
+ (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
+ ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
+ if (tot_enh_size_mult > max_enh_size_mult) {
+ printf("Total enhanced size exceeds maximum (%u > %u)\n",
+ tot_enh_size_mult, max_enh_size_mult);
+ return -EMEDIUMTYPE;
+ }
+
+ /* The default value of EXT_CSD_WR_REL_SET is device
+ * dependent, the values can only be changed if the
+ * EXT_CSD_HS_CTRL_REL bit is set. The values can be
+ * changed only once and before partitioning is completed. */
+ wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
+ if (conf->user.wr_rel_change) {
+ if (conf->user.wr_rel_set)
+ wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
+ else
+ wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
+ }
+ for (pidx = 0; pidx < 4; pidx++) {
+ if (conf->gp_part[pidx].wr_rel_change) {
+ if (conf->gp_part[pidx].wr_rel_set)
+ wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
+ else
+ wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
+ }
+ }
+
+ if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
+ !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
+ puts("Card does not support host controlled partition write "
+ "reliability settings\n");
+ return -EMEDIUMTYPE;
+ }
+
+ if (ext_csd[EXT_CSD_PARTITION_SETTING] &
+ EXT_CSD_PARTITION_SETTING_COMPLETED) {
+ printf("Card already partitioned\n");
+ return -EPERM;
+ }
+
+ if (mode == MMC_HWPART_CONF_CHECK)
+ return 0;
+
+ /* Partitioning requires high-capacity size definitions */
+ if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_ERASE_GROUP_DEF, 1);
+
+ if (err)
+ return err;
+
+ ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
+
+ /* update erase group size to be high-capacity */
+ mmc->erase_grp_size =
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
+
+ }
+
+ /* all OK, write the configuration */
+ for (i = 0; i < 4; i++) {
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_ENH_START_ADDR+i,
+ (enh_start_addr >> (i*8)) & 0xFF);
+ if (err)
+ return err;
+ }
+ for (i = 0; i < 3; i++) {
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_ENH_SIZE_MULT+i,
+ (enh_size_mult >> (i*8)) & 0xFF);
+ if (err)
+ return err;
+ }
+ for (pidx = 0; pidx < 4; pidx++) {
+ for (i = 0; i < 3; i++) {
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_GP_SIZE_MULT+pidx*3+i,
+ (gp_size_mult[pidx] >> (i*8)) & 0xFF);
+ if (err)
+ return err;
+ }
+ }
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
+ if (err)
+ return err;
+
+ if (mode == MMC_HWPART_CONF_SET)
+ return 0;
+
+ /* The WR_REL_SET is a write-once register but shall be
+ * written before setting PART_SETTING_COMPLETED. As it is
+ * write-once we can only write it when completing the
+ * partitioning. */
+ if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_WR_REL_SET, wr_rel_set);
+ if (err)
+ return err;
+ }
+
+ /* Setting PART_SETTING_COMPLETED confirms the partition
+ * configuration but it only becomes effective after power
+ * cycle, so we do not adjust the partition related settings
+ * in the mmc struct. */
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_PARTITION_SETTING,
+ EXT_CSD_PARTITION_SETTING_COMPLETED);
+ if (err)
+ return err;
+
+ return 0;
+}
+
int mmc_getcd(struct mmc *mmc)
{
int cd;
@@ -818,6 +1014,8 @@
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
int timeout = 1000;
+ bool has_parts = false;
+ bool part_completed;
#ifdef CONFIG_MMC_SPI_CRC_ON
if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
@@ -970,7 +1168,9 @@
if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
/* check ext_csd version and capacity */
err = mmc_send_ext_csd(mmc, ext_csd);
- if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
+ if (err)
+ return err;
+ if (ext_csd[EXT_CSD_REV] >= 2) {
/*
* According to the JEDEC Standard, the value of
* ext_csd's capacity is valid if the value is more
@@ -1006,13 +1206,70 @@
break;
}
+ /* The partition data may be non-zero but it is only
+ * effective if PARTITION_SETTING_COMPLETED is set in
+ * EXT_CSD, so ignore any data if this bit is not set,
+ * except for enabling the high-capacity group size
+ * definition (see below). */
+ part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
+ EXT_CSD_PARTITION_SETTING_COMPLETED);
+
+ /* store the partition info of emmc */
+ mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
+ if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
+ ext_csd[EXT_CSD_BOOT_MULT])
+ mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
+ if (part_completed &&
+ (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
+ mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
+
+ mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
+
+ mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
+
+ for (i = 0; i < 4; i++) {
+ int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
+ uint mult = (ext_csd[idx + 2] << 16) +
+ (ext_csd[idx + 1] << 8) + ext_csd[idx];
+ if (mult)
+ has_parts = true;
+ if (!part_completed)
+ continue;
+ mmc->capacity_gp[i] = mult;
+ mmc->capacity_gp[i] *=
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
+ mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+ mmc->capacity_gp[i] <<= 19;
+ }
+
+ if (part_completed) {
+ mmc->enh_user_size =
+ (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
+ (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
+ ext_csd[EXT_CSD_ENH_SIZE_MULT];
+ mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
+ mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+ mmc->enh_user_size <<= 19;
+ mmc->enh_user_start =
+ (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
+ (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
+ (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
+ ext_csd[EXT_CSD_ENH_START_ADDR];
+ if (mmc->high_capacity)
+ mmc->enh_user_start <<= 9;
+ }
+
/*
* Host needs to enable ERASE_GRP_DEF bit if device is
* partitioned. This bit will be lost every time after a reset
* or power off. This will affect erase size.
*/
+ if (part_completed)
+ has_parts = true;
if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
- (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) {
+ (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
+ has_parts = true;
+ if (has_parts) {
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
EXT_CSD_ERASE_GROUP_DEF, 1);
@@ -1020,19 +1277,18 @@
return err;
else
ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
+ }
+ if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
/* Read out group size from ext_csd */
mmc->erase_grp_size =
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
- MMC_MAX_BLOCK_LEN * 1024;
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
/*
* if high capacity and partition setting completed
* SEC_COUNT is valid even if it is smaller than 2 GiB
* JEDEC Standard JESD84-B45, 6.2.4
*/
- if (mmc->high_capacity &&
- (ext_csd[EXT_CSD_PARTITION_SETTING] &
- EXT_CSD_PARTITION_SETTING_COMPLETED)) {
+ if (mmc->high_capacity && part_completed) {
capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
(ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
(ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
@@ -1049,23 +1305,11 @@
* (erase_gmul + 1);
}
- /* store the partition info of emmc */
- if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
- ext_csd[EXT_CSD_BOOT_MULT])
- mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
+ mmc->hc_wp_grp_size = 1024
+ * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
+ * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
- mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
-
- mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
-
- for (i = 0; i < 4; i++) {
- int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
- mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) +
- (ext_csd[idx + 1] << 8) + ext_csd[idx];
- mmc->capacity_gp[i] *=
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
- mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
- }
+ mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
}
err = mmc_set_capacity(mmc, mmc->part_num);
@@ -1107,7 +1351,8 @@
mmc->tran_speed = 50000000;
else
mmc->tran_speed = 25000000;
- } else {
+ } else if (mmc->version >= MMC_VERSION_4) {
+ /* Only version 4 of MMC supports wider bus widths */
int idx;
/* An array of possible bus widths in order of preference */
@@ -1139,6 +1384,18 @@
unsigned int caps = ext_to_hostcaps[extw];
/*
+ * If the bus width is still not changed,
+ * don't try to set the default again.
+ * Otherwise, recover from switch attempts
+ * by switching to 1-bit bus width.
+ */
+ if (extw == EXT_CSD_BUS_WIDTH_1 &&
+ mmc->bus_width == 1) {
+ err = 0;
+ break;
+ }
+
+ /*
* Check to make sure the card and controller support
* these capabilities
*/
diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c
new file mode 100644
index 0000000..cc62c89
--- /dev/null
+++ b/drivers/mmc/sh_sdhi.c
@@ -0,0 +1,695 @@
+/*
+ * drivers/mmc/sh_sdhi.c
+ *
+ * SD/MMC driver for Renesas rmobile ARM SoCs.
+ *
+ * Copyright (C) 2011,2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2008-2009 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/sh_sdhi.h>
+
+#define DRIVER_NAME "sh-sdhi"
+
+struct sh_sdhi_host {
+ unsigned long addr;
+ int ch;
+ int bus_shift;
+ unsigned long quirks;
+ unsigned char wait_int;
+ unsigned char sd_error;
+ unsigned char detect_waiting;
+};
+static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val)
+{
+ writew(val, host->addr + (reg << host->bus_shift));
+}
+
+static inline u16 sh_sdhi_readw(struct sh_sdhi_host *host, int reg)
+{
+ return readw(host->addr + (reg << host->bus_shift));
+}
+
+static void *mmc_priv(struct mmc *mmc)
+{
+ return (void *)mmc->priv;
+}
+
+static void sh_sdhi_detect(struct sh_sdhi_host *host)
+{
+ sh_sdhi_writew(host, SDHI_OPTION,
+ OPT_BUS_WIDTH_1 | sh_sdhi_readw(host, SDHI_OPTION));
+
+ host->detect_waiting = 0;
+}
+
+static int sh_sdhi_intr(void *dev_id)
+{
+ struct sh_sdhi_host *host = dev_id;
+ int state1 = 0, state2 = 0;
+
+ state1 = sh_sdhi_readw(host, SDHI_INFO1);
+ state2 = sh_sdhi_readw(host, SDHI_INFO2);
+
+ debug("%s: state1 = %x, state2 = %x\n", __func__, state1, state2);
+
+ /* CARD Insert */
+ if (state1 & INFO1_CARD_IN) {
+ sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_IN);
+ if (!host->detect_waiting) {
+ host->detect_waiting = 1;
+ sh_sdhi_detect(host);
+ }
+ sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
+ INFO1M_ACCESS_END | INFO1M_CARD_IN |
+ INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
+ return -EAGAIN;
+ }
+ /* CARD Removal */
+ if (state1 & INFO1_CARD_RE) {
+ sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_RE);
+ if (!host->detect_waiting) {
+ host->detect_waiting = 1;
+ sh_sdhi_detect(host);
+ }
+ sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
+ INFO1M_ACCESS_END | INFO1M_CARD_RE |
+ INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
+ sh_sdhi_writew(host, SDHI_SDIO_INFO1_MASK, SDIO_INFO1M_ON);
+ sh_sdhi_writew(host, SDHI_SDIO_MODE, SDIO_MODE_OFF);
+ return -EAGAIN;
+ }
+
+ if (state2 & INFO2_ALL_ERR) {
+ sh_sdhi_writew(host, SDHI_INFO2,
+ (unsigned short)~(INFO2_ALL_ERR));
+ sh_sdhi_writew(host, SDHI_INFO2_MASK,
+ INFO2M_ALL_ERR |
+ sh_sdhi_readw(host, SDHI_INFO2_MASK));
+ host->sd_error = 1;
+ host->wait_int = 1;
+ return 0;
+ }
+ /* Respons End */
+ if (state1 & INFO1_RESP_END) {
+ sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END);
+ sh_sdhi_writew(host, SDHI_INFO1_MASK,
+ INFO1M_RESP_END |
+ sh_sdhi_readw(host, SDHI_INFO1_MASK));
+ host->wait_int = 1;
+ return 0;
+ }
+ /* SD_BUF Read Enable */
+ if (state2 & INFO2_BRE_ENABLE) {
+ sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BRE_ENABLE);
+ sh_sdhi_writew(host, SDHI_INFO2_MASK,
+ INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ |
+ sh_sdhi_readw(host, SDHI_INFO2_MASK));
+ host->wait_int = 1;
+ return 0;
+ }
+ /* SD_BUF Write Enable */
+ if (state2 & INFO2_BWE_ENABLE) {
+ sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BWE_ENABLE);
+ sh_sdhi_writew(host, SDHI_INFO2_MASK,
+ INFO2_BWE_ENABLE | INFO2M_BUF_ILL_WRITE |
+ sh_sdhi_readw(host, SDHI_INFO2_MASK));
+ host->wait_int = 1;
+ return 0;
+ }
+ /* Access End */
+ if (state1 & INFO1_ACCESS_END) {
+ sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_ACCESS_END);
+ sh_sdhi_writew(host, SDHI_INFO1_MASK,
+ INFO1_ACCESS_END |
+ sh_sdhi_readw(host, SDHI_INFO1_MASK));
+ host->wait_int = 1;
+ return 0;
+ }
+ return -EAGAIN;
+}
+
+static int sh_sdhi_wait_interrupt_flag(struct sh_sdhi_host *host)
+{
+ int timeout = 10000000;
+
+ while (1) {
+ timeout--;
+ if (timeout < 0) {
+ debug(DRIVER_NAME": %s timeout\n", __func__);
+ return 0;
+ }
+
+ if (!sh_sdhi_intr(host))
+ break;
+
+ udelay(1); /* 1 usec */
+ }
+
+ return 1; /* Return value: NOT 0 = complete waiting */
+}
+
+static int sh_sdhi_clock_control(struct sh_sdhi_host *host, unsigned long clk)
+{
+ u32 clkdiv, i, timeout;
+
+ if (sh_sdhi_readw(host, SDHI_INFO2) & (1 << 14)) {
+ printf(DRIVER_NAME": Busy state ! Cannot change the clock\n");
+ return -EBUSY;
+ }
+
+ sh_sdhi_writew(host, SDHI_CLK_CTRL,
+ ~CLK_ENABLE & sh_sdhi_readw(host, SDHI_CLK_CTRL));
+
+ if (clk == 0)
+ return -EIO;
+
+ clkdiv = 0x80;
+ i = CONFIG_SH_SDHI_FREQ >> (0x8 + 1);
+ for (; clkdiv && clk >= (i << 1); (clkdiv >>= 1))
+ i <<= 1;
+
+ sh_sdhi_writew(host, SDHI_CLK_CTRL, clkdiv);
+
+ timeout = 100000;
+ /* Waiting for SD Bus busy to be cleared */
+ while (timeout--) {
+ if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000))
+ break;
+ }
+
+ if (timeout)
+ sh_sdhi_writew(host, SDHI_CLK_CTRL,
+ CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL));
+ else
+ return -EBUSY;
+
+ return 0;
+}
+
+static int sh_sdhi_sync_reset(struct sh_sdhi_host *host)
+{
+ u32 timeout;
+ sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_ON);
+ sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_OFF);
+ sh_sdhi_writew(host, SDHI_CLK_CTRL,
+ CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL));
+
+ timeout = 100000;
+ while (timeout--) {
+ if (!(sh_sdhi_readw(host, SDHI_INFO2) & INFO2_CBUSY))
+ break;
+ udelay(100);
+ }
+
+ if (!timeout)
+ return -EBUSY;
+
+ if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
+ sh_sdhi_writew(host, SDHI_HOST_MODE, 1);
+
+ return 0;
+}
+
+static int sh_sdhi_error_manage(struct sh_sdhi_host *host)
+{
+ unsigned short e_state1, e_state2;
+ int ret;
+
+ host->sd_error = 0;
+ host->wait_int = 0;
+
+ e_state1 = sh_sdhi_readw(host, SDHI_ERR_STS1);
+ e_state2 = sh_sdhi_readw(host, SDHI_ERR_STS2);
+ if (e_state2 & ERR_STS2_SYS_ERROR) {
+ if (e_state2 & ERR_STS2_RES_STOP_TIMEOUT)
+ ret = TIMEOUT;
+ else
+ ret = -EILSEQ;
+ debug("%s: ERR_STS2 = %04x\n",
+ DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS2));
+ sh_sdhi_sync_reset(host);
+
+ sh_sdhi_writew(host, SDHI_INFO1_MASK,
+ INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
+ return ret;
+ }
+ if (e_state1 & ERR_STS1_CRC_ERROR || e_state1 & ERR_STS1_CMD_ERROR)
+ ret = -EILSEQ;
+ else
+ ret = TIMEOUT;
+
+ debug("%s: ERR_STS1 = %04x\n",
+ DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS1));
+ sh_sdhi_sync_reset(host);
+ sh_sdhi_writew(host, SDHI_INFO1_MASK,
+ INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
+ return ret;
+}
+
+static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data)
+{
+ long time;
+ unsigned short blocksize, i;
+ unsigned short *p = (unsigned short *)data->dest;
+
+ if ((unsigned long)p & 0x00000001) {
+ debug(DRIVER_NAME": %s: The data pointer is unaligned.",
+ __func__);
+ return -EIO;
+ }
+
+ host->wait_int = 0;
+ sh_sdhi_writew(host, SDHI_INFO2_MASK,
+ ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) &
+ sh_sdhi_readw(host, SDHI_INFO2_MASK));
+ sh_sdhi_writew(host, SDHI_INFO1_MASK,
+ ~INFO1M_ACCESS_END &
+ sh_sdhi_readw(host, SDHI_INFO1_MASK));
+ time = sh_sdhi_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_sdhi_error_manage(host);
+
+ host->wait_int = 0;
+ blocksize = sh_sdhi_readw(host, SDHI_SIZE);
+ for (i = 0; i < blocksize / 2; i++)
+ *p++ = sh_sdhi_readw(host, SDHI_BUF0);
+
+ time = sh_sdhi_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_sdhi_error_manage(host);
+
+ host->wait_int = 0;
+ return 0;
+}
+
+static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data)
+{
+ long time;
+ unsigned short blocksize, i, sec;
+ unsigned short *p = (unsigned short *)data->dest;
+
+ if ((unsigned long)p & 0x00000001) {
+ debug(DRIVER_NAME": %s: The data pointer is unaligned.",
+ __func__);
+ return -EIO;
+ }
+
+ debug("%s: blocks = %d, blocksize = %d\n",
+ __func__, data->blocks, data->blocksize);
+
+ host->wait_int = 0;
+ for (sec = 0; sec < data->blocks; sec++) {
+ sh_sdhi_writew(host, SDHI_INFO2_MASK,
+ ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) &
+ sh_sdhi_readw(host, SDHI_INFO2_MASK));
+
+ time = sh_sdhi_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_sdhi_error_manage(host);
+
+ host->wait_int = 0;
+ blocksize = sh_sdhi_readw(host, SDHI_SIZE);
+ for (i = 0; i < blocksize / 2; i++)
+ *p++ = sh_sdhi_readw(host, SDHI_BUF0);
+ }
+
+ return 0;
+}
+
+static int sh_sdhi_single_write(struct sh_sdhi_host *host,
+ struct mmc_data *data)
+{
+ long time;
+ unsigned short blocksize, i;
+ const unsigned short *p = (const unsigned short *)data->src;
+
+ if ((unsigned long)p & 0x00000001) {
+ debug(DRIVER_NAME": %s: The data pointer is unaligned.",
+ __func__);
+ return -EIO;
+ }
+
+ debug("%s: blocks = %d, blocksize = %d\n",
+ __func__, data->blocks, data->blocksize);
+
+ host->wait_int = 0;
+ sh_sdhi_writew(host, SDHI_INFO2_MASK,
+ ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) &
+ sh_sdhi_readw(host, SDHI_INFO2_MASK));
+ sh_sdhi_writew(host, SDHI_INFO1_MASK,
+ ~INFO1M_ACCESS_END &
+ sh_sdhi_readw(host, SDHI_INFO1_MASK));
+
+ time = sh_sdhi_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_sdhi_error_manage(host);
+
+ host->wait_int = 0;
+ blocksize = sh_sdhi_readw(host, SDHI_SIZE);
+ for (i = 0; i < blocksize / 2; i++)
+ sh_sdhi_writew(host, SDHI_BUF0, *p++);
+
+ time = sh_sdhi_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_sdhi_error_manage(host);
+
+ host->wait_int = 0;
+ return 0;
+}
+
+static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data)
+{
+ long time;
+ unsigned short i, sec, blocksize;
+ const unsigned short *p = (const unsigned short *)data->src;
+
+ debug("%s: blocks = %d, blocksize = %d\n",
+ __func__, data->blocks, data->blocksize);
+
+ host->wait_int = 0;
+ for (sec = 0; sec < data->blocks; sec++) {
+ sh_sdhi_writew(host, SDHI_INFO2_MASK,
+ ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) &
+ sh_sdhi_readw(host, SDHI_INFO2_MASK));
+
+ time = sh_sdhi_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_sdhi_error_manage(host);
+
+ host->wait_int = 0;
+ blocksize = sh_sdhi_readw(host, SDHI_SIZE);
+ for (i = 0; i < blocksize / 2; i++)
+ sh_sdhi_writew(host, SDHI_BUF0, *p++);
+ }
+
+ return 0;
+}
+
+static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
+{
+ unsigned short i, j, cnt = 1;
+ unsigned short resp[8];
+ unsigned long *p1, *p2;
+
+ if (cmd->resp_type & MMC_RSP_136) {
+ cnt = 4;
+ resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
+ resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
+ resp[2] = sh_sdhi_readw(host, SDHI_RSP02);
+ resp[3] = sh_sdhi_readw(host, SDHI_RSP03);
+ resp[4] = sh_sdhi_readw(host, SDHI_RSP04);
+ resp[5] = sh_sdhi_readw(host, SDHI_RSP05);
+ resp[6] = sh_sdhi_readw(host, SDHI_RSP06);
+ resp[7] = sh_sdhi_readw(host, SDHI_RSP07);
+
+ /* SDHI REGISTER SPECIFICATION */
+ for (i = 7, j = 6; i > 0; i--) {
+ resp[i] = (resp[i] << 8) & 0xff00;
+ resp[i] |= (resp[j--] >> 8) & 0x00ff;
+ }
+ resp[0] = (resp[0] << 8) & 0xff00;
+
+ /* SDHI REGISTER SPECIFICATION */
+ p1 = ((unsigned long *)resp) + 3;
+
+ } else {
+ resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
+ resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
+
+ p1 = ((unsigned long *)resp);
+ }
+
+ p2 = (unsigned long *)cmd->response;
+#if defined(__BIG_ENDIAN_BITFIELD)
+ for (i = 0; i < cnt; i++) {
+ *p2++ = ((*p1 >> 16) & 0x0000ffff) |
+ ((*p1 << 16) & 0xffff0000);
+ p1--;
+ }
+#else
+ for (i = 0; i < cnt; i++)
+ *p2++ = *p1--;
+#endif /* __BIG_ENDIAN_BITFIELD */
+}
+
+static unsigned short sh_sdhi_set_cmd(struct sh_sdhi_host *host,
+ struct mmc_data *data, unsigned short opc)
+{
+ switch (opc) {
+ case SD_CMD_APP_SEND_OP_COND:
+ case SD_CMD_APP_SEND_SCR:
+ opc |= SDHI_APP;
+ break;
+ case SD_CMD_APP_SET_BUS_WIDTH:
+ /* SD_APP_SET_BUS_WIDTH*/
+ if (!data)
+ opc |= SDHI_APP;
+ else /* SD_SWITCH */
+ opc = SDHI_SD_SWITCH;
+ break;
+ default:
+ break;
+ }
+ return opc;
+}
+
+static unsigned short sh_sdhi_data_trans(struct sh_sdhi_host *host,
+ struct mmc_data *data, unsigned short opc)
+{
+ unsigned short ret;
+
+ switch (opc) {
+ case MMC_CMD_READ_MULTIPLE_BLOCK:
+ ret = sh_sdhi_multi_read(host, data);
+ break;
+ case MMC_CMD_WRITE_MULTIPLE_BLOCK:
+ ret = sh_sdhi_multi_write(host, data);
+ break;
+ case MMC_CMD_WRITE_SINGLE_BLOCK:
+ ret = sh_sdhi_single_write(host, data);
+ break;
+ case MMC_CMD_READ_SINGLE_BLOCK:
+ case SDHI_SD_APP_SEND_SCR:
+ case SDHI_SD_SWITCH: /* SD_SWITCH */
+ ret = sh_sdhi_single_read(host, data);
+ break;
+ default:
+ printf(DRIVER_NAME": SD: NOT SUPPORT CMD = d'%04d\n", opc);
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int sh_sdhi_start_cmd(struct sh_sdhi_host *host,
+ struct mmc_data *data, struct mmc_cmd *cmd)
+{
+ long time;
+ unsigned short opc = cmd->cmdidx;
+ int ret = 0;
+ unsigned long timeout;
+
+ debug("opc = %d, arg = %x, resp_type = %x\n",
+ opc, cmd->cmdarg, cmd->resp_type);
+
+ if (opc == MMC_CMD_STOP_TRANSMISSION) {
+ /* SDHI sends the STOP command automatically by STOP reg */
+ sh_sdhi_writew(host, SDHI_INFO1_MASK, ~INFO1M_ACCESS_END &
+ sh_sdhi_readw(host, SDHI_INFO1_MASK));
+
+ time = sh_sdhi_wait_interrupt_flag(host);
+ if (time == 0 || host->sd_error != 0)
+ return sh_sdhi_error_manage(host);
+
+ sh_sdhi_get_response(host, cmd);
+ return 0;
+ }
+
+ if (data) {
+ if ((opc == MMC_CMD_READ_MULTIPLE_BLOCK) ||
+ opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
+ sh_sdhi_writew(host, SDHI_STOP, STOP_SEC_ENABLE);
+ sh_sdhi_writew(host, SDHI_SECCNT, data->blocks);
+ }
+ sh_sdhi_writew(host, SDHI_SIZE, data->blocksize);
+ }
+ opc = sh_sdhi_set_cmd(host, data, opc);
+
+ /*
+ * U-boot cannot use interrupt.
+ * So this flag may not be clear by timing
+ */
+ sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END);
+
+ sh_sdhi_writew(host, SDHI_INFO1_MASK,
+ INFO1M_RESP_END | sh_sdhi_readw(host, SDHI_INFO1_MASK));
+ sh_sdhi_writew(host, SDHI_ARG0,
+ (unsigned short)(cmd->cmdarg & ARG0_MASK));
+ sh_sdhi_writew(host, SDHI_ARG1,
+ (unsigned short)((cmd->cmdarg >> 16) & ARG1_MASK));
+
+ timeout = 100000;
+ /* Waiting for SD Bus busy to be cleared */
+ while (timeout--) {
+ if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000))
+ break;
+ }
+
+ sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(opc & CMD_MASK));
+
+ host->wait_int = 0;
+ sh_sdhi_writew(host, SDHI_INFO1_MASK,
+ ~INFO1M_RESP_END & sh_sdhi_readw(host, SDHI_INFO1_MASK));
+ sh_sdhi_writew(host, SDHI_INFO2_MASK,
+ ~(INFO2M_CMD_ERROR | INFO2M_CRC_ERROR |
+ INFO2M_END_ERROR | INFO2M_TIMEOUT |
+ INFO2M_RESP_TIMEOUT | INFO2M_ILA) &
+ sh_sdhi_readw(host, SDHI_INFO2_MASK));
+
+ time = sh_sdhi_wait_interrupt_flag(host);
+ if (!time)
+ return sh_sdhi_error_manage(host);
+
+ if (host->sd_error) {
+ switch (cmd->cmdidx) {
+ case MMC_CMD_ALL_SEND_CID:
+ case MMC_CMD_SELECT_CARD:
+ case SD_CMD_SEND_IF_COND:
+ case MMC_CMD_APP_CMD:
+ ret = TIMEOUT;
+ break;
+ default:
+ debug(DRIVER_NAME": Cmd(d'%d) err\n", opc);
+ debug(DRIVER_NAME": cmdidx = %d\n", cmd->cmdidx);
+ ret = sh_sdhi_error_manage(host);
+ break;
+ }
+ host->sd_error = 0;
+ host->wait_int = 0;
+ return ret;
+ }
+ if (sh_sdhi_readw(host, SDHI_INFO1) & INFO1_RESP_END)
+ return -EINVAL;
+
+ if (host->wait_int) {
+ sh_sdhi_get_response(host, cmd);
+ host->wait_int = 0;
+ }
+ if (data)
+ ret = sh_sdhi_data_trans(host, data, opc);
+
+ debug("ret = %d, resp = %08x, %08x, %08x, %08x\n",
+ ret, cmd->response[0], cmd->response[1],
+ cmd->response[2], cmd->response[3]);
+ return ret;
+}
+
+static int sh_sdhi_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct sh_sdhi_host *host = mmc_priv(mmc);
+ int ret;
+
+ host->sd_error = 0;
+
+ ret = sh_sdhi_start_cmd(host, data, cmd);
+
+ return ret;
+}
+
+static void sh_sdhi_set_ios(struct mmc *mmc)
+{
+ int ret;
+ struct sh_sdhi_host *host = mmc_priv(mmc);
+
+ ret = sh_sdhi_clock_control(host, mmc->clock);
+ if (ret)
+ return;
+
+ if (mmc->bus_width == 4)
+ sh_sdhi_writew(host, SDHI_OPTION, ~OPT_BUS_WIDTH_1 &
+ sh_sdhi_readw(host, SDHI_OPTION));
+ else
+ sh_sdhi_writew(host, SDHI_OPTION, OPT_BUS_WIDTH_1 |
+ sh_sdhi_readw(host, SDHI_OPTION));
+
+ debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
+}
+
+static int sh_sdhi_initialize(struct mmc *mmc)
+{
+ struct sh_sdhi_host *host = mmc_priv(mmc);
+ int ret = sh_sdhi_sync_reset(host);
+
+ sh_sdhi_writew(host, SDHI_PORTSEL, USE_1PORT);
+
+#if defined(__BIG_ENDIAN_BITFIELD)
+ sh_sdhi_writew(host, SDHI_EXT_SWAP, SET_SWAP);
+#endif
+
+ sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END |
+ INFO1M_ACCESS_END | INFO1M_CARD_RE |
+ INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN);
+
+ return ret;
+}
+
+static const struct mmc_ops sh_sdhi_ops = {
+ .send_cmd = sh_sdhi_send_cmd,
+ .set_ios = sh_sdhi_set_ios,
+ .init = sh_sdhi_initialize,
+};
+
+static struct mmc_config sh_sdhi_cfg = {
+ .name = DRIVER_NAME,
+ .ops = &sh_sdhi_ops,
+ .f_min = CLKDEV_INIT,
+ .f_max = CLKDEV_HS_DATA,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .host_caps = MMC_MODE_4BIT | MMC_MODE_HS,
+ .part_type = PART_TYPE_DOS,
+ .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
+int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks)
+{
+ int ret = 0;
+ struct mmc *mmc;
+ struct sh_sdhi_host *host = NULL;
+
+ if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL)
+ return -ENODEV;
+
+ host = malloc(sizeof(struct sh_sdhi_host));
+ if (!host)
+ return -ENOMEM;
+
+ mmc = mmc_create(&sh_sdhi_cfg, host);
+ if (!mmc) {
+ ret = -1;
+ goto error;
+ }
+
+ host->ch = ch;
+ host->addr = addr;
+ host->quirks = quirks;
+
+ if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
+ host->bus_shift = 1;
+
+ return ret;
+error:
+ if (host)
+ free(host);
+ return ret;
+}
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 231f0a0..5104795 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -22,7 +22,6 @@
unsigned mmc_no;
uint32_t *mclkreg;
unsigned fatal_err;
- unsigned mod_clk;
struct sunxi_mmc *reg;
struct mmc_config cfg;
};
@@ -73,16 +72,77 @@
mmchost->mmc_no = sdc_no;
cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
- if (cd_pin != -1)
+ if (cd_pin != -1) {
ret = gpio_request(cd_pin, "mmc_cd");
+ if (!ret)
+ ret = gpio_direction_input(cd_pin);
+ }
return ret;
}
+static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
+{
+ unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
+
+ if (hz <= 24000000) {
+ pll = CCM_MMC_CTRL_OSCM24;
+ pll_hz = 24000000;
+ } else {
+#ifdef CONFIG_MACH_SUN9I
+ pll = CCM_MMC_CTRL_PLL_PERIPH0;
+ pll_hz = clock_get_pll4_periph0();
+#else
+ pll = CCM_MMC_CTRL_PLL6;
+ pll_hz = clock_get_pll6();
+#endif
+ }
+
+ div = pll_hz / hz;
+ if (pll_hz % hz)
+ div++;
+
+ n = 0;
+ while (div > 16) {
+ n++;
+ div = (div + 1) / 2;
+ }
+
+ if (n > 3) {
+ printf("mmc %u error cannot set clock to %u\n",
+ mmchost->mmc_no, hz);
+ return -1;
+ }
+
+ /* determine delays */
+ if (hz <= 400000) {
+ oclk_dly = 0;
+ sclk_dly = 7;
+ } else if (hz <= 25000000) {
+ oclk_dly = 0;
+ sclk_dly = 5;
+ } else if (hz <= 50000000) {
+ oclk_dly = 3;
+ sclk_dly = 5;
+ } else {
+ /* hz > 50000000 */
+ oclk_dly = 2;
+ sclk_dly = 4;
+ }
+
+ writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
+ CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
+ CCM_MMC_CTRL_M(div), mmchost->mclkreg);
+
+ debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
+ mmchost->mmc_no, hz, pll_hz, 1u << n, div,
+ pll_hz / (1u << n) / div);
+
+ return 0;
+}
+
static int mmc_clk_io_on(int sdc_no)
{
- unsigned int pll_clk;
- unsigned int divider;
struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
@@ -91,20 +151,18 @@
/* config ahb clock */
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
+ defined(CONFIG_MACH_SUN9I)
/* unassert reset */
setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
#endif
+#if defined(CONFIG_MACH_SUN9I)
+ /* sun9i has a mmc-common module, also set the gate and reset there */
+ writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
+ SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
+#endif
- /* config mod clock */
- pll_clk = clock_get_pll6();
- /* should be close to 100 MHz but no more, so round up */
- divider = ((pll_clk + 99999999) / 100000000) - 1;
- writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider,
- mmchost->mclkreg);
- mmchost->mod_clk = pll_clk / (divider + 1);
-
- return 0;
+ return mmc_set_mod_clk(mmchost, 24000000);
}
static int mmc_update_clk(struct mmc *mmc)
@@ -129,7 +187,7 @@
return 0;
}
-static int mmc_config_clock(struct mmc *mmc, unsigned div)
+static int mmc_config_clock(struct mmc *mmc)
{
struct sunxi_mmc_host *mmchost = mmc->priv;
unsigned rval = readl(&mmchost->reg->clkcr);
@@ -140,16 +198,17 @@
if (mmc_update_clk(mmc))
return -1;
- /* Change Divider Factor */
- rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
- rval |= div;
- writel(rval, &mmchost->reg->clkcr);
- if (mmc_update_clk(mmc))
+ /* Set mod_clk to new rate */
+ if (mmc_set_mod_clk(mmchost, mmc->clock))
return -1;
+
+ /* Clear internal divider */
+ rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
+ writel(rval, &mmchost->reg->clkcr);
+
/* Re-enable Clock */
rval |= SUNXI_MMC_CLK_ENABLE;
writel(rval, &mmchost->reg->clkcr);
-
if (mmc_update_clk(mmc))
return -1;
@@ -159,18 +218,14 @@
static void mmc_set_ios(struct mmc *mmc)
{
struct sunxi_mmc_host *mmchost = mmc->priv;
- unsigned int clkdiv = 0;
- debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
- mmc->bus_width, mmc->clock, mmchost->mod_clk);
+ debug("set ios: bus_width: %x, clock: %d\n",
+ mmc->bus_width, mmc->clock);
/* Change clock first */
- clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
- if (mmc->clock) {
- if (mmc_config_clock(mmc, clkdiv)) {
- mmchost->fatal_err = 1;
- return;
- }
+ if (mmc->clock && mmc_config_clock(mmc) != 0) {
+ mmchost->fatal_err = 1;
+ return;
}
/* Change bus width */
@@ -311,7 +366,7 @@
}
}
- error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
+ error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
if (error)
goto out;
@@ -373,7 +428,7 @@
if (cd_pin == -1)
return 1;
- return !gpio_direction_input(cd_pin);
+ return !gpio_get_value(cd_pin);
}
static const struct mmc_ops sunxi_mmc_ops = {
@@ -395,7 +450,8 @@
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
+ defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
cfg->host_caps |= MMC_MODE_HC;
#endif
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index fdce2c2..7887f11 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -13,7 +13,7 @@
#include <sdhci.h>
#include <asm/arch/sys_proto.h>
-int zynq_sdhci_init(u32 regbase)
+int zynq_sdhci_init(phys_addr_t regbase)
{
struct sdhci_host *host = NULL;
@@ -40,7 +40,7 @@
{
int offset = 0;
u32 ret = 0;
- u32 reg;
+ phys_addr_t reg;
debug("ZYNQ SDHCI: Initialization\n");
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 63bdf65..6db6566 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1065,11 +1065,6 @@
}
}
#endif
-#ifdef PPCHAMELON_NAND_TIMER_HACK
- time_start = get_timer(0);
- while (get_timer(time_start) < 10)
- ;
-#endif /* PPCHAMELON_NAND_TIMER_HACK */
led_trigger_event(nand_led_trigger, LED_OFF);
status = (int)chip->read_byte(mtd);
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 459904d..fc64f48 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -441,6 +441,115 @@
return (err) ? err : error_count;
}
+#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
+
+#define PREFETCH_CONFIG1_CS_SHIFT 24
+#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
+#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
+#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
+#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
+#define ENABLE_PREFETCH (1 << 7)
+
+/**
+ * omap_prefetch_enable - configures and starts prefetch transfer
+ * @fifo_th: fifo threshold to be used for read/ write
+ * @count: number of bytes to be transferred
+ * @is_write: prefetch read(0) or write post(1) mode
+ * @cs: chip select to use
+ */
+static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
+{
+ uint32_t val;
+
+ if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
+ return -EINVAL;
+
+ if (readl(&gpmc_cfg->prefetch_control))
+ return -EBUSY;
+
+ /* Set the amount of bytes to be prefetched */
+ writel(count, &gpmc_cfg->prefetch_config2);
+
+ val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
+ PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
+ writel(val, &gpmc_cfg->prefetch_config1);
+
+ /* Start the prefetch engine */
+ writel(1, &gpmc_cfg->prefetch_control);
+
+ return 0;
+}
+
+/**
+ * omap_prefetch_reset - disables and stops the prefetch engine
+ */
+static void omap_prefetch_reset(void)
+{
+ writel(0, &gpmc_cfg->prefetch_control);
+ writel(0, &gpmc_cfg->prefetch_config1);
+}
+
+static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
+{
+ int ret;
+ uint32_t cnt;
+ struct omap_nand_info *info = chip->priv;
+
+ ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
+ if (ret < 0)
+ return ret;
+
+ do {
+ int i;
+
+ cnt = readl(&gpmc_cfg->prefetch_status);
+ cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
+
+ for (i = 0; i < cnt / 4; i++) {
+ *buf++ = readl(CONFIG_SYS_NAND_BASE);
+ len -= 4;
+ }
+ } while (len);
+
+ omap_prefetch_reset();
+
+ return 0;
+}
+
+static void omap_nand_read_prefetch8(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int ret;
+ uint32_t head, tail;
+ struct nand_chip *chip = mtd->priv;
+
+ /*
+ * If the destination buffer is unaligned, start with reading
+ * the overlap byte-wise.
+ */
+ head = ((uint32_t) buf) % 4;
+ if (head) {
+ nand_read_buf(mtd, buf, head);
+ buf += head;
+ len -= head;
+ }
+
+ /*
+ * Only transfer multiples of 4 bytes in a pre-fetched fashion.
+ * If there's a residue, care for it byte-wise afterwards.
+ */
+ tail = len % 4;
+
+ ret = __read_prefetch_aligned(chip, (uint32_t *) buf, len - tail);
+ if (ret < 0) {
+ /* fallback in case the prefetch engine is busy */
+ nand_read_buf(mtd, buf, len);
+ } else if (tail) {
+ buf += len - tail;
+ nand_read_buf(mtd, buf, tail);
+ }
+}
+#endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
+
/**
* omap_read_page_bch - hardware ecc based page read function
* @mtd: mtd info structure
@@ -880,11 +989,12 @@
if (err)
return err;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
+ /* TODO: Implement for 16-bit bus width */
if (nand->options & NAND_BUSWIDTH_16)
nand->read_buf = nand_read_buf16;
else
- nand->read_buf = nand_read_buf;
+ nand->read_buf = omap_nand_read_prefetch8;
#endif
nand->dev_ready = omap_dev_ready;
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index fb0cf8c..46c4ac6 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -66,3 +66,4 @@
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/
+obj-$(CONFIG_VSC9953) += vsc9953.o
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index f1e39b9..1d1089d 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -410,10 +410,15 @@
fmc_tx_port_graceful_stop_disable(fm_eth);
#ifdef CONFIG_PHYLIB
- ret = phy_startup(fm_eth->phydev);
- if (ret) {
- printf("%s: Could not initialize\n", fm_eth->phydev->dev->name);
- return ret;
+ if (fm_eth->phydev) {
+ ret = phy_startup(fm_eth->phydev);
+ if (ret) {
+ printf("%s: Could not initialize\n",
+ fm_eth->phydev->dev->name);
+ return ret;
+ }
+ } else {
+ return 0;
}
#else
fm_eth->phydev->speed = SPEED_1000;
@@ -447,7 +452,8 @@
/* disable bmi Rx port */
bmi_rx_port_disable(fm_eth->rx_port);
- phy_shutdown(fm_eth->phydev);
+ if (fm_eth->phydev)
+ phy_shutdown(fm_eth->phydev);
}
static int fm_eth_send(struct eth_device *dev, void *buf, int len)
@@ -625,11 +631,12 @@
if (fm_eth->bus) {
phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
fm_eth->enet_if);
- }
-
- if (!phydev) {
- printf("Failed to connect\n");
- return -1;
+ if (!phydev) {
+ printf("Failed to connect\n");
+ return -1;
+ }
+ } else {
+ return 0;
}
if (fm_eth->type == FM_ETH_1G_E) {
@@ -711,8 +718,7 @@
if (!fm_eth_startup(fm_eth))
return 0;
- if (init_phy(dev))
- return 0;
+ init_phy(dev);
/* clear the ethernet address */
for (i = 0; i < 6; i++)
diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c
index d2a097e..0458366 100644
--- a/drivers/net/fm/t1040.c
+++ b/drivers/net/fm/t1040.c
@@ -50,7 +50,8 @@
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
- if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1))
+ if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) ||
+ is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_QSGMII;
case FM1_DTSEC3:
case FM1_DTSEC4:
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
index d9d6f4f..d2a8ae0 100644
--- a/drivers/net/mpc5xxx_fec.c
+++ b/drivers/net/mpc5xxx_fec.c
@@ -407,13 +407,8 @@
*/
if (fec->xcv_type == SEVENWIRE) {
/* 10MBit with 7-wire operation */
-#if defined(CONFIG_TOTAL5200)
- /* 7-wire and USB2 on Ethernet */
- *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
-#else /* !CONFIG_TOTAL5200 */
/* 7-wire only */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
-#endif /* CONFIG_TOTAL5200 */
} else {
/* 100MBit with MD operation */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 6ef6cac..6b31a82 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -35,6 +35,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_MVGBE_PORTS
+# define CONFIG_MVGBE_PORTS {0, 0}
+#endif
+
#define MV_PHY_ADR_REQUEST 0xee
#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index f46bf00..d096db8 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_PHYLIB) += phy.o
obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
+obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o
obj-$(CONFIG_PHY_ATHEROS) += atheros.o
obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
obj-$(CONFIG_PHY_CORTINA) += cortina.o
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
new file mode 100644
index 0000000..ef4da4e
--- /dev/null
+++ b/drivers/net/phy/aquantia.c
@@ -0,0 +1,156 @@
+/*
+ * Aquantia PHY drivers
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+#include <config.h>
+#include <common.h>
+#include <phy.h>
+
+#ifndef CONFIG_PHYLIB_10G
+#error The Aquantia PHY needs 10G support
+#endif
+
+#define AQUNTIA_10G_CTL 0x20
+#define AQUNTIA_VENDOR_P1 0xc400
+
+#define AQUNTIA_SPEED_LSB_MASK 0x2000
+#define AQUNTIA_SPEED_MSB_MASK 0x40
+
+int aquantia_config(struct phy_device *phydev)
+{
+ u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
+
+ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ /* 1000BASE-T mode */
+ phydev->advertising = SUPPORTED_1000baseT_Full;
+ phydev->supported = phydev->advertising;
+
+ val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
+ phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
+ } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) {
+ /* 10GBASE-T mode */
+ phydev->advertising = SUPPORTED_10000baseT_Full;
+ phydev->supported = phydev->advertising;
+
+ if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
+ !(val & AQUNTIA_SPEED_MSB_MASK))
+ phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
+ AQUNTIA_SPEED_LSB_MASK |
+ AQUNTIA_SPEED_MSB_MASK);
+ } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) {
+ /* 2.5GBASE-T mode */
+ phydev->advertising = SUPPORTED_1000baseT_Full;
+ phydev->supported = phydev->advertising;
+
+ phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
+ phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
+ } else if (phydev->interface == PHY_INTERFACE_MODE_MII) {
+ /* 100BASE-TX mode */
+ phydev->advertising = SUPPORTED_100baseT_Full;
+ phydev->supported = phydev->advertising;
+
+ val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
+ phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
+ }
+ return 0;
+}
+
+int aquantia_startup(struct phy_device *phydev)
+{
+ u32 reg, speed;
+ int i = 0;
+
+ phydev->duplex = DUPLEX_FULL;
+
+ /* if the AN is still in progress, wait till timeout. */
+ phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+ reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+ if (!(reg & MDIO_AN_STAT1_COMPLETE)) {
+ printf("%s Waiting for PHY auto negotiation to complete",
+ phydev->dev->name);
+ do {
+ udelay(1000);
+ reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+ if ((i++ % 500) == 0)
+ printf(".");
+ } while (!(reg & MDIO_AN_STAT1_COMPLETE) &&
+ i < (4 * PHY_ANEG_TIMEOUT));
+
+ if (i > PHY_ANEG_TIMEOUT)
+ printf(" TIMEOUT !\n");
+ }
+
+ /* Read twice because link state is latched and a
+ * read moves the current state into the register */
+ phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+ reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
+ if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
+ phydev->link = 0;
+ else
+ phydev->link = 1;
+
+ speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
+ if (speed & AQUNTIA_SPEED_MSB_MASK) {
+ if (speed & AQUNTIA_SPEED_LSB_MASK)
+ phydev->speed = SPEED_10000;
+ else
+ phydev->speed = SPEED_1000;
+ } else {
+ if (speed & AQUNTIA_SPEED_LSB_MASK)
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_10;
+ }
+
+ return 0;
+}
+
+struct phy_driver aq1202_driver = {
+ .name = "Aquantia AQ1202",
+ .uid = 0x3a1b445,
+ .mask = 0xfffffff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
+struct phy_driver aq2104_driver = {
+ .name = "Aquantia AQ2104",
+ .uid = 0x3a1b460,
+ .mask = 0xfffffff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
+struct phy_driver aqr105_driver = {
+ .name = "Aquantia AQR105",
+ .uid = 0x3a1b4a2,
+ .mask = 0xfffffff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+};
+int phy_aquantia_init(void)
+{
+ phy_register(&aq1202_driver);
+ phy_register(&aq2104_driver);
+ phy_register(&aqr105_driver);
+
+ return 0;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 5b04c85..df7e945 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -442,6 +442,9 @@
int phy_init(void)
{
+#ifdef CONFIG_PHY_AQUANTIA
+ phy_aquantia_init();
+#endif
#ifdef CONFIG_PHY_ATHEROS
phy_atheros_init();
#endif
diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c
new file mode 100644
index 0000000..9fc3c18
--- /dev/null
+++ b/drivers/net/vsc9953.c
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Driver for the Vitesse VSC9953 L2 Switch
+ */
+
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <asm/fsl_memac.h>
+#include <vsc9953.h>
+
+static struct vsc9953_info vsc9953_l2sw = {
+ .port[0] = VSC9953_PORT_INFO_INITIALIZER(0),
+ .port[1] = VSC9953_PORT_INFO_INITIALIZER(1),
+ .port[2] = VSC9953_PORT_INFO_INITIALIZER(2),
+ .port[3] = VSC9953_PORT_INFO_INITIALIZER(3),
+ .port[4] = VSC9953_PORT_INFO_INITIALIZER(4),
+ .port[5] = VSC9953_PORT_INFO_INITIALIZER(5),
+ .port[6] = VSC9953_PORT_INFO_INITIALIZER(6),
+ .port[7] = VSC9953_PORT_INFO_INITIALIZER(7),
+ .port[8] = VSC9953_PORT_INFO_INITIALIZER(8),
+ .port[9] = VSC9953_PORT_INFO_INITIALIZER(9),
+};
+
+void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus)
+{
+ if (!VSC9953_PORT_CHECK(port))
+ return;
+
+ vsc9953_l2sw.port[port].bus = bus;
+}
+
+void vsc9953_port_info_set_phy_address(int port, int address)
+{
+ if (!VSC9953_PORT_CHECK(port))
+ return;
+
+ vsc9953_l2sw.port[port].phyaddr = address;
+}
+
+void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int)
+{
+ if (!VSC9953_PORT_CHECK(port))
+ return;
+
+ vsc9953_l2sw.port[port].enet_if = phy_int;
+}
+
+void vsc9953_port_enable(int port)
+{
+ if (!VSC9953_PORT_CHECK(port))
+ return;
+
+ vsc9953_l2sw.port[port].enabled = 1;
+}
+
+void vsc9953_port_disable(int port)
+{
+ if (!VSC9953_PORT_CHECK(port))
+ return;
+
+ vsc9953_l2sw.port[port].enabled = 0;
+}
+
+static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr,
+ int regnum, int value)
+{
+ int timeout = 50000;
+
+ out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) |
+ ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
+ (0x1 << 1));
+ asm("sync");
+
+ while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout)
+ udelay(1);
+
+ if (timeout == 0)
+ debug("Timeout waiting for MDIO write\n");
+}
+
+static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr,
+ int regnum)
+{
+ int value = 0xFFFF;
+ int timeout = 50000;
+
+ while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout)
+ udelay(1);
+ if (timeout == 0) {
+ debug("Timeout waiting for MDIO operation to finish\n");
+ return value;
+ }
+
+ /* Put the address of the phy, and the register
+ * number into MIICMD
+ */
+ out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) |
+ ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
+ (0x2 << 1));
+
+ timeout = 50000;
+ /* Wait for the the indication that the read is done */
+ while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout)
+ udelay(1);
+ if (timeout == 0)
+ debug("Timeout waiting for MDIO read\n");
+
+ /* Grab the value read from the PHY */
+ value = in_le32(&phyregs->miimdata);
+
+ if ((value & 0x00030000) == 0)
+ return value & 0x0000ffff;
+
+ return value;
+}
+
+static int init_phy(struct eth_device *dev)
+{
+ struct vsc9953_port_info *l2sw_port = dev->priv;
+ struct phy_device *phydev = NULL;
+
+#ifdef CONFIG_PHYLIB
+ if (!l2sw_port->bus)
+ return 0;
+ phydev = phy_connect(l2sw_port->bus, l2sw_port->phyaddr, dev,
+ l2sw_port->enet_if);
+ if (!phydev) {
+ printf("Failed to connect\n");
+ return -1;
+ }
+
+ phydev->supported &= SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_1000baseT_Full;
+ phydev->advertising = phydev->supported;
+
+ l2sw_port->phydev = phydev;
+
+ phy_config(phydev);
+#endif
+
+ return 0;
+}
+
+static int vsc9953_port_init(int port)
+{
+ struct eth_device *dev;
+
+ /* Internal ports never have a PHY */
+ if (VSC9953_INTERNAL_PORT_CHECK(port))
+ return 0;
+
+ /* alloc eth device */
+ dev = (struct eth_device *)calloc(1, sizeof(struct eth_device));
+ if (!dev)
+ return 1;
+
+ sprintf(dev->name, "SW@PORT%d", port);
+ dev->priv = &vsc9953_l2sw.port[port];
+ dev->init = NULL;
+ dev->halt = NULL;
+ dev->send = NULL;
+ dev->recv = NULL;
+
+ if (init_phy(dev)) {
+ free(dev);
+ return 1;
+ }
+
+ return 0;
+}
+
+void vsc9953_init(bd_t *bis)
+{
+ u32 i, hdx_cfg = 0, phy_addr = 0;
+ int timeout;
+ struct vsc9953_system_reg *l2sys_reg;
+ struct vsc9953_qsys_reg *l2qsys_reg;
+ struct vsc9953_dev_gmii *l2dev_gmii_reg;
+ struct vsc9953_analyzer *l2ana_reg;
+ struct vsc9953_devcpu_gcb *l2dev_gcb;
+
+ l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET +
+ VSC9953_DEV_GMII_OFFSET);
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET +
+ VSC9953_SYS_OFFSET);
+
+ l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
+ VSC9953_QSYS_OFFSET);
+
+ l2dev_gcb = (struct vsc9953_devcpu_gcb *)(VSC9953_OFFSET +
+ VSC9953_DEVCPU_GCB);
+
+ out_le32(&l2dev_gcb->chip_regs.soft_rst,
+ CONFIG_VSC9953_SOFT_SWC_RST_ENA);
+ timeout = 50000;
+ while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) &
+ CONFIG_VSC9953_SOFT_SWC_RST_ENA) && --timeout)
+ udelay(1); /* busy wait for vsc9953 soft reset */
+ if (timeout == 0)
+ debug("Timeout waiting for VSC9953 to reset\n");
+
+ out_le32(&l2sys_reg->sys.reset_cfg, CONFIG_VSC9953_MEM_ENABLE |
+ CONFIG_VSC9953_MEM_INIT);
+
+ timeout = 50000;
+ while ((in_le32(&l2sys_reg->sys.reset_cfg) &
+ CONFIG_VSC9953_MEM_INIT) && --timeout)
+ udelay(1); /* busy wait for vsc9953 memory init */
+ if (timeout == 0)
+ debug("Timeout waiting for VSC9953 memory to initialize\n");
+
+ out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg)
+ | CONFIG_VSC9953_CORE_ENABLE));
+
+ /* VSC9953 Setting to be done once only */
+ out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00);
+
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ if (vsc9953_port_init(i))
+ printf("Failed to initialize l2switch port %d\n", i);
+
+ /* Enable VSC9953 GMII Ports Port ID 0 - 7 */
+ if (VSC9953_INTERNAL_PORT_CHECK(i)) {
+ out_le32(&l2ana_reg->pfc[i].pfc_cfg,
+ CONFIG_VSC9953_PFC_FC_QSGMII);
+ out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
+ CONFIG_VSC9953_MAC_FC_CFG_QSGMII);
+ } else {
+ out_le32(&l2ana_reg->pfc[i].pfc_cfg,
+ CONFIG_VSC9953_PFC_FC);
+ out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
+ CONFIG_VSC9953_MAC_FC_CFG);
+ }
+ out_le32(&l2dev_gmii_reg->port_mode.clock_cfg,
+ CONFIG_VSC9953_CLOCK_CFG);
+ out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg,
+ CONFIG_VSC9953_MAC_ENA_CFG);
+ out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg,
+ CONFIG_VSC9953_MAC_MODE_CFG);
+ out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg,
+ CONFIG_VSC9953_MAC_IFG_CFG);
+ /* mac_hdx_cfg varies with port id*/
+ hdx_cfg = (CONFIG_VSC9953_MAC_HDX_CFG | (i << 16));
+ out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg);
+ out_le32(&l2sys_reg->sys.front_port_mode[i],
+ CONFIG_VSC9953_FRONT_PORT_MODE);
+ out_le32(&l2qsys_reg->sys.switch_port_mode[i],
+ CONFIG_VSC9953_PORT_ENA);
+ out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg,
+ CONFIG_VSC9953_MAC_MAX_LEN);
+ out_le32(&l2sys_reg->pause_cfg.pause_cfg[i],
+ CONFIG_VSC9953_PAUSE_CFG);
+ /* WAIT FOR 2 us*/
+ udelay(2);
+
+ l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(
+ (char *)l2dev_gmii_reg
+ + T1040_SWITCH_GMII_DEV_OFFSET);
+
+ /* Initialize Lynx PHY Wrappers */
+ phy_addr = 0;
+ if (vsc9953_l2sw.port[i].enet_if ==
+ PHY_INTERFACE_MODE_QSGMII)
+ phy_addr = (i + 0x4) & 0x1F;
+ else if (vsc9953_l2sw.port[i].enet_if ==
+ PHY_INTERFACE_MODE_SGMII)
+ phy_addr = (i + 1) & 0x1F;
+
+ if (phy_addr) {
+ /* SGMII IF mode + AN enable */
+ vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
+ 0x14, PHY_SGMII_IF_MODE_AN |
+ PHY_SGMII_IF_MODE_SGMII);
+ /* Dev ability according to SGMII specification */
+ vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
+ 0x4, PHY_SGMII_DEV_ABILITY_SGMII);
+ /* Adjust link timer for SGMII
+ * 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40
+ */
+ vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
+ 0x13, 0x0003);
+ vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
+ 0x12, 0x0d40);
+ /* Restart AN */
+ vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
+ 0x0, PHY_SGMII_CR_DEF_VAL |
+ PHY_SGMII_CR_RESET_AN);
+
+ timeout = 50000;
+ while ((vsc9953_mdio_read(&l2dev_gcb->mii_mng[0],
+ phy_addr, 0x01) & 0x0020) && --timeout)
+ udelay(1); /* wait for AN to complete */
+ if (timeout == 0)
+ debug("Timeout waiting for AN to complete\n");
+ }
+ }
+
+ printf("VSC9953 L2 switch initialized\n");
+ return;
+}
+
+#ifdef CONFIG_VSC9953_CMD
+/* Enable/disable status of a VSC9953 port */
+static void vsc9953_port_status_set(int port_nr, u8 enabled)
+{
+ u32 val;
+ struct vsc9953_qsys_reg *l2qsys_reg;
+
+ /* Administrative down */
+ if (vsc9953_l2sw.port[port_nr].enabled == 0)
+ return;
+
+ l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
+ VSC9953_QSYS_OFFSET);
+
+ val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_nr]);
+ if (enabled == 1)
+ val |= (1 << 13);
+ else
+ val &= ~(1 << 13);
+
+ out_le32(&l2qsys_reg->sys.switch_port_mode[port_nr], val);
+}
+
+/* Set all VSC9953 ports' status */
+static void vsc9953_port_all_status_set(u8 enabled)
+{
+ int i;
+
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_status_set(i, enabled);
+}
+
+/* Start autonegotiation for a VSC9953 PHY */
+static void vsc9953_phy_autoneg(int port_nr)
+{
+ if (!vsc9953_l2sw.port[port_nr].phydev)
+ return;
+
+ if (vsc9953_l2sw.port[port_nr].phydev->drv->startup(
+ vsc9953_l2sw.port[port_nr].phydev))
+ printf("Failed to start PHY for port %d\n", port_nr);
+}
+
+/* Start autonegotiation for all VSC9953 PHYs */
+static void vsc9953_phy_all_autoneg(void)
+{
+ int i;
+
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_phy_autoneg(i);
+}
+
+/* Print a VSC9953 port's configuration */
+static void vsc9953_port_config_show(int port)
+{
+ int speed;
+ int duplex;
+ int link;
+ u8 enabled;
+ u32 val;
+ struct vsc9953_qsys_reg *l2qsys_reg;
+
+ l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
+ VSC9953_QSYS_OFFSET);
+
+ val = in_le32(&l2qsys_reg->sys.switch_port_mode[port]);
+ enabled = vsc9953_l2sw.port[port].enabled &
+ ((val & 0x00002000) >> 13);
+
+ /* internal ports (8 and 9) are fixed */
+ if (VSC9953_INTERNAL_PORT_CHECK(port)) {
+ link = 1;
+ speed = SPEED_2500;
+ duplex = DUPLEX_FULL;
+ } else {
+ if (vsc9953_l2sw.port[port].phydev) {
+ link = vsc9953_l2sw.port[port].phydev->link;
+ speed = vsc9953_l2sw.port[port].phydev->speed;
+ duplex = vsc9953_l2sw.port[port].phydev->duplex;
+ } else {
+ link = -1;
+ speed = -1;
+ duplex = -1;
+ }
+ }
+
+ printf("%8d ", port);
+ printf("%8s ", enabled == 1 ? "enabled" : "disabled");
+ printf("%8s ", link == 1 ? "up" : "down");
+
+ switch (speed) {
+ case SPEED_10:
+ printf("%8d ", 10);
+ break;
+ case SPEED_100:
+ printf("%8d ", 100);
+ break;
+ case SPEED_1000:
+ printf("%8d ", 1000);
+ break;
+ case SPEED_2500:
+ printf("%8d ", 2500);
+ break;
+ case SPEED_10000:
+ printf("%8d ", 10000);
+ break;
+ default:
+ printf("%8s ", "-");
+ }
+
+ printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half");
+}
+
+/* Print VSC9953 ports' configuration */
+static void vsc9953_port_all_config_show(void)
+{
+ int i;
+
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_config_show(i);
+}
+
+/* function to interpret commands starting with "ethsw " */
+static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u8 enable;
+ u32 port;
+
+ if (argc < 4)
+ return -1;
+
+ if (strcmp(argv[1], "port"))
+ return -1;
+
+ if (!strcmp(argv[3], "show")) {
+ if (!strcmp(argv[2], "all")) {
+ vsc9953_phy_all_autoneg();
+ printf("%8s %8s %8s %8s %8s\n",
+ "Port", "Status", "Link", "Speed",
+ "Duplex");
+ vsc9953_port_all_config_show();
+ return 0;
+ } else {
+ port = simple_strtoul(argv[2], NULL, 10);
+ if (!VSC9953_PORT_CHECK(port))
+ return -1;
+ vsc9953_phy_autoneg(port);
+ printf("%8s %8s %8s %8s %8s\n",
+ "Port", "Status", "Link", "Speed",
+ "Duplex");
+ vsc9953_port_config_show(port);
+ return 0;
+ }
+ } else if (!strcmp(argv[3], "enable")) {
+ enable = 1;
+ } else if (!strcmp(argv[3], "disable")) {
+ enable = 0;
+ } else {
+ return -1;
+ }
+
+ if (!strcmp(argv[2], "all")) {
+ vsc9953_port_all_status_set(enable);
+ return 0;
+ } else {
+ port = simple_strtoul(argv[2], NULL, 10);
+ if (!VSC9953_PORT_CHECK(port))
+ return -1;
+ vsc9953_port_status_set(port, enable);
+ return 0;
+ }
+
+ return -1;
+}
+
+U_BOOT_CMD(ethsw, 5, 0, do_ethsw,
+ "vsc9953 l2 switch commands",
+ "port <port_nr> enable|disable\n"
+ " - enable/disable an l2 switch port\n"
+ " port_nr=0..9; use \"all\" for all ports\n"
+ "ethsw port <port_nr> show\n"
+ " - show an l2 switch port's configuration\n"
+ " port_nr=0..9; use \"all\" for all ports\n"
+);
+#endif /* CONFIG_VSC9953_CMD */
diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c
index dab78d0..7cc8657 100644
--- a/drivers/net/xilinx_ll_temac.c
+++ b/drivers/net/xilinx_ll_temac.c
@@ -231,7 +231,7 @@
struct ll_temac *ll_temac = dev->priv;
int ret;
- printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n",
+ printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08lx.\n",
dev->name, dev->index, dev->iobase);
if (!ll_temac_setup_ctrl(dev))
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3cadd23..430e228 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -489,7 +489,8 @@
return phywrite(dev, addr, reg, val);
}
-int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
+int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
+ int phy_addr, u32 emio)
{
struct eth_device *dev;
struct zynq_gem_priv *priv;
@@ -521,7 +522,7 @@
priv->phyaddr = phy_addr;
priv->emio = emio;
- sprintf(dev->name, "Gem.%x", base_addr);
+ sprintf(dev->name, "Gem.%lx", base_addr);
dev->iobase = base_addr;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3daf73c..950a247 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -19,6 +19,8 @@
#include <asm/io.h>
#include <pci.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define PCI_HOSE_OP(rw, size, type) \
int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, \
@@ -123,6 +125,14 @@
static struct pci_controller* hose_head;
+struct pci_controller *pci_get_hose_head(void)
+{
+ if (gd->hose)
+ return gd->hose;
+
+ return hose_head;
+}
+
void pci_register_hose(struct pci_controller* hose)
{
struct pci_controller **phose = &hose_head;
@@ -139,7 +149,7 @@
{
struct pci_controller *hose;
- for (hose = hose_head; hose; hose = hose->next) {
+ for (hose = pci_get_hose_head(); hose; hose = hose->next) {
if (bus >= hose->first_busno && bus <= hose->last_busno)
return hose;
}
@@ -152,7 +162,7 @@
{
struct pci_controller *hose;
- for (hose = hose_head; hose; hose = hose->next) {
+ for (hose = pci_get_hose_head(); hose; hose = hose->next) {
if (hose->cfg_addr == cfg_addr)
return hose;
}
@@ -162,7 +172,7 @@
int pci_last_busno(void)
{
- struct pci_controller *hose = hose_head;
+ struct pci_controller *hose = pci_get_hose_head();
if (!hose)
return -1;
@@ -181,19 +191,14 @@
pci_dev_t bdf;
int i, bus, found_multi = 0;
- for (hose = hose_head; hose; hose = hose->next) {
+ for (hose = pci_get_hose_head(); hose; hose = hose->next) {
#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
#else
for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
#endif
for (bdf = PCI_BDF(bus, 0, 0);
-#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
- bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
- PCI_MAX_PCI_FUNCTIONS - 1);
-#else
bdf < PCI_BDF(bus + 1, 0, 0);
-#endif
bdf += PCI_BDF(0, 0, 1)) {
if (pci_skip_dev(hose, bdf))
continue;
@@ -233,7 +238,7 @@
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
{
- static struct pci_device_id ids[2] = {{}, {0, 0}};
+ struct pci_device_id ids[2] = { {}, {0, 0} };
ids[0].vendor = vendor;
ids[0].device = device;
@@ -709,11 +714,10 @@
int pci_hose_scan(struct pci_controller *hose)
{
#if defined(CONFIG_PCI_BOOTDELAY)
- static int pcidelay_done;
char *s;
int i;
- if (!pcidelay_done) {
+ if (!gd->pcidelay_done) {
/* wait "pcidelay" ms (if defined)... */
s = getenv("pcidelay");
if (s) {
@@ -721,7 +725,7 @@
for (i = 0; i < val; i++)
udelay(1000);
}
- pcidelay_done = 1;
+ gd->pcidelay_done = 1;
}
#endif /* CONFIG_PCI_BOOTDELAY */
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index af6a3ae..7d25cc9 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -156,6 +156,8 @@
target = (void *)PCI_VGA_RAM_IMAGE_START;
if (target != rom_header) {
+ ulong start = get_timer(0);
+
debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
rom_header, target, rom_size);
memcpy(target, rom_header, rom_size);
@@ -163,6 +165,7 @@
printf("VGA ROM copy failed\n");
return -EFAULT;
}
+ debug("Copy took %lums\n", get_timer(start));
}
*ram_headerp = target;
@@ -205,7 +208,7 @@
gdev->vprBase = vesa->phys_base_ptr;
gdev->cprBase = vesa->phys_base_ptr;
- return 0;
+ return gdev->winSizeX ? 0 : -ENOSYS;
#else
return -ENOSYS;
#endif
@@ -244,7 +247,7 @@
defined(CONFIG_FRAMEBUFFER_VESA_MODE)
vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
#endif
- debug("Selected vesa mode %d\b", vesa_mode);
+ debug("Selected vesa mode %#x\n", vesa_mode);
if (emulate) {
#ifdef CONFIG_BIOSEMU
BE_VGAInfo *info;
@@ -272,7 +275,7 @@
return -ENOSYS;
#endif
}
- debug("Final vesa mode %d\n", mode_info.video_mode);
+ debug("Final vesa mode %#x\n", mode_info.video_mode);
return 0;
}
diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index a03ad5f..f9e05ad 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -458,6 +458,7 @@
unsigned int *index,
unsigned int *lanes)
{
+ struct fdt_pci_addr addr;
pci_dev_t bdf;
int err;
@@ -469,7 +470,7 @@
*lanes = err;
- err = fdtdec_pci_get_bdf(fdt, node, &bdf);
+ err = fdtdec_get_pci_bdf(fdt, node, &addr, &bdf);
if (err < 0) {
error("failed to parse \"reg\" property");
return err;
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 1ec7c0e..f8f0239 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -1,47 +1,75 @@
config AXP221_POWER
- boolean "axp221 pmic support"
- depends on MACH_SUN6I
+ boolean "axp221 / axp223 pmic support"
+ depends on MACH_SUN6I || MACH_SUN8I
default y
---help---
- Say y here to enable support for the axp221 pmic found on most sun6i
- (A31) boards.
+ Say y here to enable support for the axp221 / axp223 pmic found on most
+ sun6i (A31) / sun8i (A23) boards.
+
+config AXP221_DCDC1_VOLT
+ int "axp221 dcdc1 voltage"
+ depends on AXP221_POWER
+ default 3000
+ ---help---
+ Set the voltage (mV) to program the axp221 dcdc1 at, set to 0 to
+ disable dcdc1. This is typically used as generic 3.3V IO voltage for
+ things like GPIO-s, sdcard interfaces, etc. On most boards this is
+ undervolted to 3.0V to safe battery.
config AXP221_DLDO1_VOLT
int "axp221 dldo1 voltage"
depends on AXP221_POWER
- default -1
+ default 0
---help---
- Set the voltage (mV) to program the axp221 dldo1 at, set to -1 to
- disable dldo1.
+ Set the voltage (mV) to program the axp221 dldo1 at, set to 0 to
+ disable dldo1. On sun6i (A31) boards with ethernet this is often used
+ to power the ethernet phy. On sun8i (A23) boards this is often used to
+ power the wifi.
config AXP221_DLDO4_VOLT
int "axp221 dldo4 voltage"
depends on AXP221_POWER
- default -1
+ default 0
---help---
- Set the voltage (mV) to program the axp221 dldo4 at, set to -1 to
+ Set the voltage (mV) to program the axp221 dldo4 at, set to 0 to
disable dldo4.
config AXP221_ALDO1_VOLT
int "axp221 aldo1 voltage"
depends on AXP221_POWER
- default -1
+ default 0
---help---
- Set the voltage (mV) to program the axp221 aldo1 at, set to -1 to
- disable aldo1.
+ Set the voltage (mV) to program the axp221 aldo1 at, set to 0 to
+ disable aldo1. On sun6i (A31) boards which have a wifi module this is
+ often used to power the wifi module.
config AXP221_ALDO2_VOLT
int "axp221 aldo2 voltage"
depends on AXP221_POWER
- default -1
+ default 0 if MACH_SUN6I
+ default 2500 if MACH_SUN8I
---help---
- Set the voltage (mV) to program the axp221 aldo2 at, set to -1 to
- disable aldo2.
+ Set the voltage (mV) to program the axp221 aldo2 at, set to 0 to
+ disable aldo2. On sun6i (A31) boards this is typically unused and
+ should be disabled, if it is used for LPDDR2 it should be set to 1.8V.
+ On sun8i (A23) this is typically connected to VDD-DLL and must be set
+ to 2.5V.
config AXP221_ALDO3_VOLT
int "axp221 aldo3 voltage"
depends on AXP221_POWER
- default -1
+ default 3000
---help---
- Set the voltage (mV) to program the axp221 aldo3 at, set to -1 to
- disable aldo3.
+ Set the voltage (mV) to program the axp221 aldo3 at, set to 0 to
+ disable aldo3. This is typically connected to VCC-PLL and AVCC and
+ must be set to 3V.
+
+config AXP221_ELDO3_VOLT
+ int "axp221 eldo3 voltage"
+ depends on AXP221_POWER
+ default 0
+ ---help---
+ Set the voltage (mV) to program the axp221 eldo3 at, set to 0 to
+ disable eldo3. On some A31(s) tablets it might be used to supply
+ 1.2V for the SSD2828 chip (converter of parallel LCD interface
+ into MIPI DSI).
diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c
index 9798e5b..4565398 100644
--- a/drivers/power/axp209.c
+++ b/drivers/power/axp209.c
@@ -16,8 +16,18 @@
AXP209_DCDC3_VOLTAGE = 0x27,
AXP209_LDO24_VOLTAGE = 0x28,
AXP209_LDO3_VOLTAGE = 0x29,
+ AXP209_IRQ_ENABLE1 = 0x40,
+ AXP209_IRQ_ENABLE2 = 0x41,
+ AXP209_IRQ_ENABLE3 = 0x42,
+ AXP209_IRQ_ENABLE4 = 0x43,
+ AXP209_IRQ_ENABLE5 = 0x44,
AXP209_IRQ_STATUS5 = 0x4c,
AXP209_SHUTDOWN = 0x32,
+ AXP209_GPIO0_CTRL = 0x90,
+ AXP209_GPIO1_CTRL = 0x92,
+ AXP209_GPIO2_CTRL = 0x93,
+ AXP209_GPIO_STATE = 0x94,
+ AXP209_GPIO3_CTRL = 0x95,
};
#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0)
@@ -27,6 +37,15 @@
#define AXP209_POWEROFF (1 << 7)
+#define AXP209_GPIO_OUTPUT_LOW 0x00 /* Drive pin low */
+#define AXP209_GPIO_OUTPUT_HIGH 0x01 /* Drive pin high */
+#define AXP209_GPIO_INPUT 0x02 /* Float pin */
+
+/* GPIO3 is different from the others */
+#define AXP209_GPIO3_OUTPUT_LOW 0x00 /* Drive pin low, Output mode */
+#define AXP209_GPIO3_OUTPUT_HIGH 0x02 /* Float pin, Output mode */
+#define AXP209_GPIO3_INPUT 0x06 /* Float pin, Input mode */
+
static int axp209_write(enum axp209_reg reg, u8 val)
{
return i2c_write(0x34, reg, 1, &val, 1);
@@ -129,7 +148,7 @@
int axp209_init(void)
{
u8 ver;
- int rc;
+ int i, rc;
rc = axp209_read(AXP209_CHIP_VERSION, &ver);
if (rc)
@@ -141,6 +160,13 @@
if (ver != 0x1)
return -1;
+ /* Mask all interrupts */
+ for (i = AXP209_IRQ_ENABLE1; i <= AXP209_IRQ_ENABLE5; i++) {
+ rc = axp209_write(i, 0);
+ if (rc)
+ return rc;
+ }
+
return 0;
}
@@ -165,3 +191,61 @@
return v & AXP209_IRQ5_PEK_DOWN;
}
+
+static u8 axp209_get_gpio_ctrl_reg(unsigned int pin)
+{
+ switch (pin) {
+ case 0: return AXP209_GPIO0_CTRL;
+ case 1: return AXP209_GPIO1_CTRL;
+ case 2: return AXP209_GPIO2_CTRL;
+ case 3: return AXP209_GPIO3_CTRL;
+ }
+ return 0;
+}
+
+int axp_gpio_direction_input(unsigned int pin)
+{
+ u8 reg = axp209_get_gpio_ctrl_reg(pin);
+ /* GPIO3 is "special" */
+ u8 val = (pin == 3) ? AXP209_GPIO3_INPUT : AXP209_GPIO_INPUT;
+
+ return axp209_write(reg, val);
+}
+
+int axp_gpio_direction_output(unsigned int pin, unsigned int val)
+{
+ u8 reg = axp209_get_gpio_ctrl_reg(pin);
+
+ if (val) {
+ val = (pin == 3) ? AXP209_GPIO3_OUTPUT_HIGH :
+ AXP209_GPIO_OUTPUT_HIGH;
+ } else {
+ val = (pin == 3) ? AXP209_GPIO3_OUTPUT_LOW :
+ AXP209_GPIO_OUTPUT_LOW;
+ }
+
+ return axp209_write(reg, val);
+}
+
+int axp_gpio_get_value(unsigned int pin)
+{
+ u8 val, mask;
+ int rc;
+
+ if (pin == 3) {
+ rc = axp209_read(AXP209_GPIO3_CTRL, &val);
+ mask = 1;
+ } else {
+ rc = axp209_read(AXP209_GPIO_STATE, &val);
+ mask = 1 << (pin + 4);
+ }
+ if (rc)
+ return rc;
+
+ return (val & mask) ? 1 : 0;
+}
+
+int axp_gpio_set_value(unsigned int pin, unsigned int val)
+{
+ return axp_gpio_direction_output(pin, val);
+}
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index 941193a..58bbd45 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -1,4 +1,10 @@
/*
+ * AXP221 and AXP223 driver
+ *
+ * IMPORTANT when making changes to this file check that the registers
+ * used are the same for the axp221 and axp223.
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
* (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -7,8 +13,50 @@
#include <common.h>
#include <errno.h>
#include <asm/arch/p2wi.h>
+#include <asm/arch/rsb.h>
#include <axp221.h>
+/*
+ * The axp221 uses the p2wi bus, the axp223 is identical (for all registers
+ * used sofar) but uses the rsb bus. These functions abstract this.
+ */
+static int pmic_bus_init(void)
+{
+#ifdef CONFIG_MACH_SUN6I
+ p2wi_init();
+ return p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
+ AXP221_INIT_DATA);
+#else
+ int ret;
+
+ rsb_init();
+
+ ret = rsb_set_device_mode(AXP223_DEVICE_MODE_DATA);
+ if (ret)
+ return ret;
+
+ return rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
+#endif
+}
+
+static int pmic_bus_read(const u8 addr, u8 *data)
+{
+#ifdef CONFIG_MACH_SUN6I
+ return p2wi_read(addr, data);
+#else
+ return rsb_read(AXP223_RUNTIME_ADDR, addr, data);
+#endif
+}
+
+static int pmic_bus_write(const u8 addr, u8 data)
+{
+#ifdef CONFIG_MACH_SUN6I
+ return p2wi_write(addr, data);
+#else
+ return rsb_write(AXP223_RUNTIME_ADDR, addr, data);
+#endif
+}
+
static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div)
{
if (mvolt < min)
@@ -24,12 +72,25 @@
int ret;
u8 val;
- ret = p2wi_read(reg, &val);
+ ret = pmic_bus_read(reg, &val);
if (ret)
return ret;
val |= bits;
- return p2wi_write(reg, val);
+ return pmic_bus_write(reg, val);
+}
+
+static int axp221_clrbits(u8 reg, u8 bits)
+{
+ int ret;
+ u8 val;
+
+ ret = pmic_bus_read(reg, &val);
+ if (ret)
+ return ret;
+
+ val &= ~bits;
+ return pmic_bus_write(reg, val);
}
int axp221_set_dcdc1(unsigned int mvolt)
@@ -37,40 +98,89 @@
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100);
- ret = p2wi_write(AXP221_DCDC1_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC1_EN);
+
+ ret = pmic_bus_write(AXP221_DCDC1_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DCDC1_EN);
+ ret = axp221_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DCDC1SW_EN);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC1_EN);
}
int axp221_set_dcdc2(unsigned int mvolt)
{
+ int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
- return p2wi_write(AXP221_DCDC2_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC2_EN);
+
+ ret = pmic_bus_write(AXP221_DCDC2_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC2_EN);
}
int axp221_set_dcdc3(unsigned int mvolt)
{
+ int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20);
- return p2wi_write(AXP221_DCDC3_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC3_EN);
+
+ ret = pmic_bus_write(AXP221_DCDC3_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC3_EN);
}
int axp221_set_dcdc4(unsigned int mvolt)
{
+ int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
- return p2wi_write(AXP221_DCDC4_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC4_EN);
+
+ ret = pmic_bus_write(AXP221_DCDC4_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC4_EN);
}
int axp221_set_dcdc5(unsigned int mvolt)
{
+ int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50);
- return p2wi_write(AXP221_DCDC5_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC5_EN);
+
+ ret = pmic_bus_write(AXP221_DCDC5_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC5_EN);
}
int axp221_set_dldo1(unsigned int mvolt)
@@ -78,7 +188,11 @@
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
- ret = p2wi_write(AXP221_DLDO1_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO1_EN);
+
+ ret = pmic_bus_write(AXP221_DLDO1_CTRL, cfg);
if (ret)
return ret;
@@ -91,7 +205,11 @@
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
- ret = p2wi_write(AXP221_DLDO2_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO2_EN);
+
+ ret = pmic_bus_write(AXP221_DLDO2_CTRL, cfg);
if (ret)
return ret;
@@ -104,7 +222,11 @@
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
- ret = p2wi_write(AXP221_DLDO3_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO3_EN);
+
+ ret = pmic_bus_write(AXP221_DLDO3_CTRL, cfg);
if (ret)
return ret;
@@ -117,7 +239,11 @@
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
- ret = p2wi_write(AXP221_DLDO4_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO4_EN);
+
+ ret = pmic_bus_write(AXP221_DLDO4_CTRL, cfg);
if (ret)
return ret;
@@ -130,7 +256,11 @@
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
- ret = p2wi_write(AXP221_ALDO1_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_ALDO1_EN);
+
+ ret = pmic_bus_write(AXP221_ALDO1_CTRL, cfg);
if (ret)
return ret;
@@ -143,7 +273,11 @@
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
- ret = p2wi_write(AXP221_ALDO2_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_ALDO2_EN);
+
+ ret = pmic_bus_write(AXP221_ALDO2_CTRL, cfg);
if (ret)
return ret;
@@ -156,7 +290,11 @@
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
- ret = p2wi_write(AXP221_ALDO3_CTRL, cfg);
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL3,
+ AXP221_OUTPUT_CTRL3_ALDO3_EN);
+
+ ret = pmic_bus_write(AXP221_ALDO3_CTRL, cfg);
if (ret)
return ret;
@@ -164,23 +302,123 @@
AXP221_OUTPUT_CTRL3_ALDO3_EN);
}
-int axp221_init(void)
+int axp221_set_eldo(int eldo_num, unsigned int mvolt)
{
- u8 axp_chip_id;
int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
+ u8 addr, bits;
- p2wi_init();
- ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
- AXP221_INIT_DATA);
+ switch (eldo_num) {
+ case 3:
+ addr = AXP221_ELDO3_CTRL;
+ bits = AXP221_OUTPUT_CTRL2_ELDO3_EN;
+ break;
+ case 2:
+ addr = AXP221_ELDO2_CTRL;
+ bits = AXP221_OUTPUT_CTRL2_ELDO2_EN;
+ break;
+ case 1:
+ addr = AXP221_ELDO1_CTRL;
+ bits = AXP221_OUTPUT_CTRL2_ELDO1_EN;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mvolt == 0)
+ return axp221_clrbits(AXP221_OUTPUT_CTRL2, bits);
+
+ ret = pmic_bus_write(addr, cfg);
if (ret)
return ret;
- ret = p2wi_read(AXP221_CHIP_ID, &axp_chip_id);
+ return axp221_setbits(AXP221_OUTPUT_CTRL2, bits);
+}
+
+int axp221_init(void)
+{
+ /* This cannot be 0 because it is used in SPL before BSS is ready */
+ static int needs_init = 1;
+ u8 axp_chip_id;
+ int ret;
+
+ if (!needs_init)
+ return 0;
+
+ ret = pmic_bus_init();
+ if (ret)
+ return ret;
+
+ ret = pmic_bus_read(AXP221_CHIP_ID, &axp_chip_id);
if (ret)
return ret;
if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17))
return -ENODEV;
+ needs_init = 0;
return 0;
}
+
+int axp221_get_sid(unsigned int *sid)
+{
+ u8 *dest = (u8 *)sid;
+ int i, ret;
+
+ ret = axp221_init();
+ if (ret)
+ return ret;
+
+ ret = pmic_bus_write(AXP221_PAGE, 1);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < 16; i++) {
+ ret = pmic_bus_read(AXP221_SID + i, &dest[i]);
+ if (ret)
+ return ret;
+ }
+
+ pmic_bus_write(AXP221_PAGE, 0);
+
+ for (i = 0; i < 4; i++)
+ sid[i] = be32_to_cpu(sid[i]);
+
+ return 0;
+}
+
+static int axp_drivebus_setup(void)
+{
+ int ret;
+
+ ret = axp221_init();
+ if (ret)
+ return ret;
+
+ /* Set N_VBUSEN pin to output / DRIVEBUS function */
+ return axp221_clrbits(AXP221_MISC_CTRL, AXP221_MISC_CTRL_N_VBUSEN_FUNC);
+}
+
+int axp_drivebus_enable(void)
+{
+ int ret;
+
+ ret = axp_drivebus_setup();
+ if (ret)
+ return ret;
+
+ /* Set DRIVEBUS high */
+ return axp221_setbits(AXP221_VBUS_IPSOUT, AXP221_VBUS_IPSOUT_DRIVEBUS);
+}
+
+int axp_drivebus_disable(void)
+{
+ int ret;
+
+ ret = axp_drivebus_setup();
+ if (ret)
+ return ret;
+
+ /* Set DRIVEBUS low */
+ return axp221_clrbits(AXP221_VBUS_IPSOUT, AXP221_VBUS_IPSOUT_DRIVEBUS);
+}
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index e7b07eb..985cfdb 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -14,5 +14,6 @@
obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c
new file mode 100644
index 0000000..2123685
--- /dev/null
+++ b/drivers/power/pmic/pmic_tps62362.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
+#include <power/pmic.h>
+#include <power/tps62362.h>
+
+/**
+ * tps62362_voltage_update() - Function to change a voltage level, as this
+ * is a multi-step process.
+ * @reg: Register address to write to
+ * @volt_sel: Voltage register value to write
+ * @return: 0 on success, 1 on failure
+ */
+int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel)
+{
+ if (reg > TPS62362_NUM_REGS)
+ return 1;
+
+ return i2c_write(TPS62362_I2C_ADDR, reg, 1, &volt_sel, 1);
+}
+
+int power_tps62362_init(unsigned char bus)
+{
+ static const char name[] = "TPS62362";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+ p->name = name;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = TPS62362_NUM_REGS;
+ p->hw.i2c.addr = TPS62362_I2C_ADDR;
+ p->hw.i2c.tx_num = 1;
+ p->bus = bus;
+
+ return 0;
+}
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index af5beba..70c9462 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -289,7 +289,38 @@
struct ns16550_platdata *plat = dev->platdata;
fdt_addr_t addr;
+ /* try Processor Local Bus device first */
addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+#ifdef CONFIG_PCI
+ if (addr == FDT_ADDR_T_NONE) {
+ /* then try pci device */
+ struct fdt_pci_addr pci_addr;
+ u32 bar;
+ int ret;
+
+ /* we prefer to use a memory-mapped register */
+ ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
+ FDT_PCI_SPACE_MEM32, "reg",
+ &pci_addr);
+ if (ret) {
+ /* try if there is any i/o-mapped register */
+ ret = fdtdec_get_pci_addr(gd->fdt_blob,
+ dev->of_offset,
+ FDT_PCI_SPACE_IO,
+ "reg", &pci_addr);
+ if (ret)
+ return ret;
+ }
+
+ ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset,
+ &pci_addr, &bar);
+ if (ret)
+ return ret;
+
+ addr = bar;
+ }
+#endif
+
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c
index e81e035..4bf6062 100644
--- a/drivers/serial/serial_x86.c
+++ b/drivers/serial/serial_x86.c
@@ -6,9 +6,12 @@
#include <common.h>
#include <dm.h>
+#include <fdtdec.h>
#include <ns16550.h>
#include <serial.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static const struct udevice_id x86_serial_ids[] = {
{ .compatible = "x86-uart" },
{ }
@@ -22,10 +25,13 @@
ret = ns16550_serial_ofdata_to_platdata(dev);
if (ret)
return ret;
- plat->clock = 1843200;
+
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", 1843200);
return 0;
}
+
U_BOOT_DRIVER(serial_ns16550) = {
.name = "serial_x86",
.id = UCLASS_SERIAL,
diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c
index b8ca720..0ef85db 100644
--- a/drivers/usb/eth/asix88179.c
+++ b/drivers/usb/eth/asix88179.c
@@ -271,6 +271,19 @@
return 0;
}
+static int asix_write_mac(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ int ret;
+
+ ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
+ ETH_ALEN, eth->enetaddr);
+ if (ret < 0)
+ debug("Failed to set MAC address: %02x\n", ret);
+
+ return ret;
+}
+
static int asix_basic_reset(struct ueth_data *dev)
{
struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
@@ -686,6 +699,7 @@
eth->send = asix_send;
eth->recv = asix_recv;
eth->halt = asix_halt;
+ eth->write_hwaddr = asix_write_mac;
eth->priv = ss;
if (asix_basic_reset(ss))
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index a4c5606..98c2da6 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -761,6 +761,14 @@
if (value >= 0)
value = min(w_length, (u16) value);
break;
+ case USB_DT_BOS:
+ /*
+ * The USB compliance test (USB 2.0 Command Verifier)
+ * issues this request. We should not run into the
+ * default path here. But return for now until
+ * the superspeed support is added.
+ */
+ break;
default:
goto unknown;
}
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index ead71eb..77a1567 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -780,6 +780,13 @@
return 0;
}
+static int __dfu_get_alt(struct usb_function *f, unsigned intf)
+{
+ struct f_dfu *f_dfu = func_to_dfu(f);
+
+ return f_dfu->altsetting;
+}
+
/* TODO: is this really what we need here? */
static void dfu_disable(struct usb_function *f)
{
@@ -806,6 +813,7 @@
f_dfu->usb_function.bind = dfu_bind;
f_dfu->usb_function.unbind = dfu_unbind;
f_dfu->usb_function.set_alt = dfu_set_alt;
+ f_dfu->usb_function.get_alt = __dfu_get_alt;
f_dfu->usb_function.disable = dfu_disable;
f_dfu->usb_function.strings = dfu_generic_strings;
f_dfu->usb_function.setup = dfu_handle;
diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c
index 8945c5b..d4460b2 100644
--- a/drivers/usb/gadget/pxa25x_udc.c
+++ b/drivers/usb/gadget/pxa25x_udc.c
@@ -1950,11 +1950,11 @@
dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
dev->watchdog.function = udc_watchdog;
+ dev->mach = &mach_info;
+
udc_disable(dev);
udc_reinit(dev);
- dev->mach = &mach_info;
-
dev->gadget.name = "pxa2xx_udc";
retval = driver->bind(&dev->gadget);
if (retval) {
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index bc76066..f1fb190 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1148,7 +1148,7 @@
struct int_queue *
create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
- int elementsize, void *buffer)
+ int elementsize, void *buffer, int interval)
{
struct ehci_ctrl *ctrl = dev->controller;
struct int_queue *result = NULL;
@@ -1398,7 +1398,7 @@
debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
dev, pipe, buffer, length, interval);
- queue = create_int_queue(dev, pipe, 1, length, buffer);
+ queue = create_int_queue(dev, pipe, 1, length, buffer, interval);
if (!queue)
return -1;
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index cc9a8fa..eda9f69 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -9,199 +9,23 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
+#include <asm/arch/usbc.h>
#include <common.h>
#include "ehci.h"
-#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
-#define SUNXI_USB_CSR 0x404
-#define SUNXI_USB_PASSBY_EN 1
-
-#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
-#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
-#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
-#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
-
-static struct sunxi_ehci_hcd {
- struct usb_hcd *hcd;
- int usb_rst_mask;
- int ahb_clk_mask;
- int gpio_vbus;
- int irq;
- int id;
-} sunxi_echi_hcd[] = {
- {
- .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
- .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
-#ifndef CONFIG_MACH_SUN6I
- .irq = 39,
-#else
- .irq = 72,
-#endif
- .id = 1,
- },
-#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
- {
- .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
- .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
-#ifndef CONFIG_MACH_SUN6I
- .irq = 40,
-#else
- .irq = 74,
-#endif
- .id = 2,
- }
-#endif
-};
-
-static int enabled_hcd_count;
-
-static void *get_io_base(int hcd_id)
-{
- switch (hcd_id) {
- case 0:
- return (void *)SUNXI_USB0_BASE;
- case 1:
- return (void *)SUNXI_USB1_BASE;
- case 2:
- return (void *)SUNXI_USB2_BASE;
- default:
- return NULL;
- }
-}
-
-static int get_vbus_gpio(int hcd_id)
-{
- switch (hcd_id) {
- case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
- case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
- }
- return -1;
-}
-
-static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr,
- int data, int len)
-{
- int j = 0, usbc_bit = 0;
- void *dest = get_io_base(0) + SUNXI_USB_CSR;
-
- usbc_bit = 1 << (sunxi_ehci->id * 2);
- for (j = 0; j < len; j++) {
- /* set the bit address to be written */
- clrbits_le32(dest, 0xff << 8);
- setbits_le32(dest, (addr + j) << 8);
-
- clrbits_le32(dest, usbc_bit);
- /* set data bit */
- if (data & 0x1)
- setbits_le32(dest, 1 << 7);
- else
- clrbits_le32(dest, 1 << 7);
-
- setbits_le32(dest, usbc_bit);
-
- clrbits_le32(dest, usbc_bit);
-
- data >>= 1;
- }
-}
-
-static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci)
-{
- /* The following comments are machine
- * translated from Chinese, you have been warned!
- */
-
- /* adjust PHY's magnitude and rate */
- usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
-
- /* threshold adjustment disconnect */
-#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I
- usb_phy_write(sunxi_ehci, 0x2a, 3, 2);
-#else
- usb_phy_write(sunxi_ehci, 0x2a, 2, 2);
-#endif
-
- return;
-}
-
-static void sunxi_usb_passby(struct sunxi_ehci_hcd *sunxi_ehci, int enable)
-{
- unsigned long bits = 0;
- void *addr = get_io_base(sunxi_ehci->id) + SUNXI_USB_PMU_IRQ_ENABLE;
-
- bits = SUNXI_EHCI_AHB_ICHR8_EN |
- SUNXI_EHCI_AHB_INCR4_BURST_EN |
- SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
- SUNXI_EHCI_ULPI_BYPASS_EN;
-
- if (enable)
- setbits_le32(addr, bits);
- else
- clrbits_le32(addr, bits);
-
- return;
-}
-
-static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci)
-{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
- setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
-#ifdef CONFIG_MACH_SUN6I
- setbits_le32(&ccm->ahb_reset0_cfg, sunxi_ehci->ahb_clk_mask);
-#endif
-
- sunxi_usb_phy_init(sunxi_ehci);
-
- sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN);
-
- if (sunxi_ehci->gpio_vbus != -1)
- gpio_direction_output(sunxi_ehci->gpio_vbus, 1);
-}
-
-static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci)
-{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- if (sunxi_ehci->gpio_vbus != -1)
- gpio_direction_output(sunxi_ehci->gpio_vbus, 0);
-
- sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN);
-
-#ifdef CONFIG_MACH_SUN6I
- clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_ehci->ahb_clk_mask);
-#endif
- clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
- clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
-}
-
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
int err;
- sunxi_ehci->gpio_vbus = get_vbus_gpio(sunxi_ehci->id);
+ err = sunxi_usbc_request_resources(index + 1);
+ if (err)
+ return err;
- /* enable common PHY only once */
- if (index == 0)
- setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+ sunxi_usbc_enable(index + 1);
+ sunxi_usbc_vbus_enable(index + 1);
- if (sunxi_ehci->gpio_vbus != -1) {
- err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus");
- if (err)
- return err;
- }
-
- sunxi_ehci_enable(sunxi_ehci);
-
- *hccr = get_io_base(sunxi_ehci->id);
+ *hccr = sunxi_usbc_get_io_base(index + 1);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
@@ -210,30 +34,13 @@
(uint32_t)*hccr, (uint32_t)*hcor,
(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
- enabled_hcd_count++;
-
return 0;
}
int ehci_hcd_stop(int index)
{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
- int err;
+ sunxi_usbc_vbus_disable(index + 1);
+ sunxi_usbc_disable(index + 1);
- sunxi_ehci_disable(sunxi_ehci);
-
- if (sunxi_ehci->gpio_vbus != -1) {
- err = gpio_free(sunxi_ehci->gpio_vbus);
- if (err)
- return err;
- }
-
- /* disable common PHY only once, for the last enabled hcd */
- if (enabled_hcd_count == 1)
- clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
-
- enabled_hcd_count--;
-
- return 0;
+ return sunxi_usbc_free_resources(index + 1);
}
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 3facf0f..9edeece 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
+obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
ccflags-y := $(call cc-option,-Wno-unused-variable) \
$(call cc-option,-Wno-unused-but-set-variable) \
diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c
index bbcee88..437309c 100644
--- a/drivers/usb/musb-new/musb_host.c
+++ b/drivers/usb/musb-new/musb_host.c
@@ -2130,8 +2130,6 @@
return ret;
}
-
-#ifndef __UBOOT__
/*
* abort a transfer that's at the head of a hardware queue.
* called with controller locked, irqs blocked
@@ -2195,7 +2193,14 @@
return status;
}
-static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+#ifndef __UBOOT__
+static int musb_urb_dequeue(
+#else
+int musb_urb_dequeue(
+#endif
+ struct usb_hcd *hcd,
+ struct urb *urb,
+ int status)
{
struct musb *musb = hcd_to_musb(hcd);
struct musb_qh *qh;
@@ -2253,6 +2258,7 @@
return ret;
}
+#ifndef __UBOOT__
/* disable an endpoint */
static void
musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
diff --git a/drivers/usb/musb-new/musb_host.h b/drivers/usb/musb-new/musb_host.h
index ebebe0c..546b4a2 100644
--- a/drivers/usb/musb-new/musb_host.h
+++ b/drivers/usb/musb-new/musb_host.h
@@ -110,5 +110,6 @@
#ifdef __UBOOT__
int musb_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
+int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
#endif
#endif /* _MUSB_HOST_H */
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h
index 03f2655..27e4ed4 100644
--- a/drivers/usb/musb-new/musb_regs.h
+++ b/drivers/usb/musb-new/musb_regs.h
@@ -216,6 +216,9 @@
#ifndef CONFIG_BLACKFIN
+/* SUNXI has different reg addresses, but identical r/w functions */
+#ifndef CONFIG_ARCH_SUNXI
+
/*
* Common USB registers
*/
@@ -318,6 +321,85 @@
#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
(0x80 + (8*(_epnum)) + (_offset))
+#else /* CONFIG_ARCH_SUNXI */
+
+/*
+ * Common USB registers
+ */
+
+#define MUSB_FADDR 0x0098
+#define MUSB_POWER 0x0040
+
+#define MUSB_INTRTX 0x0044
+#define MUSB_INTRRX 0x0046
+#define MUSB_INTRTXE 0x0048
+#define MUSB_INTRRXE 0x004A
+#define MUSB_INTRUSB 0x004C
+#define MUSB_INTRUSBE 0x0050
+#define MUSB_FRAME 0x0054
+#define MUSB_INDEX 0x0042
+#define MUSB_TESTMODE 0x007C
+
+/* Get offset for a given FIFO from musb->mregs */
+#define MUSB_FIFO_OFFSET(epnum) (0x00 + ((epnum) * 4))
+
+/*
+ * Additional Control Registers
+ */
+
+#define MUSB_DEVCTL 0x0041
+
+/* These are always controlled through the INDEX register */
+#define MUSB_TXFIFOSZ 0x0090
+#define MUSB_RXFIFOSZ 0x0094
+#define MUSB_TXFIFOADD 0x0092
+#define MUSB_RXFIFOADD 0x0096
+
+#define MUSB_EPINFO 0x0078
+#define MUSB_RAMINFO 0x0079
+#define MUSB_LINKINFO 0x007A
+#define MUSB_VPLEN 0x007B
+#define MUSB_HS_EOF1 0x007C
+#define MUSB_FS_EOF1 0x007D
+#define MUSB_LS_EOF1 0x007E
+
+/* Offsets to endpoint registers */
+#define MUSB_TXMAXP 0x0080
+#define MUSB_TXCSR 0x0082
+#define MUSB_CSR0 0x0082
+#define MUSB_RXMAXP 0x0084
+#define MUSB_RXCSR 0x0086
+#define MUSB_RXCOUNT 0x0088
+#define MUSB_COUNT0 0x0088
+#define MUSB_TXTYPE 0x008C
+#define MUSB_TYPE0 0x008C
+#define MUSB_TXINTERVAL 0x008D
+#define MUSB_NAKLIMIT0 0x008D
+#define MUSB_RXTYPE 0x008E
+#define MUSB_RXINTERVAL 0x008F
+
+#define MUSB_CONFIGDATA 0x00b0 /* musb_read_configdata adds 0x10 ! */
+#define MUSB_FIFOSIZE 0x0090
+
+/* Offsets to endpoint registers in indexed model (using INDEX register) */
+#define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset)
+
+#define MUSB_TXCSR_MODE 0x2000
+
+/* "bus control"/target registers, for host side multipoint (external hubs) */
+#define MUSB_TXFUNCADDR 0x0098
+#define MUSB_TXHUBADDR 0x009A
+#define MUSB_TXHUBPORT 0x009B
+
+#define MUSB_RXFUNCADDR 0x009C
+#define MUSB_RXHUBADDR 0x009E
+#define MUSB_RXHUBPORT 0x009F
+
+/* Endpoint is selected with MUSB_INDEX. */
+#define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset)
+
+#endif /* CONFIG_ARCH_SUNXI */
+
static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
{
musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
@@ -340,7 +422,9 @@
static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
{
+#ifndef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
+#endif
}
static inline u8 musb_read_txfifosz(void __iomem *mbase)
@@ -365,7 +449,11 @@
static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
{
+#ifdef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */
+ return 0;
+#else
return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
+#endif
}
static inline u8 musb_read_configdata(void __iomem *mbase)
@@ -376,7 +464,11 @@
static inline u16 musb_read_hwvers(void __iomem *mbase)
{
+#ifdef CONFIG_ARCH_SUNXI
+ return 0; /* Unknown version */
+#else
return musb_readw(mbase, MUSB_HWVERS);
+#endif
}
static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
index 2676f09..6e58ddf 100644
--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
@@ -12,6 +12,11 @@
#include "musb_gadget.h"
#ifdef CONFIG_MUSB_HOST
+struct int_queue {
+ struct usb_host_endpoint hep;
+ struct urb urb;
+};
+
static struct musb *host;
static struct usb_hcd hcd;
static enum usb_device_speed host_speed;
@@ -25,45 +30,42 @@
static struct usb_host_endpoint hep;
static struct urb urb;
-static struct urb *construct_urb(struct usb_device *dev, int endpoint_type,
- unsigned long pipe, void *buffer, int len,
- struct devrequest *setup, int interval)
+static void construct_urb(struct urb *urb, struct usb_host_endpoint *hep,
+ struct usb_device *dev, int endpoint_type,
+ unsigned long pipe, void *buffer, int len,
+ struct devrequest *setup, int interval)
{
int epnum = usb_pipeendpoint(pipe);
int is_in = usb_pipein(pipe);
- memset(&urb, 0, sizeof(struct urb));
- memset(&hep, 0, sizeof(struct usb_host_endpoint));
- INIT_LIST_HEAD(&hep.urb_list);
- INIT_LIST_HEAD(&urb.urb_list);
- urb.ep = &hep;
- urb.complete = musb_host_complete_urb;
- urb.status = -EINPROGRESS;
- urb.dev = dev;
- urb.pipe = pipe;
- urb.transfer_buffer = buffer;
- urb.transfer_dma = (unsigned long)buffer;
- urb.transfer_buffer_length = len;
- urb.setup_packet = (unsigned char *)setup;
+ memset(urb, 0, sizeof(struct urb));
+ memset(hep, 0, sizeof(struct usb_host_endpoint));
+ INIT_LIST_HEAD(&hep->urb_list);
+ INIT_LIST_HEAD(&urb->urb_list);
+ urb->ep = hep;
+ urb->complete = musb_host_complete_urb;
+ urb->status = -EINPROGRESS;
+ urb->dev = dev;
+ urb->pipe = pipe;
+ urb->transfer_buffer = buffer;
+ urb->transfer_dma = (unsigned long)buffer;
+ urb->transfer_buffer_length = len;
+ urb->setup_packet = (unsigned char *)setup;
- urb.ep->desc.wMaxPacketSize =
+ urb->ep->desc.wMaxPacketSize =
__cpu_to_le16(is_in ? dev->epmaxpacketin[epnum] :
dev->epmaxpacketout[epnum]);
- urb.ep->desc.bmAttributes = endpoint_type;
- urb.ep->desc.bEndpointAddress =
+ urb->ep->desc.bmAttributes = endpoint_type;
+ urb->ep->desc.bEndpointAddress =
(is_in ? USB_DIR_IN : USB_DIR_OUT) | epnum;
- urb.ep->desc.bInterval = interval;
-
- return &urb;
+ urb->ep->desc.bInterval = interval;
}
-#define MUSB_HOST_TIMEOUT 0x3ffffff
-
static int submit_urb(struct usb_hcd *hcd, struct urb *urb)
{
struct musb *host = hcd->hcd_priv;
int ret;
- int timeout;
+ unsigned long timeout;
ret = musb_urb_enqueue(hcd, urb, 0);
if (ret < 0) {
@@ -71,12 +73,16 @@
return ret;
}
- timeout = MUSB_HOST_TIMEOUT;
+ timeout = get_timer(0) + USB_TIMEOUT_MS(urb->pipe);
do {
if (ctrlc())
return -EIO;
host->isr(0, host);
- } while ((urb->dev->status & USB_ST_NOT_PROC) && --timeout);
+ } while (urb->status == -EINPROGRESS &&
+ get_timer(0) < timeout);
+
+ if (urb->status == -EINPROGRESS)
+ musb_urb_dequeue(hcd, urb, -ETIME);
return urb->status;
}
@@ -84,38 +90,117 @@
int submit_control_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int len, struct devrequest *setup)
{
- struct urb *urb = construct_urb(dev, USB_ENDPOINT_XFER_CONTROL, pipe,
- buffer, len, setup, 0);
+ construct_urb(&urb, &hep, dev, USB_ENDPOINT_XFER_CONTROL, pipe,
+ buffer, len, setup, 0);
/* Fix speed for non hub-attached devices */
if (!dev->parent)
dev->speed = host_speed;
- return submit_urb(&hcd, urb);
+ return submit_urb(&hcd, &urb);
}
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int len)
{
- struct urb *urb = construct_urb(dev, USB_ENDPOINT_XFER_BULK, pipe,
- buffer, len, NULL, 0);
- return submit_urb(&hcd, urb);
+ construct_urb(&urb, &hep, dev, USB_ENDPOINT_XFER_BULK, pipe,
+ buffer, len, NULL, 0);
+ return submit_urb(&hcd, &urb);
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int len, int interval)
{
- struct urb *urb = construct_urb(dev, USB_ENDPOINT_XFER_INT, pipe,
- buffer, len, NULL, interval);
- return submit_urb(&hcd, urb);
+ construct_urb(&urb, &hep, dev, USB_ENDPOINT_XFER_INT, pipe,
+ buffer, len, NULL, interval);
+ return submit_urb(&hcd, &urb);
+}
+
+struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe,
+ int queuesize, int elementsize, void *buffer, int interval)
+{
+ struct int_queue *queue;
+ int ret, index = usb_pipein(pipe) * 16 + usb_pipeendpoint(pipe);
+
+ if (queuesize != 1) {
+ printf("ERROR musb int-queues only support queuesize 1\n");
+ return NULL;
+ }
+
+ if (dev->int_pending & (1 << index)) {
+ printf("ERROR int-urb is already pending on pipe %lx\n", pipe);
+ return NULL;
+ }
+
+ queue = malloc(sizeof(*queue));
+ if (!queue)
+ return NULL;
+
+ construct_urb(&queue->urb, &queue->hep, dev, USB_ENDPOINT_XFER_INT,
+ pipe, buffer, elementsize, NULL, interval);
+
+ ret = musb_urb_enqueue(&hcd, &queue->urb, 0);
+ if (ret < 0) {
+ printf("Failed to enqueue URB to controller\n");
+ free(queue);
+ return NULL;
+ }
+
+ dev->int_pending |= 1 << index;
+ return queue;
+}
+
+int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
+{
+ int index = usb_pipein(queue->urb.pipe) * 16 +
+ usb_pipeendpoint(queue->urb.pipe);
+
+ if (queue->urb.status == -EINPROGRESS)
+ musb_urb_dequeue(&hcd, &queue->urb, -ETIME);
+
+ dev->int_pending &= ~(1 << index);
+ free(queue);
+ return 0;
+}
+
+void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
+{
+ if (queue->urb.status != -EINPROGRESS)
+ return NULL; /* URB has already completed in a prev. poll */
+
+ host->isr(0, host);
+
+ if (queue->urb.status != -EINPROGRESS)
+ return queue->urb.transfer_buffer; /* Done */
+
+ return NULL; /* URB still pending */
+}
+
+void usb_reset_root_port(void)
+{
+ void *mbase = host->mregs;
+ u8 power;
+
+ power = musb_readb(mbase, MUSB_POWER);
+ power &= 0xf0;
+ musb_writeb(mbase, MUSB_POWER, MUSB_POWER_RESET | power);
+ mdelay(50);
+ power = musb_readb(mbase, MUSB_POWER);
+ musb_writeb(mbase, MUSB_POWER, ~MUSB_POWER_RESET & power);
+ host->isr(0, host);
+ host_speed = (musb_readb(mbase, MUSB_POWER) & MUSB_POWER_HSMODE) ?
+ USB_SPEED_HIGH :
+ (musb_readb(mbase, MUSB_DEVCTL) & MUSB_DEVCTL_FSDEV) ?
+ USB_SPEED_FULL : USB_SPEED_LOW;
+ mdelay((host_speed == USB_SPEED_LOW) ? 200 : 50);
}
int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
{
- u8 power;
void *mbase;
- int timeout = MUSB_HOST_TIMEOUT;
+ /* USB spec says it may take up to 1 second for a device to connect */
+ unsigned long timeout = get_timer(0) + 1000;
if (!host) {
printf("MUSB host is not registered\n");
@@ -127,20 +212,11 @@
do {
if (musb_readb(mbase, MUSB_DEVCTL) & MUSB_DEVCTL_HM)
break;
- } while (--timeout);
- if (!timeout)
+ } while (get_timer(0) < timeout);
+ if (get_timer(0) >= timeout)
return -ENODEV;
- power = musb_readb(mbase, MUSB_POWER);
- musb_writeb(mbase, MUSB_POWER, MUSB_POWER_RESET | power);
- udelay(30000);
- power = musb_readb(mbase, MUSB_POWER);
- musb_writeb(mbase, MUSB_POWER, ~MUSB_POWER_RESET & power);
- host->isr(0, host);
- host_speed = (musb_readb(mbase, MUSB_POWER) & MUSB_POWER_HSMODE) ?
- USB_SPEED_HIGH :
- (musb_readb(mbase, MUSB_DEVCTL) & MUSB_DEVCTL_FSDEV) ?
- USB_SPEED_FULL : USB_SPEED_LOW;
+ usb_reset_root_port();
host->is_active = 1;
hcd.hcd_priv = host;
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
new file mode 100644
index 0000000..778916d
--- /dev/null
+++ b/drivers/usb/musb-new/sunxi.c
@@ -0,0 +1,279 @@
+/*
+ * Allwinner SUNXI "glue layer"
+ *
+ * Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
+ * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
+ *
+ * Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
+ * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
+ * javen <javen@allwinnertech.com>
+ *
+ * Based on the DA8xx "glue layer" code.
+ * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
+ * Copyright (C) 2005-2006 by Texas Instruments
+ *
+ * This file is part of the Inventra Controller Driver for Linux.
+ *
+ * The Inventra Controller Driver for Linux is free software; you
+ * can redistribute it and/or modify it under the terms of the GNU
+ * General Public License version 2 as published by the Free Software
+ * Foundation.
+ *
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/usbc.h>
+#include "linux-compat.h"
+#include "musb_core.h"
+
+/******************************************************************************
+ ******************************************************************************
+ * From the Allwinner driver
+ ******************************************************************************
+ ******************************************************************************/
+
+/******************************************************************************
+ * From include/sunxi_usb_bsp.h
+ ******************************************************************************/
+
+/* reg offsets */
+#define USBC_REG_o_ISCR 0x0400
+#define USBC_REG_o_PHYCTL 0x0404
+#define USBC_REG_o_PHYBIST 0x0408
+#define USBC_REG_o_PHYTUNE 0x040c
+
+#define USBC_REG_o_VEND0 0x0043
+
+/* Interface Status and Control */
+#define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
+#define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
+#define USBC_BP_ISCR_EXT_ID_STATUS 28
+#define USBC_BP_ISCR_EXT_DM_STATUS 27
+#define USBC_BP_ISCR_EXT_DP_STATUS 26
+#define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
+#define USBC_BP_ISCR_MERGED_ID_STATUS 24
+
+#define USBC_BP_ISCR_ID_PULLUP_EN 17
+#define USBC_BP_ISCR_DPDM_PULLUP_EN 16
+#define USBC_BP_ISCR_FORCE_ID 14
+#define USBC_BP_ISCR_FORCE_VBUS_VALID 12
+#define USBC_BP_ISCR_VBUS_VALID_SRC 10
+
+#define USBC_BP_ISCR_HOSC_EN 7
+#define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
+#define USBC_BP_ISCR_ID_CHANGE_DETECT 5
+#define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
+#define USBC_BP_ISCR_IRQ_ENABLE 3
+#define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
+#define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
+#define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
+
+/******************************************************************************
+ * From usbc/usbc.c
+ ******************************************************************************/
+
+static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
+{
+ u32 temp = reg_val;
+
+ temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
+ temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
+ temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
+
+ return temp;
+}
+
+static void USBC_EnableIdPullUp(__iomem void *base)
+{
+ u32 reg_val;
+
+ reg_val = musb_readl(base, USBC_REG_o_ISCR);
+ reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
+ reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+ musb_writel(base, USBC_REG_o_ISCR, reg_val);
+}
+
+static void USBC_DisableIdPullUp(__iomem void *base)
+{
+ u32 reg_val;
+
+ reg_val = musb_readl(base, USBC_REG_o_ISCR);
+ reg_val &= ~(1 << USBC_BP_ISCR_ID_PULLUP_EN);
+ reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+ musb_writel(base, USBC_REG_o_ISCR, reg_val);
+}
+
+static void USBC_EnableDpDmPullUp(__iomem void *base)
+{
+ u32 reg_val;
+
+ reg_val = musb_readl(base, USBC_REG_o_ISCR);
+ reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
+ reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+ musb_writel(base, USBC_REG_o_ISCR, reg_val);
+}
+
+static void USBC_DisableDpDmPullUp(__iomem void *base)
+{
+ u32 reg_val;
+
+ reg_val = musb_readl(base, USBC_REG_o_ISCR);
+ reg_val &= ~(1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
+ reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+ musb_writel(base, USBC_REG_o_ISCR, reg_val);
+}
+
+static void USBC_ForceIdToLow(__iomem void *base)
+{
+ u32 reg_val;
+
+ reg_val = musb_readl(base, USBC_REG_o_ISCR);
+ reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
+ reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
+ reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+ musb_writel(base, USBC_REG_o_ISCR, reg_val);
+}
+
+static void USBC_ForceIdToHigh(__iomem void *base)
+{
+ u32 reg_val;
+
+ reg_val = musb_readl(base, USBC_REG_o_ISCR);
+ reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
+ reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
+ reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+ musb_writel(base, USBC_REG_o_ISCR, reg_val);
+}
+
+static void USBC_ForceVbusValidDisable(__iomem void *base)
+{
+ u32 reg_val;
+
+ reg_val = musb_readl(base, USBC_REG_o_ISCR);
+ reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
+ reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+ musb_writel(base, USBC_REG_o_ISCR, reg_val);
+}
+
+static void USBC_ForceVbusValidToHigh(__iomem void *base)
+{
+ u32 reg_val;
+
+ reg_val = musb_readl(base, USBC_REG_o_ISCR);
+ reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
+ reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
+ reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+ musb_writel(base, USBC_REG_o_ISCR, reg_val);
+}
+
+static void USBC_ConfigFIFO_Base(void)
+{
+ u32 reg_value;
+
+ /* config usb fifo, 8kb mode */
+ reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
+ reg_value &= ~(0x03 << 0);
+ reg_value |= (1 << 0);
+ writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
+}
+
+/******************************************************************************
+ * MUSB Glue code
+ ******************************************************************************/
+
+static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
+{
+ struct musb *musb = __hci;
+ irqreturn_t retval = IRQ_NONE;
+
+ /* read and flush interrupts */
+ musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+ if (musb->int_usb)
+ musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
+ musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
+ if (musb->int_tx)
+ musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
+ musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
+ if (musb->int_rx)
+ musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
+
+ if (musb->int_usb || musb->int_tx || musb->int_rx)
+ retval |= musb_interrupt(musb);
+
+ return retval;
+}
+
+static void sunxi_musb_enable(struct musb *musb)
+{
+ pr_debug("%s():\n", __func__);
+
+ /* select PIO mode */
+ musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
+
+ if (is_host_enabled(musb)) {
+ /* port power on */
+ sunxi_usbc_vbus_enable(0);
+ }
+}
+
+static void sunxi_musb_disable(struct musb *musb)
+{
+ pr_debug("%s():\n", __func__);
+
+ /* Put the controller back in a pristane state for "usb reset" */
+ if (musb->is_active) {
+ sunxi_usbc_disable(0);
+ sunxi_usbc_enable(0);
+ musb->is_active = 0;
+ }
+}
+
+static int sunxi_musb_init(struct musb *musb)
+{
+ int err;
+
+ pr_debug("%s():\n", __func__);
+
+ err = sunxi_usbc_request_resources(0);
+ if (err)
+ return err;
+
+ musb->isr = sunxi_musb_interrupt;
+ sunxi_usbc_enable(0);
+
+ USBC_ConfigFIFO_Base();
+ USBC_EnableDpDmPullUp(musb->mregs);
+ USBC_EnableIdPullUp(musb->mregs);
+
+ if (is_host_enabled(musb)) {
+ /* Host mode */
+ USBC_ForceIdToLow(musb->mregs);
+ USBC_ForceVbusValidToHigh(musb->mregs);
+ } else {
+ /* Peripheral mode */
+ USBC_ForceIdToHigh(musb->mregs);
+ USBC_ForceVbusValidDisable(musb->mregs);
+ }
+
+ return 0;
+}
+
+static int sunxi_musb_exit(struct musb *musb)
+{
+ pr_debug("%s():\n", __func__);
+
+ USBC_DisableDpDmPullUp(musb->mregs);
+ USBC_DisableIdPullUp(musb->mregs);
+ sunxi_usbc_vbus_disable(0);
+ sunxi_usbc_disable(0);
+
+ return sunxi_usbc_free_resources(0);
+}
+
+const struct musb_platform_ops sunxi_musb_ops = {
+ .init = sunxi_musb_init,
+ .exit = sunxi_musb_exit,
+
+ .enable = sunxi_musb_enable,
+ .disable = sunxi_musb_disable,
+};
diff --git a/drivers/usb/musb-new/usb-compat.h b/drivers/usb/musb-new/usb-compat.h
index 27f656f..50bad37 100644
--- a/drivers/usb/musb-new/usb-compat.h
+++ b/drivers/usb/musb-new/usb-compat.h
@@ -48,6 +48,7 @@
list_add_tail(&urb->urb_list, &urb->ep->urb_list); \
ret; })
#define usb_hcd_unlink_urb_from_ep(hcd, urb) list_del_init(&urb->urb_list)
+#define usb_hcd_check_unlink_urb(hdc, urb, status) 0
static inline void usb_hcd_giveback_urb(struct usb_hcd *hcd,
struct urb *urb,
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index e69de29..ccbd7e2 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -0,0 +1,89 @@
+config VIDEO_X86
+ bool "Enable x86 video driver support"
+ depends on X86
+ default n
+ help
+ Turn on this option to enable a very simple driver which uses vesa
+ to discover the video mode and then provides a frame buffer for use
+ by U-Boot.
+
+config VIDEO_LCD_SSD2828
+ bool "SSD2828 bridge chip"
+ default n
+ ---help---
+ Support for the SSD2828 bridge chip, which can take pixel data coming
+ from a parallel LCD interface and translate it on the fly into MIPI DSI
+ interface for driving a MIPI compatible LCD panel. It uses SPI for
+ configuration.
+
+config VIDEO_LCD_SSD2828_TX_CLK
+ int "SSD2828 TX_CLK frequency (in MHz)"
+ depends on VIDEO_LCD_SSD2828
+ default 0
+ ---help---
+ The frequency of the crystal, which is clocking SSD2828. It may be
+ anything in the 8MHz-30MHz range and the exact value should be
+ retrieved from the board schematics. Or in the case of Allwinner
+ hardware, it can be usually found as 'lcd_xtal_freq' variable in
+ FEX files. It can be also set to 0 for selecting PCLK from the
+ parallel LCD interface instead of TX_CLK as the PLL clock source.
+
+config VIDEO_LCD_SSD2828_RESET
+ string "RESET pin of SSD2828"
+ depends on VIDEO_LCD_SSD2828
+ default ""
+ ---help---
+ The reset pin of SSD2828 chip. This takes a string in the format
+ understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+
+config VIDEO_LCD_HITACHI_TX18D42VM
+ bool "Hitachi tx18d42vm LVDS LCD panel support"
+ depends on VIDEO
+ default n
+ ---help---
+ Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
+ lcd controller which needs to be initialized over SPI, once that is
+ done they work like a regular LVDS panel.
+
+config VIDEO_LCD_SPI_CS
+ string "SPI CS pin for LCD related config job"
+ depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
+ default ""
+ ---help---
+ This is one of the SPI communication pins, involved in setting up a
+ working LCD configuration. The exact role of SPI may differ for
+ different hardware setups. The option takes a string in the format
+ understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+
+config VIDEO_LCD_SPI_SCLK
+ string "SPI SCLK pin for LCD related config job"
+ depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
+ default ""
+ ---help---
+ This is one of the SPI communication pins, involved in setting up a
+ working LCD configuration. The exact role of SPI may differ for
+ different hardware setups. The option takes a string in the format
+ understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+
+config VIDEO_LCD_SPI_MOSI
+ string "SPI MOSI pin for LCD related config job"
+ depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
+ default ""
+ ---help---
+ This is one of the SPI communication pins, involved in setting up a
+ working LCD configuration. The exact role of SPI may differ for
+ different hardware setups. The option takes a string in the format
+ understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+
+config VIDEO_LCD_SPI_MISO
+ string "SPI MISO pin for LCD related config job (optional)"
+ depends on VIDEO_LCD_SSD2828
+ default ""
+ ---help---
+ This is one of the SPI communication pins, involved in setting up a
+ working LCD configuration. The exact role of SPI may differ for
+ different hardware setups. If wired up, this pin may provide additional
+ useful functionality. Such as bi-directional communication with the
+ hardware and LCD panel id retrieval (if the panel can report it). The
+ option takes a string in the format understood by 'name_to_gpio'
+ function, e.g. PH1 for pin 1 of port H.
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 00b563f..c3fcf45 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -29,6 +29,8 @@
obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o
+obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
@@ -39,7 +41,7 @@
obj-$(CONFIG_VIDEO_SED13806) += sed13806.o
obj-$(CONFIG_VIDEO_SM501) += sm501.o
obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
-obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o
+obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_VIDEO_X86) += x86_fb.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index a653bb4..d4226e3 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -117,24 +117,11 @@
* Defines for the SED13806 driver
*/
#ifdef CONFIG_VIDEO_SED13806
-
-#ifndef CONFIG_TOTAL5200
#define VIDEO_FB_LITTLE_ENDIAN
-#endif
#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT
#endif
-/*
- * Defines for the SED13806 driver
- */
-#ifdef CONFIG_VIDEO_SM501
-
-#ifdef CONFIG_HH405
-#define VIDEO_FB_LITTLE_ENDIAN
-#endif
-#endif
-
#ifdef CONFIG_VIDEO_MXS
#define VIDEO_FB_16BPP_WORD_SWAP
#endif
diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c
new file mode 100644
index 0000000..1ce4a8c
--- /dev/null
+++ b/drivers/video/hitachi_tx18d42vm_lcd.c
@@ -0,0 +1,81 @@
+/*
+ * Hitachi tx18d42vm LVDS LCD panel driver
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/gpio.h>
+#include <errno.h>
+
+/*
+ * Very simple write only SPI support, this does not use the generic SPI infra
+ * because that assumes R/W SPI, requiring a MISO pin. Also the necessary glue
+ * code alone would be larger then this minimal version.
+ */
+static void lcd_panel_spi_write(int cs, int clk, int mosi,
+ unsigned int data, int bits)
+{
+ int i, offset;
+
+ gpio_direction_output(cs, 0);
+ for (i = 0; i < bits; i++) {
+ gpio_direction_output(clk, 0);
+ offset = (bits - 1) - i;
+ gpio_direction_output(mosi, (data >> offset) & 1);
+ udelay(2);
+ gpio_direction_output(clk, 1);
+ udelay(2);
+ }
+ gpio_direction_output(cs, 1);
+ udelay(2);
+}
+
+int hitachi_tx18d42vm_init(void)
+{
+ const u16 init_data[] = {
+ 0x0029, /* reset */
+ 0x0025, /* standby */
+ 0x0840, /* enable normally black */
+ 0x0430, /* enable FRC/dither */
+ 0x385f, /* enter test mode(1) */
+ 0x3ca4, /* enter test mode(2) */
+ 0x3409, /* enable SDRRS, enlarge OE width */
+ 0x4041, /* adopt 2 line / 1 dot */
+ };
+ int i, cs, clk, mosi, ret = 0;
+
+ cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS);
+ clk = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK);
+ mosi = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI);
+
+ if (cs == -1 || clk == -1 || mosi == 1) {
+ printf("Error tx18d42vm spi gpio config is invalid\n");
+ return -EINVAL;
+ }
+
+ if (gpio_request(cs, "tx18d42vm-spi-cs") != 0 ||
+ gpio_request(clk, "tx18d42vm-spi-clk") != 0 ||
+ gpio_request(mosi, "tx18d42vm-spi-mosi") != 0) {
+ printf("Error cannot request tx18d42vm spi gpios\n");
+ ret = -EBUSY;
+ goto out;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(init_data); i++)
+ lcd_panel_spi_write(cs, clk, mosi, init_data[i], 16);
+
+ mdelay(50); /* All the tx18d42vm drivers have a delay here ? */
+
+ lcd_panel_spi_write(cs, clk, mosi, 0x00ad, 16); /* display on */
+
+out:
+ gpio_free(mosi);
+ gpio_free(clk);
+ gpio_free(cs);
+
+ return ret;
+}
diff --git a/drivers/video/hitachi_tx18d42vm_lcd.h b/drivers/video/hitachi_tx18d42vm_lcd.h
new file mode 100644
index 0000000..1b72800
--- /dev/null
+++ b/drivers/video/hitachi_tx18d42vm_lcd.h
@@ -0,0 +1,9 @@
+/*
+ * Hitachi tx18d42vm LVDS LCD panel driver
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+void hitachi_tx18d42vm_init(void);
diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c
index 50eed89..add7215 100644
--- a/drivers/video/mpc8xx_lcd.c
+++ b/drivers/video/mpc8xx_lcd.c
@@ -34,11 +34,6 @@
#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
#endif
-#if defined(CONFIG_EDT32F10)
-#undef CONFIG_LCD_LOGO
-#undef CONFIG_LCD_INFO
-#endif
-
/*----------------------------------------------------------------------*/
#ifdef CONFIG_KYOCERA_KCS057QV1AJ
/*
@@ -224,20 +219,6 @@
};
#endif /* CONFIG_OPTREX_BW */
-/*-----------------------------------------------------------------*/
-#ifdef CONFIG_EDT32F10
-/*
- * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
- */
-#define LCD_BPP LCD_MONOCHROME
-#define LCD_DF 10
-
-vidinfo_t panel_info = {
- 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
- LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0
-};
-#endif
-
/************************************************************************/
/* ----------------- chipset specific functions ----------------------- */
/************************************************************************/
@@ -305,7 +286,6 @@
immr->im_clkrst.car_sccr &= ~0x1F;
immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */
-#if !defined(CONFIG_EDT32F10)
/* Enable LCD on port D.
*/
immr->im_ioport.iop_pdpar |= 0x1FFF;
@@ -315,14 +295,6 @@
*/
immr->im_cpm.cp_pbpar |= 0x00005001;
immr->im_cpm.cp_pbdir |= 0x00005001;
-#else
- /* Enable LCD on port D.
- */
- immr->im_ioport.iop_pdpar |= 0x1DFF;
- immr->im_ioport.iop_pdpar &= ~0x0200;
- immr->im_ioport.iop_pddir |= 0x1FFF;
- immr->im_ioport.iop_pddat |= 0x0200;
-#endif
/* Load the physical address of the linear frame buffer
* into the LCD controller.
@@ -373,9 +345,7 @@
colreg = ((red & 0x0F) << 8) |
((green & 0x0F) << 4) |
(blue & 0x0F) ;
-#ifdef CONFIG_SYS_INVERT_COLORS
- colreg ^= 0x0FFF;
-#endif
+
*cmap_ptr = colreg;
debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
@@ -387,23 +357,6 @@
/*----------------------------------------------------------------------*/
-#if LCD_BPP == LCD_MONOCHROME
-static
-void lcd_initcolregs (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cp = &(immr->im_cpm);
- ushort regno;
-
- for (regno = 0; regno < 16; regno++) {
- cp->lcd_cmap[regno * 2] = 0;
- cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
- }
-}
-#endif
-
-/*----------------------------------------------------------------------*/
-
void lcd_enable (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
index e19f6ac..f66f615 100644
--- a/drivers/video/pxa_lcd.c
+++ b/drivers/video/pxa_lcd.c
@@ -379,21 +379,6 @@
#endif /* LCD_COLOR8 */
/*----------------------------------------------------------------------*/
-#if LCD_BPP == LCD_MONOCHROME
-void lcd_initcolregs (void)
-{
- struct pxafb_info *fbi = &panel_info.pxa;
- cmap = (ushort *)fbi->palette;
- ushort regno;
-
- for (regno = 0; regno < 16; regno++) {
- cmap[regno * 2] = 0;
- cmap[(regno * 2) + 1] = regno & 0x0f;
- }
-}
-#endif /* LCD_MONOCHROME */
-
-/*----------------------------------------------------------------------*/
__weak void lcd_enable(void)
{
}
diff --git a/drivers/video/sed13806.c b/drivers/video/sed13806.c
index da653c0..cd7fac6 100644
--- a/drivers/video/sed13806.c
+++ b/drivers/video/sed13806.c
@@ -18,13 +18,8 @@
#define writeByte(ptrReg,value) \
*(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value
-#ifdef CONFIG_TOTAL5200
-#define writeWord(ptrReg,value) \
- (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = value)
-#else
#define writeWord(ptrReg,value) \
(*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00))
-#endif
GraphicDevice sed13806;
diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c
new file mode 100644
index 0000000..8b09082
--- /dev/null
+++ b/drivers/video/ssd2828.c
@@ -0,0 +1,436 @@
+/*
+ * (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Support for the SSD2828 bridge chip, which can take pixel data coming
+ * from a parallel LCD interface and translate it on the flight into MIPI DSI
+ * interface for driving a MIPI compatible TFT display.
+ */
+
+#include <common.h>
+#include <mipi_display.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+
+#include "videomodes.h"
+#include "ssd2828.h"
+
+#define SSD2828_DIR 0xB0
+#define SSD2828_VICR1 0xB1
+#define SSD2828_VICR2 0xB2
+#define SSD2828_VICR3 0xB3
+#define SSD2828_VICR4 0xB4
+#define SSD2828_VICR5 0xB5
+#define SSD2828_VICR6 0xB6
+#define SSD2828_CFGR 0xB7
+#define SSD2828_VCR 0xB8
+#define SSD2828_PCR 0xB9
+#define SSD2828_PLCR 0xBA
+#define SSD2828_CCR 0xBB
+#define SSD2828_PSCR1 0xBC
+#define SSD2828_PSCR2 0xBD
+#define SSD2828_PSCR3 0xBE
+#define SSD2828_PDR 0xBF
+#define SSD2828_OCR 0xC0
+#define SSD2828_MRSR 0xC1
+#define SSD2828_RDCR 0xC2
+#define SSD2828_ARSR 0xC3
+#define SSD2828_LCR 0xC4
+#define SSD2828_ICR 0xC5
+#define SSD2828_ISR 0xC6
+#define SSD2828_ESR 0xC7
+#define SSD2828_DAR1 0xC9
+#define SSD2828_DAR2 0xCA
+#define SSD2828_DAR3 0xCB
+#define SSD2828_DAR4 0xCC
+#define SSD2828_DAR5 0xCD
+#define SSD2828_DAR6 0xCE
+#define SSD2828_HTTR1 0xCF
+#define SSD2828_HTTR2 0xD0
+#define SSD2828_LRTR1 0xD1
+#define SSD2828_LRTR2 0xD2
+#define SSD2828_TSR 0xD3
+#define SSD2828_LRR 0xD4
+#define SSD2828_PLLR 0xD5
+#define SSD2828_TR 0xD6
+#define SSD2828_TECR 0xD7
+#define SSD2828_ACR1 0xD8
+#define SSD2828_ACR2 0xD9
+#define SSD2828_ACR3 0xDA
+#define SSD2828_ACR4 0xDB
+#define SSD2828_IOCR 0xDC
+#define SSD2828_VICR7 0xDD
+#define SSD2828_LCFR 0xDE
+#define SSD2828_DAR7 0xDF
+#define SSD2828_PUCR1 0xE0
+#define SSD2828_PUCR2 0xE1
+#define SSD2828_PUCR3 0xE2
+#define SSD2828_CBCR1 0xE9
+#define SSD2828_CBCR2 0xEA
+#define SSD2828_CBSR 0xEB
+#define SSD2828_ECR 0xEC
+#define SSD2828_VSDR 0xED
+#define SSD2828_TMR 0xEE
+#define SSD2828_GPIO1 0xEF
+#define SSD2828_GPIO2 0xF0
+#define SSD2828_DLYA01 0xF1
+#define SSD2828_DLYA23 0xF2
+#define SSD2828_DLYB01 0xF3
+#define SSD2828_DLYB23 0xF4
+#define SSD2828_DLYC01 0xF5
+#define SSD2828_DLYC23 0xF6
+#define SSD2828_ACR5 0xF7
+#define SSD2828_RR 0xFF
+
+#define SSD2828_CFGR_HS (1 << 0)
+#define SSD2828_CFGR_CKE (1 << 1)
+#define SSD2828_CFGR_SLP (1 << 2)
+#define SSD2828_CFGR_VEN (1 << 3)
+#define SSD2828_CFGR_HCLK (1 << 4)
+#define SSD2828_CFGR_CSS (1 << 5)
+#define SSD2828_CFGR_DCS (1 << 6)
+#define SSD2828_CFGR_REN (1 << 7)
+#define SSD2828_CFGR_ECD (1 << 8)
+#define SSD2828_CFGR_EOT (1 << 9)
+#define SSD2828_CFGR_LPE (1 << 10)
+#define SSD2828_CFGR_TXD (1 << 11)
+
+#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES (0 << 2)
+#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (1 << 2)
+#define SSD2828_VIDEO_MODE_BURST (2 << 2)
+
+#define SSD2828_VIDEO_PIXEL_FORMAT_16BPP 0
+#define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED 1
+#define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED 2
+#define SSD2828_VIDEO_PIXEL_FORMAT_24BPP 3
+
+#define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F)
+
+/*
+ * SPI transfer, using the "24-bit 3 wire" mode (that's how it is called in
+ * the SSD2828 documentation). The 'dout' input parameter specifies 24-bits
+ * of data to be written to SSD2828. Returns the lowest 16-bits of data,
+ * that is received back.
+ */
+static u32 soft_spi_xfer_24bit_3wire(const struct ssd2828_config *drv, u32 dout)
+{
+ int j, bitlen = 24;
+ u32 tmpdin = 0;
+ /*
+ * According to the "24 Bit 3 Wire SPI Interface Timing Characteristics"
+ * and "TX_CLK Timing Characteristics" tables in the SSD2828 datasheet,
+ * the lowest possible 'tx_clk' clock frequency is 8MHz, and SPI runs
+ * at 1/8 of that after reset. So using 1 microsecond delays is safe in
+ * the main loop. But the delays around chip select pin manipulations
+ * need to be longer (up to 16 'tx_clk' cycles, or 2 microseconds in
+ * the worst case).
+ */
+ const int spi_delay_us = 1;
+ const int spi_cs_delay_us = 2;
+
+ gpio_set_value(drv->csx_pin, 0);
+ udelay(spi_cs_delay_us);
+ for (j = bitlen - 1; j >= 0; j--) {
+ gpio_set_value(drv->sck_pin, 0);
+ gpio_set_value(drv->sdi_pin, (dout & (1 << j)) != 0);
+ udelay(spi_delay_us);
+ if (drv->sdo_pin != -1)
+ tmpdin = (tmpdin << 1) | gpio_get_value(drv->sdo_pin);
+ gpio_set_value(drv->sck_pin, 1);
+ udelay(spi_delay_us);
+ }
+ udelay(spi_cs_delay_us);
+ gpio_set_value(drv->csx_pin, 1);
+ udelay(spi_cs_delay_us);
+ return tmpdin & 0xFFFF;
+}
+
+/*
+ * Read from a SSD2828 hardware register (regnum >= 0xB0)
+ */
+static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum)
+{
+ soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
+ return soft_spi_xfer_24bit_3wire(cfg, 0x730000);
+}
+
+/*
+ * Write to a SSD2828 hardware register (regnum >= 0xB0)
+ */
+static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum,
+ u16 val)
+{
+ soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
+ soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val);
+}
+
+/*
+ * Send MIPI command to the LCD panel (cmdnum < 0xB0)
+ */
+static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum)
+{
+ /* Set packet size to 1 (a single command with no parameters) */
+ write_hw_register(cfg, SSD2828_PSCR1, 1);
+ /* Send the command */
+ write_hw_register(cfg, SSD2828_PDR, cmdnum);
+}
+
+/*
+ * Reset SSD2828
+ */
+static void ssd2828_reset(const struct ssd2828_config *cfg)
+{
+ /* RESET needs 10 milliseconds according to the datasheet */
+ gpio_set_value(cfg->reset_pin, 0);
+ mdelay(10);
+ gpio_set_value(cfg->reset_pin, 1);
+ mdelay(10);
+}
+
+static int ssd2828_enable_gpio(const struct ssd2828_config *cfg)
+{
+ if (gpio_request(cfg->csx_pin, "ssd2828_csx")) {
+ printf("SSD2828: request for 'ssd2828_csx' pin failed\n");
+ return 1;
+ }
+ if (gpio_request(cfg->sck_pin, "ssd2828_sck")) {
+ gpio_free(cfg->csx_pin);
+ printf("SSD2828: request for 'ssd2828_sck' pin failed\n");
+ return 1;
+ }
+ if (gpio_request(cfg->sdi_pin, "ssd2828_sdi")) {
+ gpio_free(cfg->csx_pin);
+ gpio_free(cfg->sck_pin);
+ printf("SSD2828: request for 'ssd2828_sdi' pin failed\n");
+ return 1;
+ }
+ if (gpio_request(cfg->reset_pin, "ssd2828_reset")) {
+ gpio_free(cfg->csx_pin);
+ gpio_free(cfg->sck_pin);
+ gpio_free(cfg->sdi_pin);
+ printf("SSD2828: request for 'ssd2828_reset' pin failed\n");
+ return 1;
+ }
+ if (cfg->sdo_pin != -1 && gpio_request(cfg->sdo_pin, "ssd2828_sdo")) {
+ gpio_free(cfg->csx_pin);
+ gpio_free(cfg->sck_pin);
+ gpio_free(cfg->sdi_pin);
+ gpio_free(cfg->reset_pin);
+ printf("SSD2828: request for 'ssd2828_sdo' pin failed\n");
+ return 1;
+ }
+ gpio_direction_output(cfg->reset_pin, 0);
+ gpio_direction_output(cfg->csx_pin, 1);
+ gpio_direction_output(cfg->sck_pin, 1);
+ gpio_direction_output(cfg->sdi_pin, 1);
+ if (cfg->sdo_pin != -1)
+ gpio_direction_input(cfg->sdo_pin);
+
+ return 0;
+}
+
+static int ssd2828_free_gpio(const struct ssd2828_config *cfg)
+{
+ gpio_free(cfg->csx_pin);
+ gpio_free(cfg->sck_pin);
+ gpio_free(cfg->sdi_pin);
+ gpio_free(cfg->reset_pin);
+ if (cfg->sdo_pin != -1)
+ gpio_free(cfg->sdo_pin);
+ return 1;
+}
+
+/*
+ * PLL configuration register settings.
+ *
+ * See the "PLL Configuration Register Description" in the SSD2828 datasheet.
+ */
+static u32 construct_pll_config(u32 desired_pll_freq_kbps,
+ u32 reference_freq_khz)
+{
+ u32 div_factor = 1, mul_factor, fr = 0;
+ u32 output_freq_kbps;
+
+ /* The intermediate clock after division can't be less than 5MHz */
+ while (reference_freq_khz / (div_factor + 1) >= 5000)
+ div_factor++;
+ if (div_factor > 31)
+ div_factor = 31;
+
+ mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
+ reference_freq_khz);
+
+ output_freq_kbps = reference_freq_khz * mul_factor / div_factor;
+
+ if (output_freq_kbps >= 501000)
+ fr = 3;
+ else if (output_freq_kbps >= 251000)
+ fr = 2;
+ else if (output_freq_kbps >= 126000)
+ fr = 1;
+
+ return (fr << 14) | (div_factor << 8) | mul_factor;
+}
+
+static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz)
+{
+ u32 mul_factor = pll_config & 0xFF;
+ u32 div_factor = (pll_config >> 8) & 0x1F;
+ if (mul_factor == 0)
+ mul_factor = 1;
+ if (div_factor == 0)
+ div_factor = 1;
+ return reference_freq_khz * mul_factor / div_factor;
+}
+
+static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg,
+ const struct ctfb_res_modes *mode)
+{
+ u32 val;
+
+ /* RGB Interface Control Register 1 */
+ write_hw_register(cfg, SSD2828_VICR1, (mode->vsync_len << 8) |
+ (mode->hsync_len));
+
+ /* RGB Interface Control Register 2 */
+ u32 vbp = mode->vsync_len + mode->upper_margin;
+ u32 hbp = mode->hsync_len + mode->left_margin;
+ write_hw_register(cfg, SSD2828_VICR2, (vbp << 8) | hbp);
+
+ /* RGB Interface Control Register 3 */
+ write_hw_register(cfg, SSD2828_VICR3, (mode->lower_margin << 8) |
+ (mode->right_margin));
+
+ /* RGB Interface Control Register 4 */
+ write_hw_register(cfg, SSD2828_VICR4, mode->xres);
+
+ /* RGB Interface Control Register 5 */
+ write_hw_register(cfg, SSD2828_VICR5, mode->yres);
+
+ /* RGB Interface Control Register 6 */
+ val = SSD2828_VIDEO_MODE_BURST;
+ switch (cfg->ssd2828_color_depth) {
+ case 16:
+ val |= SSD2828_VIDEO_PIXEL_FORMAT_16BPP;
+ break;
+ case 18:
+ val |= cfg->mipi_dsi_loosely_packed_pixel_format ?
+ SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED :
+ SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED;
+ break;
+ case 24:
+ val |= SSD2828_VIDEO_PIXEL_FORMAT_24BPP;
+ break;
+ default:
+ printf("SSD2828: unsupported color depth\n");
+ return 1;
+ }
+ write_hw_register(cfg, SSD2828_VICR6, val);
+
+ /* Lane Configuration Register */
+ write_hw_register(cfg, SSD2828_LCFR,
+ cfg->mipi_dsi_number_of_data_lanes - 1);
+
+ return 0;
+}
+
+int ssd2828_init(const struct ssd2828_config *cfg,
+ const struct ctfb_res_modes *mode)
+{
+ u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config;
+ /* The LP clock speed is limited by 10MHz */
+ const u32 mipi_dsi_low_power_clk_khz = 10000;
+ /*
+ * This is just the reset default value of CFGR register (0x301).
+ * Because we are not always able to read back from SPI, have
+ * it initialized here.
+ */
+ u32 cfgr_reg = SSD2828_CFGR_EOT | /* EOT Packet Enable */
+ SSD2828_CFGR_ECD | /* Disable ECC and CRC */
+ SSD2828_CFGR_HS; /* Data lanes are in HS mode */
+
+ /* Initialize the pins */
+ if (ssd2828_enable_gpio(cfg) != 0)
+ return 1;
+
+ /* Reset the chip */
+ ssd2828_reset(cfg);
+
+ /*
+ * If there is a pin to read data back from SPI, then we are lucky. Try
+ * to check if SPI is configured correctly and SSD2828 is actually able
+ * to talk back.
+ */
+ if (cfg->sdo_pin != -1) {
+ if (read_hw_register(cfg, SSD2828_DIR) != 0x2828 ||
+ read_hw_register(cfg, SSD2828_CFGR) != cfgr_reg) {
+ printf("SSD2828: SPI communication failed.\n");
+ ssd2828_free_gpio(cfg);
+ return 1;
+ }
+ }
+
+ /*
+ * Pick the reference clock for PLL. If we know the exact 'tx_clk'
+ * clock speed, then everything is good. If not, then we can fallback
+ * to 'pclk' (pixel clock from the parallel LCD interface). In the
+ * case of using this fallback, it is necessary to have parallel LCD
+ * already initialized and running at this point.
+ */
+ reference_freq_khz = cfg->ssd2828_tx_clk_khz;
+ if (reference_freq_khz == 0) {
+ reference_freq_khz = mode->pixclock_khz;
+ /* Use 'pclk' as the reference clock for PLL */
+ cfgr_reg |= SSD2828_CFGR_CSS;
+ }
+
+ /*
+ * Setup the parallel LCD timings in the appropriate registers.
+ */
+ if (ssd2828_configure_video_interface(cfg, mode) != 0) {
+ ssd2828_free_gpio(cfg);
+ return 1;
+ }
+
+ /* Configuration Register */
+ cfgr_reg &= ~SSD2828_CFGR_HS; /* Data lanes are in LP mode */
+ cfgr_reg |= SSD2828_CFGR_CKE; /* Clock lane is in HS mode */
+ cfgr_reg |= SSD2828_CFGR_DCS; /* Only use DCS packets */
+ write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
+
+ /* PLL Configuration Register */
+ pll_config = construct_pll_config(
+ cfg->mipi_dsi_bitrate_per_data_lane_mbps * 1000,
+ reference_freq_khz);
+ write_hw_register(cfg, SSD2828_PLCR, pll_config);
+
+ pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz);
+ lp_div = DIV_ROUND_UP(pll_freq_kbps, mipi_dsi_low_power_clk_khz * 8);
+
+ /* VC Control Register */
+ write_hw_register(cfg, SSD2828_VCR, 0);
+
+ /* Clock Control Register */
+ write_hw_register(cfg, SSD2828_CCR, SSD2828_LP_CLOCK_DIVIDER(lp_div));
+
+ /* PLL Control Register */
+ write_hw_register(cfg, SSD2828_PCR, 1); /* Enable PLL */
+
+ /* Wait for PLL lock */
+ udelay(500);
+
+ send_mipi_dcs_command(cfg, MIPI_DCS_EXIT_SLEEP_MODE);
+ mdelay(cfg->mipi_dsi_delay_after_exit_sleep_mode_ms);
+
+ send_mipi_dcs_command(cfg, MIPI_DCS_SET_DISPLAY_ON);
+ mdelay(cfg->mipi_dsi_delay_after_set_display_on_ms);
+
+ cfgr_reg |= SSD2828_CFGR_HS; /* Enable HS mode for data lanes */
+ cfgr_reg |= SSD2828_CFGR_VEN; /* Enable video pipeline */
+ write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
+
+ return 0;
+}
diff --git a/drivers/video/ssd2828.h b/drivers/video/ssd2828.h
new file mode 100644
index 0000000..1af6fa4
--- /dev/null
+++ b/drivers/video/ssd2828.h
@@ -0,0 +1,128 @@
+/*
+ * (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Support for the SSD2828 bridge chip, which can take pixel data coming
+ * from a parallel LCD interface and translate it on the flight into MIPI DSI
+ * interface for driving a MIPI compatible TFT display.
+ *
+ * Implemented as a utility function. To be used from display drivers, which are
+ * responsible for driving parallel LCD hardware in front of the video pipeline.
+ */
+
+#ifndef _SSD2828_H
+#define _SSD2828_H
+
+struct ctfb_res_modes;
+
+struct ssd2828_config {
+ /*********************************************************************/
+ /* SSD2828 configuration */
+ /*********************************************************************/
+
+ /*
+ * The pins, which are used for SPI communication. This is only used
+ * for configuring SSD2828, so the performance is irrelevant (only
+ * around a hundred of bytes is moved). Also these can be any arbitrary
+ * GPIO pins (not necessarily the pins having hardware SPI function).
+ * Moreover, the 'sdo' pin may be even not wired up in some devices.
+ *
+ * These configuration variables need to be set as pin numbers for
+ * the standard u-boot GPIO interface (gpio_get_value/gpio_set_value
+ * functions). Note that -1 value can be used for the pins, which are
+ * not really wired up.
+ */
+ int csx_pin;
+ int sck_pin;
+ int sdi_pin;
+ int sdo_pin;
+ /* SSD2828 reset pin (shared with LCD panel reset) */
+ int reset_pin;
+
+ /*
+ * The SSD2828 has its own dedicated clock source 'tx_clk' (connected
+ * to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for
+ * clocking SPI after reset. The exact clock speed is not strictly,
+ * defined, but the datasheet says that it must be somewhere in the
+ * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also
+ * used as a reference clock for PLL. If the exact clock frequency
+ * is known, then it can be specified here. If it is unknown, or the
+ * information is not trustworthy, then it can be set to 0.
+ *
+ * If unsure, set to 0.
+ */
+ int ssd2828_tx_clk_khz;
+
+ /*
+ * This is not a property of the used LCD panel, but more like a
+ * property of the SSD2828 wiring. See the "SSD2828QN4 RGB data
+ * arrangement" table in the datasheet. The SSD2828 pins are arranged
+ * in such a way that 18bpp and 24bpp configurations are completely
+ * incompatible with each other.
+ *
+ * Depending on the color depth, this must be set to 16, 18 or 24.
+ */
+ int ssd2828_color_depth;
+
+ /*********************************************************************/
+ /* LCD panel configuration */
+ /*********************************************************************/
+
+ /*
+ * The number of lanes in the MIPI DSI interface. May vary from 1 to 4.
+ *
+ * This information can be found in the LCD panel datasheet.
+ */
+ int mipi_dsi_number_of_data_lanes;
+
+ /*
+ * Data transfer bit rate per lane. Please note that it is expected
+ * to be higher than the pixel clock rate of the used video mode when
+ * multiplied by the number of lanes. This is perfectly normal because
+ * MIPI DSI handles data transfers in periodic bursts, and uses the
+ * idle time between bursts for sending configuration information and
+ * commands. Or just for saving power.
+ *
+ * The necessary Mbps/lane information can be found in the LCD panel
+ * datasheet. Note that the transfer rate can't be always set precisely
+ * and it may be rounded *up* (introducing no more than 10Mbps error).
+ */
+ int mipi_dsi_bitrate_per_data_lane_mbps;
+
+ /*
+ * Setting this to 1 enforces packing of 18bpp pixel data in 24bpp
+ * envelope when sending it over the MIPI DSI link.
+ *
+ * If unsure, set to 0.
+ */
+ int mipi_dsi_loosely_packed_pixel_format;
+
+ /*
+ * According to the "Example for system sleep in and out" section in
+ * the SSD2828 datasheet, some LCD panel specific delays are necessary
+ * after MIPI DCS commands EXIT_SLEEP_MODE and SET_DISPLAY_ON.
+ *
+ * For example, Allwinner uses 100 milliseconds delay after
+ * EXIT_SLEEP_MODE and 200 milliseconds delay after SET_DISPLAY_ON.
+ */
+ int mipi_dsi_delay_after_exit_sleep_mode_ms;
+ int mipi_dsi_delay_after_set_display_on_ms;
+};
+
+/*
+ * Initialize the SSD2828 chip. It needs the 'ssd2828_config' structure
+ * and also the video mode timings.
+ *
+ * The right place to insert this function call is after the parallel LCD
+ * interface is initialized and before turning on the backlight. This is
+ * advised in the "Example for system sleep in and out" section of the
+ * SSD2828 datasheet. And also SS2828 may use 'pclk' as the clock source
+ * for PLL, which means that the input signal must be already there.
+ */
+int ssd2828_init(const struct ssd2828_config *cfg,
+ const struct ctfb_res_modes *mode);
+
+#endif
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index d241397..af728b5 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -11,26 +11,68 @@
#include <asm/arch/clock.h>
#include <asm/arch/display.h>
+#include <asm/arch/gpio.h>
#include <asm/global_data.h>
+#include <asm/gpio.h>
#include <asm/io.h>
+#include <errno.h>
#include <fdtdec.h>
#include <fdt_support.h>
-#include <linux/fb.h>
#include <video_fb.h>
+#include "videomodes.h"
+#include "hitachi_tx18d42vm_lcd.h"
+#include "ssd2828.h"
+
+#ifdef CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW
+#define PWM_ON 0
+#define PWM_OFF 1
+#else
+#define PWM_ON 1
+#define PWM_OFF 0
+#endif
DECLARE_GLOBAL_DATA_PTR;
+enum sunxi_monitor {
+ sunxi_monitor_none,
+ sunxi_monitor_dvi,
+ sunxi_monitor_hdmi,
+ sunxi_monitor_lcd,
+ sunxi_monitor_vga,
+};
+#define SUNXI_MONITOR_LAST sunxi_monitor_vga
+
struct sunxi_display {
GraphicDevice graphic_device;
- bool enabled;
+ enum sunxi_monitor monitor;
+ unsigned int depth;
} sunxi_display;
-static int sunxi_hdmi_hpd_detect(void)
+#ifdef CONFIG_VIDEO_HDMI
+
+/*
+ * Wait up to 200ms for value to be set in given part of reg.
+ */
+static int await_completion(u32 *reg, u32 mask, u32 val)
+{
+ unsigned long tmo = timer_get_us() + 200000;
+
+ while ((readl(reg) & mask) != val) {
+ if (timer_get_us() > tmo) {
+ printf("DDC: timeout reading EDID\n");
+ return -ETIME;
+ }
+ }
+ return 0;
+}
+
+static int sunxi_hdmi_hpd_detect(int hpd_delay)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_hdmi_reg * const hdmi =
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+ unsigned long tmo = timer_get_us() + hpd_delay * 1000;
/* Set pll3 to 300MHz */
clock_set_pll3(300000000);
@@ -51,12 +93,21 @@
writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
- udelay(1000);
+ while (timer_get_us() < tmo) {
+ if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
+ return 1;
+ }
- if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
- return 1;
+ return 0;
+}
- /* No need to keep these running */
+static void sunxi_hdmi_shutdown(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+
clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
@@ -64,10 +115,279 @@
clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
#endif
clock_set_pll3(0);
+}
+
+static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
+{
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+
+ setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
+ writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
+ SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
+ SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
+ SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
+#ifndef CONFIG_MACH_SUN6I
+ writel(n, &hdmi->ddc_byte_count);
+ writel(cmnd, &hdmi->ddc_cmnd);
+#else
+ writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
+#endif
+ setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
+
+ return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
+}
+
+static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
+{
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+ int i, n;
+
+ while (count > 0) {
+ if (count > 16)
+ n = 16;
+ else
+ n = count;
+
+ if (sunxi_hdmi_ddc_do_command(
+ SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
+ offset, n))
+ return -ETIME;
+
+ for (i = 0; i < n; i++)
+ *buf++ = readb(&hdmi->ddc_fifo_data);
+
+ offset += n;
+ count -= n;
+ }
return 0;
}
+static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
+{
+ int r, retries = 2;
+
+ do {
+ r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
+ if (r)
+ continue;
+ r = edid_check_checksum(buf);
+ if (r) {
+ printf("EDID block %d: checksum error%s\n",
+ block, retries ? ", retrying" : "");
+ }
+ } while (r && retries--);
+
+ return r;
+}
+
+static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
+{
+ struct edid1_info edid1;
+ struct edid_cea861_info cea681[4];
+ struct edid_detailed_timing *t =
+ (struct edid_detailed_timing *)edid1.monitor_details.timing;
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int i, r, ext_blocks = 0;
+
+ /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
+ writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
+ &hdmi->pad_ctrl1);
+ writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
+ &hdmi->pll_ctrl);
+ writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
+
+ /* Reset i2c controller */
+ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
+ writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
+ SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
+ SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
+ SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
+ if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
+ return -EIO;
+
+ writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
+#ifndef CONFIG_MACH_SUN6I
+ writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
+ SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
+#endif
+
+ r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
+ if (r == 0) {
+ r = edid_check_info(&edid1);
+ if (r) {
+ printf("EDID: invalid EDID data\n");
+ r = -EINVAL;
+ }
+ }
+ if (r == 0) {
+ ext_blocks = edid1.extension_flag;
+ if (ext_blocks > 4)
+ ext_blocks = 4;
+ for (i = 0; i < ext_blocks; i++) {
+ if (sunxi_hdmi_edid_get_block(1 + i,
+ (u8 *)&cea681[i]) != 0) {
+ ext_blocks = i;
+ break;
+ }
+ }
+ }
+
+ /* Disable DDC engine, no longer needed */
+ clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
+ clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
+
+ if (r)
+ return r;
+
+ /* We want version 1.3 or 1.2 with detailed timing info */
+ if (edid1.version != 1 || (edid1.revision < 3 &&
+ !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
+ printf("EDID: unsupported version %d.%d\n",
+ edid1.version, edid1.revision);
+ return -EINVAL;
+ }
+
+ /* Take the first usable detailed timing */
+ for (i = 0; i < 4; i++, t++) {
+ r = video_edid_dtd_to_ctfb_res_modes(t, mode);
+ if (r == 0)
+ break;
+ }
+ if (i == 4) {
+ printf("EDID: no usable detailed timing found\n");
+ return -ENOENT;
+ }
+
+ /* Check for basic audio support, if found enable hdmi output */
+ sunxi_display.monitor = sunxi_monitor_dvi;
+ for (i = 0; i < ext_blocks; i++) {
+ if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
+ cea681[i].revision < 2)
+ continue;
+
+ if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
+ sunxi_display.monitor = sunxi_monitor_hdmi;
+ }
+
+ return 0;
+}
+
+#endif /* CONFIG_VIDEO_HDMI */
+
+#ifdef CONFIG_MACH_SUN4I
+/*
+ * Testing has shown that on sun4i the display backend engine does not have
+ * deep enough fifo-s causing flickering / tearing in full-hd mode due to
+ * fifo underruns. So on sun4i we use the display frontend engine to do the
+ * dma from memory, as the frontend does have deep enough fifo-s.
+ */
+
+static const u32 sun4i_vert_coef[32] = {
+ 0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd,
+ 0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
+ 0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb,
+ 0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
+ 0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd,
+ 0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
+ 0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff,
+ 0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
+};
+
+static const u32 sun4i_horz_coef[64] = {
+ 0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03,
+ 0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06,
+ 0x3efb0000, 0x0000ff08, 0x3dfb0000, 0x0000ff09,
+ 0x3bfa0000, 0x0000fe0d, 0x39fa0000, 0x0000fe0f,
+ 0x38fa0000, 0x0000fe10, 0x36fa0000, 0x0000fe12,
+ 0x33fa0000, 0x0000fd16, 0x31fa0000, 0x0000fd18,
+ 0x2ffa0000, 0x0000fd1a, 0x2cfa0000, 0x0000fc1e,
+ 0x29fa0000, 0x0000fc21, 0x27fb0000, 0x0000fb23,
+ 0x24fb0000, 0x0000fb26, 0x21fb0000, 0x0000fb29,
+ 0x1ffc0000, 0x0000fa2b, 0x1cfc0000, 0x0000fa2e,
+ 0x19fd0000, 0x0000fa30, 0x16fd0000, 0x0000fa33,
+ 0x14fd0000, 0x0000fa35, 0x11fe0000, 0x0000fa37,
+ 0x0ffe0000, 0x0000fa39, 0x0dfe0000, 0x0000fa3b,
+ 0x0afe0000, 0x0000fa3e, 0x08ff0000, 0x0000fb3e,
+ 0x06ff0000, 0x0000fb40, 0x05ff0000, 0x0000fc40,
+ 0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42,
+};
+
+static void sunxi_frontend_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_de_fe_reg * const de_fe =
+ (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
+ int i;
+
+ /* Clocks on */
+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0);
+ setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0);
+ clock_set_de_mod_clock(&ccm->fe0_clk_cfg, 300000000);
+
+ setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN);
+
+ for (i = 0; i < 32; i++) {
+ writel(sun4i_horz_coef[2 * i], &de_fe->ch0_horzcoef0[i]);
+ writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch0_horzcoef1[i]);
+ writel(sun4i_vert_coef[i], &de_fe->ch0_vertcoef[i]);
+ writel(sun4i_horz_coef[2 * i], &de_fe->ch1_horzcoef0[i]);
+ writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch1_horzcoef1[i]);
+ writel(sun4i_vert_coef[i], &de_fe->ch1_vertcoef[i]);
+ }
+
+ setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_COEF_RDY);
+}
+
+static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
+ unsigned int address)
+{
+ struct sunxi_de_fe_reg * const de_fe =
+ (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
+
+ setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS);
+ writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
+ writel(mode->xres * 4, &de_fe->ch0_stride);
+ writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt);
+ writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt);
+
+ writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
+ &de_fe->ch0_insize);
+ writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
+ &de_fe->ch0_outsize);
+ writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_horzfact);
+ writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_vertfact);
+
+ writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
+ &de_fe->ch1_insize);
+ writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
+ &de_fe->ch1_outsize);
+ writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_horzfact);
+ writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_vertfact);
+
+ setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_REG_RDY);
+}
+
+static void sunxi_frontend_enable(void)
+{
+ struct sunxi_de_fe_reg * const de_fe =
+ (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
+
+ setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_FRM_START);
+}
+#else
+static void sunxi_frontend_init(void) {}
+static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
+ unsigned int address) {}
+static void sunxi_frontend_enable(void) {}
+#endif
+
/*
* This is the entity that mixes and matches the different layers and inputs.
* Allwinner calls it the back-end, but i like composer better.
@@ -80,14 +400,18 @@
(struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
int i;
-#ifdef CONFIG_MACH_SUN6I
+ sunxi_frontend_init();
+
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
/* Reset off */
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
#endif
/* Clocks on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
+#ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */
setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
+#endif
clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
/* Engine bug, clear registers after reset */
@@ -97,41 +421,72 @@
setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
}
-static void sunxi_composer_mode_set(struct fb_videomode *mode,
+static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
unsigned int address)
{
struct sunxi_de_be_reg * const de_be =
(struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
+ sunxi_frontend_mode_set(mode, address);
+
writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
&de_be->disp_size);
writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
&de_be->layer0_size);
+#ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */
writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
writel(address << 3, &de_be->layer0_addr_low32b);
writel(address >> 29, &de_be->layer0_addr_high4b);
+#else
+ writel(SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0, &de_be->layer0_attr0_ctrl);
+#endif
writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
}
+static void sunxi_composer_enable(void)
+{
+ struct sunxi_de_be_reg * const de_be =
+ (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
+
+ sunxi_frontend_enable();
+
+ setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
+ setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
+}
+
/*
* LCDC, what allwinner calls a CRTC, so timing controller and serializer.
*/
-static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
+static void sunxi_lcdc_pll_set(int tcon, int dotclock,
+ int *clk_div, int *clk_double)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- int value, n, m, diff;
+ int value, n, m, min_m, max_m, diff;
int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
int best_double = 0;
+ if (tcon == 0) {
+#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
+ min_m = 6;
+ max_m = 127;
+#endif
+#ifdef CONFIG_VIDEO_LCD_IF_LVDS
+ min_m = max_m = 7;
+#endif
+ } else {
+ min_m = 1;
+ max_m = 15;
+ }
+
/*
* Find the lowest divider resulting in a matching clock, if there
* is no match, pick the closest lower clock, as monitors tend to
* not sync to higher frequencies.
*/
- for (m = 15; m > 0; m--) {
+ for (m = min_m; m <= max_m; m++) {
n = (m * dotclock) / 3000;
if ((n >= 9) && (n <= 127)) {
@@ -168,9 +523,17 @@
clock_set_pll3(best_n * 3000000);
- writel(CCM_LCD_CH1_CTRL_GATE |
- (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
- CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
+ if (tcon == 0) {
+ writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST |
+ (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X :
+ CCM_LCD_CH0_CTRL_PLL3),
+ &ccm->lcd0_ch0_clk_cfg);
+ } else {
+ writel(CCM_LCD_CH1_CTRL_GATE |
+ (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
+ CCM_LCD_CH1_CTRL_PLL3) |
+ CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
+ }
*clk_div = best_m;
*clk_double = best_double;
@@ -184,7 +547,7 @@
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
/* Reset off */
-#ifdef CONFIG_MACH_SUN6I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
#else
setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
@@ -192,6 +555,9 @@
/* Clock on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
+#ifdef CONFIG_VIDEO_LCD_IF_LVDS
+ setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);
+#endif
/* Init lcdc */
writel(0, &lcdc->ctrl); /* Disable tcon */
@@ -205,20 +571,175 @@
writel(0xffffffff, &lcdc->tcon1_io_tristate);
}
-static void sunxi_lcdc_mode_set(struct fb_videomode *mode,
- int *clk_div, int *clk_double)
+static void sunxi_lcdc_enable(void)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
- int bp, total;
+
+ setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
+#ifdef CONFIG_VIDEO_LCD_IF_LVDS
+ setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
+ setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
+ setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
+ udelay(2); /* delay at least 1200 ns */
+ setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
+ udelay(1); /* delay at least 120 ns */
+ setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
+ setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
+#endif
+}
+
+static void sunxi_lcdc_panel_enable(void)
+{
+ int pin;
+
+ /*
+ * Start with backlight disabled to avoid the screen flashing to
+ * white while the lcd inits.
+ */
+ pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
+ if (pin != -1) {
+ gpio_request(pin, "lcd_backlight_enable");
+ gpio_direction_output(pin, 0);
+ }
+
+ pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
+ if (pin != -1) {
+ gpio_request(pin, "lcd_backlight_pwm");
+ gpio_direction_output(pin, PWM_OFF);
+ }
+
+ /* Give the backlight some time to turn off and power up the panel. */
+ mdelay(40);
+ pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
+ if (pin != -1) {
+ gpio_request(pin, "lcd_power");
+ gpio_direction_output(pin, 1);
+ }
+}
+
+static void sunxi_lcdc_backlight_enable(void)
+{
+ int pin;
+
+ /*
+ * We want to have scanned out at least one frame before enabling the
+ * backlight to avoid the screen flashing to white when we enable it.
+ */
+ mdelay(40);
+
+ pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
+ if (pin != -1)
+ gpio_direction_output(pin, 1);
+
+ pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
+ if (pin != -1)
+ gpio_direction_output(pin, PWM_ON);
+}
+
+static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode)
+{
+ int delay;
+
+ delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2;
+ return (delay > 30) ? 30 : delay;
+}
+
+static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
+{
+ struct sunxi_lcdc_reg * const lcdc =
+ (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+ int bp, clk_delay, clk_div, clk_double, pin, total, val;
+
+ for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
+#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
+#endif
+#ifdef CONFIG_VIDEO_LCD_IF_LVDS
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LVDS0);
+#endif
+
+ sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
+
+ /* Use tcon0 */
+ clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
+ SUNXI_LCDC_CTRL_IO_MAP_TCON0);
+
+ clk_delay = sunxi_lcdc_get_clk_delay(mode);
+ writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
+ SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
+
+ writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
+ SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
+
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ &lcdc->tcon0_timing_active);
+
+ bp = mode->hsync_len + mode->left_margin;
+ total = mode->xres + mode->right_margin + bp;
+ writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
+ SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
+
+ bp = mode->vsync_len + mode->upper_margin;
+ total = mode->yres + mode->lower_margin + bp;
+ writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
+ SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
+
+#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
+ writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
+ &lcdc->tcon0_timing_sync);
+
+ writel(0, &lcdc->tcon0_hv_intf);
+ writel(0, &lcdc->tcon0_cpu_intf);
+#endif
+#ifdef CONFIG_VIDEO_LCD_IF_LVDS
+ val = (sunxi_display.depth == 18) ? 1 : 0;
+ writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val), &lcdc->tcon0_lvds_intf);
+#endif
+
+ if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
+ writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
+ writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
+ writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
+ writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
+ writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
+ writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
+ writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
+ writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
+ writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
+ writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
+ writel(((sunxi_display.depth == 18) ?
+ SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
+ SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
+ &lcdc->tcon0_frm_ctrl);
+ }
+
+ val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
+ if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
+ val |= SUNXI_LCDC_TCON_HSYNC_MASK;
+ if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
+ val |= SUNXI_LCDC_TCON_VSYNC_MASK;
+ writel(val, &lcdc->tcon0_io_polarity);
+
+ writel(0, &lcdc->tcon0_io_tristate);
+}
+
+#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA
+static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
+ int *clk_div, int *clk_double,
+ bool use_portd_hvsync)
+{
+ struct sunxi_lcdc_reg * const lcdc =
+ (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+ int bp, clk_delay, total, val;
/* Use tcon1 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
- /* Enabled, 0x1e start delay */
+ clk_delay = sunxi_lcdc_get_clk_delay(mode);
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
- SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
+ SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
&lcdc->tcon1_timing_source);
@@ -240,22 +761,75 @@
writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
&lcdc->tcon1_timing_sync);
- sunxi_lcdc_pll_set(mode->pixclock, clk_div, clk_double);
-}
+ if (use_portd_hvsync) {
+ sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD0_LCD0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD0_LCD0);
-#ifdef CONFIG_MACH_SUN6I
-static void sunxi_drc_init(void)
+ val = 0;
+ if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+ val |= SUNXI_LCDC_TCON_HSYNC_MASK;
+ if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+ val |= SUNXI_LCDC_TCON_VSYNC_MASK;
+ writel(val, &lcdc->tcon1_io_polarity);
+
+ clrbits_le32(&lcdc->tcon1_io_tristate,
+ SUNXI_LCDC_TCON_VSYNC_MASK |
+ SUNXI_LCDC_TCON_HSYNC_MASK);
+ }
+ sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
+}
+#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA */
+
+#ifdef CONFIG_VIDEO_HDMI
+
+static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+ u8 checksum = 0;
+ u8 avi_info_frame[17] = {
+ 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00
+ };
+ u8 vendor_info_frame[19] = {
+ 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00
+ };
+ int i;
- /* On sun6i the drc must be clocked even when in pass-through mode */
- setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
- clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
+ if (mode->pixclock_khz <= 27000)
+ avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
+ else
+ avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
+
+ if (mode->xres * 100 / mode->yres < 156)
+ avi_info_frame[5] |= 0x18; /* 4 : 3 */
+ else
+ avi_info_frame[5] |= 0x28; /* 16 : 9 */
+
+ for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
+ checksum += avi_info_frame[i];
+
+ avi_info_frame[3] = 0x100 - checksum;
+
+ for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
+ writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
+
+ writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
+ writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
+
+ for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
+ writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
+
+ writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
+ writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
+
+ setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
}
-#endif
-static void sunxi_hdmi_mode_set(struct fb_videomode *mode,
+static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
int clk_div, int clk_double)
{
struct sunxi_hdmi_reg * const hdmi =
@@ -265,6 +839,12 @@
/* Write clear interrupt status bits */
writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
+ if (sunxi_display.monitor == sunxi_monitor_hdmi)
+ sunxi_hdmi_setup_info_frames(mode);
+
+ /* Set input sync enable */
+ writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
+
/* Init various registers, select pll3 as clock source */
writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
@@ -301,84 +881,191 @@
setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
}
+static void sunxi_hdmi_enable(void)
+{
+ struct sunxi_hdmi_reg * const hdmi =
+ (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
+
+ udelay(100);
+ setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
+}
+
+#endif /* CONFIG_VIDEO_HDMI */
+
+#ifdef CONFIG_VIDEO_VGA
+
+static void sunxi_vga_mode_set(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_tve_reg * const tve =
+ (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
+
+ /* Clock on */
+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
+
+ /* Set TVE in VGA mode */
+ writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
+ writel(SUNXI_TVE_GCTRL_CFG0_VGA, &tve->cfg0);
+ writel(SUNXI_TVE_GCTRL_DAC_CFG0_VGA, &tve->dac_cfg0);
+ writel(SUNXI_TVE_GCTRL_UNKNOWN1_VGA, &tve->unknown1);
+}
+
+static void sunxi_vga_enable(void)
+{
+ struct sunxi_tve_reg * const tve =
+ (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
+
+ setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE);
+}
+
+#endif /* CONFIG_VIDEO_VGA */
+
+static void sunxi_drc_init(void)
+{
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* On sun6i the drc must be clocked even when in pass-through mode */
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
+ clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
+#endif
+}
+
+#ifdef CONFIG_VIDEO_VGA_VIA_LCD
+static void sunxi_vga_external_dac_enable(void)
+{
+ int pin;
+
+ pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
+ if (pin != -1) {
+ gpio_request(pin, "vga_enable");
+ gpio_direction_output(pin, 1);
+ }
+}
+#endif /* CONFIG_VIDEO_VGA_VIA_LCD */
+
+#ifdef CONFIG_VIDEO_LCD_SSD2828
+static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
+{
+ struct ssd2828_config cfg = {
+ .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
+ .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
+ .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
+ .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
+ .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
+ .ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000,
+ .ssd2828_color_depth = 24,
+#ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
+ .mipi_dsi_number_of_data_lanes = 4,
+ .mipi_dsi_bitrate_per_data_lane_mbps = 513,
+ .mipi_dsi_delay_after_exit_sleep_mode_ms = 100,
+ .mipi_dsi_delay_after_set_display_on_ms = 200
+#else
+#error MIPI LCD panel needs configuration parameters
+#endif
+ };
+
+ if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) {
+ printf("SSD2828: SPI pins are not properly configured\n");
+ return 1;
+ }
+ if (cfg.reset_pin == -1) {
+ printf("SSD2828: Reset pin is not properly configured\n");
+ return 1;
+ }
+
+ return ssd2828_init(&cfg, mode);
+}
+#endif /* CONFIG_VIDEO_LCD_SSD2828 */
+
static void sunxi_engines_init(void)
{
sunxi_composer_init();
sunxi_lcdc_init();
-#ifdef CONFIG_MACH_SUN6I
sunxi_drc_init();
-#endif
}
-static void sunxi_mode_set(struct fb_videomode *mode, unsigned int address)
+static void sunxi_mode_set(const struct ctfb_res_modes *mode,
+ unsigned int address)
{
- struct sunxi_de_be_reg * const de_be =
- (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
- struct sunxi_lcdc_reg * const lcdc =
- (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
- struct sunxi_hdmi_reg * const hdmi =
- (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
- int clk_div, clk_double;
- int retries = 3;
+ int __maybe_unused clk_div, clk_double;
-retry:
- clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
- clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
- clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
-
- sunxi_composer_mode_set(mode, address);
- sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
- sunxi_hdmi_mode_set(mode, clk_div, clk_double);
-
- setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
- setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
-
- udelay(1000000 / mode->refresh + 500);
-
- setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
-
- udelay(1000000 / mode->refresh + 500);
-
- setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
-
- udelay(1000000 / mode->refresh + 500);
-
- /*
- * Sometimes the display pipeline does not sync up properly, if
- * this happens the hdmi fifo underrun or overrun bits are set.
- */
- if (readl(&hdmi->irq) &
- (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
- if (retries--)
- goto retry;
- printf("HDMI fifo under or overrun\n");
+ switch (sunxi_display.monitor) {
+ case sunxi_monitor_none:
+ break;
+ case sunxi_monitor_dvi:
+ case sunxi_monitor_hdmi:
+#ifdef CONFIG_VIDEO_HDMI
+ sunxi_composer_mode_set(mode, address);
+ sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
+ sunxi_hdmi_mode_set(mode, clk_div, clk_double);
+ sunxi_composer_enable();
+ sunxi_lcdc_enable();
+ sunxi_hdmi_enable();
+#endif
+ break;
+ case sunxi_monitor_lcd:
+ sunxi_lcdc_panel_enable();
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
+ mdelay(50); /* Wait for lcd controller power on */
+ hitachi_tx18d42vm_init();
+ }
+ sunxi_composer_mode_set(mode, address);
+ sunxi_lcdc_tcon0_mode_set(mode);
+ sunxi_composer_enable();
+ sunxi_lcdc_enable();
+#ifdef CONFIG_VIDEO_LCD_SSD2828
+ sunxi_ssd2828_init(mode);
+#endif
+ sunxi_lcdc_backlight_enable();
+ break;
+ case sunxi_monitor_vga:
+#ifdef CONFIG_VIDEO_VGA
+ sunxi_composer_mode_set(mode, address);
+ sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
+ sunxi_vga_mode_set();
+ sunxi_composer_enable();
+ sunxi_lcdc_enable();
+ sunxi_vga_enable();
+#elif defined CONFIG_VIDEO_VGA_VIA_LCD
+ sunxi_composer_mode_set(mode, address);
+ sunxi_lcdc_tcon0_mode_set(mode);
+ sunxi_composer_enable();
+ sunxi_lcdc_enable();
+ sunxi_vga_external_dac_enable();
+#endif
+ break;
}
}
+static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
+{
+ switch (monitor) {
+ case sunxi_monitor_none: return "none";
+ case sunxi_monitor_dvi: return "dvi";
+ case sunxi_monitor_hdmi: return "hdmi";
+ case sunxi_monitor_lcd: return "lcd";
+ case sunxi_monitor_vga: return "vga";
+ }
+ return NULL; /* never reached */
+}
+
void *video_hw_init(void)
{
static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
- /*
- * Vesa standard 1024x768@60
- * 65.0 1024 1048 1184 1344 768 771 777 806 -hsync -vsync
- */
- struct fb_videomode mode = {
- .name = "1024x768",
- .refresh = 60,
- .xres = 1024,
- .yres = 768,
- .pixclock = 65000,
- .left_margin = 160,
- .right_margin = 24,
- .upper_margin = 29,
- .lower_margin = 3,
- .hsync_len = 136,
- .vsync_len = 6,
- .sync = 0,
- .vmode = 0,
- .flag = 0,
- };
- int ret;
+ const struct ctfb_res_modes *mode;
+ struct ctfb_res_modes custom;
+ const char *options;
+#ifdef CONFIG_VIDEO_HDMI
+ int ret, hpd, hpd_delay, edid;
+#endif
+ char mon[16];
+ char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
+ int i;
memset(&sunxi_display, 0, sizeof(struct sunxi_display));
@@ -386,16 +1073,98 @@
CONFIG_SUNXI_FB_SIZE >> 10);
gd->fb_base = gd->ram_top;
- ret = sunxi_hdmi_hpd_detect();
- if (!ret)
+ video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
+ &sunxi_display.depth, &options);
+#ifdef CONFIG_VIDEO_HDMI
+ hpd = video_get_option_int(options, "hpd", 1);
+ hpd_delay = video_get_option_int(options, "hpd_delay", 500);
+ edid = video_get_option_int(options, "edid", 1);
+ sunxi_display.monitor = sunxi_monitor_dvi;
+#elif defined CONFIG_VIDEO_VGA_VIA_LCD
+ sunxi_display.monitor = sunxi_monitor_vga;
+#else
+ sunxi_display.monitor = sunxi_monitor_lcd;
+#endif
+ video_get_option_string(options, "monitor", mon, sizeof(mon),
+ sunxi_get_mon_desc(sunxi_display.monitor));
+ for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
+ if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
+ sunxi_display.monitor = i;
+ break;
+ }
+ }
+ if (i > SUNXI_MONITOR_LAST)
+ printf("Unknown monitor: '%s', falling back to '%s'\n",
+ mon, sunxi_get_mon_desc(sunxi_display.monitor));
+
+#ifdef CONFIG_VIDEO_HDMI
+ /* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
+ if (sunxi_display.monitor == sunxi_monitor_dvi ||
+ sunxi_display.monitor == sunxi_monitor_hdmi) {
+ /* Always call hdp_detect, as it also enables clocks, etc. */
+ ret = sunxi_hdmi_hpd_detect(hpd_delay);
+ if (ret) {
+ printf("HDMI connected: ");
+ if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
+ mode = &custom;
+ } else if (hpd) {
+ sunxi_hdmi_shutdown();
+ /* Fallback to lcd / vga / none */
+ if (lcd_mode[0]) {
+ sunxi_display.monitor = sunxi_monitor_lcd;
+ } else {
+#if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
+ sunxi_display.monitor = sunxi_monitor_vga;
+#else
+ sunxi_display.monitor = sunxi_monitor_none;
+#endif
+ }
+ } /* else continue with hdmi/dvi without a cable connected */
+ }
+#endif
+
+ switch (sunxi_display.monitor) {
+ case sunxi_monitor_none:
return NULL;
+ case sunxi_monitor_dvi:
+ case sunxi_monitor_hdmi:
+#ifdef CONFIG_VIDEO_HDMI
+ break;
+#else
+ printf("HDMI/DVI not supported on this board\n");
+ sunxi_display.monitor = sunxi_monitor_none;
+ return NULL;
+#endif
+ case sunxi_monitor_lcd:
+ if (lcd_mode[0]) {
+ sunxi_display.depth = video_get_params(&custom, lcd_mode);
+ mode = &custom;
+ break;
+ }
+ printf("LCD not supported on this board\n");
+ sunxi_display.monitor = sunxi_monitor_none;
+ return NULL;
+ case sunxi_monitor_vga:
+#if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
+ sunxi_display.depth = 18;
+ break;
+#else
+ printf("VGA not supported on this board\n");
+ sunxi_display.monitor = sunxi_monitor_none;
+ return NULL;
+#endif
+ }
- printf("HDMI connected.\n");
- sunxi_display.enabled = true;
+ if (mode->vmode != FB_VMODE_NONINTERLACED) {
+ printf("Only non-interlaced modes supported, falling back to 1024x768\n");
+ mode = &res_mode_init[RES_MODE_1024x768];
+ } else {
+ printf("Setting up a %dx%d %s console\n", mode->xres,
+ mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
+ }
- printf("Setting up a %s console.\n", mode.name);
sunxi_engines_init();
- sunxi_mode_set(&mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
+ sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
/*
* These are the only members of this structure that are used. All the
@@ -405,8 +1174,8 @@
graphic_device->frameAdrs = gd->fb_base;
graphic_device->gdfIndex = GDF_32BIT_X888RGB;
graphic_device->gdfBytesPP = 4;
- graphic_device->winSizeX = mode.xres;
- graphic_device->winSizeY = mode.yres;
+ graphic_device->winSizeX = mode->xres;
+ graphic_device->winSizeY = mode->yres;
return graphic_device;
}
@@ -419,16 +1188,39 @@
{
static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
int offset, ret;
+ const char *pipeline = NULL;
- if (!sunxi_display.enabled)
+#ifdef CONFIG_MACH_SUN4I
+#define PIPELINE_PREFIX "de_fe0-"
+#else
+#define PIPELINE_PREFIX
+#endif
+
+ switch (sunxi_display.monitor) {
+ case sunxi_monitor_none:
return 0;
+ case sunxi_monitor_dvi:
+ case sunxi_monitor_hdmi:
+ pipeline = PIPELINE_PREFIX "de_be0-lcd0-hdmi";
+ break;
+ case sunxi_monitor_lcd:
+ pipeline = PIPELINE_PREFIX "de_be0-lcd0";
+ break;
+ case sunxi_monitor_vga:
+#ifdef CONFIG_VIDEO_VGA
+ pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
+#elif defined CONFIG_VIDEO_VGA_VIA_LCD
+ pipeline = PIPELINE_PREFIX "de_be0-lcd0";
+#endif
+ break;
+ }
- /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
+ /* Find a prefilled simpefb node, matching out pipeline config */
offset = fdt_node_offset_by_compatible(blob, -1,
"allwinner,simple-framebuffer");
while (offset >= 0) {
ret = fdt_find_string(blob, offset, "allwinner,pipeline",
- "de_be0-lcd0-hdmi");
+ pipeline);
if (ret == 0)
break;
offset = fdt_node_offset_by_compatible(blob, offset,
diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c
index 18c1f3d..cf71ad1 100644
--- a/drivers/video/videomodes.c
+++ b/drivers/video/videomodes.c
@@ -58,6 +58,8 @@
****************************************************************************/
#include <common.h>
+#include <edid.h>
+#include <errno.h>
#include <linux/ctype.h>
#include "videomodes.h"
@@ -84,13 +86,26 @@
{0x31B, RES_MODE_1280x1024, 24},
};
const struct ctfb_res_modes res_mode_init[RES_MODES_COUNT] = {
- /* x y pixclk le ri up lo hs vs s vmode */
- {640, 480, 39721, 40, 24, 32, 11, 96, 2, 0, FB_VMODE_NONINTERLACED},
- {800, 600, 27778, 64, 24, 22, 1, 72, 2, 0, FB_VMODE_NONINTERLACED},
- {1024, 768, 15384, 168, 8, 29, 3, 144, 4, 0, FB_VMODE_NONINTERLACED},
- {960, 720, 13100, 160, 40, 32, 8, 80, 4, 0, FB_VMODE_NONINTERLACED},
- {1152, 864, 12004, 200, 64, 32, 16, 80, 4, 0, FB_VMODE_NONINTERLACED},
- {1280, 1024, 9090, 200, 48, 26, 1, 184, 3, 0, FB_VMODE_NONINTERLACED},
+ /* x y hz pixclk ps/kHz le ri up lo hs vs s vmode */
+#ifndef CONFIG_VIDEO_STD_TIMINGS
+ { 640, 480, 60, 39721, 25180, 40, 24, 32, 11, 96, 2, 0, FB_VMODE_NONINTERLACED},
+ { 800, 600, 60, 27778, 36000, 64, 24, 22, 1, 72, 2, 0, FB_VMODE_NONINTERLACED},
+ {1024, 768, 60, 15384, 65000, 168, 8, 29, 3, 144, 4, 0, FB_VMODE_NONINTERLACED},
+ { 960, 720, 80, 13100, 76335, 160, 40, 32, 8, 80, 4, 0, FB_VMODE_NONINTERLACED},
+ {1152, 864, 60, 12004, 83300, 200, 64, 32, 16, 80, 4, 0, FB_VMODE_NONINTERLACED},
+ {1280, 1024, 60, 9090, 110000, 200, 48, 26, 1, 184, 3, 0, FB_VMODE_NONINTERLACED},
+#else
+ { 640, 480, 60, 39683, 25200, 48, 16, 33, 10, 96, 2, 0, FB_VMODE_NONINTERLACED},
+ { 800, 600, 60, 25000, 40000, 88, 40, 23, 1, 128, 4, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+ {1024, 768, 60, 15384, 65000, 160, 24, 29, 3, 136, 6, 0, FB_VMODE_NONINTERLACED},
+ { 960, 720, 75, 13468, 74250, 176, 72, 27, 1, 112, 2, 0, FB_VMODE_NONINTERLACED},
+ {1152, 864, 75, 9259, 108000, 256, 64, 32, 1, 128, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+ {1280, 1024, 60, 9259, 108000, 248, 48, 38, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+#endif
+ {1280, 720, 60, 13468, 74250, 220, 110, 20, 5, 40, 5, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+ {1360, 768, 60, 11696, 85500, 256, 64, 17, 3, 112, 7, 0, FB_VMODE_NONINTERLACED},
+ {1920, 1080, 60, 6734, 148500, 148, 88, 36, 4, 44, 5, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED},
+ {1920, 1200, 60, 6494, 154000, 80, 48, 26, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED},
};
/************************************************************************
@@ -100,7 +115,7 @@
* returns the length to the next seperator
*/
static int
-video_get_param_len (char *start, char sep)
+video_get_param_len(const char *start, char sep)
{
int i = 0;
while ((*start != 0) && (*start != sep)) {
@@ -183,6 +198,7 @@
while ((i = video_get_param_len (p, ',')) != 0) {
GET_OPTION ("x:", pPar->xres)
GET_OPTION ("y:", pPar->yres)
+ GET_OPTION ("refresh:", pPar->refresh)
GET_OPTION ("le:", pPar->left_margin)
GET_OPTION ("ri:", pPar->right_margin)
GET_OPTION ("up:", pPar->upper_margin)
@@ -192,6 +208,7 @@
GET_OPTION ("sync:", pPar->sync)
GET_OPTION ("vmode:", pPar->vmode)
GET_OPTION ("pclk:", pPar->pixclock)
+ GET_OPTION ("pclk_khz:", pPar->pixclock_khz)
GET_OPTION ("depth:", bpp)
p += i;
if (*p != 0)
@@ -260,3 +277,171 @@
return 1;
}
+
+/*
+ * Parse the 'video-mode' environment variable using video_get_video_mode()
+ * and lookup the matching ctfb_res_modes in res_mode_init.
+ *
+ * @default_mode: RES_MODE_##x## define for the mode to store in mode_ret
+ * when 'video-mode' is not set or does not contain a valid mode
+ * @default_depth: depth to set when 'video-mode' is not set
+ * @mode_ret: pointer where the mode will be stored
+ * @depth_ret: pointer where the depth will be stored
+ * @options: pointer to any remaining options, or NULL
+ */
+void video_get_ctfb_res_modes(int default_mode, unsigned int default_depth,
+ const struct ctfb_res_modes **mode_ret,
+ unsigned int *depth_ret,
+ const char **options)
+{
+ unsigned int i, xres, yres, depth, refresh;
+
+ *mode_ret = &res_mode_init[default_mode];
+ *depth_ret = default_depth;
+ *options = NULL;
+
+ if (!video_get_video_mode(&xres, &yres, &depth, &refresh, options))
+ return;
+
+ for (i = 0; i < RES_MODES_COUNT; i++) {
+ if (res_mode_init[i].xres == xres &&
+ res_mode_init[i].yres == yres &&
+ res_mode_init[i].refresh == refresh) {
+ *mode_ret = &res_mode_init[i];
+ *depth_ret = depth;
+ return;
+ }
+ }
+
+ printf("video-mode %dx%d-%d@%d not available, falling back to %dx%d-%d@%d\n",
+ xres, yres, depth, refresh, (*mode_ret)->xres,
+ (*mode_ret)->yres, *depth_ret, (*mode_ret)->refresh);
+}
+
+/*
+ * Find the named string option within the ',' separated options string, and
+ * store its value in dest.
+ *
+ * @options: ',' separated options string
+ * @name: name of the option to look for
+ * @dest: destination buffer to store the value of the option in
+ * @dest_len: length of dest
+ * @def: value to store in dest if the option is not present in options
+ */
+void video_get_option_string(const char *options, const char *name,
+ char *dest, int dest_len, const char *def)
+{
+ const char *p = options;
+ const int name_len = strlen(name);
+ int i, len;
+
+ while (p && (i = video_get_param_len(p, ',')) != 0) {
+ if (strncmp(p, name, name_len) == 0 && p[name_len] == '=') {
+ len = i - (name_len + 1);
+ if (len >= dest_len)
+ len = dest_len - 1;
+ memcpy(dest, &p[name_len + 1], len);
+ dest[len] = 0;
+ return;
+ }
+ p += i;
+ if (*p != 0)
+ p++; /* skip ',' */
+ }
+ strcpy(dest, def);
+}
+
+/*
+ * Find the named integer option within the ',' separated options string, and
+ * return its value.
+ *
+ * @options: ',' separated options string
+ * @name: name of the option to look for
+ * @def: value to return if the option is not present in options
+ */
+int video_get_option_int(const char *options, const char *name, int def)
+{
+ const char *p = options;
+ const int name_len = strlen(name);
+ int i;
+
+ while (p && (i = video_get_param_len(p, ',')) != 0) {
+ if (strncmp(p, name, name_len) == 0 && p[name_len] == '=')
+ return simple_strtoul(&p[name_len + 1], NULL, 10);
+
+ p += i;
+ if (*p != 0)
+ p++; /* skip ',' */
+ }
+ return def;
+}
+
+/**
+ * Convert an EDID detailed timing to a struct ctfb_res_modes
+ *
+ * @param t The EDID detailed timing to be converted
+ * @param mode Returns the converted timing
+ *
+ * @return 0 on success, or a negative errno on error
+ */
+int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
+ struct ctfb_res_modes *mode)
+{
+ int margin, h_total, v_total;
+
+ /* Check all timings are non 0 */
+ if (EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) == 0 ||
+ EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*t) == 0 ||
+ EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*t) == 0 ||
+ EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*t) == 0 ||
+ EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) == 0 ||
+ EDID_DETAILED_TIMING_HSYNC_OFFSET(*t) == 0 ||
+ EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*t) == 0 ||
+ EDID_DETAILED_TIMING_VSYNC_OFFSET(*t) == 0 ||
+ EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*t) == 0 ||
+ /* 3d formats are not supported*/
+ EDID_DETAILED_TIMING_FLAG_STEREO(*t) != 0)
+ return -EINVAL;
+
+ mode->xres = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*t);
+ mode->yres = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*t);
+
+ h_total = mode->xres + EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*t);
+ v_total = mode->yres + EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t);
+ mode->refresh = EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) /
+ (h_total * v_total);
+
+ mode->pixclock_khz = EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) / 1000;
+ mode->pixclock = 1000000000L / mode->pixclock_khz;
+
+ mode->right_margin = EDID_DETAILED_TIMING_HSYNC_OFFSET(*t);
+ mode->hsync_len = EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(*t);
+ margin = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*t) -
+ (mode->right_margin + mode->hsync_len);
+ if (margin <= 0)
+ return -EINVAL;
+
+ mode->left_margin = margin;
+
+ mode->lower_margin = EDID_DETAILED_TIMING_VSYNC_OFFSET(*t);
+ mode->vsync_len = EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(*t);
+ margin = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*t) -
+ (mode->lower_margin + mode->vsync_len);
+ if (margin <= 0)
+ return -EINVAL;
+
+ mode->upper_margin = margin;
+
+ mode->sync = 0;
+ if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t))
+ mode->sync |= FB_SYNC_HOR_HIGH_ACT;
+ if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t))
+ mode->sync |= FB_SYNC_VERT_HIGH_ACT;
+
+ if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t))
+ mode->vmode = FB_VMODE_INTERLACED;
+ else
+ mode->vmode = FB_VMODE_NONINTERLACED;
+
+ return 0;
+}
diff --git a/drivers/video/videomodes.h b/drivers/video/videomodes.h
index d83993a..82190a2 100644
--- a/drivers/video/videomodes.h
+++ b/drivers/video/videomodes.h
@@ -5,6 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <edid.h>
#ifndef CONFIG_SYS_DEFAULT_VIDEO_MODE
#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x301
@@ -35,8 +36,10 @@
struct ctfb_res_modes {
int xres; /* visible resolution */
int yres;
+ int refresh; /* vertical refresh rate in hz */
/* Timing: All values in pixclocks, except pixclock (of course) */
int pixclock; /* pixel clock in ps (pico seconds) */
+ int pixclock_khz; /* pixel clock in kHz */
int left_margin; /* time from sync to picture */
int right_margin; /* time from picture to sync */
int upper_margin; /* time from sync to picture */
@@ -62,7 +65,11 @@
#define RES_MODE_960_720 3
#define RES_MODE_1152x864 4
#define RES_MODE_1280x1024 5
-#define RES_MODES_COUNT 6
+#define RES_MODE_1280x720 6
+#define RES_MODE_1360x768 7
+#define RES_MODE_1920x1080 8
+#define RES_MODE_1920x1200 9
+#define RES_MODES_COUNT 10
#define VESA_MODES_COUNT 19
@@ -73,3 +80,16 @@
int video_get_video_mode(unsigned int *xres, unsigned int *yres,
unsigned int *depth, unsigned int *freq, const char **options);
+
+void video_get_ctfb_res_modes(int default_mode, unsigned int default_depth,
+ const struct ctfb_res_modes **mode_ret,
+ unsigned int *depth_ret,
+ const char **options);
+
+void video_get_option_string(const char *options, const char *name,
+ char *dest, int dest_len, const char *def);
+
+int video_get_option_int(const char *options, const char *name, int def);
+
+int video_edid_dtd_to_ctfb_res_modes(struct edid_detailed_timing *t,
+ struct ctfb_res_modes *mode);
diff --git a/drivers/video/x86_fb.c b/drivers/video/x86_fb.c
index 8743a8c..6641033 100644
--- a/drivers/video/x86_fb.c
+++ b/drivers/video/x86_fb.c
@@ -32,6 +32,7 @@
sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
bits_per_pixel);
printf("%s\n", gdev->modeIdent);
+ debug("Frame buffer at %x\n", gdev->frameAdrs);
return (void *)gdev;
}
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
deleted file mode 100644
index 3deeeea..0000000
--- a/include/74xx_7xx.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * 74xx_7xx.h
- *
- * 74xx/7xx specific definitions
- */
-
-#ifndef __MPC74XX_H__
-#define __MPC74XX_H__
-
-/*----------------------------------------------------------------
- * Exception offsets (PowerPC standard)
- */
-#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
-#define _START_OFFSET EXC_OFF_SYS_RESET
-
-/*----------------------------------------------------------------
- * l2cr values
- */
-#define l2cr 1017
-
-#define L2CR_L2E 0x80000000 /* bit 0 - enable */
-#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
-#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
-#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
-#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
-#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
-#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
-#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
-#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
-#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
-#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
-#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
-#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
-#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
-#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
-#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
-#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
-#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
-#define L2CR_TS 0x00040000 /* bit 13 - test support on */
-#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
-#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
-#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
-#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
-#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
-
-#ifndef __ASSEMBLY__
-/* cpu ids we detect */
-typedef enum __cpu_t {
- CPU_740, CPU_750,
- CPU_740P, CPU_750P,
- CPU_745, CPU_755,
- CPU_750CX, CPU_750FX, CPU_750GX,
- CPU_7400,
- CPU_7410,
- CPU_7447A, CPU_7448,
- CPU_7450, CPU_7455, CPU_7457,
- CPU_UNKNOWN} cpu_t;
-
-extern cpu_t get_cpu_type(void);
-
-#define l1icache_enable icache_enable
-
-void l2cache_enable(void);
-void l1dcache_enable(void);
-
-static __inline__ unsigned long get_msr (void)
-{
- unsigned long msr;
- asm volatile("mfmsr %0" : "=r" (msr) :);
- return msr;
-}
-
-static __inline__ void set_msr (unsigned long msr)
-{
- asm volatile("mtmsr %0" : : "r" (msr));
-}
-
-static __inline__ unsigned long get_hid0 (void)
-{
- unsigned long hid0;
- asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
- return hid0;
-}
-
-static __inline__ unsigned long get_hid1 (void)
-{
- unsigned long hid1;
- asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
- return hid1;
-}
-
-static __inline__ void set_hid0 (unsigned long hid0)
-{
- asm volatile("mtspr 1008, %0" : : "r" (hid0));
-}
-
-static __inline__ void set_hid1 (unsigned long hid1)
-{
- asm volatile("mtspr 1009, %0" : : "r" (hid1));
-}
-
-#endif /* __ASSEMBLY__ */
-#endif /* __MPC74XX_H__ */
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 9c5a1e1..3d14d5f 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -91,6 +91,12 @@
unsigned long malloc_limit; /* limit address */
unsigned long malloc_ptr; /* current address */
#endif
+#ifdef CONFIG_PCI
+ struct pci_controller *hose; /* PCI hose for early use */
+#endif
+#ifdef CONFIG_PCI_BOOTDELAY
+ int pcidelay_done;
+#endif
struct udevice *cur_serial_dev; /* current serial device */
struct arch_global_data arch; /* architecture-specific data */
} gd_t;
diff --git a/include/axp209.h b/include/axp209.h
index 21efce6..0436249 100644
--- a/include/axp209.h
+++ b/include/axp209.h
@@ -4,6 +4,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#define AXP_GPIO
+
extern int axp209_set_dcdc2(int mvolt);
extern int axp209_set_dcdc3(int mvolt);
extern int axp209_set_ldo2(int mvolt);
@@ -12,3 +14,8 @@
extern int axp209_init(void);
extern int axp209_poweron_by_dc(void);
extern int axp209_power_button(void);
+
+extern int axp_gpio_direction_input(unsigned int pin);
+extern int axp_gpio_direction_output(unsigned int pin, unsigned int val);
+extern int axp_gpio_get_value(unsigned int pin);
+extern int axp_gpio_set_value(unsigned int pin, unsigned int val);
diff --git a/include/axp221.h b/include/axp221.h
index 26d25ff..6f24a61 100644
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -10,22 +10,39 @@
#define AXP221_CTRL_ADDR 0x3e
#define AXP221_INIT_DATA 0x3e
+#define AXP223_DEVICE_ADDR 0x3a3
+#define AXP223_RUNTIME_ADDR 0x2d
+#define AXP223_DEVICE_MODE_DATA 0x7c3e00
+
+/* Page 0 addresses */
#define AXP221_CHIP_ID 0x03
#define AXP221_OUTPUT_CTRL1 0x10
+#define AXP221_OUTPUT_CTRL1_DCDC0_EN (1 << 0)
+#define AXP221_OUTPUT_CTRL1_DCDC1_EN (1 << 1)
+#define AXP221_OUTPUT_CTRL1_DCDC2_EN (1 << 2)
+#define AXP221_OUTPUT_CTRL1_DCDC3_EN (1 << 3)
+#define AXP221_OUTPUT_CTRL1_DCDC4_EN (1 << 4)
+#define AXP221_OUTPUT_CTRL1_DCDC5_EN (1 << 5)
#define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6)
#define AXP221_OUTPUT_CTRL1_ALDO2_EN (1 << 7)
#define AXP221_OUTPUT_CTRL2 0x12
+#define AXP221_OUTPUT_CTRL2_ELDO1_EN (1 << 0)
+#define AXP221_OUTPUT_CTRL2_ELDO2_EN (1 << 1)
+#define AXP221_OUTPUT_CTRL2_ELDO3_EN (1 << 2)
#define AXP221_OUTPUT_CTRL2_DLDO1_EN (1 << 3)
#define AXP221_OUTPUT_CTRL2_DLDO2_EN (1 << 4)
#define AXP221_OUTPUT_CTRL2_DLDO3_EN (1 << 5)
#define AXP221_OUTPUT_CTRL2_DLDO4_EN (1 << 6)
-#define AXP221_OUTPUT_CTRL2_DCDC1_EN (1 << 7)
+#define AXP221_OUTPUT_CTRL2_DCDC1SW_EN (1 << 7)
#define AXP221_OUTPUT_CTRL3 0x13
#define AXP221_OUTPUT_CTRL3_ALDO3_EN (1 << 7)
#define AXP221_DLDO1_CTRL 0x15
#define AXP221_DLDO2_CTRL 0x16
#define AXP221_DLDO3_CTRL 0x17
#define AXP221_DLDO4_CTRL 0x18
+#define AXP221_ELDO1_CTRL 0x19
+#define AXP221_ELDO2_CTRL 0x1a
+#define AXP221_ELDO3_CTRL 0x1b
#define AXP221_DCDC1_CTRL 0x21
#define AXP221_DCDC2_CTRL 0x22
#define AXP221_DCDC3_CTRL 0x23
@@ -34,6 +51,17 @@
#define AXP221_ALDO1_CTRL 0x28
#define AXP221_ALDO2_CTRL 0x29
#define AXP221_ALDO3_CTRL 0x2a
+#define AXP221_VBUS_IPSOUT 0x30
+#define AXP221_VBUS_IPSOUT_DRIVEBUS (1 << 2)
+#define AXP221_MISC_CTRL 0x8f
+#define AXP221_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
+#define AXP221_PAGE 0xff
+
+/* Page 1 addresses */
+#define AXP221_SID 0x20
+
+/* We support drivebus control */
+#define AXP_DRIVEBUS
int axp221_set_dcdc1(unsigned int mvolt);
int axp221_set_dcdc2(unsigned int mvolt);
@@ -47,4 +75,8 @@
int axp221_set_aldo1(unsigned int mvolt);
int axp221_set_aldo2(unsigned int mvolt);
int axp221_set_aldo3(unsigned int mvolt);
+int axp221_set_eldo(int eldo_num, unsigned int mvolt);
int axp221_init(void);
+int axp221_get_sid(unsigned int *sid);
+int axp_drivebus_enable(void);
+int axp_drivebus_disable(void);
diff --git a/include/bootm.h b/include/bootm.h
index b3d1a62..6181488 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -56,4 +56,21 @@
void arch_preboot_os(void);
+/**
+ * bootm_decomp_image() - decompress the operating system
+ *
+ * @comp: Compression algorithm that is used (IH_COMP_...)
+ * @load: Destination load address in U-Boot memory
+ * @image_start Image start address (where we are decompressing from)
+ * @type: OS type (IH_OS_...)
+ * @load_bug: Place to decompress to
+ * @image_buf: Address to decompress from
+ * @image_len: Number of bytes in @image_buf to decompress
+ * @unc_len: Available space for decompression
+ * @return 0 if OK, -ve on error (BOOTM_ERR_...)
+ */
+int bootm_decomp_image(int comp, ulong load, ulong image_start, int type,
+ void *load_buf, void *image_buf, ulong image_len,
+ uint unc_len, ulong *load_end);
+
#endif
diff --git a/include/common.h b/include/common.h
index 29350e4..4b3e0d3 100644
--- a/include/common.h
+++ b/include/common.h
@@ -435,13 +435,6 @@
extern ssize_t spi_write (uchar *, int, uchar *, int);
#endif
-#ifdef CONFIG_EVB64260
-void evb64260_init(void);
-void debug_led(int, int);
-void display_mem_map(void);
-void perform_soft_reset(void);
-#endif
-
/* $(BOARD)/$(BOARD).c */
int board_early_init_f (void);
int board_late_init (void);
@@ -486,10 +479,6 @@
void trap_init (ulong);
#if defined (CONFIG_4xx) || \
defined (CONFIG_MPC5xxx) || \
- defined (CONFIG_74xx_7xx) || \
- defined (CONFIG_74x) || \
- defined (CONFIG_75x) || \
- defined (CONFIG_74xx) || \
defined (CONFIG_MPC85xx) || \
defined (CONFIG_MPC86xx) || \
defined (CONFIG_MPC83xx)
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index be616e8..becbe3f 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -90,15 +90,8 @@
#endif
#ifdef CONFIG_CMD_USB
-#define BOOTENV_RUN_USB_INIT "run usb_init; "
-#define BOOTENV_SET_USB_NEED_INIT "setenv usb_need_init; "
+#define BOOTENV_RUN_USB_INIT "usb start; "
#define BOOTENV_SHARED_USB \
- "usb_init=" \
- "if ${usb_need_init}; then " \
- "setenv usb_need_init false; " \
- "usb start 0; " \
- "fi\0" \
- \
"usb_boot=" \
BOOTENV_RUN_USB_INIT \
BOOTENV_SHARED_BLKDEV_BODY(usb)
@@ -106,7 +99,6 @@
#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV
#else
#define BOOTENV_RUN_USB_INIT
-#define BOOTENV_SET_USB_NEED_INIT
#define BOOTENV_SHARED_USB
#define BOOTENV_DEV_USB \
BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
@@ -202,7 +194,7 @@
\
BOOT_TARGET_DEVICES(BOOTENV_DEV) \
\
- "bootcmd=" BOOTENV_SET_USB_NEED_INIT BOOTENV_SET_SCSI_NEED_INIT \
+ "bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \
"for target in ${boot_targets}; do " \
"run bootcmd_${target}; " \
"done\0"
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
deleted file mode 100644
index 2678f50..0000000
--- a/include/configs/APC405.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * (C) Copyright 2005-2008
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_APCG405 1 /* ...on a APC405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_BOARD_EARLY_INIT_R 1
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */
-#define CONFIG_BOOTCOUNT_LIMIT 1
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_SYS_USB_LOAD_COMMAND "fatload usb 0 200000 pImage;" \
- "fatload usb 0 300000 pImage.initrd"
-#define CONFIG_SYS_USB_SELF_COMMAND "usb start;run usb_load;usb stop;" \
- "run ramargs addip addcon usbargs;" \
- "bootm 200000 300000"
-#define CONFIG_SYS_USB_ARGS "setenv bootargs $(bootargs) usbboot=1"
-#define CONFIG_SYS_BOOTLIMIT "3"
-#define CONFIG_SYS_ALT_BOOTCOMMAND "run usb_self;reset"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hostname=abg405\0" \
- "bd_type=abg405\0" \
- "serial#=AA0000\0" \
- "kernel_addr=fe000000\0" \
- "ramdisk_addr=fe100000\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname)::off panic=1\0" \
- "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)" \
- " $(optargs)\0" \
- "flash_self=run ramargs addip addcon;" \
- "bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;" \
- "bootm\0" \
- "rootpath=/tftpboot/abg405/target_root\0" \
- "img=/tftpboot/abg405/pImage\0" \
- "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0" \
- "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
- "cp.b 100000 fff80000 80000\0" \
- "ipaddr=10.0.111.111\0" \
- "netmask=255.255.0.0\0" \
- "serverip=10.0.0.190\0" \
- "splashimage=ffe80000\0" \
- "usb_load="CONFIG_SYS_USB_LOAD_COMMAND"\0" \
- "usb_self="CONFIG_SYS_USB_SELF_COMMAND"\0" \
- "usbargs="CONFIG_SYS_USB_ARGS"\0" \
- "bootlimit="CONFIG_SYS_BOOTLIMIT"\0" \
- "altbootcmd="CONFIG_SYS_ALT_BOOTCOMMAND"\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self;reset"
-
-#define CONFIG_ETHADDR 00:02:27:8e:00:00
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_USB
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_AUTO_UPDATE 1 /* autoupdate via CF or USB */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/* Only interrupt boot if space is pressed */
-/* If a long serial cable is connected but */
-/* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT \
- "Press SPACE to abort autoboot in %d seconds\n", bootdelay
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*
- * PCI stuff
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-#define CONFIG_PCI_SKIP_HOST_BRIDGE 1
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*
- * IDE/ATA stuff
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init. Memory map for Linux */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
-#define CONFIG_SYS_FLASH_QUIET_TEST 1
-#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { \
- {0xfe000000, 0x500000}, \
- {0xffe80000, 0x180000} \
- }
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_BANKS_LIST { \
- CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT \
- }
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the */
- /* beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
-#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting vendor vars */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define FLASH0_BA (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT) /* FLASH 0 BA */
-#define FLASH1_BA CONFIG_SYS_FLASH_BASE /* FLASH 1 Base Address */
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define DUART0_BA 0xF0000400 /* DUART Base Address */
-#define DUART1_BA 0xF0000408 /* DUART Base Address */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define PS2_BA 0xF0000600 /* PS/2 Base Address */
-#define CF_BA 0xF0100000 /* CompactFlash Base Address */
-#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */
-#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */
-#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */
-#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */
-#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
-
-#define CONFIG_SYS_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
-#define CONFIG_SYS_EBC_PB0AP_HWREV8 CONFIG_SYS_EBC_PB0AP
-#define CONFIG_SYS_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
-
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (PCMCIA Slot 1) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 5 (Epson VGA) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CONFIG_SYS_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 6 (PCMCIA Slot 2) initialization */
-#define CONFIG_SYS_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
-
-/*
- * FPGA stuff
- */
-
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_CTRL 0x008
-#define CONFIG_SYS_FPGA_CTRL2 0x00a
-
-/* FPGA Control Reg */
-#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
-#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*
- * LCD Setup
- */
-#define CONFIG_SYS_LCD_BIG_MEM (VGA_BA + 0x200000) /* S1D13806 Mem Base */
-#define CONFIG_SYS_LCD_BIG_REG VGA_BA /* S1D13806 Reg Base */
-
-#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */
-
-/* Image information... */
-#define CONFIG_LCD_USED CONFIG_LCD_BIG
-
-#define CONFIG_SYS_LCD_MEM CONFIG_SYS_LCD_BIG_MEM
-#define CONFIG_SYS_LCD_REG CONFIG_SYS_LCD_BIG_REG
-
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-/* reserve some memory for BOOT limit info */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
-#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8)
-#endif
-
-/*
- * PCI OHCI controller
- */
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_PCI_OHCI 1
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
deleted file mode 100644
index 45dd46a..0000000
--- a/include/configs/AR405.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
-#define CONFIG_AR405 1 /* ...on a AR405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-#if 0
-#define CONFIG_BOOTARGS "root=/dev/nfs " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
- "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
-#else
-#define CONFIG_BOOTARGS "root=/dev/hda1 " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
-
-#endif
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MII
-#undef CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_BSP
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xfff00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xfff00001 /* 1MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
-
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (CAN0, 1, 2, 3) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */
-#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (Expension Bus) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (16552) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */
-#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 4 (FPGA regs) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */
-#define CONFIG_SYS_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
-
-/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x92015480
-#define CONFIG_SYS_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
deleted file mode 100644
index 2ff9b59..0000000
--- a/include/configs/ASH405.h
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_ASH405 1 /* ...on a ASH405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define DUART0_BA 0xF0000400 /* DUART Base Address */
-#define DUART1_BA 0xF0000408 /* DUART Base Address */
-#define DUART2_BA 0xF0000410 /* DUART Base Address */
-#define DUART3_BA 0xF0000418 /* DUART Base Address */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define CONFIG_SYS_NAND_BASE 0xF4000000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
-
-#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index eeb0671..6aaaaa4 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -433,6 +433,7 @@
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index e8a8d29..59a8d1b 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -675,6 +675,7 @@
#define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
#ifdef CONFIG_SDCARD
#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index ecb3d7b..e24b923 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -581,4 +581,6 @@
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#include <asm/fsl_secure_boot.h>
+
#endif /* __CONFIG_H */
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
deleted file mode 100644
index 27539d2..0000000
--- a/include/configs/CATcenter.h
+++ /dev/null
@@ -1,750 +0,0 @@
-/*
- * ueberarbeitet durch Christoph Seyfert
- *
- * (C) Copyright 2004-2005 DENX Software Engineering,
- * Wolfgang Grandegger <wg@denx.de>
- * (C) Copyright 2003
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * Credits: Stefan Roese, Wolfgang Denk
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
-#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
-#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
-#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
-#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
-#endif
-
-/* Only one of the following two symbols must be defined (default is 25 MHz)
- * CONFIG_PPCHAMELEON_CLK_25
- * CONFIG_PPCHAMELEON_CLK_33
- */
-#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_PPCHAMELEON_CLK_25
-#endif
-
-#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
-#error "* Two external frequencies (SysClk) are defined! *"
-#endif
-
-#undef CONFIG_PPCHAMELEON_SMI712
-
-/*
- * Debug stuff
- */
-#undef __DEBUG_START_FROM_SRAM__
-#define __DISABLE_MACHINE_EXCEPTION__
-
-#ifdef __DEBUG_START_FROM_SRAM__
-#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#else
-# error "* External frequency (SysClk) not defined! *"
-#endif
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_VERSION_VARIABLE 1 /* add version variable */
-#define CONFIG_IDENT_STRING "1"
-
-#undef CONFIG_BOOTARGS
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-#define CONFIG_PPC4xx_EMAC
-#undef CONFIG_EXT_PHY
-
-#define CONFIG_MII 1 /* MII PHY management */
-#ifndef CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
-#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
-#else
-#define CONFIG_PHY_ADDR 2 /* PHY address */
-#endif
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND0_BASE 0xFF400000
-#define CONFIG_SYS_NAND1_BASE 0xFF000000
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
-#define NAND_BIG_DELAY_US 25
-
-/* For CATcenter there is only NAND on the module */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_NO_RB
-
-#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
-#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
-#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
-#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
-
-
-#define MACRO_NAND_DISABLE_CE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_ENABLE_CE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRALE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_SETALE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
- switch((unsigned long)nandptr) { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
- break; \
- } \
-} while(0)
-
-#ifdef NAND_NO_RB
-/* constant delay (see also tR in the datasheet) */
-#define NAND_WAIT_READY(nand) do { \
- udelay(12); \
-} while (0)
-#else
-/* use the R/B pin */
-/* TBD */
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#if 0 /* No PCI on CATcenter */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-#endif /* No PCI */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
-#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
-#define CONFIG_ENV_SIZE_REDUND 0x2000
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (External SRAM) initialization */
-/* Since this must replace NOR Flash, we use the same settings for CS0 */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x92015480
-#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x92015480
-#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
-
-#ifdef CONFIG_PPCHAMELEON_SMI712
-/*
- * Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_VIDEO_BMP_LOGO*/
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
-#define CONFIG_SYS_ISA_IO 0xE8000000
-/* see also drivers/video/videomodes.c */
-#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
-#endif
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE 0x00
-#define CONFIG_SYS_FPGA_STATUS 0x02
-#define CONFIG_SYS_FPGA_TS 0x04
-#define CONFIG_SYS_FPGA_TS_LOW 0x06
-#define CONFIG_SYS_FPGA_TS_CAP0 0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
-#define CONFIG_SYS_FPGA_TS_CAP1 0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
-#define CONFIG_SYS_FPGA_TS_CAP2 0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30] - EMAC0 input
- * GPIO0[31] - EMAC1 reject packet as output
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
-
-#define CONFIG_NO_SERIAL_EEPROM
-
-/*--------------------------------------------------------------------*/
-
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-----------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-! are plugged in the board will be utilized as non-ECC DIMMs.
-!-----------------------------------------------------------------------
-*/
-#undef AUTO_MEMORY_CONFIG
-#define DIMM_READ_ADDR 0xAB
-#define DIMM_WRITE_ADDR 0xAA
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
- /* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
- /* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
- /* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
- /* PLL tune bits */
-#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
-
-/* Defines for CPC0_PLLMR0 Register fields */
- /* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
- /* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
- /* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
- /* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
- /* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
- /* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#else
-#error "* External frequency (SysClk) not defined! *"
-#endif
-
-#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-/* Model HI */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
-#define CONFIG_SYS_OPB_FREQ 55555555
-/* Model ME */
-#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ 66666666
-#else
-/* Model BA (default) */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ 66666666
-#endif
-
-#endif /* CONFIG_NO_SERIAL_EEPROM */
-
-#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nand"
-#define CONFIG_JFFS2_PART_SIZE 0x00200000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support
- *
- * Note: fake mtd_id used, no linux mtd map file
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nand0=catcenter"
-#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
deleted file mode 100644
index 5b872f6..0000000
--- a/include/configs/CMS700.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * (C) Copyright 2005
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * CMS700.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_VOM405 1 /* ...on a VOM405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-#undef CONFIG_PRAM /* no "protected RAM" */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * RTC stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
-
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_MAX_ECCPOS 48
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-
-#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CONFIG_SYS_RAMBOOT 1
-#else
-# undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_SYS_EEPROM_WREN 1
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-#define CONFIG_SYS_PLD_BASE 0xf0000000
-#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
-/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
-/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
-/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
-
-#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
-#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 05106cd..845ed81 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -20,6 +20,8 @@
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
deleted file mode 100644
index 34252d4..0000000
--- a/include/configs/CPCI405.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-#undef CONFIG_HAS_ETH1
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_EEPROM
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_LOOPW 1 /* enable loopw command */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
-
-#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
- /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (CompactFlash IDE) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (NVRAM) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
-#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 5 (Quart) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#if 1 /* test-only */
-#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index bf85439..ceddd7a 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -23,6 +23,8 @@
#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
deleted file mode 100644
index 7d58e9d..0000000
--- a/include/configs/CPCI405AB.h
+++ /dev/null
@@ -1,373 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
-#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
-#define CONFIG_CPCI405AB 1 /* ...and special AB version */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#undef CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING /* add command line history */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT \
- "Press SPACE to abort autoboot in %d seconds\n", bootdelay
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
-
-#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-#define CONFIG_PRAM 0 /* use pram variable to overwrite */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC32) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC32 is 4096 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0, 1) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_LED_ADDR 0xF0000380
-
-/* Memory Bank 3 (CompactFlash IDE) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (NVRAM/RTC) initialization */
-/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
-#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
-#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 5 (optional Quart) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 6 (FPGA internal) initialization */
-#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE 0x00
-#define CONFIG_SYS_FPGA_STATUS 0x02
-#define CONFIG_SYS_FPGA_TS 0x04
-#define CONFIG_SYS_FPGA_TS_LOW 0x06
-#define CONFIG_SYS_FPGA_TS_CAP0 0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
-#define CONFIG_SYS_FPGA_TS_CAP1 0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
-#define CONFIG_SYS_FPGA_TS_CAP2 0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
-#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
-#define CONFIG_SYS_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */
-#define CONFIG_SYS_FPGA_MODE_SIM_OK_DIR 0x0200
-#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
-#define CONFIG_SYS_FPGA_MODE_1WIRE 0x1000
-#define CONFIG_SYS_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */
-#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL 0x4000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
-#define CONFIG_SYS_FPGA_STATUS_1WIRE 0x1000
-#define CONFIG_SYS_FPGA_STATUS_SIM_OK 0x2000
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S30 */
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
deleted file mode 100644
index c2598a3..0000000
--- a/include/configs/CPCI405DT.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
-#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_LOOPW 1 /* enable loopw command */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/* Only interrupt boot if special string is typed */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT \
- "Autobooting in %d seconds\n", bootdelay
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */
-#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
-
-#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-#endif
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0, 1) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_LED_ADDR 0xF0000380
-
-/* Memory Bank 3 (CompactFlash IDE) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (NVRAM/RTC) initialization */
-/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
-#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
-#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 5 (optional Quart) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
-#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 6 (FPGA internal) initialization */
-#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE 0x00
-#define CONFIG_SYS_FPGA_STATUS 0x02
-#define CONFIG_SYS_FPGA_TS 0x04
-#define CONFIG_SYS_FPGA_TS_LOW 0x06
-#define CONFIG_SYS_FPGA_TS_CAP0 0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
-#define CONFIG_SYS_FPGA_TS_CAP1 0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
-#define CONFIG_SYS_FPGA_TS_CAP2 0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
-#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
deleted file mode 100644
index 25365f7..0000000
--- a/include/configs/CPCIISER4.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-
-#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "bootm fff00000"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
- /* total size of a CAT24WC08 is 1024 bytes */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Uart 8bit) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */
-#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (Uart 32bit) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
-
-/* Memory Bank 3 (FPGA Reset) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
deleted file mode 100644
index 68e4a7f..0000000
--- a/include/configs/DP405.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_DP405 1 /* ...on a DP405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-#define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-
-#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CONFIG_SYS_RAMBOOT 1
-#else
-# undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
-/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
-/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
-/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
deleted file mode 100644
index 9be2310..0000000
--- a/include/configs/DU405.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_DU405 1 /* ...on a DU405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "bootm fff00000"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-#undef CONFIG_HAS_ETH1
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_EDITENV
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
- /* total size of a CAT24WC08 is 1024 bytes */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */
-#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define DUART_BA 0xF0300000 /* DUART Base Address */
-#define CF_BA 0xF0100000 /* CompactFlash Base Address */
-#define SRAM_BA 0xF0200000 /* SRAM Base Address */
-#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */
-#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */
-
-#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (CAN0) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (DUART) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 4 (CompactFlash IDE) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 5 (SRAM) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 6 (DURAG Bus IO Space) initialization */
-#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
-
-/* Memory Bank 7 (DURAG Bus Mem Space) initialization */
-#define CONFIG_SYS_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
deleted file mode 100644
index be5494b..0000000
--- a/include/configs/DU440.h
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * (C) Copyright 2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
- *
- * based on the Sequoia board configuration by
- * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- **********************************************************************
- * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
- **********************************************************************
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_DU440 1 /* Board is esd DU440 */
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
-
-#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
-#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
-#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
-#define CONFIG_SYS_PCI_IOBASE 0xe8000000
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
-#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
-
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-
-/*
- * Initial RAM & stack pointer
- */
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*
- * Video Port
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
-#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET 0 /* environment starts at */
- /* the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
-#endif
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
- /* 440EPx errata CHIP 11 */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define CONFIG_DDR_ECC /* Use ECC when available */
-#define SPD_EEPROM_ADDRESS {0x50}
-#define CONFIG_PROG_SDRAM_TLB
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-#define CONFIG_SYS_I2C_PPC4XX_CH1
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define IIC1_MCP3021_ADDR 0x4d
-#define IIC1_USB2507_ADDR 0x2c
-#define CONFIG_SYS_I2C_NOPROBES { {1, IIC1_USB2507_ADDR} }
-
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
-
-#define CONFIG_SYS_EEPROM_WREN 1
-#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
-
-/*
- * standard dtt sensor configuration - bottom bit will determine local or
- * remote sensor of the TMP401
- */
-#define CONFIG_DTT_SENSORS { 0, 1 }
-
-/*
- * The PMC440 uses a TI TMP401 temperature sensor. This part
- * is basically compatible to the ADM1021 that is supported
- * by U-Boot.
- *
- * - i2c addr 0x4c
- * - conversion rate 0x02 = 0.25 conversions/second
- * - ALERT ouput disabled
- * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
- * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
- */
-#define CONFIG_DTT_ADM1021
-#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
-
-/*
- * RTC stuff
- */
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "ethrotate=no\0" \
- "hostname=du440\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_self=run ramargs addip addtty optargs;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
- "bootm\0" \
- "rootpath=/tftpboot/du440/target_root_du440\0" \
- "img=/tftpboot/du440/uImage\0" \
- "kernel_addr=FFC00000\0" \
- "ramdisk_addr=FFE00000\0" \
- "initrd_high=30000000\0" \
- "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
- "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
- "cp.b 100000 FFFA0000 60000\0" \
- ""
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#ifndef __ASSEMBLY__
-int du440_phy_addr(int devnum);
-#endif
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
-
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#undef CONFIG_PHY_GIGE /* no GbE detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER 128
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR du440_phy_addr(1)
-
-/*
- * USB
- */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_USB
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT \
- "Press SPACE to abort autoboot in %d seconds\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_CPLD_BASE 0xC0000000
-#define CONFIG_SYS_CPLD_RANGE 0x00000010
-#define CONFIG_SYS_DUMEM_BASE 0xC0100000
-#define CONFIG_SYS_DUMEM_RANGE 0x00100000
-#define CONFIG_SYS_DUIO_BASE 0xC0200000
-#define CONFIG_SYS_DUIO_RANGE 0x00010000
-
-#define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */
-#define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x04017200
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
-#define CONFIG_SYS_EBC_PB1AP 0x018003c0
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
-
-/* Memory Bank 2 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x018003c0
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR | 0x1c000)
-
-/* Memory Bank 3 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x018003c0
-#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR | 0x1c000)
-
-/* Memory Bank 4 (DUMEM, 1MB) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x018053c0
-#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE | 0x18000)
-
-/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
-#define CONFIG_SYS_EBC_PB5AP 0x018053c0
-#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE | 0x18000)
-
-/*
- * NAND FLASH
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
- CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#define CONFIG_SOURCE 1
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
deleted file mode 100644
index debfc36..0000000
--- a/include/configs/ELPPC.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * (C) Copyright 2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define GTREGREAD(x) 0xffffffff /* needed for debug */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-/* these hardware addresses are pretty bogus, please change them to
- suit your needs */
-
-/* first ethernet */
-#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
-
-#define CONFIG_IPADDR 192.168.0.105
-#define CONFIG_SERVERIP 192.168.0.100
-
-#define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */
-
-#define CONFIG_BAUDRATE 9600 /* console baudrate */
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp 1000000; " \
- "setenv bootargs root=ramfs console=ttyS00,9600 " \
- "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
- "${netmask}:${hostname}:eth0:none; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_JFFS2
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-/*
- * choose between COM1 and COM2 as serial console
- */
-#define CONFIG_CONS_INDEX 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-#define CONFIG_SYS_BOARD_ASM_INIT
-#define CONFIG_MISC_INIT_R
-
-/*
- * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
- */
-#undef CONFIG_SYS_ADDRESS_MAP_A
-
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
-
-#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000
-
-#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
-#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000
-#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
-
-#define CONFIG_SYS_PCI_IO_BUS 0x00800000
-#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000
-#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
-
-#define CONFIG_SYS_ISA_IO_BUS 0x00000000
-#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000
-#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
-
-/* driver defines FDC,IDE,... */
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
-#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
-#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_USR_LED_BASE 0x78000000
-#define CONFIG_SYS_NVRAM_BASE 0xff000000
-#define CONFIG_SYS_UART_BASE 0xff400000
-#define CONFIG_SYS_FLASH_BASE 0xfff00000
-
-#define MPC107_EUMB_ADDR 0xfce00000
-#define MPC107_EUMB_PI 0xfce41090
-#define MPC107_EUMB_GCR 0xfce41020
-#define MPC107_EUMB_IACKR 0xfce600a0
-#define MPC107_I2C_ADDR 0xfce03000
-
-/*
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Flash mapping/organization on the MPC10x.
- */
-#define FLASH_BASE0_PRELIM 0xff800000
-#define FLASH_BASE1_PRELIM 0xffc00000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1"
-#define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
-*/
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
-#undef CONFIG_SYS_MEMTEST
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#define CONFIG_SYS_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */
-#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
-#define CONFIG_ENV_ADDR 0x0
-#define CONFIG_ENV_MAP_ADRS 0xff000000
-#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
-#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
-
-/*
- * Serial devices
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 24000000
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_UART_BASE + 8)
-
-/*
- * PCI stuff
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO
-#undef CONFIG_PCI_SCAN_SHOW
-
-/*
- * Optional Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
-#define VIDEO_TSTC_FCT serial_stub_tstc
-#define VIDEO_GETC_FCT serial_stub_getc
-
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-
-/*
- * Initial BATs
- */
-#if 1
-
-#define CONFIG_SYS_IBAT0L 0
-#define CONFIG_SYS_IBAT0U 0
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
-
-#define CONFIG_SYS_IBAT1L 0
-#define CONFIG_SYS_IBAT1U 0
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-#define CONFIG_SYS_IBAT2L 0
-#define CONFIG_SYS_IBAT2U 0
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-#define CONFIG_SYS_IBAT3L 0
-#define CONFIG_SYS_IBAT3U 0
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#else
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
-
-/* address range for flashes */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* ISA IO space */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* ISA memory space */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#endif
-
-/*
- * Speed settings are board specific
- */
-#define CONFIG_SYS_BUS_CLK 100000000
-#define CONFIG_SYS_CPU_CLK 400000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * L2CR setup -- make sure this is right for your board!
- * look in include/74xx_7xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-#if 1
-#define L2_INIT 0 /* cpu 750 CXe*/
-#else
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
deleted file mode 100644
index 0c66092..0000000
--- a/include/configs/G2000.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_G2000 1 /* ...on a PLU405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#if 0 /* test-only */
-#define CONFIG_BAUDRATE 115200
-#else
-#define CONFIG_BAUDRATE 9600
-#endif
-
-#define CONFIG_PREBOOT
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off\0" \
- "addmisc=setenv bootargs ${bootargs} " \
- "console=ttyS0,${baudrate} " \
- "panic=1\0" \
- "flash_nfs=run nfsargs addip addmisc;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};" \
- "run nfsargs addip addmisc;bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/g2000/pImage\0" \
- "kernel_addr=ff800000\0" \
- "ramdisk_addr=ff900000\0" \
- "pciconfighost=yes\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run net_nfs"
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_PHY1_ADDR 1 /* PHY address */
-
-#if 0 /* test-only */
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#if 0 /* test-only */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*----------------------------------------------------------------------------*/
-/* adding Ethernet setting: FTS OUI 00:11:0B */
-/*----------------------------------------------------------------------------*/
-#define CONFIG_ETHADDR 00:11:0B:00:00:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:11:0B:00:00:02
-#define CONFIG_IPADDR 10.48.8.178
-#define CONFIG_IP1ADDR 10.48.8.188
-#define CONFIG_NETMASK 255.255.255.128
-#define CONFIG_SERVERIP 10.48.8.138
-
-/*-----------------------------------------------------------------------
- * RTC stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-#if 0 /* test-only */
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#if 0 /* APC405 */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* test-only...*/
-#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */
-#else /* G2000 */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* test-only...*/
-#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */
-#endif
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#if 1 /* test-only */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#else /* DEFAULT: environment in flash, using redundand flash sectors */
-
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CONFIG_ENV_ADDR 0xFFFA0000 /* environment starts before u-boot */
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k bytes may be used for env vars*/
-
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
-/* CAT24WC08/16... */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Intel Strata Flash) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFF87A000 /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 1 ( Power TAU) initialization */
-/* #define CONFIG_SYS_EBC_PB1AP 0x04041000 */
-/* #define CONFIG_SYS_EBC_PB1CR 0xF0018000 */ /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB1AP 0x00000000
-#define CONFIG_SYS_EBC_PB1CR 0x00000000
-
-/* Memory Bank 2 (Intel Flash) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x00000000
-#define CONFIG_SYS_EBC_PB2CR 0x00000000
-
-/* Memory Bank 3 (NAND) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x92015480
-#define CONFIG_SYS_EBC_PB3CR 0xF40B8000 /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
-
-/* Memory Bank 4 (FPGA regs) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x00000000
-#define CONFIG_SYS_EBC_PB4CR 0x00000000 /* leave it blank */
-
-#define CONFIG_SYS_NAND_BASE 0xF4000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- *
- * following GPIO setting changed for G20000, 080304
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40005555
-#define CONFIG_SYS_GPIO0_OSRH 0x40000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_266_66_33_33
-#define PLLMR1_DEFAULT PLLMR1_266_66_33_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
deleted file mode 100644
index 033dcbf..0000000
--- a/include/configs/HH405.h
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_HH405 1 /* ...on a HH405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT "autoupd"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "pciconfighost=1\0" \
- ""
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-/*
- * Video console
- */
-#define CONFIG_VIDEO /* for sm501 video support */
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501
-#if 0
-#define CONFIG_VIDEO_SM501_32BPP
-#else
-#define CONFIG_VIDEO_SM501_16BPP
-#endif
-#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
-
-#endif /* CONFIG_VIDEO */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_CMD_BMP
-#endif
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
-#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
-
-#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * RTC stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */
-
-#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CONFIG_SYS_RAMBOOT 1
-#else
-# undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#if 0 /* test-only */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#else
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#endif
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
-#define CONFIG_SYS_EEPROM_WREN 1
-
-#if 1 /* test-only */
-/* CAT24WC08/16... */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#else
-/* CAT24WC32/64... */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#endif
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define LCD_BA 0xF1000000 /* Epson LCD Base Address */
-#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
-#define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (Epson LCD) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * LCD Setup
- */
-
-#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
-#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
-#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
-#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
-
-/*-----------------------------------------------------------------------
- * Universal Interrupt Controller (UIC) Setup
- */
-
-/*
- * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
- */
-#define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-
-#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
-
-#define LCD_CLK_OFF 0x0000 /* Off */
-#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
-#define LCD_CLK_03135 0x2000 /* 3.135 MHz */
-#define LCD_CLK_04165 0x3000 /* 4.165 MHz */
-#define LCD_CLK_06250 0x4000 /* 6.250 MHz */
-#define LCD_CLK_08330 0x5000 /* 8.330 MHz */
-#define LCD_CLK_12500 0x6000 /* 12.50 MHz */
-#define LCD_CLK_25000 0x7000 /* 25.00 MHz */
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
-
-#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
-#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
-#define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */
-#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
-#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
deleted file mode 100644
index 1783b9f..0000000
--- a/include/configs/HUB405.h
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_HUB405 1 /* ...on a HUB405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#undef CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: UART) initialization */
-#if 0
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#else
-#define CONFIG_SYS_EBC_PB2AP 0x92015480
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#endif
-
-#define DUART0_BA 0xF0000000 /* DUART Base Address */
-#define DUART1_BA 0xF0000008 /* DUART Base Address */
-#define DUART2_BA 0xF0000010 /* DUART Base Address */
-#define DUART3_BA 0xF0000018 /* DUART Base Address */
-#define CONFIG_SYS_NAND_BASE 0xF4000000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
-
-#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
-#define CONFIG_SYS_UART2_RS232 (0x80000000 >> 5)
-#define CONFIG_SYS_UART3_RS232 (0x80000000 >> 6)
-#define CONFIG_SYS_UART4_RS232 (0x80000000 >> 7)
-#define CONFIG_SYS_UART5_RS232 (0x80000000 >> 8)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
deleted file mode 100644
index 1861aa8..0000000
--- a/include/configs/IceCube.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
-#define CONFIG_ICECUBE 1 /* ... on IceCube board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000 boot high (standard configuration)
- * 0xFF000000 boot low for 16 MiB boards
- * 0xFF800000 boot low for 8 MiB boards
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI
-
-#if defined(CONFIG_PCI)
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-#endif
-
-#define CONFIG_SYS_XLB_PIPELINING 1
-
-#define CONFIG_MII 1
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
-#define CONFIG_SYS_OHCI_BE_CONTROLLER
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT16 1
-#endif
-#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-#if defined(CONFIG_LITE5200B)
-# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
-#else
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT08 1
-#endif
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/MPC5200/uImage\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#else
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_CPU "PowerPC,5200@0"
-#define OF_SOC "soc5200@f0000000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-
-/*
- * Flash configuration
- */
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#if defined(CONFIG_SYS_LOWBOOT08)
-# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
-#endif
-#if defined(CONFIG_SYS_LOWBOOT16)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
-#endif
-#endif /* CONFIG_SYS_LOWBOOT */
-#else /* !CONFIG_LITE5200B (IceCube)*/
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-#if !defined(CONFIG_SYS_LOWBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
-#else /* CONFIG_SYS_LOWBOOT */
-#if defined(CONFIG_SYS_LOWBOOT08)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
-#endif
-#if defined(CONFIG_SYS_LOWBOOT16)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
-#endif
-#endif /* CONFIG_SYS_LOWBOOT */
-#endif /* CONFIG_LITE5200B */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
-
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
-
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
-#endif
-
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#else
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#endif
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- */
-#ifdef CONFIG_MPC5200_DDR
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
-#else
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#if defined(CONFIG_LITE5200B)
-#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_CFG 0x00047800
-#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00047800
-#else /* IceCube aka Lite5200 */
-#ifdef CONFIG_MPC5200_DDR
-
-#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
-#define CONFIG_SYS_BOOTCS_SIZE 0x00800000
-#define CONFIG_SYS_BOOTCS_CFG 0x00047801
-#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS1_SIZE 0x00800000
-#define CONFIG_SYS_CS1_CFG 0x00047800
-
-#else /* !CONFIG_MPC5200_DDR */
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00047801
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#endif /* CONFIG_MPC5200_DDR */
-#endif /*CONFIG_LITE5200B */
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#define CONFIG_ATAPI 1
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
deleted file mode 100644
index aefde74..0000000
--- a/include/configs/MPC8360EMDS.h
+++ /dev/null
@@ -1,735 +0,0 @@
-/*
- * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
-#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
-#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_CLKIN_33MHZ
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 33330000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 33330000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 33330000
-#endif
-
-#elif defined(CONFIG_CLKIN_66MHZ)
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-#endif
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
-#endif
-#else
-#error Unknown oscillator frequency.
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#ifdef CONFIG_CLKIN_33MHZ
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_8X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CE_PLL_VCO_DIV_4 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X15 |\
- HRCWL_CORE_TO_CSB_2X1)
-#elif defined(CONFIG_CLKIN_66MHZ)
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CE_PLL_VCO_DIV_4 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X6 |\
- HRCWL_CORE_TO_CSB_2X1)
-#endif
-
-#ifdef CONFIG_PCISLAVE
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_AGENT |\
- HRCWH_PCI1_ARBITER_DISABLE |\
- HRCWH_PCICKDRV_DISABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCICKDRV_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT)
-#endif
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x00000000
-#define CONFIG_SYS_SICRL 0x40000000
-
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
- /* + 256M */
-#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000)
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_DDR_ECC /* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
-
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#if defined(CONFIG_SPD_EEPROM)
-/*
- * Determine DDR configuration from I2C interface.
- */
-#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
-#else
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR 0x80080001
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
-#define CONFIG_SYS_DDR_TIMING_0 0x00220802
-#define CONFIG_SYS_DDR_TIMING_1 0x38357322
-#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
-#define CONFIG_SYS_DDR_MODE 0x47d00432
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#else
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_9)
-#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
-#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
-#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
-#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
-#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
-#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
-#endif
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00100000
-
-/*
- * The reserved memory
- */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * BCSR on the Local Bus
- */
-#define CONFIG_SYS_BCSR 0xF8000000
- /* Access window base at BCSR base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xFFFFE9F7 */
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-#define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */
-
-#ifdef CONFIG_SYS_LB_SDRAM
-#define CONFIG_SYS_LBLAWBAR2 0
-#define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB)
-
-/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- *
- * For BR2, need:
- * Base address = BR[0:16] = dynamic
- * port size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
- */
-
-/* Port size=32bit, MSEL=DRAM */
-#define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
- | OR_SDRAM_XAM \
- | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
- | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
- | OR_SDRAM_EAD)
- /* 0xFC006901 */
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-
-#endif
-
-/*
- * Windows to access Platform I/O Boards (PIB) via local bus
- */
-#define CONFIG_SYS_PIB_BASE 0xF8008000
-#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
-
-/* [RFC] This LBLAW only covers the 2nd window (CS5) */
-#define CONFIG_SYS_LBLAWBAR3_PRELIM \
- CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-
-/*
- * CS4 on Local Bus, to PIB
- */
- /* CS4 base address at 0xf8008000 */
-#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8008801 */
-#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
-
-/*
- * CS5 on Local Bus, to PIB
- */
- /* CS5 base address at 0xf8010000 */
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \
- CONFIG_SYS_PIB_WINDOW_SIZE) \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
- /* 0xF8010801 */
-#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \
- | OR_GPCM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
- /* 0xffffe9f7 */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_83XX_PCI_STREAMING
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-
-#define CONFIG_HWCONFIG 1
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-#define CONFIG_PHY_MODE_NEED_CHANGE
-
-#define CONFIG_UEC_ETH1 /* GETH1 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 0
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
-#endif
-
-#define CONFIG_UEC_ETH2 /* GETH2 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
-#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 1
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
-#endif
-
-/*
- * Environment
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x20000
- #define CONFIG_ENV_SIZE 0x2000
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_SDRAM
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-#define CONFIG_BAT_RW
-
-/* DDR/LBC SDRAM: cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* BCSR: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* DDR/LBC SDRAM next 256M: cacheable */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc836x_mds.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
deleted file mode 100644
index 1b8bad1..0000000
--- a/include/configs/MPC8360ERDK.h
+++ /dev/null
@@ -1,620 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_QE 1 /* Has QE */
-#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
-#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFF800000
-
-/*
- * System Clock Setup
- */
-#ifdef CONFIG_CLKIN_33MHZ
-#define CONFIG_83XX_CLKIN 33333333
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_PCI_33M 1
-#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
-#else
-#define CONFIG_83XX_CLKIN 66000000
-#define CONFIG_SYS_CLK_FREQ 66000000
-#define CONFIG_PCI_66M 1
-#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
-#endif /* CONFIG_CLKIN_33MHZ */
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
- HRCWL_CORE_TO_CSB_2X1 |\
- HRCWL_CE_TO_PLL_1X15)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCICKDRV_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_SECONDARY_DDR_DISABLE |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_EARLY)
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x00000000
-#define CONFIG_SYS_SICRL 0x40000000
-
-#define CONFIG_BOARD_EARLY_INIT_R
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR 0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_DDR_ECC /* support DDR ECC function */
-#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
-
-/*
- * DDRCDR - DDR Control Driver Register
- */
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x80080001 */
-
-#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_DDR_II
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10 \
- | CSCONFIG_ODT_WR_ONLY_CURRENT)
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_ECC_EN)
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
-#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
- | (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
-#define CONFIG_SYS_DDR_MODE 0x47800432
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-
-#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
- (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
- (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
- (0 << TIMING_CFG0_WWT_SHIFT) | \
- (0 << TIMING_CFG0_RRT_SHIFT) | \
- (0 << TIMING_CFG0_WRT_SHIFT) | \
- (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
- (2 << TIMING_CFG1_WRTORD_SHIFT) | \
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
- (3 << TIMING_CFG1_WRREC_SHIFT) | \
- (10 << TIMING_CFG1_REFREC_SHIFT) | \
- (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
- (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
- (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
- (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
- (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
- (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
- (0 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00100000
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
-#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
-
- /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 /* 16 bit port */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * NAND flash on the local bus
- */
-#define CONFIG_SYS_NAND_BASE 0x60000000
-#define CONFIG_CMD_NAND 1
-#define CONFIG_NAND_FSL_UPM 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
-/*
- * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
- * ... What's correct?
- */
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
-
-/* Port size 8 bit, UPMA */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_PS_8 \
- | BR_MS_UPMA \
- | BR_V)
- /* 0x60000881 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD)
- /* 0xFC000001 */
-
-/*
- * Fujitsu MB86277 (MINT) graphics controller
- */
-#define CONFIG_SYS_VIDEO_BASE 0x70000000
-
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-/* Port size 32 bit, UPMB */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \
- | BR_PS_32 \
- | BR_MS_UPMB \
- | BR_V)
- /* 0x000018a1 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD)
- /* 0xFC000001 */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_PCI
-
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#define CONFIG_UEC_ETH1 /* GETH1 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 2
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
-#endif
-
-#define CONFIG_UEC_ETH2 /* GETH2 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
-#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 4
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
-#endif
-
-/*
- * Environment
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
-#define CONFIG_ENV_SIZE 0x20000
-#else /* CONFIG_SYS_RAMBOOT */
-#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_LOADS
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2 HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
- | BATU_BL_4M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
- | BATU_BL_64M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
- | BATU_BL_32M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
- | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
- | BATU_BL_128K \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
- | BATU_BL_64M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#else /* CONFIG_PCI */
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_LOADADDR a00000
-#define CONFIG_HOSTNAME mpc8360erdk
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_ROOTPATH "/nfsroot/"
-
-#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "loadaddr=a00000\0" \
- "fdtaddr=900000\0" \
- "fdtfile=mpc836x_rdk.dtb\0" \
- "fsfile=fs\0" \
- "ubootfile=u-boot.bin\0" \
- "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
- "-(rootfs)\0" \
- "setbootargs=setenv bootargs console=$consoledev,$baudrate " \
- "$mtdparts panic=1\0" \
- "adddhcpargs=setenv bootargs $bootargs ip=on\0" \
- "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
- "$gatewayip:$netmask:$hostname:$netdev:off " \
- "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
- "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
- "rootfstype=jffs2 rw\0" \
- "tftp_get_uboot=tftp 100000 $ubootfile\0" \
- "tftp_get_kernel=tftp $loadaddr $bootfile\0" \
- "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
- "tftp_get_fs=tftp c00000 $fsfile\0" \
- "nand_erase_kernel=nand erase 0 400000\0" \
- "nand_erase_dtb=nand erase 400000 20000\0" \
- "nand_erase_fs=nand erase 420000 3be0000\0" \
- "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
- "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
- "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
- "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
- "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
- "nor_reflash=protect off ff800000 ff87ffff ; " \
- "erase ff800000 ff87ffff ; " \
- "cp.b 100000 ff800000 $filesize\0" \
- "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
- "nand_write_kernel\0" \
- "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
- "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
- "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
- "nand_reflash_fs\0" \
- "boot_m=bootm $loadaddr - $fdtaddr\0" \
- "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
- "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
- "boot_m\0" \
- "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
- "boot_m\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run dhcpboot"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 8ed0f7c..19e0e30 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -15,6 +15,8 @@
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XERDB 1
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_TEXT_BASE 0xFE000000
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
deleted file mode 100644
index 4680afe..0000000
--- a/include/configs/OCRTC.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_OCRTC 1 /* ...on a OCRTC board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "go fff00100"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
- /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (PLD - FPGA-boot) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (PLD - OSL) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 4 (Spartan2 1) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 5 (Spartan2 2) initialization */
-#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 6 (Virtex 1) initialization */
-#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 7 (Virtex 2) initialization */
-#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
- /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
-
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
deleted file mode 100644
index c75638a..0000000
--- a/include/configs/P1_P2_RDB.h
+++ /dev/null
@@ -1,808 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * P1 P2 RDB board configuration file
- * This file is intended to address a set of Low End and Ultra Low End
- * Freescale SOCs of QorIQ series(RDB platforms).
- * Currently only P2020RDB
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_36BIT
-#define CONFIG_PHYS_64BIT
-#endif
-
-#ifdef CONFIG_P1011RDB
-#define CONFIG_P1011
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#endif
-#ifdef CONFIG_P1020RDB
-#define CONFIG_P1020
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-#endif
-#ifdef CONFIG_P2010RDB
-#define CONFIG_P2010
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#endif
-#ifdef CONFIG_P2020RDB
-#define CONFIG_P2020
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_MMC_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
-#define CONFIG_SPL_MMC_BOOT
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SPL_MAX_SIZE (128 * 1024)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
-#define CONFIG_SPL_SPI_BOOT
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_COMMON_INIT_DDR
-#endif
-#endif
-
-#ifdef CONFIG_NAND
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SPL_NAND_BOOT
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_NAND_INIT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SPL_MAX_SIZE (128 << 10)
-#define CONFIG_SPL_TEXT_BASE 0xf8f81000
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
-#elif defined(CONFIG_SPL_BUILD)
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_TEXT_BASE 0xff800000
-#define CONFIG_SPL_MAX_SIZE 4096
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
-#endif /* not CONFIG_TPL_BUILD */
-
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_TPL_PAD_TO 0x20000
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-#endif
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff40000
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
-
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#if defined(CONFIG_PCI)
-#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#endif /* #if defined(CONFIG_PCI) */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_PCI)
-#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
-
-#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
-#define CONFIG_MP
-#endif
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x1fffffff
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
-
-/*
- * Config the L2 Cache as L2 SRAM
-*/
-#if defined(CONFIG_SPL_BUILD)
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
-#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#if defined(CONFIG_P2020RDB)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
-#else
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
-#endif
-#elif defined(CONFIG_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
-#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-#endif /* CONFIG_TPL_BUILD */
-#endif
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
-#undef CONFIG_FSL_DDR_INTERACTIVE
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB)
-/*
- * P1020 and it's derivatives support max 32bit DDR width
- * So Reduce available DDR size
-*/
-#define CONFIG_SYS_SDRAM_SIZE 512
-#else
-#define CONFIG_SYS_SDRAM_SIZE 1024
-#endif
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00FF0000
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
- * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
- * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xff000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_HWCONFIG
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
-
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-
-#define CONFIG_SYS_VSC7385_BASE 0xffb00000
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
-#else
-#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
-#endif
-
-#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
- | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
- OR_GPCM_EHTR | OR_GPCM_EAD)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* new uImage format support */
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
-
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_RTC_DS1337_NOOSC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/* eSPI - Enhanced SPI */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#if defined(CONFIG_PCI)
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-#undef CONFIG_RTL8139
-
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) (x)
-#define _IO_BASE 0x00000000
-#endif
-
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
-
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define CONFIG_VSC7385_ENET
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-/* The size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-#endif
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#elif defined(CONFIG_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_OFFSET (512 * 0x800)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#elif defined(CONFIG_NAND)
-#ifdef CONFIG_TPL_BUILD
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#else
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#endif
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET (1024 * 1024)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_MMC 1
-
-#ifdef CONFIG_MMC
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#ifdef CONFIG_P2020
-#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
-#endif
-#endif
-
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_STORAGE
-#endif
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_HOSTNAME P2020RDB
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "loadaddr=1000000\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs.ext2.gz.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=p2020rdb.dtb\0" \
- "bdev=sda1\0" \
- "jffs2nor=mtdblock3\0" \
- "norbootaddr=ef080000\0" \
- "norfdtaddr=ef040000\0" \
- "jffs2nand=mtdblock9\0" \
- "nandbootaddr=100000\0" \
- "nandfdtaddr=80000\0" \
- "nandimgsize=400000\0" \
- "nandfdtsize=80000\0" \
- "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
- "vscfw_addr=ef000000\0" \
- "othbootargs=ramdisk_size=600000\0" \
- "usbfatboot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "fatload usb 0:2 $loadaddr $bootfile;" \
- "fatload usb 0:2 $fdtaddr $fdtfile;" \
- "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "usbext2boot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
- "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
- "bootm $norbootaddr - $norfdtaddr\0" \
- "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "nand read 2000000 $nandbootaddr $nandimgsize;" \
- "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
- "bootm 2000000 - 3000000;\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h
deleted file mode 100644
index d414b84..0000000
--- a/include/configs/P2020COME.h
+++ /dev/null
@@ -1,547 +0,0 @@
-/*
- * Copyright 2009-2010,2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* The P2020COME board is only booted via the Freescale On-Chip ROM */
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-
-#define CONFIG_SYS_TEXT_BASE 0xf8f80000
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD 1
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH 1
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_P2020 1
-#define CONFIG_P2020COME 1
-#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
-#define CONFIG_MP
-
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#if defined(CONFIG_PCI)
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
-
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#endif /* #if defined(CONFIG_PCI) */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_PCI)
-#define CONFIG_E1000 1 /* E1000 pci Ethernet card */
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_ddr_clk(unsigned long dummy);
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-
-/*
- * For P2020COME DDRCLK and SYSCLK are from the same oscillator
- * For DA phase the SYSCLK is 66MHz
- * For EA phase the SYSCLK is 100MHz
- */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch prediction */
-
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x1fffffff
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
-
- /*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \
- + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-
-#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00ff0000
-
-#define CONFIG_SYS_SPD_BUS_NUM 1
-#define SPD_EEPROM_ADDRESS 0x53
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable
- * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable
- * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable
- * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable
- * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable
- * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable
- * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable
- *
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-
-/* There is no NOR Flash on P2020COME */
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-#define CONFIG_HWCONFIG
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* the assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* new uImage format support */
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#if defined(CONFIG_PCI)
-
-/* controller 3, Slot 3, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-#undef CONFIG_RTL8139
-
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x) (x)
-#define _IO_BASE 0x00000000
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 2
-#define TSEC3_PHY_ADDR 1
-
-#undef CONFIG_VSC7385_ENET
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#if defined(CONFIG_RAMBOOT_SDCARD)
- #define CONFIG_ENV_IS_IN_MMC 1
- #define CONFIG_FSL_FIXED_MMC_LOCATION
- #define CONFIG_ENV_SIZE 0x2000
- #define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
- #define CONFIG_ENV_IS_IN_SPI_FLASH
- #define CONFIG_ENV_SPI_BUS 0
- #define CONFIG_ENV_SPI_CS 0
- #define CONFIG_ENV_SPI_MAX_HZ 10000000
- #define CONFIG_ENV_SPI_MODE 0
- #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
- #define CONFIG_ENV_SECT_SIZE 0x10000
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_MMC 1
-
-#ifdef CONFIG_MMC
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#endif /* CONFIG_MMC */
-
-#define CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_STORAGE
-#endif
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/* Misc Extra Settings */
-#define CONFIG_CMD_DHCP 1
-
-#define CONFIG_CMD_DATE 1
-#define CONFIG_RTC_M41T62 1
-#define CONFIG_SYS_RTC_BUS_NUM 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20)
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ecc=on\0" \
- "bootcmd=run sdboot\0" \
- "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \
- "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
- "$othbootargs; mmcinfo; " \
- "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \
- "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \
- "bootm $loadaddr - $fdtaddr\0" \
- "sdfatboot=setenv bootargs root=/dev/ram rw " \
- "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
- "$othbootargs; mmcinfo; " \
- "fatload mmc 0:1 $loadaddr $bootfile; " \
- "fatload mmc 0:1 $fdtaddr $fdtfile; " \
- "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "usbboot=setenv bootargs root=/dev/sda1 rw " \
- "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
- "$othbootargs; " \
- "usb start; " \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \
- "bootm $loadaddr - $fdtaddr\0" \
- "usbfatboot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start; " \
- "fatload usb 0:2 $loadaddr $bootfile; " \
- "fatload usb 0:2 $fdtaddr $fdtfile; " \
- "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "usbext2boot=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs; " \
- "usb start; " \
- "ext2load usb 0:4 $loadaddr $bootfile; " \
- "ext2load usb 0:4 $fdtaddr $fdtfile; " \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
- "upgradespi=sf probe 0; " \
- "setenv startaddr 0; " \
- "setenv erasesize a0000; " \
- "tftp 1000000 $tftppath/$uboot_spi; " \
- "sf erase $startaddr $erasesize; " \
- "sf write 1000000 $startaddr $filesize; " \
- "sf erase 100000 120000\0" \
- "clearspienv=sf probe 0;sf erase 100000 20000\0" \
- "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \
- "netdev=eth0\0" \
- "rootdelaysecond=15\0" \
- "uboot_nor=u-boot-nor.bin\0" \
- "uboot_spi=u-boot-p2020.spi\0" \
- "uboot_sd=u-boot-p2020.bin\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=rootfs-dev.ext2.img\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=uImage-2.6.32-p2020.dtb\0" \
- "tftppath=p2020\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $tftppath/$bootfile;" \
- "tftp $fdtaddr $tftppath/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \
- "tftp $loadaddr $tftppath/$bootfile;" \
- "tftp $fdtaddr $tftppath/$fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
deleted file mode 100644
index 820b633..0000000
--- a/include/configs/P2020DS.h
+++ /dev/null
@@ -1,751 +0,0 @@
-/*
- * Copyright 2007-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * p2020ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifdef CONFIG_36BIT
-#define CONFIG_PHYS_64BIT
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0xf8f40000
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE 0xf8f40000
-#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_P2020 1
-#define CONFIG_P2020DS 1
-#define CONFIG_MP 1 /* support multiple processors */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff40000
-#endif
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-
-#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
-#define CONFIG_PCI 1 /* Enable PCI/PCIE */
-#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
-
-/*
- * Config the L2 Cache
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_VERY_BIG_RAM
-#ifdef CONFIG_DDR2
-#define CONFIG_SYS_FSL_DDR2
-#else
-#define CONFIG_SYS_FSL_DDR3 1
-#endif
-
-/* ECC will be enabled based on perf_mode environment variable */
-/* #define CONFIG_DDR_ECC */
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
-
-/* Default settings for "stable" mode */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330804
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
-#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
-#define CONFIG_SYS_DDR_MODE_1 0x00421422
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x61800100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
-#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
-#define CONFIG_SYS_DDR_CONTROL2 0x24400011
-#define CONFIG_SYS_DDR_CDR1 0x00040000
-#define CONFIG_SYS_DDR_CDR2 0x00000000
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-
-/* Settings that differ for "performance" mode */
-#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
-#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
-#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
-#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
-#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
-#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
-
-/*
- * The following set of values were tested for DDR2
- * with a DDR3 to DDR2 interposer
- *
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06180100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC3008000
-#define CONFIG_SYS_DDR_CONTROL2 0x04400010
- *
- */
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
- * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
- * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
- * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
- * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
-#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-
-#ifdef CONFIG_FSL_NGPIXIS
-#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS 0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
-#define PIXIS_LBMAP_SWITCH 7
-#define PIXIS_LBMAP_MASK 0xf0
-#define PIXIS_LBMAP_SHIFT 4
-#define PIXIS_LBMAP_ALTBANK 0x20
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
- CONFIG_SYS_NAND_BASE + 0x40000, \
- CONFIG_SYS_NAND_BASE + 0x80000,\
- CONFIG_SYS_NAND_BASE + 0xC0000}
-#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_FSL_ESPI
-
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
-
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 3, Slot 1, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_NAME "Slot 1"
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "ULI"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
-
-/* video */
-#undef CONFIG_VIDEO
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-/* SRIO1 uses the same window as PCIE2 mem window */
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
-
-/* SRIO2 uses the same window as PCIE1 mem window */
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SCSI_AHCI
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
-#endif /* SCSI */
-
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define CONFIG_FSL_SGMII_RISER 1
-#define SGMII_RISER_PHY_OFFSET 0x1b
-
-#ifdef CONFIG_FSL_SGMII_RISER
-#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
-#endif
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_SPIFLASH)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_ENV_SPI_MODE 0
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_SCSI
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
-
-/*
- * SDHC/MMC
- */
-#define CONFIG_MMC
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_IPADDR 192.168.1.254
-
-#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"perf_mode=performance\0" \
- "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=ulpi\0" \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
-"satabootcmd=setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=p2020ds/ramdisk.uboot\0" \
-"fdtaddr=c00000\0" \
-"othbootargs=cache-sram-size=0x10000\0" \
-"fdtfile=p2020ds/p2020ds.dtb\0" \
-"bdev=sda3\0" \
-"partition=scsi 0:0\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "ext2load $partition $loadaddr $bootfile;" \
- "ext2load $partition $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
deleted file mode 100644
index ac75d3e..0000000
--- a/include/configs/P3G4.h
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-#include "../board/evb64260/local.h"
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_P3G4 1 /* this is a P3G4 board */
-#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
-
-#undef CONFIG_ECC /* enable ECC support */
-/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R 1
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-#define CONFIG_SYS_BOARD_NAME "P3G4"
-
-#undef CONFIG_SYS_HUSH_PARSER
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-#define CONFIG_MPSC
-#define CONFIG_MPSC_PORT 0
-
-
-/* define this if you want to enable GT MAC filtering */
-#define CONFIG_GT_USE_MAC_HASH_TABLE
-
-#undef CONFIG_ETHER_PORT_MII /* use RMII */
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=p3g4\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "rootpath=/opt/eldk/ppc_74xx\0" \
- "bootfile=/tftpboot/p3g4/uImage\0" \
- "kernel_addr=ff000000\0" \
- "ramdisk_addr=ff010000\0" \
- "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
- "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
- "cp.b 100000 fff00000 ${filesize};" \
- "setenv filesize;saveenv\0" \
- "upd=run load update\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_ALTIVEC /* undef to disable */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_UNIVERSE
-#define CONFIG_CMD_BSP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
-#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_RAM_LOCK
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xff000000
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS 1
-#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
-
-/* Peripheral Device section */
-#define CONFIG_SYS_GT_REGS 0xf8000000
-#define CONFIG_SYS_DEV_BASE 0xff000000
-
-#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
-#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
-#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
-#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
-
-#define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */
-#define CONFIG_SYS_DEV1_SIZE 0 /* unused */
-#define CONFIG_SYS_DEV2_SIZE 0 /* unused */
-#define CONFIG_SYS_DEV3_SIZE 0 /* unused */
-
-#define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c
-#define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR
-
-#if 0 /* Wrong?? NTL */
-#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
- /* DMAAck[1:0] GNT0[1:0] */
-#else
-#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
- /* REQ0[1:0] GNT0[1:0] */
-#endif
-#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
- /* DMAReq[4] DMAAck[4] WDNMI WDE */
-#if 0 /* Wrong?? NTL */
-#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
- /* DMAAck[1:0] GNT1[1:0] */
-#else
-#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
- /* GPP[22] (RS232IntB or PCI1Int) */
- /* GPP[21] (RS323IntA) */
- /* BClkIn */
- /* REQ1[1:0] GNT1[1:0] */
-#endif
-
-#if 0 /* Wrong?? NTL */
-# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
- /* GPP[27:26] Int[1:0] */
-#else
-# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
- /* GPP[29] (PCI1Int) */
- /* BClkOut0 */
- /* GPP[27] (PCI0Int) */
- /* GPP[26] (RtcInt or PCI1Int) */
- /* CPUInt[25:24] */
-#endif
-
-#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
-
-#if 0 /* Wrong?? - NTL */
-# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
-#else
-# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
- /* gpp[29] */
- /* gpp[27:26] */
- /* gpp[22:21] */
-
-# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
- /* idmas use buffer 1,1
- comm use buffer 0
- pci use buffer 1,1
- cpu use buffer 0
- normal load (see also ifdef HVL)
- standard SDRAM (see also ifdef REG)
- non staggered refresh */
- /* 31:26 25 23 20 19 18 16 */
- /* 110110 00 111 0 0 00 1 */
- /* refresh_count=0x200
- phisical interleaving disable
- virtual interleaving enable */
- /* 15 14 13:0 */
- /* 1 0 0x200 */
-#endif
-
-#if 0
-#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
-#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
-#endif
-#undef CONFIG_SYS_INIT_CHAN1
-#undef CONFIG_SYS_INIT_CHAN2
-#if 0
-#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
-#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
-#endif
-
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE _128M
-#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
-
-#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE _128M
-#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE _16M
-#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
-
-#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE _16M
-#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 in one BAT */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/* I2C speed and slave address (for compatability) defaults */
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/* I2C addresses for the two DIMM SPD chips */
-#ifndef CONFIG_EVB64260_750CX
-#define DIMM0_I2C_ADDR 0x56
-#define DIMM1_I2C_ADDR 0x54
-#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
-#define DIMM0_I2C_ADDR 0x54
-#define DIMM1_I2C_ADDR 0x54
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
-#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_CFI 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR 0xFFFE0000
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/74xx_7xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-#define CONFIG_SYS_BOARD_ASM_INIT 1
-
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
deleted file mode 100644
index 0989407..0000000
--- a/include/configs/PCI405.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * (C) Copyright 2007
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
- *
- * (C) Copyright 2001-2004
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_PCI405 1 /* ...on a PCI405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
-
-#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mem_linux=14336k\0" \
- "optargs=panic=0\0" \
- "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
- "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci"
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_ITEST
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
-#undef CONFIG_PCI_PNP /* no pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-
-#define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */
-#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
- /* total size of a CAT24WC08 is 1024 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (NVRAM/RTC) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
-#define CONFIG_SYS_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (CAN0, 1) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-/*#define CONFIG_SYS_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (FPGA internal) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
-#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE 0x00
-#define CONFIG_SYS_FPGA_STATUS 0x02
-#define CONFIG_SYS_FPGA_TS 0x04
-#define CONFIG_SYS_FPGA_TS_LOW 0x06
-#define CONFIG_SYS_FPGA_TS_CAP0 0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
-#define CONFIG_SYS_FPGA_TS_CAP1 0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
-#define CONFIG_SYS_FPGA_TS_CAP2 0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
-/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */
-#define CONFIG_SYS_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 8705161..a236e11 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -21,6 +21,8 @@
#define CONFIG_PLU405 1 /* ...on a PLU405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
deleted file mode 100644
index de46216..0000000
--- a/include/configs/PM520.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200
-#define CONFIG_PM520 1 /* PM520 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_MII 1
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#undef CONFIG_NS8382X
-
-
-/* Partitions */
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 1
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
-
-#define CONFIG_CMD_PCI
-
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=pm520\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk30/ppc_82xx\0" \
- "bootfile=/tftpboot/PM520/uImage\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-#define CONFIG_SYS_DOC_BASE 0xE0000000
-#define CONFIG_SYS_DOC_SIZE 0x00100000
-
-#if defined(CONFIG_BOOT_ROM)
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFA000000 for 64 MB
- * 0xFC000000 for 32 MB
- * 0xFD000000 for 16 MB
- * 0xFD800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0xFA000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000
-#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
-#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
-#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
-#else
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0xFC000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000
-#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
-#endif
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-
-#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
-
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xf0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#if defined(CONFIG_BOOT_ROM)
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00047800
-#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
-#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_CFG 0x0004FF00
-#else
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
-#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
-#define CONFIG_SYS_CS1_CFG 0x00047800
-#endif
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00005000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#undef CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
deleted file mode 100644
index c68d9a6..0000000
--- a/include/configs/PMC405.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_PMC405 1 /* ...on a PMC405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-/* Only interrupt boot if space is pressed. */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT \
- "Press SPACE to abort autoboot in %d seconds\n", bootdelay
-#undef CONFIG_AUTOBOOT_DELAY_STR
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_UNIVERSE
-#define CONFIG_CMD_EEPROM
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */
-#define CONFIG_SYS_BASE_BAUD 806400
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16
-
-/*
- * PCI stuff
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
-
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */
-
-#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
-#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
-
-#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */
-
-#define CONFIG_PRAM 0 /* use pram variable to overwrite */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
-#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */
-
-/*
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-
-/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_OFFSET 0x000
-#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
-#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
-#define CAN_BA 0xF0000000 /* CAN Base Addres */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
-
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
-#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000)
-
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
-#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000)
-
-/* Memory Bank 2 (CAN0, 1, RTC) initialization */
-/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
-#define CONFIG_SYS_EBC_PB2AP 0x03000440
-/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000)
-
-/* Memory Bank 3 -> unused */
-
-/* Memory Bank 4 (NVRAM) initialization */
-/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
-#define CONFIG_SYS_EBC_PB4AP 0x03000440
-/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000)
-
-/*
- * FPGA stuff
- */
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */
-
-/* pass Ethernet MAC to VxWorks */
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000
-
-/*
- * GPIOs
- */
-#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */
-#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */
-#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
-#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
-#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
-#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
-
-/*
- * Definitions for initial stack pointer and data area (in data cache)
- */
-
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-
-/* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
-
-/* End of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index 94b9547..f7d28e3 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -12,6 +12,8 @@
#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
deleted file mode 100644
index e277d0d..0000000
--- a/include/configs/PPChameleonEVB.h
+++ /dev/null
@@ -1,777 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2003
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * Credits: Stefan Roese, Wolfgang Denk
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
-#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
-#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
-#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
-#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
-#endif
-
-
-/* Only one of the following two symbols must be defined (default is 25 MHz)
- * CONFIG_PPCHAMELEON_CLK_25
- * CONFIG_PPCHAMELEON_CLK_33
- */
-#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_PPCHAMELEON_CLK_25
-#endif
-
-#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
-#error "* Two external frequencies (SysClk) are defined! *"
-#endif
-
-#undef CONFIG_PPCHAMELEON_SMI712
-
-/*
- * Debug stuff
- */
-#undef __DEBUG_START_FROM_SRAM__
-#define __DISABLE_MACHINE_EXCEPTION__
-
-#ifdef __DEBUG_START_FROM_SRAM__
-#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#else
-# error "* External frequency (SysClk) not defined! *"
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#undef CONFIG_BOOTARGS
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_EXT_PHY
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#ifndef CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
-#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
-#else
-#define CONFIG_PHY_ADDR 2 /* PHY address */
-#endif
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 1900
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 2
-#define CONFIG_SYS_SDRAM_tRP 20
-#define CONFIG_SYS_SDRAM_tRC 65
-#define CONFIG_SYS_SDRAM_tRCD 20
-#undef CONFIG_SYS_SDRAM_tRFC
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-
-/*
- * nand device 1 on dave (PPChameleonEVB) needs more time,
- * so we just introduce additional wait in nand_wait(),
- * effectively for both devices.
- */
-#define PPCHAMELON_NAND_TIMER_HACK
-
-#define CONFIG_SYS_NAND0_BASE 0xFF400000
-#define CONFIG_SYS_NAND1_BASE 0xFF000000
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
-#define NAND_BIG_DELAY_US 25
-#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
-
-#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
-#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
-#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
-#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
-
-#define MACRO_NAND_DISABLE_CE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_ENABLE_CE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRALE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_SETALE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
-{ \
- switch((unsigned long)nandptr) \
- { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
- break; \
- } \
-} while(0)
-
-#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
- switch((unsigned long)nandptr) { \
- case CONFIG_SYS_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
- break; \
- case CONFIG_SYS_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
- break; \
- } \
-} while(0)
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* Reserve 256 kB for Monitor */
-/*
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-*/
-
-/* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_FLASH_BASE 0xFFFB0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
-
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#ifdef ENVIRONMENT_IN_EEPROM
-
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
-
-#else /* DEFAULT: environment in flash, using redundand flash sectors */
-
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
-#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
-#define CONFIG_ENV_SIZE_REDUND 0x2000
-
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#endif /* ENVIRONMENT_IN_EEPROM */
-
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (External SRAM) initialization */
-/* Since this must replace NOR Flash, we use the same settings for CS0 */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x92015480
-#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x92015480
-#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
-
-#ifdef CONFIG_PPCHAMELEON_SMI712
-/*
- * Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_VIDEO_BMP_LOGO*/
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
-#define CONFIG_SYS_ISA_IO 0xE8000000
-/* see also drivers/video/videomodes.c */
-#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
-#endif
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE 0x00
-#define CONFIG_SYS_FPGA_STATUS 0x02
-#define CONFIG_SYS_FPGA_TS 0x04
-#define CONFIG_SYS_FPGA_TS_LOW 0x06
-#define CONFIG_SYS_FPGA_TS_CAP0 0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
-#define CONFIG_SYS_FPGA_TS_CAP1 0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
-#define CONFIG_SYS_FPGA_TS_CAP2 0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30] - EMAC0 input
- * GPIO0[31] - EMAC1 reject packet as output
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
-
-#define CONFIG_NO_SERIAL_EEPROM
-
-/*--------------------------------------------------------------------*/
-
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-----------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-! are plugged in the board will be utilized as non-ECC DIMMs.
-!-----------------------------------------------------------------------
-*/
-#undef AUTO_MEMORY_CONFIG
-#define DIMM_READ_ADDR 0xAB
-#define DIMM_WRITE_ADDR 0xAA
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
- /* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
- /* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
- /* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
- /* PLL tune bits */
-#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
-
-/* Defines for CPC0_PLLMR0 Register fields */
- /* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
- /* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
- /* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
- /* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
- /* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
- /* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#else
-#error "* External frequency (SysClk) not defined! *"
-#endif
-
-#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-/* Model HI */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
-#define CONFIG_SYS_OPB_FREQ 55555555
-/* Model ME */
-#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ 66666666
-#else
-/* Model BA (default) */
-#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
-#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ 66666666
-#endif
-
-#endif /* CONFIG_NO_SERIAL_EEPROM */
-
-#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00400000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
-*/
-
-/* 256 kB U-boot image */
-/*
-#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
- "1792k(user),256k(u-boot);" \
- "ppchameleonevb-nand:-(nand)"
-*/
-
-/* 320 kB U-boot image */
-/*
-#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
- "1728k(user),320k(u-boot);" \
- "ppchameleonevb-nand:-(nand)"
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index c2bdbb9..3f02ced 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -35,7 +35,10 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 82b669b..bd40d6a 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -36,7 +36,10 @@
/* support deep sleep */
#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
@@ -51,7 +54,7 @@
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_FSL_LAW /* Use common FSL init code */
-#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
@@ -67,21 +70,21 @@
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#define CONFIG_SPL_NAND_BOOT
#endif
#ifdef CONFIG_SPIFLASH
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#ifndef CONFIG_SPL_BUILD
@@ -91,12 +94,12 @@
#endif
#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
+#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
+#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#ifndef CONFIG_SPL_BUILD
@@ -759,8 +762,10 @@
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_AQUANTIA
#define RGMII_PHY1_ADDR 0x2
#define RGMII_PHY2_ADDR 0x6
+#define SGMII_PHY1_ADDR 0x2
#define FM1_10GEC1_PHY_ADDR 0x1
#endif
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index b70bdfe..92f5f56 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -47,7 +47,10 @@
/* support deep sleep */
#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
+#define CONFIG_BOARD_EARLY_INIT_F
+#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
@@ -689,6 +692,12 @@
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
+/* Enable VSC9953 L2 Switch driver */
+#define CONFIG_VSC9953
+#define CONFIG_VSC9953_CMD
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
+
/*
* Dynamic MTD Partition support with mtdparts
*/
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 57cdf72..d47f1be 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -726,6 +726,14 @@
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
+/* Enable VSC9953 L2 Switch driver on T1040 SoC */
+#ifdef CONFIG_T1040RDB
+#define CONFIG_VSC9953
+#define CONFIG_VSC9953_CMD
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
+#endif
+
#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC4"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
deleted file mode 100644
index 5ad9383..0000000
--- a/include/configs/TASREG.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Configuation settings for the esd TASREG board.
- *
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _TASREG_H
-#define _TASREG_H
-
-#ifndef __ASSEMBLY__
-#include <asm/m5249.h>
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MCF52x2 /* define processor family */
-#define CONFIG_M5249 /* define processor type */
-
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_MCFTMR
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
-
-#undef CONFIG_WATCHDOG
-
-#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_CMD_NET
-
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-
-#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START 0x400
-#define CONFIG_SYS_MEMTEST_END 0x380000
-
-/*
- * Clock configuration: enable only one of the following options
- */
-
-#if 0 /* this setting will run the cpu at 11MHz */
-#define CONFIG_SYS_PLL_BYPASS 1 /* bypass PLL for test purpose */
-#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
-#define CONFIG_SYS_CLK 11289600 /* PLL bypass */
-#endif
-
-#if 0 /* this setting will run the cpu at 70MHz */
-#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
-#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
-#define CONFIG_SYS_CLK 72185018 /* The next lower speed */
-#endif
-
-#if 1 /* this setting will run the cpu at 140MHz */
-#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
-#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
-#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
-#endif
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
-#define CONFIG_SYS_MBAR2 0x80000000
-
-/*-----------------------------------------------------------------------
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 100000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-
-#if 0 /* push-pull */
-#define SDA 0x00800000
-#define SCL 0x00000008
-#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
-#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
-#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
-#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
-#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
-#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
-#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;}
-#define I2C_READ ((IN1&SDA)?1:0)
-#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;}
-#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;}
-#define I2C_DELAY {udelay(5);}
-#define I2C_ACTIVE {DIR1|=SDA;}
-#define I2C_TRISTATE {DIR1&=~SDA;}
-#else /* open-collector */
-#define SDA 0x00800000
-#define SCL 0x00000008
-#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
-#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
-#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
-#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
-#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
-#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
-#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
-#define I2C_READ ((IN1&SDA)?1:0)
-#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;}
-#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;}
-#define I2C_DELAY {udelay(5);}
-#define I2C_ACTIVE {DIR1|=SDA;}
-#define I2C_TRISTATE {DIR1&=~SDA;}
-#endif
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
-/*
- * The Catalyst CAT24WC32 has 32 byte page write mode using
- * last 5 bits of the address
- */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-
-#if 0 /* test-only */
-#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-
-#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
- CF_CACR_DBWE)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-
-/* CS0 - AMD Flash, address 0xffc00000 */
-#define CONFIG_SYS_CS0_BASE 0xffc00000
-#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
-/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
-
-/* CS1 - FPGA, address 0xe0000000 */
-#define CONFIG_SYS_CS1_BASE 0xe0000000
-#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
-#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
-
-/*-----------------------------------------------------------------------
- * Port configuration
- */
-#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
-#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
-#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
-#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
-#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
-
-#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */
-
-#endif /* _TASREG_H */
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
deleted file mode 100644
index a58eeca..0000000
--- a/include/configs/Total5200.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Check valid setting of revision define.
- * Total5100 and Total5200 Rev.1 are identical except for the processor.
- */
-#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
-#error CONFIG_TOTAL5200_REV must be 1 or 2
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
-#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000 boot high (standard configuration)
- * 0xFE000000 boot low
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Video console
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SED13806
-#define CONFIG_VIDEO_SED13806_16BPP
-
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-/* #define CONFIG_VIDEO_BMP_LOGO */
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_MII 1
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT \
- "setenv stdout serial;setenv stderr serial;" \
- "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/MPC5200/uImage\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#if CONFIG_TOTAL5200_REV==2
-# define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
-#else
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
-#endif
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#if CONFIG_TOTAL5200_REV==1
-# define CONFIG_SYS_FLASH_BASE 0xFE000000
-# define CONFIG_SYS_FLASH_SIZE 0x02000000
-#elif CONFIG_TOTAL5200_REV==2
-# define CONFIG_SYS_FLASH_BASE 0xFA000000
-# define CONFIG_SYS_FLASH_SIZE 0x06000000
-#endif /* CONFIG_TOTAL5200_REV */
-
-#if defined(CONFIG_SYS_LOWBOOT)
-# define CONFIG_ENV_ADDR 0xFE040000
-#else /* CONFIG_SYS_LOWBOOT */
-# define CONFIG_ENV_ADDR 0xFFF40000
-#endif /* CONFIG_SYS_LOWBOOT */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_MBAR 0xF0000000 /* 64 kB */
-#define CONFIG_SYS_FPGA_BASE 0xF0010000 /* 64 kB */
-#define CONFIG_SYS_CPLD_BASE 0xF0020000 /* 64 kB */
-#define CONFIG_SYS_LCD_BASE 0xF1000000 /* 4096 kB */
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_SEVENWIRE
-/* dummy, 7-wire FEC does not have phy address */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * GPIO configuration
- *
- * CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
- * Reserved 0
- * ALTs: CAN1/2 on PSC2, SPI on PSC3 00
- * CS7: Interrupt GPIO on PSC3_5 0
- * CS8: Interrupt GPIO on PSC3_4 0
- * ATA: reset default, changed in ATA driver 00
- * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
- * IRDA: reset default, changed in IrDA driver 000
- * ETHER: reset default, changed in Ethernet driver 0000
- * PCI_DIS: reset default, changed in PCI driver 0
- * USB_SE: reset default, changed in USB driver 0
- * USB: reset default, changed in USB driver 00
- * PSC3: SPI and UART functionality without CD 1100
- * Reserved 0
- * PSC2: CAN1/2 001
- * Reserved 0
- * PSC1: reset default, changed in AC'97 driver 000
- *
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000C10
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#if CONFIG_TOTAL5200_REV==1
-# define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
-# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
-# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-# define CONFIG_SYS_CS0_SIZE 0x02000000 /* 32 MB */
-#else
-# define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
-# define CONFIG_SYS_BOOTCS_SIZE 0x02000000 /* 32 MB */
-# define CONFIG_SYS_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
-# define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
-# define CONFIG_SYS_CS4_SIZE 0x02000000 /* 32 MB */
-# define CONFIG_SYS_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
-# define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE
-# define CONFIG_SYS_CS5_SIZE 0x02000000 /* 32 MB */
-# define CONFIG_SYS_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
-#endif
-
-#define CONFIG_SYS_CS1_START CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_CS1_SIZE 0x00010000 /* 64 kB */
-#define CONFIG_SYS_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
-
-#define CONFIG_SYS_CS2_START CONFIG_SYS_LCD_BASE
-#define CONFIG_SYS_CS2_SIZE 0x00400000 /* 4096 kB */
-#define CONFIG_SYS_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
-
-#if CONFIG_TOTAL5200_REV==1
-# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
-# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
-# define CONFIG_SYS_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
-#else
-# define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
-# define CONFIG_SYS_CS3_SIZE 0x00010000 /* 64 kB */
-# define CONFIG_SYS_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
-#endif
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_ATA_CS_ON_I2C2
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
deleted file mode 100644
index d4a4b68..0000000
--- a/include/configs/VOH405.h
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_VOH405 1 /* ...on a VOH405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF80000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_HAS_ETH1
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_SUPPORT_VFAT
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0010
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF80000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */
-
-#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CONFIG_SYS_RAMBOOT 1
-#else
-# undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
-#define CONFIG_SYS_EEPROM_WREN 1
-
-/* CAT24WC32/64... */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
- /* 32 byte page write mode using*/
- /* last 5 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define DUART0_BA 0xF0000400 /* DUART Base Address */
-#define DUART1_BA 0xF0000408 /* DUART Base Address */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
-#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 4 (Epson VGA) initialization */
-#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
-#define CONFIG_SYS_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
-
-/*-----------------------------------------------------------------------
- * LCD Setup
- */
-
-#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
-#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
-#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
-#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
-
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-
-#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
-
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_CTRL 0x000
-
-/* FPGA Control Reg */
-#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
-#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
-#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
-
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x00000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0x777E0017
-
-#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
-#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
-#define CONFIG_SYS_IIC_ON (0x80000000 >> 8)
-#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
-#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
-#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index c06897b..e229256 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -19,6 +19,8 @@
#define CONFIG_VOM405 1 /* ...on a VOM405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
deleted file mode 100644
index e4f0d19..0000000
--- a/include/configs/WUH405.h
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_IDENT_STRING " $Name: $"
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_WUH405 1 /* ...on a WUH405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define DUART0_BA 0xF0000400 /* DUART Base Address */
-#define DUART1_BA 0xF0000408 /* DUART Base Address */
-#define DUART2_BA 0xF0000410 /* DUART Base Address */
-#define DUART3_BA 0xF0000418 /* DUART Base Address */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define CONFIG_SYS_NAND_BASE 0xF4000000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
-
-#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
deleted file mode 100644
index cac6a67..0000000
--- a/include/configs/ZUMA.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
-#define CONFIG_ETHER_PORT_MII /* use two MII ports */
-#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-#include "../board/evb64260/local.h"
-
-#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
-#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */
-
-#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
-
-#define CONFIG_ECC /* enable ECC support */
-
-#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */
-
-/* which initialization functions to call for this board */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_SYS_BOARD_ASM_INIT
-
-#define CONFIG_SYS_BOARD_NAME "Zuma APv2"
-
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
- * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
- * to 0 below.
- *
- * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
- * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
- */
-#define CONFIG_MPSC
-
-#define CONFIG_MPSC_PORT 0
-
-
-/* define this if you want to enable GT MAC filtering */
-#define CONFIG_GT_USE_MAC_HASH_TABLE
-
-#if 1
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_BOOTCOMMAND \
- "tftpboot && " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:" \
- "$netmask:$hostname:eth0:none panic=5 && bootm"
-
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_ALTIVEC /* undef to disable */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_MII /* enable MII commands */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
-#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
-*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
-
-#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_RAM_LOCK
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xfff00000
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
-
-/* areas to map different things with the GT in physical space */
-#define CONFIG_SYS_DRAM_BANKS 4
-#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
-
-/* What to put in the bats. */
-#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
-
-/* Peripheral Device section */
-#define CONFIG_SYS_GT_REGS 0xf8000000 /* later mapped GT_REGS */
-#define CONFIG_SYS_DEV_BASE 0xf0000000
-#define CONFIG_SYS_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/
-#define CONFIG_SYS_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */
-#define CONFIG_SYS_DEV2_SIZE _8M /* unused */
-#define CONFIG_SYS_DEV3_SIZE _8M /* unused */
-
-#define CONFIG_SYS_DEV0_PAR 0xc498243c
- /* c 4 9 8 2 4 3 c */
- /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
- /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
- /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
- /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */
-
-#define CONFIG_SYS_DEV1_PAR 0xc01b6ac5
- /* c 0 1 b 6 a c 5 */
- /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
- /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
- /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */
- /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */
-
-
-#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c
-
-#define CONFIG_SYS_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
-#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */
-#define CONFIG_SYS_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
-#define CONFIG_SYS_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */
- /* GPP[27:24] (27 is int4, rest are GPP) */
-
-#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */
-#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */
-
-#define CONFIG_SYS_SDRAM_CONFIG 0xe4e18200 /* 0x448 */
- /* idmas use buffer 1,1
- comm use buffer 1
- pci use buffer 0,0 (pci1->0 pci0->0)
- cpu use buffer 1 (R*18)
- normal load (see also ifdef HVL)
- standard SDRAM (see also ifdef REG)
- non staggered refresh */
- /* 31:26 25 23 20 19 18 16 */
- /* 111001 00 111 0 0 00 1 */
-
- /* refresh count=0x200
- phy interleave disable (by default,
- set later by dram config..)
- virt interleave enable */
- /* 15 14 13:0 */
- /* 1 0 0x200 */
-
-#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
-#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
-#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
-#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-
-#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-/* PCI MEMORY MAP section */
-#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI0_MEM_SIZE _128M
-#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
-#define CONFIG_SYS_PCI1_MEM_SIZE _128M
-
-#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
-#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
-
-/* PCI I/O MAP section */
-#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
-#define CONFIG_SYS_PCI0_IO_SIZE _16M
-#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
-#define CONFIG_SYS_PCI1_IO_SIZE _16M
-
-#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
-#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
-#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
-#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
-
-
-/*----------------------------------------------------------------------
- * Initial BAT mappings
- */
-
-/* NOTES:
- * 1) GUARDED and WRITE_THRU not allowed in IBATS
- * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
- */
-
-/* SDRAM */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-/* init ram */
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-
-/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */
-#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* GT regs, bootrom, all the devices, PCI I/O */
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
-
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 130 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */
-#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_CFI 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
-#define CONFIG_ENV_ADDR (0xfff80000 - CONFIG_ENV_SECT_SIZE)
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/74xx_7xx.h for the defines used here
- */
-
-#define CONFIG_SYS_L2
-
-#ifdef CONFIG_750CX
-#define L2_INIT 0
-#else
-#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
- L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
-#endif
-
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-
-/*------------------------------------------------------------------------
- * Real time clock
- */
-#define CONFIG_RTC_DS1302
-
-
-/*------------------------------------------------------------------------
- * Galileo I2C driver
- */
-#define CONFIG_GT_I2C
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index b00585c..7ccbf36 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -39,6 +39,7 @@
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_TPS65218
+#define CONFIG_POWER_TPS62362
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
@@ -235,6 +236,8 @@
"setenv fdtfile am437x-gp-evm.dtb; fi; " \
"if test $board_name = AM43__SK; then " \
"setenv fdtfile am437x-sk-evm.dtb; fi; " \
+ "if test $board_name = AM43_IDK; then " \
+ "setenv fdtfile am437x-idk-evm.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree; fi; \0"
diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h
index 88d27db..76163ab 100644
--- a/include/configs/arcangel4-be.h
+++ b/include/configs/arcangel4-be.h
@@ -14,7 +14,6 @@
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_SYS_CLK_FREQ 70000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h
index 4579eb9..81934a4 100644
--- a/include/configs/arcangel4.h
+++ b/include/configs/arcangel4.h
@@ -13,7 +13,6 @@
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_SYS_CLK_FREQ 70000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 6e8c56c..c61ddd6 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -13,7 +13,6 @@
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_SYS_CLK_FREQ 750000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* NAND controller DMA doesn't work correctly with D$ enabled */
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 8930210..7e6d239 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -15,15 +15,12 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_CAR_ADDR 0xff7e0000
-#define CONFIG_SYS_CAR_SIZE (128 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
-#define CONFIG_SYS_X86_START16 0xfffff800
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_X86_RESET_VECTOR
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+
+#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
+#define CONFIG_BOARD_EARLY_INIT_F
+
#define CONFIG_NR_DRAM_BANKS 8
#define CONFIG_X86_MRC_ADDR 0xfffa0000
#define CONFIG_CACHE_MRC_SIZE_KB 512
@@ -41,7 +38,6 @@
#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin
#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
-#define CONFIG_VIDEO_X86
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
deleted file mode 100644
index 990a2d1..0000000
--- a/include/configs/coreboot.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/x86-common.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_COREBOOT
-#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_SYS_EARLY_PCI_INIT
-
-#define CONFIG_SYS_CAR_ADDR 0x19200000
-#define CONFIG_SYS_CAR_SIZE (16 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-
-#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR 0x01400000
-
-#define CONFIG_BOOTSTAGE
-#define CONFIG_BOOTSTAGE_REPORT
-#define CONFIG_BOOTSTAGE_FDT
-#define CONFIG_CMD_BOOTSTAGE
-/* Place to stash bootstage data from first-stage U-Boot */
-#define CONFIG_BOOTSTAGE_STASH 0x0110f000
-#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc
-#define CONFIG_BOOTSTAGE_USER_COUNT 60
-
-#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
- PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
- {PCI_VENDOR_ID_INTEL, \
- PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
- {PCI_VENDOR_ID_INTEL, \
- PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
- {PCI_VENDOR_ID_INTEL, \
- PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-
-#define CONFIG_X86_SERIAL
-
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
- "stdout=vga,serial,cbmem\0" \
- "stderr=vga,serial,cbmem\0"
-
-#define CONFIG_CBMEM_CONSOLE
-
-#define CONFIG_VIDEO_COREBOOT
-
-#define CONFIG_NR_DRAM_BANKS 4
-
-#define CONFIG_TRACE
-#define CONFIG_CMD_TRACE
-#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
-
-#define CONFIG_BOOTDELAY 2
-
-#define CONFIG_CROS_EC
-#define CONFIG_CROS_EC_LPC
-#define CONFIG_CMD_CROS_EC
-#define CONFIG_ARCH_EARLY_INIT_R
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
deleted file mode 100644
index ec926fd..0000000
--- a/include/configs/cpci5200.h
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
-
- */
-
-/*************************************************************************
- * (c) 2005 esd gmbh Hannover
- *
- *
- * from IceCube.h file
- * by Reinhard Arlt reinhard.arlt@esd-electronics.com
- *
- *************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_ICECUBE 1 /* ... on IceCube board */
-#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
-#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#if 1
-#define CONFIG_PCI 1
-#if 1
-#define CONFIG_PCI_PNP 1
-#endif
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-#endif
-
-#define CONFIG_MII
-#if 0 /* test-only !!! */
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 0
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_DATE
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT16 1
-#endif
-#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT08 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome to esd CPU CPCI/5200;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
- "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
- "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
- "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
- "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
- "loadaddr=01000000\0" \
- "serverip=192.168.2.99\0" \
- "gatewayip=10.0.0.79\0" \
- "user=mu\0" \
- "target=cpci5200.esd\0" \
- "script=cpci5200.bat\0" \
- "image=/tftpboot/vxWorks_cpci5200\0" \
- "ipaddr=10.0.13.196\0" \
- "netmask=255.255.0.0\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
-
-#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000
-#define CONFIG_SYS_NVRAM_SIZE 32*1024
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
-/*
- * Flash configuration
- */
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_SIZE 0x02000000
-#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/*
- * Environment settings
- */
-#if 1 /* test-only */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OVERWRITE 1
-#else
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
- /* total size of a CAT24WC32 is 8192 bytes */
-#define CONFIG_ENV_OVERWRITE 1
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
- */
-/* #define CONFIG_FEC_10MBIT 1 */
-#define CONFIG_PHY_ADDR 0x00
-#define CONFIG_UDP_CHECKSUM 1
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
-
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS1_START 0xfd000000
-#define CONFIG_SYS_CS1_SIZE 0x00010000
-#define CONFIG_SYS_CS1_CFG 0x10101410
-
-#define CONFIG_SYS_CS3_START 0xfd010000
-#define CONFIG_SYS_CS3_SIZE 0x00010000
-#define CONFIG_SYS_CS3_CFG 0x10109410
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-/*-----------------------------------------------------------------------
- * CPLD stuff
- */
-#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
-#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
-
-/* CPLD program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
-#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
-
-#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
-#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
-
-#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
-#define JTAG_GPIO_CFG_SET 0x00000000
-#define JTAG_GPIO_CFG_RESET 0x00F00000
-
-#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
-#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
-#define JTAG_GPIO_TMS_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
-#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
-#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
-#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
-#define JTAG_GPIO_TCK_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
-#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
-#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
-#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
-#define JTAG_GPIO_TDI_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
-#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
-#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
-#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
-#define JTAG_GPIO_TDO_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
-#define JTAG_GPIO_TDO_DDR_SET 0x00000000
-#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index eadb339..b927b1c 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -14,10 +14,8 @@
#include <configs/x86-common.h>
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_SYS_X86_START16 0xfffff800
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_X86_RESET_VECTOR
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_X86_SERIAL
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 77e2f58..1c69551 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -16,12 +16,8 @@
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_GENERIC_BOARD
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
@@ -31,31 +27,31 @@
*/
#define CONFIG_SYS_TEXT_BASE 0x80100000
-#define CONFIG_SDRC /* The chip has SDRC controller */
+#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
+
+#define CONFIG_NAND
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+
+#include <configs/ti_omap3_common.h>
/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
#define CONFIG_MISC_INIT_R
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
-#define CONFIG_OF_LIBFDT 1
-
/* Size of malloc() pool */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
+#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/* Hardware drivers */
@@ -69,39 +65,18 @@
#define CONFIG_DM9000_NO_SROM 1
#undef CONFIG_DM9000_DEBUG
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-/* select serial console configuration */
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SERIAL3 3
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/* MMC */
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
+/* SPI */
+#undef CONFIG_SPI
+#undef CONFIG_OMAP3_SPI
/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#undef CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_SYS_I2C_OMAP34XX
/* TWL4030 */
-#define CONFIG_TWL4030_POWER 1
#define CONFIG_TWL4030_LED 1
/* Board NAND Info */
-#define CONFIG_SYS_NO_FLASH /* no NOR flash */
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:" \
"512k(x-loader)," \
@@ -110,14 +85,8 @@
"4m(kernel)," \
"-(fs)"
-#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access nand at */
- /* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
- /* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
@@ -127,20 +96,20 @@
/* partition */
/* commands to include */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_DHCP /* DHCP support */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
-#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_GPIO
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_BOOTZ
+#undef CONFIG_SUPPORT_RAW_INITRD
+#undef CONFIG_FAT_WRITE
+#undef CONFIG_CMD_EXT4
+#undef CONFIG_CMD_FS_GENERIC
/* BOOTP/DHCP options */
#define CONFIG_BOOTP_SUBNETMASK
@@ -157,10 +126,6 @@
#undef CONFIG_BOOTP_VENDOREX
/* Environment information */
-#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
-
-#define CONFIG_BOOTDELAY 3
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyO2,115200n8\0" \
@@ -228,88 +193,29 @@
#define CONFIG_BOOTCOMMAND "run autoboot"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
-
/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
0x01000000) /* 16MB */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
/* NAND and environment organization */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
/* SRAM config */
#define CONFIG_SYS_SRAM_START 0x40200000
#define CONFIG_SYS_SRAM_SIZE 0x10000
/* Defines for SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NAND_SIMPLE
+#undef CONFIG_SPL_MTD_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-
+#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
+#undef CONFIG_SPL_STACK
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
@@ -325,30 +231,23 @@
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
-
/* SPL OS boot options */
-#define CONFIG_SPL_OS_BOOT
-
-#define CONFIG_CMD_SPL
#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
0x400000)
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
-
+#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
+#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
+#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
+#undef CONFIG_SYS_SPL_ARGS_ADDR
#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
#endif /* __CONFIG_H */
diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h
index 46a42b3..ec7f721 100644
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -12,6 +12,8 @@
#ifndef _CONFIG_DOCKSTAR_H
#define _CONFIG_DOCKSTAR_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
index 5ed9497..836515d 100644
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -15,6 +15,8 @@
#ifndef _CONFIG_GOFLEXHOME_H
#define _CONFIG_GOFLEXHOME_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index a56a4cb..8e53af8 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -1,5 +1,6 @@
/*
- * (C) Copyright 2009
+ * (C) Copyright 2009-2014
+ * Gerald Kerma <dreagle@doukki.net>
* Marvell Semiconductor <www.marvell.com>
* Written-by: Siddarth Gore <gores@marvell.com>
*
@@ -9,6 +10,8 @@
#ifndef _CONFIG_GURUPLUG_H
#define _CONFIG_GURUPLUG_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
@@ -23,17 +26,36 @@
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
+ * Compression configuration
+ */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+#define CONFIG_LZO
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+
+/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
-#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
/*
* mv-common.h should be defined after CMD configs since it used them
@@ -55,24 +77,38 @@
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_ADDR 0x60000
-#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
+#define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
- "${x_bootcmd_ethernet}; setenv ethact egiga1; " \
- "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "bootm 0x6400000;"
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part root; " \
+ "ubifsmount ubi:rootfs; " \
+ "ubifsload 0x800000 ${kernel}; " \
+ "ubifsload 0x700000 ${fdt}; " \
+ "ubifsumount; " \
+ "fdt addr 0x700000; fdt resize; fdt chosen; " \
+ "bootz 0x800000 - 0x700000"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "x_bootcmd_ethernet=ping 192.168.2.1\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \
- "x_bootargs=console=ttyS0,115200\0" \
- "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+#define CONFIG_MTDPARTS \
+ "mtdparts=orion_nand:" \
+ "896K(uboot),128K(uboot_env)," \
+ "-@1M(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS \
+ "kernel=/boot/zImage\0" \
+ "fdt=/boot/guruplug-server-plus.dtb\0" \
+ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+#define MTDIDS_DEFAULT "nand0=orion_nand"
+
+#define MTDPARTS_DEFAULT \
+ "mtdparts="CONFIG_MTDPARTS
/*
* Ethernet Driver configuration
@@ -89,6 +125,20 @@
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+
#define CONFIG_SYS_ALT_MEMTEST
#endif /* _CONFIG_GURUPLUG_H */
diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
index f4c748a..f1ddf21 100644
--- a/include/configs/ib62x0.h
+++ b/include/configs/ib62x0.h
@@ -9,6 +9,8 @@
#ifndef _CONFIG_IB62x0_H
#define _CONFIG_IB62x0_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h
index 9f4a4b8..2baf50c 100644
--- a/include/configs/iconnect.h
+++ b/include/configs/iconnect.h
@@ -9,6 +9,8 @@
#ifndef _CONFIG_ICONNECT_H
#define _CONFIG_ICONNECT_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 8dc04f2..2874ccc 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -19,6 +19,11 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
+#define CONFIG_SILENT_CONSOLE
+#endif
+
/*
* Size of malloc() pool
*/
@@ -72,7 +77,8 @@
#define CONFIG_SPL_PAD_TO 0x1c000
#define CONFIG_SYS_TEXT_BASE 0x82000000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
@@ -365,11 +371,16 @@
/*
* Serial Port
*/
+#ifdef CONFIG_LPUART
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#endif
#define CONFIG_BAUDRATE 115200
@@ -385,6 +396,7 @@
*/
#define I2C_MUX_PCA_ADDR_PRI 0x77
#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_CH7301 0xC
/*
* MMC
@@ -427,6 +439,25 @@
#endif
/*
+ * Video
+ */
+#define CONFIG_FSL_DCU_FB
+
+#ifdef CONFIG_FSL_DCU_FB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
+#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
+#define CONFIG_SYS_I2C_DVI_ADDR 0x75
+#endif
+
+/*
* eTSEC
*/
#define CONFIG_TSEC_ENET
@@ -508,11 +539,19 @@
#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
+#ifdef CONFIG_LPUART
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+ "fdt_high=0xcfffffff\0" \
+ "initrd_high=0xcfffffff\0" \
+ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
+#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
"fdt_high=0xcfffffff\0" \
"initrd_high=0xcfffffff\0" \
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
+#endif
/*
* Miscellaneous configurable options
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 66954d0..0a0bb5f 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -186,11 +186,16 @@
/*
* Serial Port
*/
+#ifdef CONFIG_LPUART
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#endif
#define CONFIG_BAUDRATE 115200
@@ -325,10 +330,17 @@
#define CONFIG_BOOTDELAY 3
+#ifdef CONFIG_LPUART
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+ "initrd_high=0xcfffffff\0" \
+ "fdt_high=0xcfffffff\0"
+#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
"initrd_high=0xcfffffff\0" \
"fdt_high=0xcfffffff\0"
+#endif
/*
* Miscellaneous configurable options
diff --git a/include/configs/malta.h b/include/configs/malta.h
index a29b86b..684d249 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -38,8 +38,6 @@
#define CONFIG_SYS_MHZ 250 /* arbitrary value */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-#define CONFIG_SWAP_IO_SPACE
-
/*
* Memory map
*/
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
deleted file mode 100644
index b270429..0000000
--- a/include/configs/mecp5200.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-/*************************************************************************
- * (c) 2005 esd gmbh Hannover
- *
- *
- * from IceCube.h file
- * by Reinhard Arlt reinhard.arlt@esd-electronics.com
- *
- *************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_ICECUBE 1 /* ... on IceCube board */
-#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
-#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#if 0 /* test-only */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#else
-#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_MII
-#if 0 /* test-only !!! */
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 0
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_ELF
-
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT16 1
-#endif
-#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT08 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome to CBX-CPU5200 (mecp5200);" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
- "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
- "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
- "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
- "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
- "loadaddr=01000000\0" \
- "serverip=192.168.2.99\0" \
- "gatewayip=10.0.0.79\0" \
- "user=mu\0" \
- "target=mecp5200.esd\0" \
- "script=mecp5200.bat\0" \
- "image=/tftpboot/vxWorks_mecp5200\0" \
- "ipaddr=10.0.13.196\0" \
- "netmask=255.255.0.0\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_FLASH_SIZE 0x00400000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/*
- * Environment settings
- */
-#if 1 /* test-only */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_OVERWRITE 1
-#else
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
- /* total size of a CAT24WC32 is 8192 bytes */
-#define CONFIG_ENV_OVERWRITE 1
-#endif
-
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-#if 0
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#endif
-#define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
-
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-#define CONFIG_UDP_CHECKSUM 1
-
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x00085d00
-
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS1_START 0xfd000000
-#define CONFIG_SYS_CS1_SIZE 0x00010000
-#define CONFIG_SYS_CS1_CFG 0x10101410
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
deleted file mode 100644
index 0308c52..0000000
--- a/include/configs/mpc7448hpc2.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * Copyright (c) 2005 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2006
- * Alex Bounine , Tundra Semiconductor Corp.
- * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board specific configuration options for Freescale
- * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Board Configuration Definitions */
-/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
-
-#define CONFIG_MPC7448HPC2
-
-#define CONFIG_74xx
-#define CONFIG_HIGH_BATS /* High BATs supported */
-#define CONFIG_ALTIVEC /* undef to disable */
-
-#define CONFIG_SYS_TEXT_BASE 0xFF000000
-
-#define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II"
-#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
-
-#define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */
-#define CONFIG_SYS_BUS_CLK 133000000
-
-#define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
-
-#undef CONFIG_ECC /* disable ECC support */
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-/* Board-specific Initialization Functions to be called */
-#define CONFIG_SYS_BOARD_ASM_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
-
-/*#define CONFIG_SYS_HUSH_PARSER */
-#undef CONFIG_SYS_HUSH_PARSER
-
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_TSI "tsi108@c0000000"
-#define OF_TBCLK (bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808"
-
-/*
- * The following defines let you select what serial you want to use
- * for your console driver.
- *
- * what to do:
- * If you have hacked a serial cable onto the second DUART channel,
- * change the CONFIG_SYS_DUART port from 1 to 0 below.
- *
- */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08)
-
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#undef CONFIG_BOOTARGS
-/* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
-
-#if (CONFIG_BOOTDELAY >= 0)
-#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
- setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
- ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-#endif
-
-#undef CONFIG_EXTRA_ENV_SETTINGS
-
-#define CONFIG_SERIAL "No. 1"
-
-/* Networking Configuration */
-
-#define CONFIG_TSI108_ETH
-#define CONFIG_TSI108_ETH_NUM_PORTS 2
-
-
-#define CONFIG_BOOTFILE "zImage.initrd.elf"
-#define CONFIG_LOADADDR 0x400000
-
-/*-------------------------------------------------------------------------- */
-
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DATE
-
-
-/*set date in u-boot*/
-#define CONFIG_RTC_M48T35A
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000
-#define CONFIG_SYS_NVRAM_SIZE 0x8000
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_VERSION_VARIABLE 1
-#define CONFIG_TSI108_I2C
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-
-/*
- * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
- * To an unused memory region. The stack will remain in cache until RAM
- * is initialized
- */
-#undef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000/* larger space - we have SDRAM initialized */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
-#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
-
-#define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
-#define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
-
-#define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
-
-#define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
-
-#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
-
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */
-#define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
-
-#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
-
-#define PCI0_IO_BASE_BOOTM 0xfd000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0x3fffff00
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* u-boot code base */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
-
-/* Peripheral Device section */
-
-/*
- * Resources on the Tsi108
- */
-
-#define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
-#define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
-
-#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
-
-#undef DISABLE_PBM
-
-/*
- * PCI stuff
- *
- */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_TSI108_PCI /* include tsi108 pci support */
-
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-/* PCI MEMORY MAP section */
-
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
-/* PCI Memory Space */
-#define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS)
-#define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
-
-/* PCI I/O Space */
-#define CONFIG_SYS_PCI_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
-
-#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */
-
-/* PCI Config Space mapping */
-#define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
-#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */
-
-#define CONFIG_SYS_IBAT0U 0xFE0003FF
-#define CONFIG_SYS_IBAT0L 0xFE000002
-
-#define CONFIG_SYS_IBAT1U 0x00007FFF
-#define CONFIG_SYS_IBAT1L 0x00000012
-
-#define CONFIG_SYS_IBAT2U 0x80007FFF
-#define CONFIG_SYS_IBAT2L 0x80000022
-
-#define CONFIG_SYS_IBAT3U 0x00000000
-#define CONFIG_SYS_IBAT3L 0x00000000
-
-#define CONFIG_SYS_IBAT4U 0x00000000
-#define CONFIG_SYS_IBAT4L 0x00000000
-
-#define CONFIG_SYS_IBAT5U 0x00000000
-#define CONFIG_SYS_IBAT5L 0x00000000
-
-#define CONFIG_SYS_IBAT6U 0x00000000
-#define CONFIG_SYS_IBAT6L 0x00000000
-
-#define CONFIG_SYS_IBAT7U 0x00000000
-#define CONFIG_SYS_IBAT7L 0x00000000
-
-#define CONFIG_SYS_DBAT0U 0xE0003FFF
-#define CONFIG_SYS_DBAT0L 0xE000002A
-
-#define CONFIG_SYS_DBAT1U 0x00007FFF
-#define CONFIG_SYS_DBAT1L 0x00000012
-
-#define CONFIG_SYS_DBAT2U 0x00000000
-#define CONFIG_SYS_DBAT2L 0x00000000
-
-#define CONFIG_SYS_DBAT3U 0xC0000003
-#define CONFIG_SYS_DBAT3L 0xC000002A
-
-#define CONFIG_SYS_DBAT4U 0x00000000
-#define CONFIG_SYS_DBAT4L 0x00000000
-
-#define CONFIG_SYS_DBAT5U 0x00000000
-#define CONFIG_SYS_DBAT5L 0x00000000
-
-#define CONFIG_SYS_DBAT6U 0x00000000
-#define CONFIG_SYS_DBAT6L 0x00000000
-
-#define CONFIG_SYS_DBAT7U 0x00000000
-#define CONFIG_SYS_DBAT7L 0x00000000
-
-/* I2C addresses for the two DIMM SPD chips */
-#define DIMM0_I2C_ADDR 0x51
-#define DIMM1_I2C_ADDR 0x52
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
-#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ }
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
-
-#define PHYS_FLASH_SIZE 0x01000000
-#define CONFIG_SYS_MAX_FLASH_SECT (128)
-
-#define CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_ADDR 0xFC000000
-
-#define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * L2CR setup -- make sure this is right for your board!
- * look in include/mpc74xx.h for the defines used here
- */
-#undef CONFIG_SYS_L2
-
-#define L2_INIT 0
-#define L2_ENABLE (L2_INIT | L2CR_L2E)
-#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
-#endif /* __CONFIG_H */
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
new file mode 100644
index 0000000..cfb85bf
--- /dev/null
+++ b/include/configs/nas220.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
+ *
+ * based on work from:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_NAS220_H
+#define _CONFIG_NAS220_H
+
+/*
+ * Machine type definition and ID
+ */
+#define MACH_TYPE_NAS220 MACH_TYPE_RD88F6192_NAS
+#define CONFIG_MACH_TYPE MACH_TYPE_NAS220
+#define CONFIG_IDENT_STRING "\nNAS 220"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */
+#define CONFIG_KW88F6192 /* SOC Name */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/* power-on led, regulator, sata0, sata1 */
+#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))
+#define NAS220_GE_OE_VAL_HIGH (0)
+#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)))
+#define NAS220_GE_OE_HIGH (~(0))
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_IDE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT "nas220> "
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_OFFSET 0xa0000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND ""
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs=console=ttyS0,115200\0" \
+ "mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\
+ "0x010000@0xa0000(env),"\
+ "0x500000@0xc0000(uimage),"\
+ "0x1a40000@0x5c0000(rootfs)\0" \
+ "mtdids=nand0=orion_nand\0"\
+ "bootdelay=-1\0"\
+ "autostart=no\0"\
+ "autoload=no\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 8
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#endif
+
+
+/*
+ * Device Tree
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * EFI partition
+ */
+#define CONFIG_EFI_PARTITION
+
+/*
+ * Date Time
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#define CONFIG_KIRKWOOD_GPIO
+
+#endif /* _CONFIG_NAS220_H */
+
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 7d102a4..c0bb227 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -45,6 +45,9 @@
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"bootenv=uEnv.txt\0" \
+ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t $loadaddr $filesize\0" \
@@ -65,17 +68,21 @@
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loaduimage; then " \
- "run mmcboot;" \
- "fi;" \
+ "if run loadbootscript; then " \
+ "run bootscript;" \
+ "else " \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot;" \
+ "fi;" \
+ "fi ;" \
"fi;" \
/* Clock Defines */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
deleted file mode 100644
index be76478..0000000
--- a/include/configs/pf5200.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*************************************************************************
- * (c) 2005 esd gmbh Hannover
- *
- *
- * from IceCube.h file
- * by Reinhard Arlt reinhard.arlt@esd-electronics.com
- *
- *************************************************************************/
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
-#define CONFIG_ICECUBE 1 /* ... on IceCube board */
-#define CONFIG_PF5200 1 /* ... on PF5200 board */
-#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#if 0 /* test-only */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#else
-#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
-#endif
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * PCI Mapping:
- * 0x40000000 - 0x4fffffff - PCI Memory
- * 0x50000000 - 0x50ffffff - PCI IO Space
- */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-#define CONFIG_PCI_SCAN_SHOW 1
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_PCI_MEM_BUS 0x40000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_MII 1
-#if 0 /* test-only !!! */
-#define CONFIG_EEPRO100 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_NS8382X 1
-#endif
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#if 0
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-
-#define CONFIG_CMD_PCI
-
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT16 1
-#endif
-#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
-# define CONFIG_SYS_LOWBOOT 1
-# define CONFIG_SYS_LOWBOOT08 1
-#endif
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Welcome to ParaFinder pf5200;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
- "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
- "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
- "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
- "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
- "loadaddr=01000000\0" \
- "serverip=192.168.2.99\0" \
- "gatewayip=10.0.0.79\0" \
- "user=mu\0" \
- "target=pf5200.esd\0" \
- "script=pf5200.bat\0" \
- "image=/tftpboot/vxWorks_pf5200\0" \
- "ipaddr=10.0.13.196\0" \
- "netmask=255.255.0.0\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
-
-/*
- * IPB Bus clocking configuration.
- */
-#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_SIZE 0x02000000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-
-/*
- * Environment settings
- */
-#if 1 /* test-only */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_OVERWRITE 1
-#else
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
- /* total size of a CAT24WC32 is 8192 bytes */
-#define CONFIG_ENV_OVERWRITE 1
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC 1
-#define CONFIG_MPC5xxx_FEC_MII100
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 0x00
-#define CONFIG_UDP_CHECKSUM 1
-
-/*
- * GPIO configuration
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
-
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS1_START 0xfd000000
-#define CONFIG_SYS_CS1_SIZE 0x00010000
-#define CONFIG_SYS_CS1_CFG 0x10101410
-
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00001000
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff Supports IDE harddisk
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-
-#define CONFIG_IDE_RESET /* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE 4
-
-/*-----------------------------------------------------------------------
- * CPLD stuff
- */
-#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
-#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
-
-/* CPLD program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
-#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
-
-#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
-#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
-#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
-
-#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
-#define JTAG_GPIO_CFG_SET 0x00000000
-#define JTAG_GPIO_CFG_RESET 0x00F00000
-
-#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
-#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
-#define JTAG_GPIO_TMS_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
-#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
-#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
-#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
-#define JTAG_GPIO_TCK_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
-#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
-#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
-#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
-#define JTAG_GPIO_TDI_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
-#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
-#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
-
-#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
-#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
-#define JTAG_GPIO_TDO_EN_RESET 0x00000000
-#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
-#define JTAG_GPIO_TDO_DDR_SET 0x00000000
-#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 0746056..10415d3 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -20,6 +20,8 @@
#include <asm/hardware.h>
/* ARM asynchronous clock */
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_DISPLAY_BOARDINFO
#define MASTER_PLL_DIV 15
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index f0f12af..f6aebf4 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -18,6 +18,8 @@
*/
#include <asm/hardware.h>
+#define CONFIG_SYS_GENERIC_BOARD
+
/* ARM asynchronous clock */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index f78e0ec..a8dc0f0 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -22,6 +22,8 @@
*/
#include <asm/hardware.h>
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h
index 7594bdb..89560ad 100644
--- a/include/configs/pogo_e02.h
+++ b/include/configs/pogo_e02.h
@@ -13,6 +13,8 @@
#ifndef _CONFIG_POGO_E02_H
#define _CONFIG_POGO_E02_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Machine type definition and ID
*/
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
deleted file mode 100644
index 18f9a6c..0000000
--- a/include/configs/ppmc7xx.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/*
- * ppmc7xx.h
- * ---------
- *
- * Wind River PPMC 7xx/74xx board configuration file.
- *
- * By Richard Danter (richard.danter@windriver.com)
- * Copyright (C) 2005 Wind River Systems
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPMC7XX
-
-
-/*===================================================================
- *
- * User configurable settings - Modify to your preference
- *
- *===================================================================
- */
-
-/*
- * Debug
- *
- * DEBUG - Define this is you want extra debug info
- * GTREGREAD - Required to build with debug
- * do_bdinfo - Required to build with debug
- */
-
-#ifdef DEBUG
-#define GTREGREAD(x) 0xFFFFFFFF
-#define do_bdinfo(a,b,c,d)
-#endif
-
-/*
- * CPU type
- *
- * CONFIG_7xx - We have a 750 or 755 CPU
- * CONFIG_74xx - We have a 7400 CPU
- * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
- * CONFIG_BUS_CLK - System bus clock in Hz
- */
-
-#define CONFIG_7xx
-#undef CONFIG_74xx
-#undef CONFIG_ALTIVEC
-#define CONFIG_BUS_CLK 66000000
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#ifndef __ASSEMBLY__
-#include <galileo/core.h>
-#endif
-
-/*
- * Monitor configuration
- *
- * List of command sets to include in shell
- *
- * The following command sets have been tested and known to work:
- *
- * CMD_CACHE - Cache control commands
- * CMD_MEMORY - Memory display, change and test commands
- * CMD_FLASH - Erase and program flash
- * CMD_ENV - Environment commands
- * CMD_RUN - Run commands stored in env vars
- * CMD_ELF - Load ELF files
- * CMD_NET - Networking/file download commands
- * CMD_PIN - ICMP Echo Request command
- * CMD_PCI - PCI Bus scanning command
- */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PCI
-
-#undef CONFIG_CMD_KGDB
-
-
-/*
- * Serial configuration
- *
- * CONFIG_CONS_INDEX - Serial console port number (COM1)
- * CONFIG_BAUDRATE - Serial speed
- */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-
-/*
- * PCI config
- *
- * CONFIG_PCI - Enable PCI bus
- * CONFIG_PCI_PNP - Enable Plug & Play support
- * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
- */
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-#undef CONFIG_PCI_SCAN_SHOW
-
-
-/*
- * Network config
- *
- * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
- * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
- */
-
-#define CONFIG_EEPRO100
-#define CONFIG_EEPRO100_SROM_WRITE
-
-
-/*
- * Enable extra init functions
- *
- * CONFIG_MISC_INIT_F - Call pre-relocation init functions
- * CONFIG_MISC_INIT_R - Call post relocation init functions
- */
-
-#undef CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
-
-/*
- * Boot config
- *
- * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
- * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
- */
-
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
- "bootm"
-#define CONFIG_BOOTDELAY 5
-
-
-/*===================================================================
- *
- * Board configuration settings - You should not need to modify these
- *
- *===================================================================
- */
-
-
-/*
- * Memory map
- *
- * This board runs in a standard CHRP (Map-B) configuration.
- *
- * Type Start End Size Width Chip Sel
- * ----------- ----------- ----------- ------- ------- --------
- * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
- * User LED's 0x78000000 RCS3
- * UART 0x7C000000 RCS2
- * Mailbox 0xFF000000 RCS1
- * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
- *
- * Flash sectors are laid out as follows.
- *
- * Sector Start End Size Comments
- * ------- ----------- ----------- ------- -----------
- * 0 0xFFC00000 0xFFC3FFFF 256KB
- * 1 0xFFC40000 0xFFC7FFFF 256KB
- * 2 0xFFC80000 0xFFCBFFFF 256KB
- * 3 0xFFCC0000 0xFFCFFFFF 256KB
- * 4 0xFFD00000 0xFFD3FFFF 256KB
- * 5 0xFFD40000 0xFFD7FFFF 256KB
- * 6 0xFFD80000 0xFFDBFFFF 256KB
- * 7 0xFFDC0000 0xFFDFFFFF 256KB
- * 8 0xFFE00000 0xFFE3FFFF 256KB
- * 9 0xFFE40000 0xFFE7FFFF 256KB
- * 10 0xFFE80000 0xFFEBFFFF 256KB
- * 11 0xFFEC0000 0xFFEFFFFF 256KB
- * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
- * 13 0xFFF40000 0xFFF7FFFF 256KB
- * 14 0xFFF80000 0xFFFBFFFF 256KB
- * 15 0xFFFC0000 0xFFFDFFFF 128KB
- * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
- * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
- * 18 0xFFFF0000 0xFFFFFFFF 64KB
- */
-
-
-/*
- * SDRAM config - see memory map details above.
- *
- * CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
- * CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
- */
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
-
-
-/*
- * Flash config - see memory map details above.
- *
- * CONFIG_SYS_FLASH_BASE - Start address of flash memory
- * CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem
- * CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms
- * CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms
- * CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board
- * CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_FLASH_SIZE 0x00400000
-#define CONFIG_SYS_FLASH_ERASE_TOUT 250000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 5000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-
-/*
- * Monitor config - see memory map details above
- *
- * CONFIG_SYS_MONITOR_BASE - Base address of monitor code
- * CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB)
- */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN 0x20000
-
-
-/*
- * Command shell settings
- *
- * CONFIG_SYS_BARGSIZE - Boot Argument buffer size
- * CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
- * CONFIG_SYS_CBSIZE - Console Buffer (input) size
- * CONFIG_SYS_LOAD_ADDR - Default load address
- * CONFIG_SYS_LONGHELP - Provide more detailed help
- * CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands
- * CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM
- * CONFIG_SYS_MEMTEST_END - End address of RAM test
- * CONFIG_SYS_PBSIZE - Print Buffer (output) size
- * CONFIG_SYS_PROMPT - Prompt string
- */
-
-#define CONFIG_SYS_BARGSIZE 1024
-#define CONFIG_SYS_BOOTMAPSZ 0x800000
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_LOAD_ADDR 0x100000
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_MEMTEST_START 0x00040000
-#define CONFIG_SYS_MEMTEST_END 0x00040100
-#define CONFIG_SYS_PBSIZE 1024
-
-
-/*
- * Environment config - see memory map details above
- *
- * CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash
- * CONFIG_ENV_ADDR - Address of the sector containing env vars
- * CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
- * CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
- */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0xFFFE0000
-#define CONFIG_ENV_SIZE 0x1000
-#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000
-#define CONFIG_ENV_SIZE_REDUND 0x1000
-#define CONFIG_ENV_SECT_SIZE 0x8000
-
-
-/*
- * Initial RAM config
- *
- * Since the main system RAM is initialised very early, we place the INIT_RAM
- * in the main system RAM just above the exception vectors. The contents are
- * copied to top of RAM by the init code.
- *
- * CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect
- * CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM
- * GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
- * CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-
-/*
- * Initial BAT config
- *
- * BAT0 - System SDRAM
- * BAT1 - LED's and Serial Port
- * BAT2 - PCI Memory
- * BAT3 - PCI I/O including Flash Memory
- */
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-
-#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-
-/*
- * Cache config
- *
- * CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific)
- * CONFIG_SYS_L2 - L2 cache enabled if defined
- * L2_INIT - L2 cache init flags
- * L2_ENABLE - L2 cache enable flags
- */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#undef CONFIG_SYS_L2
-#define L2_INIT 0
-#define L2_ENABLE 0
-
-
-/*
- * Clocks config
- *
- * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz
- * CONFIG_SYS_HZ - Decrementer freq in Hz
- */
-
-#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK
-
-
-/*
- * Serial port config
- *
- * CONFIG_SYS_NS16550 - Include the NS16550 driver
- * CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver
- * CONFIG_SYS_NS16550_CLK - Frequency of reference clock
- * CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
- * CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port
- */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK 3686400
-#define CONFIG_SYS_NS16550_REG_SIZE -8
-#define CONFIG_SYS_NS16550_COM1 0x7C000000
-
-
-/*
- * PCI Config - Address Map B (CHRP)
- */
-
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
-#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000
-#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
-#define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000
-#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
-#define CONFIG_SYS_PCI_IO_BUS 0x00800000
-#define CONFIG_SYS_PCI_IO_PHYS 0xFE800000
-#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
-#define CONFIG_SYS_ISA_IO_BUS 0x00000000
-#define CONFIG_SYS_ISA_IO_PHYS 0xFE000000
-#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
-#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
-#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
-
-
-/*
- * Extra init functions
- *
- * CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code
- */
-
-#define CONFIG_SYS_BOARD_ASM_INIT
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 71be823..21c8bda 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -10,6 +10,8 @@
#ifndef _CONFIG_SHEEVAPLUG_H
#define _CONFIG_SHEEVAPLUG_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Version number information
*/
diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
index 7b85740..87d269b 100644
--- a/include/configs/sun4i.h
+++ b/include/configs/sun4i.h
@@ -13,7 +13,6 @@
*/
#define CONFIG_CLK_FULL_SPEED 1008000000
-#define CONFIG_SYS_PROMPT "sun4i# "
#define CONFIG_MACH_TYPE 4104
#ifdef CONFIG_USB_EHCI
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
index 09f7533..52e3a6f 100644
--- a/include/configs/sun5i.h
+++ b/include/configs/sun5i.h
@@ -13,7 +13,6 @@
*/
#define CONFIG_CLK_FULL_SPEED 1008000000
-#define CONFIG_SYS_PROMPT "sun5i# "
#define CONFIG_MACH_TYPE 4138
#ifdef CONFIG_USB_EHCI
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
index 1b73852..f5e11dd 100644
--- a/include/configs/sun6i.h
+++ b/include/configs/sun6i.h
@@ -16,8 +16,6 @@
*/
#define CONFIG_CLK_FULL_SPEED 1008000000
-#define CONFIG_SYS_PROMPT "sun6i# "
-
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
index ccec50c..7cd7890 100644
--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -14,7 +14,6 @@
*/
#define CONFIG_CLK_FULL_SPEED 912000000
-#define CONFIG_SYS_PROMPT "sun7i# "
#define CONFIG_MACH_TYPE 4283
#ifdef CONFIG_USB_EHCI
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index 6f1fc48..3bdedb3 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -12,7 +12,12 @@
/*
* A23 specific configuration
*/
-#define CONFIG_SYS_PROMPT "sun8i# "
+#define CONFIG_CLK_FULL_SPEED 1008000000
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_SUNXI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
/*
* Include common sunxi configuration where most the settings are
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 3f890b2..4a5cab2 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -40,6 +40,8 @@
*/
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_PROMPT "sunxi# "
+
/* Serial & console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
@@ -160,7 +162,10 @@
#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */
#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#if !defined(CONFIG_UART0_PORT_F)
#define CONFIG_SPL_MMC_SUPPORT
+#endif
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
@@ -202,7 +207,7 @@
* The amount of RAM that is reserved for the FB. This will not show up as
* RAM to the kernel, but will be reclaimed by a KMS driver in future.
*/
-#define CONFIG_SUNXI_FB_SIZE (8 << 20)
+#define CONFIG_SUNXI_FB_SIZE (9 << 20)
/* Do we want to initialize a simple FB? */
#define CONFIG_VIDEO_DT_SIMPLEFB
@@ -212,6 +217,8 @@
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_STD_TIMINGS
+#define CONFIG_I2C_EDID
/* allow both serial and cfb console. */
#define CONFIG_CONSOLE_MUX
@@ -242,8 +249,16 @@
#endif
#ifdef CONFIG_USB_EHCI
-#define CONFIG_CMD_USB
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+#endif
+
+#ifdef CONFIG_USB_MUSB_SUNXI
+#define CONFIG_MUSB_HOST
+#define CONFIG_MUSB_PIO_ONLY
+#endif
+
+#if defined CONFIG_USB_EHCI || defined CONFIG_USB_MUSB_SUNXI
+#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#endif
@@ -267,10 +282,19 @@
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
-/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
- * 1M script, 1M pxe and the ramdisk at the end */
+/* Enable pre-console buffer to get complete log on the VGA console */
+#define CONFIG_PRE_CONSOLE_BUFFER
+#define CONFIG_PRE_CON_BUF_SZ (1024 * 1024)
+/* Use the room between the end of bootm_size and the framebuffer */
+#define CONFIG_PRE_CON_BUF_ADDR 0x4f000000
+
+/*
+ * 240M RAM (256M minimum minus space for the framebuffer),
+ * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end.
+ */
#define MEM_LAYOUT_ENV_SETTINGS \
- "bootm_size=0x10000000\0" \
+ "bootm_size=0xf000000\0" \
"kernel_addr_r=0x42000000\0" \
"fdt_addr_r=0x43000000\0" \
"scriptaddr=0x43100000\0" \
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 8a861a8..e9218f7 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -15,7 +15,6 @@
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_SYS_CLK_FREQ 500000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index c47651d..925cb42 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -85,10 +85,16 @@
"vram=${vram} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+ "ip=dhcp\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "bootenv=uEnv.txt\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
@@ -110,6 +116,13 @@
"bootz ${loadaddr} - ${fdtaddr}; " \
"fi;" \
"fi;\0" \
+ "netboot=echo Booting from network ...; " \
+ "set env autoload no; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} ${fdtfile}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
"findfdt="\
"if test $board_name = omap5_uevm; then " \
"setenv fdtfile omap5-uevm.dtb; fi; " \
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index bd79e81..05bc7d0 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -60,11 +60,8 @@
/* UBI */
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_RBTREE
#define CONFIG_LZO
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
diff --git a/include/edid.h b/include/edid.h
index 480a773..18ec1d5 100644
--- a/include/edid.h
+++ b/include/edid.h
@@ -86,6 +86,10 @@
GET_BITS((_x).flags, 4, 3)
#define EDID_DETAILED_TIMING_FLAG_POLARITY(_x) \
GET_BITS((_x).flags, 2, 1)
+#define EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(_x) \
+ GET_BIT((_x).flags, 2)
+#define EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(_x) \
+ GET_BIT((_x).flags, 1)
#define EDID_DETAILED_TIMING_FLAG_INTERLEAVED(_x) \
GET_BIT((_x).flags, 0)
} __attribute__ ((__packed__));
@@ -226,6 +230,25 @@
unsigned char checksum;
} __attribute__ ((__packed__));
+struct edid_cea861_info {
+ unsigned char extension_tag;
+#define EDID_CEA861_EXTENSION_TAG 0x02
+ unsigned char revision;
+ unsigned char dtd_offset;
+ unsigned char dtd_count;
+#define EDID_CEA861_SUPPORTS_UNDERSCAN(_x) \
+ GET_BIT(((_x).dtd_count), 7)
+#define EDID_CEA861_SUPPORTS_BASIC_AUDIO(_x) \
+ GET_BIT(((_x).dtd_count), 6)
+#define EDID_CEA861_SUPPORTS_YUV444(_x) \
+ GET_BIT(((_x).dtd_count), 5)
+#define EDID_CEA861_SUPPORTS_YUV422(_x) \
+ GET_BIT(((_x).dtd_count), 4)
+#define EDID_CEA861_DTD_COUNT(_x) \
+ GET_BITS(((_x).dtd_count), 3, 0)
+ unsigned char data[124];
+} __attribute__ ((__packed__));
+
/**
* Print the EDID info.
*
@@ -242,6 +265,15 @@
int edid_check_info(struct edid1_info *info);
/**
+ * Check checksum of a 128 bytes EDID data block
+ *
+ * @param edid_block EDID block data
+ *
+ * @return 0 on success, or a negative errno on error
+ */
+int edid_check_checksum(u8 *edid_block);
+
+/**
* Get the horizontal and vertical rate ranges of the monitor.
*
* @param edid The EDID info
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 5effa24..75af750 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -15,6 +15,7 @@
*/
#include <libfdt.h>
+#include <pci.h>
/*
* A typedef for a physical address. Note that fdt data is always big
@@ -50,6 +51,49 @@
fdt_addr_t end;
};
+enum fdt_pci_space {
+ FDT_PCI_SPACE_CONFIG = 0,
+ FDT_PCI_SPACE_IO = 0x01000000,
+ FDT_PCI_SPACE_MEM32 = 0x02000000,
+ FDT_PCI_SPACE_MEM64 = 0x03000000,
+ FDT_PCI_SPACE_MEM32_PREF = 0x42000000,
+ FDT_PCI_SPACE_MEM64_PREF = 0x43000000,
+};
+
+#define FDT_PCI_ADDR_CELLS 3
+#define FDT_PCI_SIZE_CELLS 2
+#define FDT_PCI_REG_SIZE \
+ ((FDT_PCI_ADDR_CELLS + FDT_PCI_SIZE_CELLS) * sizeof(u32))
+
+/*
+ * The Open Firmware spec defines PCI physical address as follows:
+ *
+ * bits# 31 .... 24 23 .... 16 15 .... 08 07 .... 00
+ *
+ * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
+ * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
+ * phys.lo cell: llllllll llllllll llllllll llllllll
+ *
+ * where:
+ *
+ * n: is 0 if the address is relocatable, 1 otherwise
+ * p: is 1 if addressable region is prefetchable, 0 otherwise
+ * t: is 1 if the address is aliased (for non-relocatable I/O) below 1MB
+ * (for Memory), or below 64KB (for relocatable I/O)
+ * ss: is the space code, denoting the address space
+ * bbbbbbbb: is the 8-bit Bus Number
+ * ddddd: is the 5-bit Device Number
+ * fff: is the 3-bit Function Number
+ * rrrrrrrr: is the 8-bit Register Number
+ * hhhhhhhh: is a 32-bit unsigned number
+ * llllllll: is a 32-bit unsigned number
+ */
+struct fdt_pci_addr {
+ u32 phys_hi;
+ u32 phys_mid;
+ u32 phys_lo;
+};
+
/**
* Compute the size of a resource.
*
@@ -258,6 +302,60 @@
const char *prop_name, fdt_size_t *sizep);
/**
+ * Look at an address property in a node and return the pci address which
+ * corresponds to the given type in the form of fdt_pci_addr.
+ * The property must hold one fdt_pci_addr with a lengh.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param type pci address type (FDT_PCI_SPACE_xxx)
+ * @param prop_name name of property to find
+ * @param addr returns pci address in the form of fdt_pci_addr
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
+ const char *prop_name, struct fdt_pci_addr *addr);
+
+/**
+ * Look at the compatible property of a device node that represents a PCI
+ * device and extract pci vendor id and device id from it.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param vendor vendor id of the pci device
+ * @param device device id of the pci device
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_vendev(const void *blob, int node,
+ u16 *vendor, u16 *device);
+
+/**
+ * Look at the pci address of a device node that represents a PCI device
+ * and parse the bus, device and function number from it.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param addr pci address in the form of fdt_pci_addr
+ * @param bdf returns bus, device, function triplet
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_bdf(const void *blob, int node,
+ struct fdt_pci_addr *addr, pci_dev_t *bdf);
+
+/**
+ * Look at the pci address of a device node that represents a PCI device
+ * and return base address of the pci device's registers.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param addr pci address in the form of fdt_pci_addr
+ * @param bar returns base address of the pci device's registers
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_bar32(const void *blob, int node,
+ struct fdt_pci_addr *addr, u32 *bar);
+
+/**
* Look up a 32-bit integer property in a node and return it. The property
* must have at least 4 bytes of data. The value of the first cell is
* returned.
@@ -683,17 +781,6 @@
struct fdt_resource *res);
/**
- * Look at the reg property of a device node that represents a PCI device
- * and parse the bus, device and function number from it.
- *
- * @param fdt FDT blob
- * @param node node to examine
- * @param bdf returns bus, device, function triplet
- * @return 0 if ok, negative on error
- */
-int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf);
-
-/**
* Decode a named region within a memory bank of a given type.
*
* This function handles selection of a memory region. The region is
diff --git a/include/fpga.h b/include/fpga.h
index 914024c..e0d1298 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -49,18 +49,19 @@
} bitstream_type;
/* root function definitions */
-extern void fpga_init(void);
-extern int fpga_add(fpga_type devtype, void *desc);
-extern int fpga_count(void);
-extern int fpga_load(int devnum, const void *buf, size_t bsize,
- bitstream_type bstype);
-extern int fpga_fsload(int devnum, const void *buf, size_t size,
- fpga_fs_info *fpga_fsinfo);
-extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
- bitstream_type bstype);
-extern int fpga_dump(int devnum, const void *buf, size_t bsize);
-extern int fpga_info(int devnum);
-extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
- size_t bsize, char *fn);
+void fpga_init(void);
+int fpga_add(fpga_type devtype, void *desc);
+int fpga_count(void);
+const fpga_desc *const fpga_get_desc(int devnum);
+int fpga_load(int devnum, const void *buf, size_t bsize,
+ bitstream_type bstype);
+int fpga_fsload(int devnum, const void *buf, size_t size,
+ fpga_fs_info *fpga_fsinfo);
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+ bitstream_type bstype);
+int fpga_dump(int devnum, const void *buf, size_t bsize);
+int fpga_info(int devnum);
+const fpga_desc *const fpga_validate(int devnum, const void *buf,
+ size_t bsize, char *fn);
#endif /* _FPGA_H_ */
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 675557a..3286c95 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -23,9 +23,15 @@
#ifdef CONFIG_SYS_FSL_DDR_LE
#define ddr_in32(a) in_le32(a)
#define ddr_out32(a, v) out_le32(a, v)
+#define ddr_setbits32(a, v) setbits_le32(a, v)
+#define ddr_clrbits32(a, v) clrbits_le32(a, v)
+#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
#else
#define ddr_in32(a) in_be32(a)
#define ddr_out32(a, v) out_be32(a, v)
+#define ddr_setbits32(a, v) setbits_be32(a, v)
+#define ddr_clrbits32(a, v) clrbits_be32(a, v)
+#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
#endif
#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
diff --git a/include/galileo/core.h b/include/galileo/core.h
deleted file mode 100644
index 95013fa..0000000
--- a/include/galileo/core.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* Core.h - Basic core logic functions and definitions */
-
-/* Copyright Galileo Technology. */
-
-/*
-DESCRIPTION
-This header file contains simple read/write macros for addressing
-the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
-space). The macros take care of Big/Little endian conversions.
-*/
-
-#ifndef __INCcoreh
-#define __INCcoreh
-
-/* includes */
-#include "gt64260R.h"
-#include <stdbool.h>
-
-extern unsigned int INTERNAL_REG_BASE_ADDR;
-
-/*
- * GT-6426x variants
- */
-#define GT_64260 0 /* includes both 64260A and 64260B */
-#define GT_64261 1
-
-#if (CONFIG_SYS_GT_6426x == GT_64260)
-#ifdef CONFIG_ETHER_PORT_MII
-#define GAL_ETH_DEVS 2
-#else
-#define GAL_ETH_DEVS 3
-#endif
-#elif (CONFIG_SYS_GT_6426x == GT_64261)
-#define GAL_ETH_DEVS 2
-#else
-#define GAL_ETH_DEVS 3 /* default to a 64260 */
-#endif
-
-/****************************************/
-/* GENERAL Definitions */
-/****************************************/
-
-#define NO_BIT 0x00000000
-#define BIT0 0x00000001
-#define BIT1 0x00000002
-#define BIT2 0x00000004
-#define BIT3 0x00000008
-#define BIT4 0x00000010
-#define BIT5 0x00000020
-#define BIT6 0x00000040
-#define BIT7 0x00000080
-#define BIT8 0x00000100
-#define BIT9 0x00000200
-#define BIT10 0x00000400
-#define BIT11 0x00000800
-#define BIT12 0x00001000
-#define BIT13 0x00002000
-#define BIT14 0x00004000
-#define BIT15 0x00008000
-#define BIT16 0x00010000
-#define BIT17 0x00020000
-#define BIT18 0x00040000
-#define BIT19 0x00080000
-#define BIT20 0x00100000
-#define BIT21 0x00200000
-#define BIT22 0x00400000
-#define BIT23 0x00800000
-#define BIT24 0x01000000
-#define BIT25 0x02000000
-#define BIT26 0x04000000
-#define BIT27 0x08000000
-#define BIT28 0x10000000
-#define BIT29 0x20000000
-#define BIT30 0x40000000
-#define BIT31 0x80000000
-
-#define _1K 0x00000400
-#define _2K 0x00000800
-#define _4K 0x00001000
-#define _8K 0x00002000
-#define _16K 0x00004000
-#define _32K 0x00008000
-#define _64K 0x00010000
-#define _128K 0x00020000
-#define _256K 0x00040000
-#define _512K 0x00080000
-
-#define _1M 0x00100000
-#define _2M 0x00200000
-#define _3M 0x00300000
-#define _4M 0x00400000
-#define _5M 0x00500000
-#define _6M 0x00600000
-#define _7M 0x00700000
-#define _8M 0x00800000
-#define _9M 0x00900000
-#define _10M 0x00a00000
-#define _11M 0x00b00000
-#define _12M 0x00c00000
-#define _13M 0x00d00000
-#define _14M 0x00e00000
-#define _15M 0x00f00000
-#define _16M 0x01000000
-
-#define _32M 0x02000000
-#define _64M 0x04000000
-#define _128M 0x08000000
-#define _256M 0x10000000
-#define _512M 0x20000000
-
-#define _1G 0x40000000
-#define _2G 0x80000000
-
-/* Little to Big endian conversion macros */
-
-#ifdef LE /* Little Endian */
-#define SHORT_SWAP(X) (X)
-#define WORD_SWAP(X) (X)
-#define LONG_SWAP(X) ((l64)(X))
-
-#else /* Big Endian */
-#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
-
-#define WORD_SWAP(X) (((X)&0xff)<<24)+ \
- (((X)&0xff00)<<8)+ \
- (((X)&0xff0000)>>8)+ \
- (((X)&0xff000000)>>24)
-
-#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
- (((X)&0xff00ULL)<<40)+ \
- (((X)&0xff0000ULL)<<24)+ \
- (((X)&0xff000000ULL)<<8)+ \
- (((X)&0xff00000000ULL)>>8)+ \
- (((X)&0xff0000000000ULL)>>24)+ \
- (((X)&0xff000000000000ULL)>>40)+ \
- (((X)&0xff00000000000000ULL)>>56))
-
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-/* Those two definitions were defined to be compatible with MIPS */
-#define NONE_CACHEABLE 0x00000000
-#define CACHEABLE 0x00000000
-
-/* 750 cache line */
-#define CACHE_LINE_SIZE 32
-#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
-#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
-
-/* Read/Write to/from GT`s internal registers */
-#define GT_REG_READ(offset, pData) \
-*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \
- INTERNAL_REG_BASE_ADDR | (offset))) ) ; \
-*pData = WORD_SWAP(*pData)
-
-#define GTREGREAD(offset) \
- (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \
- INTERNAL_REG_BASE_ADDR | (offset))) ))
-
-#define GT_REG_WRITE(offset, data) \
-*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \
- WORD_SWAP(data)
-
-/* Write 32/16/8 bit */
-#define WRITE_CHAR(address, data) \
- *((unsigned char *)(address)) = data
-#define WRITE_SHORT(address, data) \
- *((unsigned short *)(address)) = data
-#define WRITE_WORD(address, data) \
- *((unsigned int *)(address)) = data
-
-/* Read 32/16/8 bits - returns data in variable. */
-#define READ_CHAR(address, pData) \
- *pData = *((volatile unsigned char *)(address))
-
-#define READ_SHORT(address, pData) \
- *pData = *((volatile unsigned short *)(address))
-
-#define READ_WORD(address, pData) \
- *pData = *((volatile unsigned int *)(address))
-
-/* Read 32/16/8 bit - returns data direct. */
-#define READCHAR(address) \
- *((volatile unsigned char *)((address) | NONE_CACHEABLE))
-
-#define READSHORT(address) \
- *((volatile unsigned short *)((address) | NONE_CACHEABLE))
-
-#define READWORD(address) \
- *((volatile unsigned int *)((address) | NONE_CACHEABLE))
-
-/* Those two Macros were defined to be compatible with MIPS */
-#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff)
-#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE)
-
-/* SET_REG_BITS(regOffset,bits) -
- gets register offset and bits: a 32bit value. It set to logic '1' in the
- internal register the bits which given as an input example:
- SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
- '1' in register 0x840 while the other bits stays as is. */
-#define SET_REG_BITS(regOffset,bits) \
- *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
- regOffset) |= (unsigned int)WORD_SWAP(bits)
-
-/* RESET_REG_BITS(regOffset,bits) -
- gets register offset and bits: a 32bit value. It set to logic '0' in the
- internal register the bits which given as an input example:
- RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
- '0' in register 0x840 while the other bits stays as is. */
-#define RESET_REG_BITS(regOffset,bits) \
- *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \
- | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
-
-#endif /* __INCcoreh */
diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h
deleted file mode 100644
index b55da9d..0000000
--- a/include/galileo/gt64260R.h
+++ /dev/null
@@ -1,1194 +0,0 @@
-/* gt64260R.h - GT64260 Internal registers definition file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCgt64260rh
-#define __INCgt64260rh
-
-#ifndef GT64260
-#define GT64260
-#endif
-
-/* CPU MASTER CONTROL REGISTER */
-#define CPU_CONFIGURATION 0x0
-#define CPU_MASTER_CONTROL 0x160
-
-/****************************************/
-/* Processor Address Space */
-/****************************************/
-
-/* Sdram's BAR'S */
-#define SCS_0_LOW_DECODE_ADDRESS 0x008
-#define SCS_0_HIGH_DECODE_ADDRESS 0x010
-#define SCS_1_LOW_DECODE_ADDRESS 0x208
-#define SCS_1_HIGH_DECODE_ADDRESS 0x210
-#define SCS_2_LOW_DECODE_ADDRESS 0x018
-#define SCS_2_HIGH_DECODE_ADDRESS 0x020
-#define SCS_3_LOW_DECODE_ADDRESS 0x218
-#define SCS_3_HIGH_DECODE_ADDRESS 0x220
-/* Devices BAR'S */
-#define CS_0_LOW_DECODE_ADDRESS 0x028
-#define CS_0_HIGH_DECODE_ADDRESS 0x030
-#define CS_1_LOW_DECODE_ADDRESS 0x228
-#define CS_1_HIGH_DECODE_ADDRESS 0x230
-#define CS_2_LOW_DECODE_ADDRESS 0x248
-#define CS_2_HIGH_DECODE_ADDRESS 0x250
-#define CS_3_LOW_DECODE_ADDRESS 0x038
-#define CS_3_HIGH_DECODE_ADDRESS 0x040
-#define BOOTCS_LOW_DECODE_ADDRESS 0x238
-#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
-
-#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
-#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
-#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
-#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
-#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
-#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
-#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
-#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
-#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
-#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
-
-#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
-#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
-#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
-#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
-#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
-#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
-#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
-#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
-#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
-#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
-
-
-#define INTERNAL_SPACE_DECODE 0x068
-
-#define CPU_0_LOW_DECODE_ADDRESS 0x290
-#define CPU_0_HIGH_DECODE_ADDRESS 0x298
-#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
-#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
-
-#define PCI_0I_O_ADDRESS_REMAP 0x0f0
-#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
-#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
-#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
-#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
-#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
-#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
-#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
-#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
-
-#define PCI_1I_O_ADDRESS_REMAP 0x108
-#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
-#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
-#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
-#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
-#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
-#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
-#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
-#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
-
-
-/****************************************/
-/* CPU Sync Barrier */
-/****************************************/
-
-#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
-#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
-
-
-/****************************************/
-/* CPU Access Protect */
-/****************************************/
-
-#define CPU_LOW_PROTECT_ADDRESS_0 0x180
-#define CPU_HIGH_PROTECT_ADDRESS_0 0x188
-#define CPU_LOW_PROTECT_ADDRESS_1 0x190
-#define CPU_HIGH_PROTECT_ADDRESS_1 0x198
-#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0
-#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8
-#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0
-#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8
-#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0
-#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8
-#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0
-#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8
-#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0
-#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8
-#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0
-#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8
-
-
-/****************************************/
-/* Snoop Control */
-/****************************************/
-
-#define SNOOP_BASE_ADDRESS_0 0x380
-#define SNOOP_TOP_ADDRESS_0 0x388
-#define SNOOP_BASE_ADDRESS_1 0x390
-#define SNOOP_TOP_ADDRESS_1 0x398
-#define SNOOP_BASE_ADDRESS_2 0x3a0
-#define SNOOP_TOP_ADDRESS_2 0x3a8
-#define SNOOP_BASE_ADDRESS_3 0x3b0
-#define SNOOP_TOP_ADDRESS_3 0x3b8
-
-/****************************************/
-/* CPU Error Report */
-/****************************************/
-
-#define CPU_ERROR_ADDRESS_LOW 0x070
-#define CPU_ERROR_ADDRESS_HIGH 0x078
-#define CPU_ERROR_DATA_LOW 0x128
-#define CPU_ERROR_DATA_HIGH 0x130
-#define CPU_ERROR_PARITY 0x138
-#define CPU_ERROR_CAUSE 0x140
-#define CPU_ERROR_MASK 0x148
-
-/****************************************/
-/* Pslave Debug */
-/****************************************/
-
-#define X_0_ADDRESS 0x360
-#define X_0_COMMAND_ID 0x368
-#define X_1_ADDRESS 0x370
-#define X_1_COMMAND_ID 0x378
-#define WRITE_DATA_LOW 0x3c0
-#define WRITE_DATA_HIGH 0x3c8
-#define WRITE_BYTE_ENABLE 0x3e0
-#define READ_DATA_LOW 0x3d0
-#define READ_DATA_HIGH 0x3d8
-#define READ_ID 0x3e8
-
-
-/****************************************/
-/* SDRAM and Device Address Space */
-/****************************************/
-
-
-/****************************************/
-/* SDRAM Configuration */
-/****************************************/
-
-
-#define SDRAM_CONFIGURATION 0x448
-#define SDRAM_OPERATION_MODE 0x474
-#define SDRAM_ADDRESS_DECODE 0x47c
-#define SDRAM_UMA_CONTROL 0x4a4
-#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8
-#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac
-#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0
-#define SDRAM_TIMING 0x4b4
-
-
-/****************************************/
-/* SDRAM Parameters */
-/****************************************/
-
-#define SDRAM_BANK0PARAMETERS 0x44C
-#define SDRAM_BANK1PARAMETERS 0x450
-#define SDRAM_BANK2PARAMETERS 0x454
-#define SDRAM_BANK3PARAMETERS 0x458
-
-
-/****************************************/
-/* SDRAM Error Report */
-/****************************************/
-
-#define SDRAM_ERROR_DATA_LOW 0x484
-#define SDRAM_ERROR_DATA_HIGH 0x480
-#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
-#define SDRAM_RECEIVED_ECC 0x488
-#define SDRAM_CALCULATED_ECC 0x48c
-#define SDRAM_ECC_CONTROL 0x494
-#define SDRAM_ECC_ERROR_COUNTER 0x498
-
-
-/****************************************/
-/* SDunit Debug (for internal use) */
-/****************************************/
-
-#define X0_ADDRESS 0x500
-#define X0_COMMAND_AND_ID 0x504
-#define X0_WRITE_DATA_LOW 0x508
-#define X0_WRITE_DATA_HIGH 0x50c
-#define X0_WRITE_BYTE_ENABLE 0x518
-#define X0_READ_DATA_LOW 0x510
-#define X0_READ_DATA_HIGH 0x514
-#define X0_READ_ID 0x51c
-#define X1_ADDRESS 0x520
-#define X1_COMMAND_AND_ID 0x524
-#define X1_WRITE_DATA_LOW 0x528
-#define X1_WRITE_DATA_HIGH 0x52c
-#define X1_WRITE_BYTE_ENABLE 0x538
-#define X1_READ_DATA_LOW 0x530
-#define X1_READ_DATA_HIGH 0x534
-#define X1_READ_ID 0x53c
-#define X0_SNOOP_ADDRESS 0x540
-#define X0_SNOOP_COMMAND 0x544
-#define X1_SNOOP_ADDRESS 0x548
-#define X1_SNOOP_COMMAND 0x54c
-
-
-/****************************************/
-/* Device Parameters */
-/****************************************/
-
-#define DEVICE_BANK0PARAMETERS 0x45c
-#define DEVICE_BANK1PARAMETERS 0x460
-#define DEVICE_BANK2PARAMETERS 0x464
-#define DEVICE_BANK3PARAMETERS 0x468
-#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
-#define DEVICE_CONTROL 0x4c0
-#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
-#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
-#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
-
-
-/****************************************/
-/* Device Interrupt */
-/****************************************/
-
-#define DEVICE_INTERRUPT_CAUSE 0x4d0
-#define DEVICE_INTERRUPT_MASK 0x4d4
-#define DEVICE_ERROR_ADDRESS 0x4d8
-
-/****************************************/
-/* DMA Record */
-/****************************************/
-
-#define CHANNEL0_DMA_BYTE_COUNT 0x800
-#define CHANNEL1_DMA_BYTE_COUNT 0x804
-#define CHANNEL2_DMA_BYTE_COUNT 0x808
-#define CHANNEL3_DMA_BYTE_COUNT 0x80C
-#define CHANNEL4_DMA_BYTE_COUNT 0x900
-#define CHANNEL5_DMA_BYTE_COUNT 0x904
-#define CHANNEL6_DMA_BYTE_COUNT 0x908
-#define CHANNEL7_DMA_BYTE_COUNT 0x90C
-#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
-#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
-#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
-#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
-#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
-#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
-#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
-#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
-#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
-#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
-#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
-#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
-#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
-#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
-#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
-#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
-#define CHANNEL0NEXT_RECORD_POINTER 0x830
-#define CHANNEL1NEXT_RECORD_POINTER 0x834
-#define CHANNEL2NEXT_RECORD_POINTER 0x838
-#define CHANNEL3NEXT_RECORD_POINTER 0x83C
-#define CHANNEL4NEXT_RECORD_POINTER 0x930
-#define CHANNEL5NEXT_RECORD_POINTER 0x934
-#define CHANNEL6NEXT_RECORD_POINTER 0x938
-#define CHANNEL7NEXT_RECORD_POINTER 0x93C
-#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
-#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
-#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
-#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
-#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
-#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
-#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
-#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
-#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
-#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
-#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
-#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
-#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
-#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
-#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
-#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
-#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
-#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
-#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
-#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
-#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
-#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
-#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
-#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
-#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
-#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
-#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
-#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
-#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
-#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
-#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
-#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
-
-/****************************************/
-/* DMA Channel Control */
-/****************************************/
-
-#define CHANNEL0CONTROL 0x840
-#define CHANNEL0CONTROL_HIGH 0x880
-#define CHANNEL1CONTROL 0x844
-#define CHANNEL1CONTROL_HIGH 0x884
-#define CHANNEL2CONTROL 0x848
-#define CHANNEL2CONTROL_HIGH 0x888
-#define CHANNEL3CONTROL 0x84C
-#define CHANNEL3CONTROL_HIGH 0x88C
-
-#define CHANNEL4CONTROL 0x940
-#define CHANNEL4CONTROL_HIGH 0x980
-#define CHANNEL5CONTROL 0x944
-#define CHANNEL5CONTROL_HIGH 0x984
-#define CHANNEL6CONTROL 0x948
-#define CHANNEL6CONTROL_HIGH 0x988
-#define CHANNEL7CONTROL 0x94C
-#define CHANNEL7CONTROL_HIGH 0x98C
-
-
-/****************************************/
-/* DMA Arbiter */
-/****************************************/
-
-#define ARBITER_CONTROL_0_3 0x860
-#define ARBITER_CONTROL_4_7 0x960
-
-
-/****************************************/
-/* DMA Interrupt */
-/****************************************/
-
-#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
-#define CHANELS0_3_INTERRUPT_MASK 0x8c4
-#define CHANELS0_3_ERROR_ADDRESS 0x8c8
-#define CHANELS0_3_ERROR_SELECT 0x8cc
-#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
-#define CHANELS4_7_INTERRUPT_MASK 0x9c4
-#define CHANELS4_7_ERROR_ADDRESS 0x9c8
-#define CHANELS4_7_ERROR_SELECT 0x9cc
-
-
-/****************************************/
-/* DMA Debug (for internal use) */
-/****************************************/
-
-#define DMA_X0_ADDRESS 0x8e0
-#define DMA_X0_COMMAND_AND_ID 0x8e4
-#define DMA_X0_WRITE_DATA_LOW 0x8e8
-#define DMA_X0_WRITE_DATA_HIGH 0x8ec
-#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
-#define DMA_X0_READ_DATA_LOW 0x8f0
-#define DMA_X0_READ_DATA_HIGH 0x8f4
-#define DMA_X0_READ_ID 0x8fc
-#define DMA_X1_ADDRESS 0x9e0
-#define DMA_X1_COMMAND_AND_ID 0x9e4
-#define DMA_X1_WRITE_DATA_LOW 0x9e8
-#define DMA_X1_WRITE_DATA_HIGH 0x9ec
-#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
-#define DMA_X1_READ_DATA_LOW 0x9f0
-#define DMA_X1_READ_DATA_HIGH 0x9f4
-#define DMA_X1_READ_ID 0x9fc
-
-/****************************************/
-/* Timer_Counter */
-/****************************************/
-
-#define TIMER_COUNTER0 0x850
-#define TIMER_COUNTER1 0x854
-#define TIMER_COUNTER2 0x858
-#define TIMER_COUNTER3 0x85C
-#define TIMER_COUNTER_0_3_CONTROL 0x864
-#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
-#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
-#define TIMER_COUNTER4 0x950
-#define TIMER_COUNTER5 0x954
-#define TIMER_COUNTER6 0x958
-#define TIMER_COUNTER7 0x95C
-#define TIMER_COUNTER_4_7_CONTROL 0x964
-#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
-#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
-
-/****************************************/
-/* PCI Slave Address Decoding */
-/****************************************/
-
-#define PCI_0SCS_0_BANK_SIZE 0xc08
-#define PCI_1SCS_0_BANK_SIZE 0xc88
-#define PCI_0SCS_1_BANK_SIZE 0xd08
-#define PCI_1SCS_1_BANK_SIZE 0xd88
-#define PCI_0SCS_2_BANK_SIZE 0xc0c
-#define PCI_1SCS_2_BANK_SIZE 0xc8c
-#define PCI_0SCS_3_BANK_SIZE 0xd0c
-#define PCI_1SCS_3_BANK_SIZE 0xd8c
-#define PCI_0CS_0_BANK_SIZE 0xc10
-#define PCI_1CS_0_BANK_SIZE 0xc90
-#define PCI_0CS_1_BANK_SIZE 0xd10
-#define PCI_1CS_1_BANK_SIZE 0xd90
-#define PCI_0CS_2_BANK_SIZE 0xd18
-#define PCI_1CS_2_BANK_SIZE 0xd98
-#define PCI_0CS_3_BANK_SIZE 0xc14
-#define PCI_1CS_3_BANK_SIZE 0xc94
-#define PCI_0CS_BOOT_BANK_SIZE 0xd14
-#define PCI_1CS_BOOT_BANK_SIZE 0xd94
-#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
-#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
-#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
-#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
-#define PCI_0P2P_I_O_BAR_SIZE 0xd24
-#define PCI_1P2P_I_O_BAR_SIZE 0xda4
-#define PCI_0CPU_BAR_SIZE 0xd28
-#define PCI_1CPU_BAR_SIZE 0xda8
-#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
-#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
-#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
-#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
-#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
-#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
-#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
-#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
-#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
-#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
-#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
-#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
-#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
-#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
-#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
-#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
-#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
-#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
-#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
-#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
-#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
-#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
-#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
-#define PCI_1DAC_CPU_BAR_SIZE 0xeac
-#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
-#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
-#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
-#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
-#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
-#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
-#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
-#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
-#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
-#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
-#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
-#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
-#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
-#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
-#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
-#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
-#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
-#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
-#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
-#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
-#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
-#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
-#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
-#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
-#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
-#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
-#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
-#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
-#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
-#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
-#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
-#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
-#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
-#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
-#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
-#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
-#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
-#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
-#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
-#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
-#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
-#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
-#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
-#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
-#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
-#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
-#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
-#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
-#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
-#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
-#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
-#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
-#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
-#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
-#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
-#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
-#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
-#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
-
-/****************************************/
-/* PCI Control */
-/****************************************/
-
-#define PCI_0COMMAND 0xc00
-#define PCI_1COMMAND 0xc80
-#define PCI_0MODE 0xd00
-#define PCI_1MODE 0xd80
-#define PCI_0TIMEOUT_RETRY 0xc04
-#define PCI_1TIMEOUT_RETRY 0xc84
-#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
-#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
-#define MSI_0TRIGGER_TIMER 0xc38
-#define MSI_1TRIGGER_TIMER 0xcb8
-#define PCI_0ARBITER_CONTROL 0x1d00
-#define PCI_1ARBITER_CONTROL 0x1d80
-/* changing untill here */
-#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
-#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
-#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
-#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
-#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
-#define PCI_0P2P_CONFIGURATION 0x1d14
-#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
-#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
-#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
-#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10
-#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
-#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
-#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20
-#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
-#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
-#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30
-#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
-#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
-#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40
-#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
-#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
-#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50
-#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
-#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
-#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60
-#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
-#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
-#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70
-#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
-#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
-#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
-#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
-#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
-#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
-#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
-#define PCI_1P2P_CONFIGURATION 0x1d94
-#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
-#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
-#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
-#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90
-#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
-#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
-#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0
-#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
-#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
-#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0
-#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
-#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
-#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0
-#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
-#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
-#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0
-#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
-#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
-#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0
-#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
-#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
-#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0
-#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
-#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
-
-/****************************************/
-/* PCI Snoop Control */
-/****************************************/
-
-#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
-#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
-#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
-#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
-#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
-#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
-#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
-#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
-#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
-#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
-#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
-#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
-#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
-#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
-#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
-#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
-#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
-#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
-#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
-#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
-#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
-#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
-#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
-#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
-
-/****************************************/
-/* PCI Configuration Address */
-/****************************************/
-
-#define PCI_0CONFIGURATION_ADDRESS 0xcf8
-#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
-#define PCI_1CONFIGURATION_ADDRESS 0xc78
-#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
-#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
-#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
-
-/****************************************/
-/* PCI Error Report */
-/****************************************/
-
-#define PCI_0SERR_MASK 0xc28
-#define PCI_0ERROR_ADDRESS_LOW 0x1d40
-#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
-#define PCI_0ERROR_DATA_LOW 0x1d48
-#define PCI_0ERROR_DATA_HIGH 0x1d4c
-#define PCI_0ERROR_COMMAND 0x1d50
-#define PCI_0ERROR_CAUSE 0x1d58
-#define PCI_0ERROR_MASK 0x1d5c
-#define PCI_1SERR_MASK 0xca8
-#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
-#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
-#define PCI_1ERROR_DATA_LOW 0x1dc8
-#define PCI_1ERROR_DATA_HIGH 0x1dcc
-#define PCI_1ERROR_COMMAND 0x1dd0
-#define PCI_1ERROR_CAUSE 0x1dd8
-#define PCI_1ERROR_MASK 0x1ddc
-
-
-/****************************************/
-/* Lslave Debug (for internal use) */
-/****************************************/
-
-#define L_SLAVE_X0_ADDRESS 0x1d20
-#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
-#define L_SLAVE_X1_ADDRESS 0x1d28
-#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
-#define L_SLAVE_WRITE_DATA_LOW 0x1d30
-#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
-#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
-#define L_SLAVE_READ_DATA_LOW 0x1d38
-#define L_SLAVE_READ_DATA_HIGH 0x1d3c
-#define L_SLAVE_READ_ID 0x1d64
-
-/****************************************/
-/* PCI Configuration Function 0 */
-/****************************************/
-
-#define PCI_DEVICE_AND_VENDOR_ID 0x000
-#define PCI_STATUS_AND_COMMAND 0x004
-#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
-#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
-#define PCI_SCS_0_BASE_ADDRESS 0x010
-#define PCI_SCS_1_BASE_ADDRESS 0x014
-#define PCI_SCS_2_BASE_ADDRESS 0x018
-#define PCI_SCS_3_BASE_ADDRESS 0x01C
-#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
-#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
-#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
-#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
-#define PCI_CAPABILTY_LIST_POINTER 0x034
-#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
-#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
-#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
-#define PCI_VPD_ADDRESS 0x048
-#define PCI_VPD_DATA 0x04c
-#define PCI_MSI_MESSAGE_CONTROL 0x050
-#define PCI_MSI_MESSAGE_ADDRESS 0x054
-#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
-#define PCI_MSI_MESSAGE_DATA 0x05c
-#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
-
-/****************************************/
-/* PCI Configuration Function 1 */
-/****************************************/
-
-#define PCI_CS_0_BASE_ADDRESS 0x110
-#define PCI_CS_1_BASE_ADDRESS 0x114
-#define PCI_CS_2_BASE_ADDRESS 0x118
-#define PCI_CS_3_BASE_ADDRESS 0x11c
-#define PCI_BOOTCS_BASE_ADDRESS 0x120
-
-/****************************************/
-/* PCI Configuration Function 2 */
-/****************************************/
-
-#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
-#define PCI_P2P_MEM1_BASE_ADDRESS 0x214
-#define PCI_P2P_I_O_BASE_ADDRESS 0x218
-#define PCI_CPU_BASE_ADDRESS 0x21c
-
-/****************************************/
-/* PCI Configuration Function 4 */
-/****************************************/
-
-#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
-#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
-#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
-#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
-#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
-
-
-/****************************************/
-/* PCI Configuration Function 5 */
-/****************************************/
-
-#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
-#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
-#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
-#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
-#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
-
-
-/****************************************/
-/* PCI Configuration Function 6 */
-/****************************************/
-
-#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
-#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
-#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
-#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
-#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
-#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
-
-/****************************************/
-/* PCI Configuration Function 7 */
-/****************************************/
-
-#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
-#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
-#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
-#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
-#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
-
-/****************************************/
-/* Interrupts */
-/****************************************/
-
-#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
-#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
-#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
-#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
-#define CPU_SELECT_CAUSE_REGISTER 0xc70
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
-#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
-#define PCI_0SELECT_CAUSE 0xc74
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
-#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
-#define PCI_1SELECT_CAUSE 0xcf4
-#define CPU_INT_0_MASK 0xe60
-#define CPU_INT_1_MASK 0xe64
-#define CPU_INT_2_MASK 0xe68
-#define CPU_INT_3_MASK 0xe6c
-
-/****************************************/
-/* I20 Support registers */
-/****************************************/
-
-#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
-#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
-#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
-#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
-#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
-#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
-#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
-
-#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
-#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
-#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
-#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
-#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
-#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
-#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C
-
-/****************************************/
-/* Communication Unit Registers */
-/****************************************/
-
-#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200
-#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
-#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
-#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
-#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
-#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
-#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
-#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
-#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
-#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
-#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
-#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
-#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
-#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
-#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
-#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
-#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
-#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
-#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
-#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
-#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
-#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
-#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
-#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
-#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
-#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
-#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
-#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0
-#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4
-#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
-#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
-#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
-#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
-#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
-#define SERIAL_INIT_LAST_DATA 0xf324
-#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
-#define COMM_UNIT_ARBITER_CONTROL 0xf300
-#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
-#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
-#define COMM_UNIT_INTERRUPT_MASK 0xf314
-#define COMM_UNIT_ERROR_ADDRESS 0xf314
-
-/****************************************/
-/* Cunit Debug (for internal use) */
-/****************************************/
-
-#define CUNIT_ADDRESS 0xf340
-#define CUNIT_COMMAND_AND_ID 0xf344
-#define CUNIT_WRITE_DATA_LOW 0xf348
-#define CUNIT_WRITE_DATA_HIGH 0xf34c
-#define CUNIT_WRITE_BYTE_ENABLE 0xf358
-#define CUNIT_READ_DATA_LOW 0xf350
-#define CUNIT_READ_DATA_HIGH 0xf354
-#define CUNIT_READ_ID 0xf35c
-
-/****************************************/
-/* Fast Ethernet Unit Registers */
-/****************************************/
-
-/* Ethernet */
-
-#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
-#define ETHERNET_SMI_REGISTER 0x2010
-
-/* Ethernet 0 */
-
-#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
-#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
-#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
-#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
-#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
-#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
-#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
-#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
-#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
-#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
-#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
-#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
-#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
-#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
-#define ETHERNET0_MIB_COUNTER_BASE 0x2500
-
-/* Ethernet 1 */
-
-#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
-#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
-#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
-#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
-#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
-#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
-#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
-#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
-#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
-#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
-#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
-#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
-#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
-#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
-#define ETHERNET1_MIB_COUNTER_BASE 0x2900
-
-/* Ethernet 2 */
-
-#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
-#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
-#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
-#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
-#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
-#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
-#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
-#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
-#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
-#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
-#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
-#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
-#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
-#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
-#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
-
-/****************************************/
-/* SDMA Registers */
-/****************************************/
-
-#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
-#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
-#define CHANNEL0_COMMAND_REGISTER 0x4008
-#define CHANNEL0_RX_CMD_STATUS 0x4800
-#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
-#define CHANNEL0_RX_BUFFER_POINTER 0x4808
-#define CHANNEL0_RX_NEXT_POINTER 0x480c
-#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
-#define CHANNEL0_TX_CMD_STATUS 0x4C00
-#define CHANNEL0_TX_PACKET_SIZE 0x4C04
-#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
-#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
-#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
-#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
-#define CHANNEL1_CONFIGURATION_REGISTER 0x5000
-#define CHANNEL1_COMMAND_REGISTER 0x5008
-#define CHANNEL1_RX_CMD_STATUS 0x5800
-#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804
-#define CHANNEL1_RX_BUFFER_POINTER 0x5808
-#define CHANNEL1_RX_NEXT_POINTER 0x580c
-#define CHANNEL1_TX_CMD_STATUS 0x5C00
-#define CHANNEL1_TX_PACKET_SIZE 0x5C04
-#define CHANNEL1_TX_BUFFER_POINTER 0x5C08
-#define CHANNEL1_TX_NEXT_POINTER 0x5C0c
-#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810
-#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10
-#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14
-#define CHANNEL2_CONFIGURATION_REGISTER 0x6000
-#define CHANNEL2_COMMAND_REGISTER 0x6008
-#define CHANNEL2_RX_CMD_STATUS 0x6800
-#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804
-#define CHANNEL2_RX_BUFFER_POINTER 0x6808
-#define CHANNEL2_RX_NEXT_POINTER 0x680c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
-#define CHANNEL2_TX_CMD_STATUS 0x6C00
-#define CHANNEL2_TX_PACKET_SIZE 0x6C04
-#define CHANNEL2_TX_BUFFER_POINTER 0x6C08
-#define CHANNEL2_TX_NEXT_POINTER 0x6C0c
-#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
-#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
-#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
-
-/* SDMA Interrupt */
-
-#define SDMA_CAUSE 0xb820
-#define SDMA_MASK 0xb8a0
-
-
-/****************************************/
-/* Baude Rate Generators Registers */
-/****************************************/
-
-/* BRG 0 */
-
-#define BRG0_CONFIGURATION_REGISTER 0xb200
-#define BRG0_BAUDE_TUNING_REGISTER 0xb204
-
-/* BRG 1 */
-
-#define BRG1_CONFIGURATION_REGISTER 0xb208
-#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
-
-/* BRG 2 */
-
-#define BRG2_CONFIGURATION_REGISTER 0xb210
-#define BRG2_BAUDE_TUNING_REGISTER 0xb214
-
-/* BRG Interrupts */
-
-#define BRG_CAUSE_REGISTER 0xb834
-#define BRG_MASK_REGISTER 0xb8b4
-
-/* MISC */
-
-#define MAIN_ROUTING_REGISTER 0xb400
-#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
-#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
-#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
-#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
-#define WATCHDOG_VALUE_REGISTER 0xb414
-
-
-/****************************************/
-/* Flex TDM Registers */
-/****************************************/
-
-/* FTDM Port */
-
-#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
-#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
-#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
-#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
-#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
-#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
-#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
-
-/* FTDM Interrupts */
-
-#define FTDM_CAUSE_REGISTER 0xb830
-#define FTDM_MASK_REGISTER 0xb8b0
-
-
-/****************************************/
-/* GPP Interface Registers */
-/****************************************/
-
-#define GPP_IO_CONTROL 0xf100
-#define GPP_LEVEL_CONTROL 0xf110
-#define GPP_VALUE 0xf104
-#define GPP_INTERRUPT_CAUSE 0xf108
-#define GPP_INTERRUPT_MASK 0xf10c
-
-#define MPP_CONTROL0 0xf000
-#define MPP_CONTROL1 0xf004
-#define MPP_CONTROL2 0xf008
-#define MPP_CONTROL3 0xf00c
-#define DEBUG_PORT_MULTIPLEX 0xf014
-#define SERIAL_PORT_MULTIPLEX 0xf010
-
-/****************************************/
-/* I2C Registers */
-/****************************************/
-
-#define I2C_SLAVE_ADDRESS 0xc000
-#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
-#define I2C_DATA 0xc004
-#define I2C_CONTROL 0xc008
-#define I2C_STATUS_BAUDE_RATE 0xc00C
-#define I2C_SOFT_RESET 0xc01c
-
-/****************************************/
-/* MPSC Registers */
-/****************************************/
-
-/* MPSC0 */
-
-#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
-#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
-#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
-#define CHANNEL0_REGISTER1 0x800c
-#define CHANNEL0_REGISTER2 0x8010
-#define CHANNEL0_REGISTER3 0x8014
-#define CHANNEL0_REGISTER4 0x8018
-#define CHANNEL0_REGISTER5 0x801c
-#define CHANNEL0_REGISTER6 0x8020
-#define CHANNEL0_REGISTER7 0x8024
-#define CHANNEL0_REGISTER8 0x8028
-#define CHANNEL0_REGISTER9 0x802c
-#define CHANNEL0_REGISTER10 0x8030
-#define CHANNEL0_REGISTER11 0x8034
-
-/* MPSC1 */
-
-#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840
-#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844
-#define MPSC1_PROTOCOL_CONFIGURATION 0x8848
-#define CHANNEL1_REGISTER1 0x884c
-#define CHANNEL1_REGISTER2 0x8850
-#define CHANNEL1_REGISTER3 0x8854
-#define CHANNEL1_REGISTER4 0x8858
-#define CHANNEL1_REGISTER5 0x885c
-#define CHANNEL1_REGISTER6 0x8860
-#define CHANNEL1_REGISTER7 0x8864
-#define CHANNEL1_REGISTER8 0x8868
-#define CHANNEL1_REGISTER9 0x886c
-#define CHANNEL1_REGISTER10 0x8870
-#define CHANNEL1_REGISTER11 0x8874
-
-/* MPSC2 */
-
-#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040
-#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044
-#define MPSC2_PROTOCOL_CONFIGURATION 0x9048
-#define CHANNEL2_REGISTER1 0x904c
-#define CHANNEL2_REGISTER2 0x9050
-#define CHANNEL2_REGISTER3 0x9054
-#define CHANNEL2_REGISTER4 0x9058
-#define CHANNEL2_REGISTER5 0x905c
-#define CHANNEL2_REGISTER6 0x9060
-#define CHANNEL2_REGISTER7 0x9064
-#define CHANNEL2_REGISTER8 0x9068
-#define CHANNEL2_REGISTER9 0x906c
-#define CHANNEL2_REGISTER10 0x9070
-#define CHANNEL2_REGISTER11 0x9074
-
-/* MPSCs Interrupts */
-
-#define MPSC0_CAUSE 0xb824
-#define MPSC0_MASK 0xb8a4
-#define MPSC1_CAUSE 0xb828
-#define MPSC1_MASK 0xb8a8
-#define MPSC2_CAUSE 0xb82c
-#define MPSC2_MASK 0xb8ac
-
-#endif /* __INCgt64260rh */
diff --git a/include/galileo/memory.h b/include/galileo/memory.h
deleted file mode 100644
index 0c46c24..0000000
--- a/include/galileo/memory.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Memory.h - Memory mappings and remapping functions declarations */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCmemoryh
-#define __INCmemoryh
-
-/* includes */
-
-#include "core.h"
-
-/* defines */
-
-#define DONT_MODIFY 0xffffffff
-#define PARITY_SUPPORT 0x40000000
-
-#define _8BIT 0x00000000
-#define _16BIT 0x00100000
-#define _32BIT 0x00200000
-#define _64BIT 0x00300000
-
-/* typedefs */
-
- typedef struct deviceParam
-{ /* boundary values */
- unsigned int turnOff; /* 0x0 - 0xf */
- unsigned int acc2First; /* 0x0 - 0x1f */
- unsigned int acc2Next; /* 0x0 - 0x1f */
- unsigned int ale2Wr; /* 0x0 - 0xf */
- unsigned int wrLow; /* 0x0 - 0xf */
- unsigned int wrHigh; /* 0x0 - 0xf */
- unsigned int deviceWidth; /* in Bytes */
-} DEVICE_PARAM;
-
-typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
-typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
-
-typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
- MEM_REGION3,MEM_REGION4,MEM_REGION5, \
- MEM_REGION6,MEM_REGION7} \
- MEMORY_PROTECT_REGION;
-typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
- MEMORY_ACCESS;
-typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
- MEMORY_ACCESS_WRITE;
-typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
- MEMORY_CACHE_PROTECT;
-typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
- MEMORY_SNOOP_TYPE;
-typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
- MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
- MEMORY_SNOOP_REGION;
-
-/* functions */
-unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
-unsigned int memoryGetDeviceBaseAddress(DEVICE device);
-unsigned int memoryGetBankSize(MEMORY_BANK bank);
-unsigned int memoryGetDeviceSize(DEVICE device);
-unsigned int memoryGetDeviceWidth(DEVICE device);
-
-/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
-bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
-bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
-
-/* Change the Internal Register Base Address to a new given Address. */
-bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
-/* returns internal Register Space Base Address. */
-unsigned int memoryGetInternalRegistersSpace(void);
-/* Configurate the protection feature to a given space. */
-bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
- MEMORY_ACCESS memoryAccess,
- MEMORY_ACCESS_WRITE memoryWrite,
- MEMORY_CACHE_PROTECT cacheProtection,
- unsigned int baseAddress,
- unsigned int regionLength);
-/* Configurate the snoop feature to a given space. */
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
- MEMORY_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength);
-
-bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
-bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-#endif /* __INCmemoryh */
diff --git a/include/galileo/pci.h b/include/galileo/pci.h
deleted file mode 100644
index 6ed8b95..0000000
--- a/include/galileo/pci.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* PCI.h - PCI functions header file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCpcih
-#define __INCpcih
-
-/* includes */
-
-#include "core.h"
-#include "memory.h"
-
-/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
-#define PCI_MAX_DEVICES 22
-
-
-/* Macros */
-#define SELF 32
-
-/* Defines for the access regions. */
-#define PREFETCH_ENABLE BIT12
-#define PREFETCH_DISABLE NO_BIT
-#define DELAYED_READ_ENABLE BIT13
-/* #define CACHING_ENABLE BIT14 */
-/* aggressive prefetch: PCI slave prefetch two burst in advance*/
-#define AGGRESSIVE_PREFETCH BIT16
-/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
-/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
-#define MAX_BURST_4 NO_BIT
-#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
-#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
-#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
-#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
-#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
-#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
-#define PCI_ACCESS_PROTECT BIT28
-#define PCI_WRITE_PROTECT BIT29
-
-/* typedefs */
-
-typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
- REGION6,REGION7} PCI_ACCESS_REGIONS;
-
-typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
-typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
-
-typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
- PCI_SNOOP_TYPE;
-typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
- PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
- PCI_SNOOP_REGION;
-
-typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
-typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
- PCI_REGION2,PCI_REGION3,
- PCI_IO}
- PCI_REGION;
-
-/* read/write configuration registers on local PCI bus. */
-void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum, unsigned int data);
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
- unsigned int pciDevNum);
-
-/* read/write configuration registers on another PCI bus. */
-void pciOverBridgeWriteConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum,unsigned int data);
-unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum);
-
-/* Master`s memory space */
-bool pciMapSpace(PCI_HOST host, PCI_REGION region,
- unsigned int remapBase,
- unsigned int deviceBase,
- unsigned int deviceLength);
-unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
-unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
-
-/* Slave`s memory space */
-void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
- unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
-
-/* PCI region options */
-
-bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
- unsigned int features, unsigned int baseAddress,
- unsigned int regionLength);
-
-void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
-
-/* PCI arbiter */
-
-bool pciArbiterEnable(PCI_HOST host);
-bool pciArbiterDisable(PCI_HOST host);
-bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
- PCI_AGENT_PARK externalAgent0,
- PCI_AGENT_PARK externalAgent1,
- PCI_AGENT_PARK externalAgent2,
- PCI_AGENT_PARK externalAgent3,
- PCI_AGENT_PARK externalAgent4,
- PCI_AGENT_PARK externalAgent5);
-bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
- PCI_SNOOP_TYPE snoopType,
- unsigned int baseAddress,
- unsigned int regionLength);
-
-#endif /* __INCpcih */
diff --git a/include/image.h b/include/image.h
index af30d60..ee3afe3 100644
--- a/include/image.h
+++ b/include/image.h
@@ -152,6 +152,7 @@
#define IH_OS_INTEGRITY 21 /* INTEGRITY */
#define IH_OS_OSE 22 /* OSE */
#define IH_OS_PLAN9 23 /* Plan 9 */
+#define IH_OS_OPENRTOS 24 /* OpenRTOS */
/*
* CPU Architecture Codes (supported by Linux)
diff --git a/include/lcd.h b/include/lcd.h
index 020d880..160f940 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -12,6 +12,7 @@
#ifndef _LCD_H_
#define _LCD_H_
+#include <lcd_console.h>
extern char lcd_is_enabled;
@@ -291,6 +292,20 @@
int lcd_get_screen_columns(void);
/**
+ * Get the background color of the LCD
+ *
+ * @return background color value
+ */
+int lcd_getbgcolor(void);
+
+/**
+ * Get the foreground color of the LCD
+ *
+ * @return foreground color value
+ */
+int lcd_getfgcolor(void);
+
+/**
* Set the position of the text cursor
*
* @param col Column to place cursor (0 = left side)
@@ -359,15 +374,7 @@
/************************************************************************/
/* ** CONSOLE CONSTANTS */
/************************************************************************/
-#if LCD_BPP == LCD_MONOCHROME
-
-/*
- * Simple black/white definitions
- */
-# define CONSOLE_COLOR_BLACK 0
-# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */
-
-#elif LCD_BPP == LCD_COLOR8
+#if LCD_BPP == LCD_COLOR8
/*
* 8bpp color definitions
diff --git a/include/lcd_console.h b/include/lcd_console.h
new file mode 100644
index 0000000..429214d
--- /dev/null
+++ b/include/lcd_console.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* By default we scroll by a single line */
+#ifndef CONFIG_CONSOLE_SCROLL_LINES
+#define CONFIG_CONSOLE_SCROLL_LINES 1
+#endif
+
+/**
+ * lcd_init_console() - Initialize lcd console parameters
+ *
+ * Setup the address of console base, and the number of rows and columns the
+ * console has.
+ *
+ * @address: Console base address
+ * @rows: Number of rows in the console
+ * @cols: Number of columns in the console
+ */
+void lcd_init_console(void *address, int rows, int cols);
+
+/**
+ * lcd_set_col() - Set the number of the current lcd console column
+ *
+ * Set the number of the console column where the cursor is.
+ *
+ * @col: Column number
+ */
+void lcd_set_col(short col);
+
+/**
+ * lcd_set_row() - Set the number of the current lcd console row
+ *
+ * Set the number of the console row where the cursor is.
+ *
+ * @row: Row number
+ */
+void lcd_set_row(short row);
+
+/**
+ * lcd_position_cursor() - Position the cursor on the screen
+ *
+ * Position the cursor at the given coordinates on the screen.
+ *
+ * @col: Column number
+ * @row: Row number
+ */
+void lcd_position_cursor(unsigned col, unsigned row);
+
+/**
+ * lcd_get_screen_rows() - Get the total number of screen rows
+ *
+ * @return: Number of screen rows
+ */
+int lcd_get_screen_rows(void);
+
+/**
+ * lcd_get_screen_columns() - Get the total number of screen columns
+ *
+ * @return: Number of screen columns
+ */
+int lcd_get_screen_columns(void);
+
+/**
+ * lcd_putc() - Print to screen a single character at the location of the cursor
+ *
+ * @c: The character to print
+ */
+void lcd_putc(const char c);
+
+/**
+ * lcd_puts() - Print to screen a string at the location of the cursor
+ *
+ * @s: The string to print
+ */
+void lcd_puts(const char *s);
+
+/**
+ * lcd_printf() - Print to screen a formatted string at location of the cursor
+ *
+ * @fmt: The formatted string to print
+ * @...: The arguments for the formatted string
+ */
+void lcd_printf(const char *fmt, ...);
diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h
index 9a86582..6cbae45 100644
--- a/include/linux/mtd/omap_gpmc.h
+++ b/include/linux/mtd/omap_gpmc.h
@@ -66,7 +66,11 @@
u32 status; /* 0x54 */
u8 res5[0x8]; /* 0x58 */
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
+ u32 prefetch_config1; /* 0x1E0 */
+ u32 prefetch_config2; /* 0x1E4 */
+ u32 res6; /* 0x1E8 */
+ u32 prefetch_control; /* 0x1EC */
+ u32 prefetch_status; /* 0x1F0 */
u32 ecc_config; /* 0x1F4 */
u32 ecc_control; /* 0x1F8 */
u32 ecc_size_config; /* 0x1FC */
diff --git a/include/mipi_display.h b/include/mipi_display.h
new file mode 100644
index 0000000..ddcc8ca
--- /dev/null
+++ b/include/mipi_display.h
@@ -0,0 +1,130 @@
+/*
+ * Defines for Mobile Industry Processor Interface (MIPI(R))
+ * Display Working Group standards: DSI, DCS, DBI, DPI
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright (C) 2006 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef MIPI_DISPLAY_H
+#define MIPI_DISPLAY_H
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+ MIPI_DSI_V_SYNC_START = 0x01,
+ MIPI_DSI_V_SYNC_END = 0x11,
+ MIPI_DSI_H_SYNC_START = 0x21,
+ MIPI_DSI_H_SYNC_END = 0x31,
+
+ MIPI_DSI_COLOR_MODE_OFF = 0x02,
+ MIPI_DSI_COLOR_MODE_ON = 0x12,
+ MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
+ MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
+
+ MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
+ MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
+ MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
+
+ MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
+ MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
+ MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
+
+ MIPI_DSI_DCS_SHORT_WRITE = 0x05,
+ MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
+
+ MIPI_DSI_DCS_READ = 0x06,
+
+ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
+
+ MIPI_DSI_END_OF_TRANSMISSION = 0x08,
+
+ MIPI_DSI_NULL_PACKET = 0x09,
+ MIPI_DSI_BLANKING_PACKET = 0x19,
+ MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
+ MIPI_DSI_DCS_LONG_WRITE = 0x39,
+
+ MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
+ MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
+};
+
+/* MIPI DSI Peripheral-to-Processor transaction types */
+enum {
+ MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
+ MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
+ MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
+ MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
+ MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
+ MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
+ MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
+ MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
+};
+
+/* MIPI DCS commands */
+enum {
+ MIPI_DCS_NOP = 0x00,
+ MIPI_DCS_SOFT_RESET = 0x01,
+ MIPI_DCS_GET_DISPLAY_ID = 0x04,
+ MIPI_DCS_GET_RED_CHANNEL = 0x06,
+ MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
+ MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
+ MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
+ MIPI_DCS_GET_POWER_MODE = 0x0A,
+ MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
+ MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
+ MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
+ MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
+ MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
+ MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
+ MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
+ MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
+ MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
+ MIPI_DCS_EXIT_INVERT_MODE = 0x20,
+ MIPI_DCS_ENTER_INVERT_MODE = 0x21,
+ MIPI_DCS_SET_GAMMA_CURVE = 0x26,
+ MIPI_DCS_SET_DISPLAY_OFF = 0x28,
+ MIPI_DCS_SET_DISPLAY_ON = 0x29,
+ MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
+ MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
+ MIPI_DCS_WRITE_MEMORY_START = 0x2C,
+ MIPI_DCS_WRITE_LUT = 0x2D,
+ MIPI_DCS_READ_MEMORY_START = 0x2E,
+ MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_SCROLL_AREA = 0x33,
+ MIPI_DCS_SET_TEAR_OFF = 0x34,
+ MIPI_DCS_SET_TEAR_ON = 0x35,
+ MIPI_DCS_SET_ADDRESS_MODE = 0x36,
+ MIPI_DCS_SET_SCROLL_START = 0x37,
+ MIPI_DCS_EXIT_IDLE_MODE = 0x38,
+ MIPI_DCS_ENTER_IDLE_MODE = 0x39,
+ MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
+ MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
+ MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
+ MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
+ MIPI_DCS_GET_SCANLINE = 0x45,
+ MIPI_DCS_READ_DDB_START = 0xA1,
+ MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
+};
+
+/* MIPI DCS pixel formats */
+#define MIPI_DCS_PIXEL_FMT_24BIT 7
+#define MIPI_DCS_PIXEL_FMT_18BIT 6
+#define MIPI_DCS_PIXEL_FMT_16BIT 5
+#define MIPI_DCS_PIXEL_FMT_12BIT 3
+#define MIPI_DCS_PIXEL_FMT_8BIT 2
+#define MIPI_DCS_PIXEL_FMT_3BIT 1
+
+#endif
diff --git a/include/mmc.h b/include/mmc.h
index 7ec255d..09101e2 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -147,11 +147,16 @@
/*
* EXT_CSD fields
*/
+#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
+#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
+#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
+#define EXT_CSD_WR_REL_PARAM 166 /* R */
+#define EXT_CSD_WR_REL_SET 167 /* R/W */
#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
#define EXT_CSD_BOOT_BUS_WIDTH 177
@@ -201,6 +206,14 @@
#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
+#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
+#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
+
+#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
+
+#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
+#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
+
#define R1_ILLEGAL_COMMAND (1 << 22)
#define R1_APP_CMD (1 << 5)
@@ -224,6 +237,7 @@
#define MMCPART_NOAVAILABLE (0xff)
#define PART_ACCESS_MASK (0x7)
#define PART_SUPPORT (0x1)
+#define ENHNCD_SUPPORT (0x2)
#define PART_ENH_ATTRIB (0x1f)
/* Maximum block size for MMC */
@@ -302,17 +316,23 @@
uint csd[4];
uint cid[4];
ushort rca;
+ u8 part_support;
+ u8 part_attr;
+ u8 wr_rel_set;
char part_config;
char part_num;
uint tran_speed;
uint read_bl_len;
uint write_bl_len;
- uint erase_grp_size;
+ uint erase_grp_size; /* in 512-byte sectors */
+ uint hc_wp_grp_size; /* in 512-byte sectors */
u64 capacity;
u64 capacity_user;
u64 capacity_boot;
u64 capacity_rpmb;
u64 capacity_gp[4];
+ u64 enh_user_start;
+ u64 enh_user_size;
block_dev_desc_t block_dev;
char op_cond_pending; /* 1 if we are waiting on an op_cond command */
char init_in_progress; /* 1 if we have done mmc_start_init() */
@@ -321,6 +341,27 @@
int ddr_mode;
};
+struct mmc_hwpart_conf {
+ struct {
+ uint enh_start; /* in 512-byte sectors */
+ uint enh_size; /* in 512-byte sectors, if 0 no enh area */
+ unsigned wr_rel_change : 1;
+ unsigned wr_rel_set : 1;
+ } user;
+ struct {
+ uint size; /* in 512-byte sectors */
+ unsigned enhanced : 1;
+ unsigned wr_rel_change : 1;
+ unsigned wr_rel_set : 1;
+ } gp_part[4];
+};
+
+enum mmc_hwpart_conf_mode {
+ MMC_HWPART_CONF_CHECK,
+ MMC_HWPART_CONF_SET,
+ MMC_HWPART_CONF_COMPLETE,
+};
+
int mmc_register(struct mmc *mmc);
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
void mmc_destroy(struct mmc *mmc);
@@ -333,6 +374,8 @@
void print_mmc_devices(char separator);
int get_mmc_num(void);
int mmc_switch_part(int dev_num, unsigned int part_num);
+int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
+ enum mmc_hwpart_conf_mode mode);
int mmc_getcd(struct mmc *mmc);
int board_mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
diff --git a/include/net.h b/include/net.h
index 18d279e..3da35fe 100644
--- a/include/net.h
+++ b/include/net.h
@@ -81,7 +81,7 @@
struct eth_device {
char name[16];
unsigned char enetaddr[6];
- int iobase;
+ phys_addr_t iobase;
int state;
int (*init) (struct eth_device *, bd_t *);
diff --git a/include/netdev.h b/include/netdev.h
index 34651ab..daffc12 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -93,7 +93,8 @@
int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
unsigned long ctrl_addr);
int zynq_gem_of_init(const void *blob);
-int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
+int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
+ int phy_addr, u32 emio);
/*
* As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
* exported by a public hader file, we need a global definition at this point.
diff --git a/include/phy.h b/include/phy.h
index 1e282e2..d117fc1 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -225,6 +225,7 @@
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);
+int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_cortina_init(void);
diff --git a/include/power/tps62362.h b/include/power/tps62362.h
new file mode 100644
index 0000000..720c338
--- /dev/null
+++ b/include/power/tps62362.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __POWER_TPS62362_H__
+#define __POWER_TPS62362_H__
+
+/* I2C chip address */
+#define TPS62362_I2C_ADDR 0x60
+
+/* Registers */
+#define TPS62362_SET0 0x00
+#define TPS62362_SET1 0x01
+#define TPS62362_SET2 0x02
+#define TPS62362_SET3 0x03
+#define TPS62362_NUM_REGS 4
+
+#define TPS62362_DCDC_VOLT_SEL_0950MV 0x12
+#define TPS62362_DCDC_VOLT_SEL_1100MV 0x21
+#define TPS62362_DCDC_VOLT_SEL_1200MV 0x2b
+#define TPS62362_DCDC_VOLT_SEL_1260MV 0x31
+#define TPS62362_DCDC_VOLT_SEL_1330MV 0x38
+
+int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel);
+int power_tps62362_init(unsigned char bus);
+#endif /* __POWER_TPS62362_H__ */
diff --git a/include/power/tps65218.h b/include/power/tps65218.h
index f8f33b8..63fc7b3 100644
--- a/include/power/tps65218.h
+++ b/include/power/tps65218.h
@@ -54,7 +54,10 @@
#define TPS65218_MASK_ALL_BITS 0xFF
+#define TPS65218_DCDC_VOLT_SEL_0950MV 0x0a
#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19
+#define TPS65218_DCDC_VOLT_SEL_1200MV 0x23
+#define TPS65218_DCDC_VOLT_SEL_1260MV 0x29
#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30
int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
diff --git a/include/spartan2.h b/include/spartan2.h
index 2aca954..14606c3 100644
--- a/include/spartan2.h
+++ b/include/spartan2.h
@@ -38,7 +38,12 @@
xilinx_post_fn post;
} xilinx_spartan2_slave_serial_fns;
+#if defined(CONFIG_FPGA_SPARTAN2)
extern struct xilinx_fpga_op spartan2_op;
+# define FPGA_SPARTAN2_OPS &spartan2_op
+#else
+# define FPGA_SPARTAN2_OPS NULL
+#endif
/* Device Image Sizes
*********************************************************************/
@@ -61,36 +66,47 @@
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN2_OPS }
#endif /* _SPARTAN2_H_ */
diff --git a/include/spartan3.h b/include/spartan3.h
index d6d67a6..fcb27b0 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -40,7 +40,12 @@
xilinx_abort_fn abort;
} xilinx_spartan3_slave_serial_fns;
+#if defined(CONFIG_FPGA_SPARTAN3)
extern struct xilinx_fpga_op spartan3_op;
+# define FPGA_SPARTAN3_OPS &spartan3_op
+#else
+# define FPGA_SPARTAN3_OPS NULL
+#endif
/* Device Image Sizes
*********************************************************************/
@@ -71,48 +76,60 @@
*********************************************************************/
/* Spartan-III devices */
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
- &spartan3_op }
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
- &spartan3_op }
+ FPGA_SPARTAN3_OPS }
#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
-{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
+{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
+ FPGA_SPARTAN3_OPS }
#endif /* _SPARTAN3_H_ */
diff --git a/include/usb.h b/include/usb.h
index d3c7415..a8fee0b 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -120,6 +120,7 @@
* Each instance needs its own set of data structures.
*/
unsigned long status;
+ unsigned long int_pending; /* 1 bit per ep, used by int_queue */
int act_len; /* transfered bytes */
int maxchild; /* Number of ports if hub */
int portnr;
@@ -154,11 +155,16 @@
defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
- defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI) || \
- defined(CONFIG_USB_DWC2)
+ defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_MUSB_SUNXI) || \
+ defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC2)
int usb_lowlevel_init(int index, enum usb_init_type init, void **controller);
int usb_lowlevel_stop(int index);
+#ifdef CONFIG_MUSB_HOST
+void usb_reset_root_port(void);
+#else
+#define usb_reset_root_port()
+#endif
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len);
@@ -167,9 +173,9 @@
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, int interval);
-#ifdef CONFIG_USB_EHCI /* Only the ehci code has pollable int support */
+#if defined CONFIG_USB_EHCI || defined CONFIG_MUSB_HOST
struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe,
- int queuesize, int elementsize, void *buffer);
+ int queuesize, int elementsize, void *buffer, int interval);
int destroy_int_queue(struct usb_device *dev, struct int_queue *queue);
void *poll_int_queue(struct usb_device *dev, struct int_queue *queue);
#endif
diff --git a/include/virtex2.h b/include/virtex2.h
index 7b7825f..503df9a 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -11,8 +11,6 @@
#include <xilinx.h>
-extern struct xilinx_fpga_op virtex2_op;
-
/*
* Slave SelectMap Implementation function table.
*/
@@ -40,12 +38,19 @@
xilinx_wdata_fn wdata;
} xilinx_virtex2_slave_serial_fns;
+#if defined(CONFIG_FPGA_VIRTEX2)
+extern struct xilinx_fpga_op virtex2_op;
+# define FPGA_VIRTEX2_OPS &virtex2_op
+#else
+# define FPGA_VIRTEX2_OPS NULL
+#endif
+
/* Device Image Sizes (in bytes)
*********************************************************************/
-#define XILINX_XC2V40_SIZE (338208 / 8)
-#define XILINX_XC2V80_SIZE (597408 / 8)
-#define XILINX_XC2V250_SIZE (1591584 / 8)
-#define XILINX_XC2V500_SIZE (2557857 / 8)
+#define XILINX_XC2V40_SIZE (338208 / 8)
+#define XILINX_XC2V80_SIZE (597408 / 8)
+#define XILINX_XC2V250_SIZE (1591584 / 8)
+#define XILINX_XC2V500_SIZE (2557857 / 8)
#define XILINX_XC2V1000_SIZE (3749408 / 8)
#define XILINX_XC2V1500_SIZE (5166240 / 8)
#define XILINX_XC2V2000_SIZE (6808352 / 8)
@@ -58,39 +63,51 @@
/* Descriptor Macros
*********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
-{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
+ FPGA_VIRTEX2_OPS }
#endif /* _VIRTEX2_H_ */
diff --git a/include/vsc9953.h b/include/vsc9953.h
new file mode 100644
index 0000000..3d11b87
--- /dev/null
+++ b/include/vsc9953.h
@@ -0,0 +1,402 @@
+/*
+ * vsc9953.h
+ *
+ * Driver for the Vitesse VSC9953 L2 Switch
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef _VSC9953_H_
+#define _VSC9953_H_
+
+#include <config.h>
+#include <miiphy.h>
+#include <asm/types.h>
+#include <malloc.h>
+
+#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
+
+#define VSC9953_SYS_OFFSET 0x010000
+#define VSC9953_DEV_GMII_OFFSET 0x100000
+#define VSC9953_QSYS_OFFSET 0x200000
+#define VSC9953_ANA_OFFSET 0x280000
+#define VSC9953_DEVCPU_GCB 0x070000
+#define VSC9953_ES0 0x040000
+#define VSC9953_IS1 0x050000
+#define VSC9953_IS2 0x060000
+
+#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
+#define VSC9953_PHY_REGS_OFFST 0x0000AC
+
+#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001
+#define CONFIG_VSC9953_CORE_ENABLE 0x80
+#define CONFIG_VSC9953_MEM_ENABLE 0x40
+#define CONFIG_VSC9953_MEM_INIT 0x20
+
+#define CONFIG_VSC9953_PORT_ENA 0x00003a00
+#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011
+#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011
+#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515
+#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043
+#define CONFIG_VSC9953_CLOCK_CFG 0x00000001
+#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001
+#define CONFIG_VSC9953_PFC_FC 0x00000001
+#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000
+#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000
+#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000
+#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe
+#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
+#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000
+#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee
+
+#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff
+#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004
+#define VSC9953_MAX_PORTS 10
+#define VSC9953_PORT_CHECK(port) \
+ (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
+#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
+ ( \
+ (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
+ ) ? 0 : 1 \
+)
+
+#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
+
+#define MIIMIND_OPR_PEND 0x00000004
+
+struct vsc9953_mdio_info {
+ struct vsc9953_mii_mng *regs;
+ char *name;
+};
+
+/* VSC9953 ANA structure for T1040 U-boot*/
+
+struct vsc9953_ana_port {
+ u32 vlan_cfg;
+ u32 drop_cfg;
+ u32 qos_cfg;
+ u32 vcap_cfg;
+ u32 vcap_s1_key_cfg[3];
+ u32 vcap_s2_cfg;
+ u32 qos_pcp_dei_map_cfg[16];
+ u32 cpu_fwd_cfg;
+ u32 cpu_fwd_bpdu_cfg;
+ u32 cpu_fwd_garp_cfg;
+ u32 cpu_fwd_ccm_cfg;
+ u32 port_cfg;
+ u32 pol_cfg;
+ u32 reserved[34];
+};
+
+struct vsc9953_ana_pol {
+ u32 pol_pir_cfg;
+ u32 pol_cir_cfg;
+ u32 pol_mode_cfg;
+ u32 pol_pir_state;
+ u32 pol_cir_state;
+ u32 reserved1[3];
+};
+
+struct vsc9953_ana_ana_tables {
+ u32 entry_lim[11];
+ u32 an_moved;
+ u32 mach_data;
+ u32 macl_data;
+ u32 mac_access;
+ u32 mact_indx;
+ u32 vlan_access;
+ u32 vlan_tidx;
+};
+
+struct vsc9953_ana_ana {
+ u32 adv_learn;
+ u32 vlan_mask;
+ u32 anag_efil;
+ u32 an_events;
+ u32 storm_limit_burst;
+ u32 storm_limit_cfg[4];
+ u32 isolated_prts;
+ u32 community_ports;
+ u32 auto_age;
+ u32 mac_options;
+ u32 learn_disc;
+ u32 agen_ctrl;
+ u32 mirror_ports;
+ u32 emirror_ports;
+ u32 flooding;
+ u32 flooding_ipmc;
+ u32 sflow_cfg[11];
+ u32 port_mode[12];
+};
+
+struct vsc9953_ana_pgid {
+ u32 port_grp_id[91];
+};
+
+struct vsc9953_ana_pfc {
+ u32 pfc_cfg;
+ u32 reserved1[15];
+};
+
+struct vsc9953_ana_pol_misc {
+ u32 pol_flowc[10];
+ u32 reserved1[17];
+ u32 pol_hyst;
+};
+
+struct vsc9953_ana_common {
+ u32 aggr_cfg;
+ u32 cpuq_cfg;
+ u32 cpuq_8021_cfg;
+ u32 dscp_cfg;
+ u32 dscp_rewr_cfg;
+ u32 vcap_rng_type_cfg;
+ u32 vcap_rng_val_cfg;
+ u32 discard_cfg;
+ u32 fid_cfg;
+};
+
+struct vsc9953_analyzer {
+ struct vsc9953_ana_port port[11];
+ u32 reserved1[9536];
+ struct vsc9953_ana_pol pol[164];
+ struct vsc9953_ana_ana_tables ana_tables;
+ u32 reserved2[14];
+ struct vsc9953_ana_ana ana;
+ u32 reserved3[22];
+ struct vsc9953_ana_pgid port_id_tbl;
+ u32 reserved4[549];
+ struct vsc9953_ana_pfc pfc[10];
+ struct vsc9953_ana_pol_misc pol_misc;
+ u32 reserved5[196];
+ struct vsc9953_ana_common common;
+};
+/* END VSC9953 ANA structure for T1040 U-boot*/
+
+/* VSC9953 DEV_GMII structure for T1040 U-boot*/
+
+struct vsc9953_dev_gmii_port_mode {
+ u32 clock_cfg;
+ u32 port_misc;
+ u32 reserved1;
+ u32 eee_cfg;
+};
+
+struct vsc9953_dev_gmii_mac_cfg_status {
+ u32 mac_ena_cfg;
+ u32 mac_mode_cfg;
+ u32 mac_maxlen_cfg;
+ u32 mac_tags_cfg;
+ u32 mac_adv_chk_cfg;
+ u32 mac_ifg_cfg;
+ u32 mac_hdx_cfg;
+ u32 mac_fc_mac_low_cfg;
+ u32 mac_fc_mac_high_cfg;
+ u32 mac_sticky;
+};
+
+struct vsc9953_dev_gmii {
+ struct vsc9953_dev_gmii_port_mode port_mode;
+ struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
+};
+
+/* END VSC9953 DEV_GMII structure for T1040 U-boot*/
+
+/* VSC9953 QSYS structure for T1040 U-boot*/
+
+struct vsc9953_qsys_hsch {
+ u32 cir_cfg;
+ u32 reserved1;
+ u32 se_cfg;
+ u32 se_dwrr_cfg[8];
+ u32 cir_state;
+ u32 reserved2[20];
+};
+
+struct vsc9953_qsys_sys {
+ u32 port_mode[12];
+ u32 switch_port_mode[11];
+ u32 stat_cnt_cfg;
+ u32 eee_cfg[10];
+ u32 eee_thrs;
+ u32 igr_no_sharing;
+ u32 egr_no_sharing;
+ u32 sw_status[11];
+ u32 ext_cpu_cfg;
+ u32 cpu_group_map;
+ u32 reserved1[23];
+};
+
+struct vsc9953_qsys_qos_cfg {
+ u32 red_profile[16];
+ u32 res_qos_mode;
+};
+
+struct vsc9953_qsys_drop_cfg {
+ u32 egr_drop_mode;
+};
+
+struct vsc9953_qsys_mmgt {
+ u32 eq_cntrl;
+ u32 reserved1;
+};
+
+struct vsc9953_qsys_hsch_misc {
+ u32 hsch_misc_cfg;
+ u32 reserved1[546];
+};
+
+struct vsc9953_qsys_res_ctrl {
+ u32 res_cfg;
+ u32 res_stat;
+
+};
+
+struct vsc9953_qsys_reg {
+ struct vsc9953_qsys_hsch hsch[108];
+ struct vsc9953_qsys_sys sys;
+ struct vsc9953_qsys_qos_cfg qos_cfg;
+ struct vsc9953_qsys_drop_cfg drop_cfg;
+ struct vsc9953_qsys_mmgt mmgt;
+ struct vsc9953_qsys_hsch_misc hsch_misc;
+ struct vsc9953_qsys_res_ctrl res_ctrl[1024];
+};
+
+/* END VSC9953 QSYS structure for T1040 U-boot*/
+
+/* VSC9953 SYS structure for T1040 U-boot*/
+
+struct vsc9953_sys_stat {
+ u32 rx_cntrs[64];
+ u32 tx_cntrs[64];
+ u32 drop_cntrs[64];
+ u32 reserved1[6];
+};
+
+struct vsc9953_sys_sys {
+ u32 reset_cfg;
+ u32 reserved1;
+ u32 vlan_etype_cfg;
+ u32 port_mode[12];
+ u32 front_port_mode[10];
+ u32 frame_aging;
+ u32 stat_cfg;
+ u32 reserved2[50];
+};
+
+struct vsc9953_sys_pause_cfg {
+ u32 pause_cfg[11];
+ u32 pause_tot_cfg;
+ u32 tail_drop_level[11];
+ u32 tot_tail_drop_lvl;
+ u32 mac_fc_cfg[10];
+};
+
+struct vsc9953_sys_mmgt {
+ u16 free_cnt;
+};
+
+struct vsc9953_system_reg {
+ struct vsc9953_sys_stat stat;
+ struct vsc9953_sys_sys sys;
+ struct vsc9953_sys_pause_cfg pause_cfg;
+ struct vsc9953_sys_mmgt mmgt;
+};
+
+/* END VSC9953 SYS structure for T1040 U-boot*/
+
+
+/* VSC9953 DEVCPU_GCB structure for T1040 U-boot*/
+
+struct vsc9953_chip_regs {
+ u32 chipd_id;
+ u32 gpr;
+ u32 soft_rst;
+};
+
+struct vsc9953_gpio {
+ u32 gpio_out_set[10];
+ u32 gpio_out_clr[10];
+ u32 gpio_out[10];
+ u32 gpio_in[10];
+};
+
+struct vsc9953_mii_mng {
+ u32 miimstatus;
+ u32 reserved1;
+ u32 miimcmd;
+ u32 miimdata;
+ u32 miimcfg;
+ u32 miimscan_0;
+ u32 miimscan_1;
+ u32 miiscan_lst_rslts;
+ u32 miiscan_lst_rslts_valid;
+};
+
+struct vsc9953_mii_read_scan {
+ u32 mii_scan_results_sticky[2];
+};
+
+struct vsc9953_devcpu_gcb {
+ struct vsc9953_chip_regs chip_regs;
+ struct vsc9953_gpio gpio;
+ struct vsc9953_mii_mng mii_mng[2];
+ struct vsc9953_mii_read_scan mii_read_scan;
+};
+
+/* END VSC9953 DEVCPU_GCB structure for T1040 U-boot*/
+
+/* VSC9953 IS* structure for T1040 U-boot*/
+
+struct vsc9953_vcap_core_cfg {
+ u32 vcap_update_ctrl;
+ u32 vcap_mv_cfg;
+};
+
+struct vsc9953_vcap {
+struct vsc9953_vcap_core_cfg vcap_core_cfg;
+};
+
+/* END VSC9953 IS* structure for T1040 U-boot*/
+
+#define VSC9953_PORT_INFO_INITIALIZER(idx) \
+{ \
+ .enabled = 0, \
+ .phyaddr = 0, \
+ .index = idx, \
+ .phy_regs = NULL, \
+ .enet_if = PHY_INTERFACE_MODE_NONE, \
+ .bus = NULL, \
+ .phydev = NULL, \
+}
+
+/* Structure to describe a VSC9953 port */
+struct vsc9953_port_info {
+ u8 enabled;
+ u8 phyaddr;
+ int index;
+ void *phy_regs;
+ phy_interface_t enet_if;
+ struct mii_dev *bus;
+ struct phy_device *phydev;
+};
+
+/* Structure to describe a VSC9953 switch */
+struct vsc9953_info {
+ struct vsc9953_port_info port[VSC9953_MAX_PORTS];
+};
+
+void vsc9953_init(bd_t *bis);
+
+void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus);
+void vsc9953_port_info_set_phy_address(int port, int address);
+void vsc9953_port_enable(int port);
+void vsc9953_port_disable(int port);
+void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int);
+
+#endif /* _VSC9953_H_ */
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 8a9ec32..1d37a51 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -12,12 +12,18 @@
#include <xilinx.h>
+#if defined(CONFIG_FPGA_ZYNQPL)
extern struct xilinx_fpga_op zynq_op;
+# define FPGA_ZYNQPL_OPS &zynq_op
+#else
+# define FPGA_ZYNQPL_OPS NULL
+#endif
#define XILINX_ZYNQ_7010 0x2
#define XILINX_ZYNQ_7015 0x1b
#define XILINX_ZYNQ_7020 0x7
#define XILINX_ZYNQ_7030 0xc
+#define XILINX_ZYNQ_7035 0x12
#define XILINX_ZYNQ_7045 0x11
#define XILINX_ZYNQ_7100 0x16
@@ -26,26 +32,37 @@
#define XILINX_XC7Z015_SIZE 28085344/8
#define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8
+#define XILINX_XC7Z035_SIZE 106571232/8
#define XILINX_XC7Z045_SIZE 106571232/8
#define XILINX_XC7Z100_SIZE 139330784/8
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z010" }
#define XILINX_XC7Z015_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z015" }
#define XILINX_XC7Z020_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z020" }
#define XILINX_XC7Z030_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z030" }
+
+#define XILINX_XC7Z035_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z035" }
#define XILINX_XC7Z045_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z045" }
#define XILINX_XC7Z100_DESC(cookie) \
-{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
+ "7z100" }
#endif /* _ZYNQPL_H_ */
diff --git a/lib/bzip2/bzlib.c b/lib/bzip2/bzlib.c
index 5844e18..9262e40 100644
--- a/lib/bzip2/bzlib.c
+++ b/lib/bzip2/bzlib.c
@@ -1350,11 +1350,11 @@
strm.avail_out = *destLen;
ret = BZ2_bzDecompress ( &strm );
+ *destLen -= strm.avail_out;
if (ret == BZ_OK) goto output_overflow_or_eof;
if (ret != BZ_STREAM_END) goto errhandler;
/* normal termination */
- *destLen -= strm.avail_out;
BZ2_bzDecompressEnd ( &strm );
return BZ_OK;
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 745b390..487122e 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -126,6 +126,163 @@
return fdtdec_get_addr_size(blob, node, prop_name, NULL);
}
+#ifdef CONFIG_PCI
+int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
+ const char *prop_name, struct fdt_pci_addr *addr)
+{
+ const u32 *cell;
+ int len;
+ int ret = -ENOENT;
+
+ debug("%s: %s: ", __func__, prop_name);
+
+ /*
+ * If we follow the pci bus bindings strictly, we should check
+ * the value of the node's parent node's #address-cells and
+ * #size-cells. They need to be 3 and 2 accordingly. However,
+ * for simplicity we skip the check here.
+ */
+ cell = fdt_getprop(blob, node, prop_name, &len);
+ if (!cell)
+ goto fail;
+
+ if ((len % FDT_PCI_REG_SIZE) == 0) {
+ int num = len / FDT_PCI_REG_SIZE;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ debug("pci address #%d: %08lx %08lx %08lx\n", i,
+ (ulong)fdt_addr_to_cpu(cell[0]),
+ (ulong)fdt_addr_to_cpu(cell[1]),
+ (ulong)fdt_addr_to_cpu(cell[2]));
+ if ((fdt_addr_to_cpu(*cell) & type) == type) {
+ addr->phys_hi = fdt_addr_to_cpu(cell[0]);
+ addr->phys_mid = fdt_addr_to_cpu(cell[1]);
+ addr->phys_lo = fdt_addr_to_cpu(cell[2]);
+ break;
+ } else {
+ cell += (FDT_PCI_ADDR_CELLS +
+ FDT_PCI_SIZE_CELLS);
+ }
+ }
+
+ if (i == num)
+ goto fail;
+
+ return 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+fail:
+ debug("(not found)\n");
+ return ret;
+}
+
+int fdtdec_get_pci_vendev(const void *blob, int node, u16 *vendor, u16 *device)
+{
+ const char *list, *end;
+ int len;
+
+ list = fdt_getprop(blob, node, "compatible", &len);
+ if (!list)
+ return -ENOENT;
+
+ end = list + len;
+ while (list < end) {
+ char *s;
+
+ len = strlen(list);
+ if (len >= strlen("pciVVVV,DDDD")) {
+ s = strstr(list, "pci");
+
+ /*
+ * check if the string is something like pciVVVV,DDDD.RR
+ * or just pciVVVV,DDDD
+ */
+ if (s && s[7] == ',' &&
+ (s[12] == '.' || s[12] == 0)) {
+ s += 3;
+ *vendor = simple_strtol(s, NULL, 16);
+
+ s += 5;
+ *device = simple_strtol(s, NULL, 16);
+
+ return 0;
+ }
+ } else {
+ list += (len + 1);
+ }
+ }
+
+ return -ENOENT;
+}
+
+int fdtdec_get_pci_bdf(const void *blob, int node,
+ struct fdt_pci_addr *addr, pci_dev_t *bdf)
+{
+ u16 dt_vendor, dt_device, vendor, device;
+ int ret;
+
+ /* get vendor id & device id from the compatible string */
+ ret = fdtdec_get_pci_vendev(blob, node, &dt_vendor, &dt_device);
+ if (ret)
+ return ret;
+
+ /* extract the bdf from fdt_pci_addr */
+ *bdf = addr->phys_hi & 0xffff00;
+
+ /* read vendor id & device id based on bdf */
+ pci_read_config_word(*bdf, PCI_VENDOR_ID, &vendor);
+ pci_read_config_word(*bdf, PCI_DEVICE_ID, &device);
+
+ /*
+ * Note there are two places in the device tree to fully describe
+ * a pci device: one is via compatible string with a format of
+ * "pciVVVV,DDDD" and the other one is the bdf numbers encoded in
+ * the device node's reg address property. We read the vendor id
+ * and device id based on bdf and compare the values with the
+ * "VVVV,DDDD". If they are the same, then we are good to use bdf
+ * to read device's bar. But if they are different, we have to rely
+ * on the vendor id and device id extracted from the compatible
+ * string and locate the real bdf by pci_find_device(). This is
+ * because normally we may only know device's device number and
+ * function number when writing device tree. The bus number is
+ * dynamically assigned during the pci enumeration process.
+ */
+ if ((dt_vendor != vendor) || (dt_device != device)) {
+ *bdf = pci_find_device(dt_vendor, dt_device, 0);
+ if (*bdf == -1)
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+int fdtdec_get_pci_bar32(const void *blob, int node,
+ struct fdt_pci_addr *addr, u32 *bar)
+{
+ pci_dev_t bdf;
+ int barnum;
+ int ret;
+
+ /* get pci devices's bdf */
+ ret = fdtdec_get_pci_bdf(blob, node, addr, &bdf);
+ if (ret)
+ return ret;
+
+ /* extract the bar number from fdt_pci_addr */
+ barnum = addr->phys_hi & 0xff;
+ if ((barnum < PCI_BASE_ADDRESS_0) || (barnum > PCI_CARDBUS_CIS))
+ return -EINVAL;
+
+ barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
+ *bar = pci_read_bar32(pci_bus_to_hose(PCI_BUS(bdf)), bdf, barnum);
+
+ return 0;
+}
+#endif
+
uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
uint64_t default_val)
{
@@ -795,20 +952,6 @@
return fdt_get_resource(fdt, node, property, index, res);
}
-int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf)
-{
- const fdt32_t *prop;
- int len;
-
- prop = fdt_getprop(fdt, node, "reg", &len);
- if (!prop)
- return len;
-
- *bdf = fdt32_to_cpu(*prop) & 0xffffff;
-
- return 0;
-}
-
int fdtdec_decode_memory_region(const void *blob, int config_node,
const char *mem_type, const char *suffix,
fdt_addr_t *basep, fdt_size_t *sizep)
diff --git a/lib/gunzip.c b/lib/gunzip.c
index 35abfb3..f469fcb 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -73,6 +73,7 @@
int stoponerr, int offset)
{
z_stream s;
+ int err = 0;
int r;
s.zalloc = gzalloc;
@@ -92,13 +93,13 @@
if (stoponerr == 1 && r != Z_STREAM_END &&
(s.avail_out == 0 || r != Z_BUF_ERROR)) {
printf("Error: inflate() returned %d\n", r);
- inflateEnd(&s);
- return -1;
+ err = -1;
+ break;
}
s.avail_in = *lenp - offset - (int)(s.next_out - (unsigned char*)dst);
} while (r == Z_BUF_ERROR);
*lenp = s.next_out - (unsigned char *) dst;
inflateEnd(&s);
- return 0;
+ return err;
}
diff --git a/lib/lzma/LzmaTools.c b/lib/lzma/LzmaTools.c
index cfc7cb0..f88629b 100644
--- a/lib/lzma/LzmaTools.c
+++ b/lib/lzma/LzmaTools.c
@@ -102,7 +102,7 @@
return SZ_ERROR_OUTPUT_EOF;
/* Decompress */
- outProcessed = outSizeFull;
+ outProcessed = min(outSizeFull, *uncompressedSize);
WATCHDOG_RESET();
@@ -112,7 +112,7 @@
inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc);
*uncompressedSize = outProcessed;
- debug("LZMA: Uncompresed ................ 0x%zx\n", outProcessed);
+ debug("LZMA: Uncompressed ............... 0x%zx\n", outProcessed);
if (res != SZ_OK) {
return res;
diff --git a/lib/lzo/lzo1x_decompress.c b/lib/lzo/lzo1x_decompress.c
index 35f3793..ebdf10b 100644
--- a/lib/lzo/lzo1x_decompress.c
+++ b/lib/lzo/lzo1x_decompress.c
@@ -102,8 +102,10 @@
tmp = dlen;
r = lzo1x_decompress_safe((u8 *) src, slen, dst, &tmp);
- if (r != LZO_E_OK)
+ if (r != LZO_E_OK) {
+ *dst_len = dst - start;
return r;
+ }
if (dlen != tmp)
return LZO_E_ERROR;
diff --git a/scripts/fill_scrapyard.py b/scripts/fill_scrapyard.py
new file mode 100755
index 0000000..9a94354
--- /dev/null
+++ b/scripts/fill_scrapyard.py
@@ -0,0 +1,166 @@
+#!/usr/bin/env python2
+#
+# Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+"""
+Fill the "Commit" and "Removed" fields of doc/README.scrapyard
+
+The file doc/README.scrapyard is used to keep track of removed boards.
+
+When we remove support for boards, we are supposed to add entries to
+doc/README.scrapyard leaving "Commit" and "Removed" fields blank.
+
+The "Commit" field is the commit hash in which the board was removed
+and the "Removed" is the date at which the board was removed. Those
+two are known only after the board removal patch was applied, thus they
+need to be filled in later.
+
+This effectively means that the person who removes other boards is
+supposed to fill in the blank fields before adding new entries to
+doc/README.scrapyard.
+
+That is a really tedious task that should be automated.
+This script fills the blank fields of doc/README.scrapyard for you!
+
+Usage:
+
+The "Commit" and "Removed" fields must be "-". The other fields should
+have already been filled in by a former commit.
+
+Run
+ scripts/fill_scrapyard.py
+"""
+
+import os
+import subprocess
+import sys
+import tempfile
+
+DOC='doc/README.scrapyard'
+
+def get_last_modify_commit(file, line_num):
+ """Get the commit that last modified the given line.
+
+ This function runs "git blame" against the given line of the given
+ file and returns the commit hash that last modified it.
+
+ Arguments:
+ file: the file to be git-blame'd.
+ line_num: the line number to be git-blame'd. This line number
+ starts from 1, not 0.
+
+ Returns:
+ Commit hash that last modified the line. The number of digits is
+ long enough to form a unique commit.
+ """
+ result = subprocess.check_output(['git', 'blame', '-L',
+ '%d,%d' % (line_num, line_num), file])
+ commit = result.split()[0]
+
+ if commit[0] == '^':
+ sys.exit('%s: line %d: ' % (file, line_num) +
+ 'this line was modified before the beginning of git history')
+
+ if commit == '0' * len(commit):
+ sys.exit('%s: line %d: locally modified\n' % (file, line_num) +
+ 'Please run this script in a clean repository.')
+
+ return commit
+
+def get_committer_date(commit):
+ """Get the committer date of the given commit.
+
+ This function returns the date when the given commit was applied.
+
+ Arguments:
+ commit: commit-ish object.
+
+ Returns:
+ The committer date of the given commit in the form YY-MM-DD.
+ """
+ committer_date = subprocess.check_output(['git', 'show', '-s',
+ '--format=%ci', commit])
+ return committer_date.split()[0]
+
+def move_to_topdir():
+ """Change directory to the top of the git repository.
+
+ Or, exit with an error message if called out of a git repository.
+ """
+ try:
+ toplevel = subprocess.check_output(['git', 'rev-parse',
+ '--show-toplevel'])
+ except subprocess.CalledProcessError:
+ sys.exit('Please run in a git repository.')
+
+ # strip '\n'
+ toplevel = toplevel.rstrip()
+
+ # Change the current working directory to the toplevel of the respository
+ # for our easier life.
+ os.chdir(toplevel)
+
+class TmpFile:
+
+ """Useful class to handle a temporary file.
+
+ tempfile.mkstemp() is often used to create a unique temporary file,
+ but what is inconvenient is that the caller is responsible for
+ deleting the file when done with it.
+
+ Even when the caller errors out on the way, the temporary file must
+ be deleted somehow. The idea here is that we delete the file in
+ the destructor of this class because the destructor is always
+ invoked when the instance of the class is freed.
+ """
+
+ def __init__(self):
+ """Constructor - create a temporary file"""
+ fd, self.filename = tempfile.mkstemp()
+ self.file = os.fdopen(fd, 'w')
+
+ def __del__(self):
+ """Destructor - delete the temporary file"""
+ try:
+ os.remove(self.filename)
+ except:
+ pass
+
+def main():
+ move_to_topdir()
+
+ line_num = 1
+
+ tmpfile = TmpFile()
+ for line in open(DOC):
+ tmp = line.split(None, 5)
+ modified = False
+
+ if len(tmp) >= 5:
+ # fill "Commit" field
+ if tmp[3] == '-':
+ tmp[3] = get_last_modify_commit(DOC, line_num)
+ modified = True
+ # fill "Removed" field
+ if tmp[4] == '-':
+ tmp[4] = get_committer_date(tmp[3])
+ if modified:
+ line = tmp[0].ljust(17)
+ line += tmp[1].ljust(12)
+ line += tmp[2].ljust(15)
+ line += tmp[3].ljust(12)
+ line += tmp[4].ljust(12)
+ if len(tmp) >= 6:
+ line += tmp[5]
+ line = line.rstrip() + '\n'
+
+ tmpfile.file.write(line)
+ line_num += 1
+
+ os.rename(tmpfile.filename, DOC)
+
+if __name__ == '__main__':
+ main()
diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh
index 70f3a5d..366e8fa 100755
--- a/scripts/multiconfig.sh
+++ b/scripts/multiconfig.sh
@@ -168,7 +168,7 @@
echo "$progname: Cannot felconfig a non-sunxi or non-SPL platform" >&2
exit 1
fi
- sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y/g' \
+ sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y\nCONFIG_UART0_PORT_F=n/g' \
.config spl/.config
}
diff --git a/test/compression.c b/test/compression.c
index 139ea01..ea2e4ad 100644
--- a/test/compression.c
+++ b/test/compression.c
@@ -7,8 +7,10 @@
#define DEBUG
#include <common.h>
+#include <bootm.h>
#include <command.h>
#include <malloc.h>
+#include <asm/io.h>
#include <u-boot/zlib.h>
#include <bzlib.h>
@@ -313,9 +315,8 @@
return ret;
}
-
-static int do_test_compression(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+static int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
{
int err = 0;
@@ -324,12 +325,94 @@
err += run_test("lzma", compress_using_lzma, uncompress_using_lzma);
err += run_test("lzo", compress_using_lzo, uncompress_using_lzo);
- printf("test_compression %s\n", err == 0 ? "ok" : "FAILED");
+ printf("ut_compression %s\n", err == 0 ? "ok" : "FAILED");
return err;
}
+static int compress_using_none(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ /* Here we just copy */
+ memcpy(out, in, in_size);
+ *out_size = in_size;
+
+ return 0;
+}
+
+/**
+ * run_bootm_test() - Run tests on the bootm decopmression function
+ *
+ * @comp_type: Compression type to test
+ * @compress: Our function to compress data
+ * @return 0 if OK, non-zero on failure
+ */
+static int run_bootm_test(int comp_type, mutate_func compress)
+{
+ ulong compress_size = 1024;
+ void *compress_buff;
+ int unc_len;
+ int err = 0;
+ const ulong image_start = 0;
+ const ulong load_addr = 0x1000;
+ ulong load_end;
+
+ printf("Testing: %s\n", genimg_get_comp_name(comp_type));
+ compress_buff = map_sysmem(image_start, 0);
+ unc_len = strlen(plain);
+ compress((void *)plain, unc_len, compress_buff, compress_size,
+ &compress_size);
+ err = bootm_decomp_image(comp_type, load_addr, image_start,
+ IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
+ compress_buff, compress_size, unc_len,
+ &load_end);
+ if (err)
+ return err;
+ err = bootm_decomp_image(comp_type, load_addr, image_start,
+ IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
+ compress_buff, compress_size, unc_len - 1,
+ &load_end);
+ if (!err)
+ return -EINVAL;
+
+ /* We can't detect corruption when not decompressing */
+ if (comp_type == IH_COMP_NONE)
+ return 0;
+ memset(compress_buff + compress_size / 2, '\x49',
+ compress_size / 2);
+ err = bootm_decomp_image(comp_type, load_addr, image_start,
+ IH_TYPE_KERNEL, map_sysmem(load_addr, 0),
+ compress_buff, compress_size, 0x10000,
+ &load_end);
+ if (!err)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int do_ut_image_decomp(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int err = 0;
+
+ err = run_bootm_test(IH_COMP_GZIP, compress_using_gzip);
+ err |= run_bootm_test(IH_COMP_BZIP2, compress_using_bzip2);
+ err |= run_bootm_test(IH_COMP_LZMA, compress_using_lzma);
+ err |= run_bootm_test(IH_COMP_LZO, compress_using_lzo);
+ err |= run_bootm_test(IH_COMP_NONE, compress_using_none);
+
+ printf("ut_image_decomp %s\n", err == 0 ? "ok" : "FAILED");
+
+ return 0;
+}
+
U_BOOT_CMD(
- test_compression, 5, 1, do_test_compression,
+ ut_compression, 5, 1, do_ut_compression,
"Basic test of compressors: gzip bzip2 lzma lzo", ""
);
+
+U_BOOT_CMD(
+ ut_image_decomp, 5, 1, do_ut_image_decomp,
+ "Basic test of bootm decompression", ""
+);
diff --git a/test/dm/sf.c b/test/dm/sf.c
index 57dd134..08098a1 100644
--- a/test/dm/sf.c
+++ b/test/dm/sf.c
@@ -29,7 +29,7 @@
* benefit is worth the extra complexity.
*/
ut_asserteq(0, run_command_list(
- "sb save hostfs - spi.bin 0 200000;"
+ "sb save hostfs - 0 spi.bin 200000;"
"sf probe;"
"sf test 0 10000", -1, 0));
/*
diff --git a/test/image/test-fit.py b/test/image/test-fit.py
index b065fcb..e9e756a 100755
--- a/test/image/test-fit.py
+++ b/test/image/test-fit.py
@@ -20,6 +20,9 @@
import sys
import tempfile
+# Enable printing of all U-Boot output
+DEBUG = True
+
# The 'command' library in patman is convenient for running commands
base_path = os.path.dirname(sys.argv[0])
patman = os.path.join(base_path, '../../tools/patman')
@@ -97,12 +100,16 @@
fdt addr %(fit_addr)x
bootm start %(fit_addr)x
bootm loados
-sb save hostfs 0 %(kernel_out)s %(kernel_addr)x %(kernel_size)x
-sb save hostfs 0 %(fdt_out)s %(fdt_addr)x %(fdt_size)x
-sb save hostfs 0 %(ramdisk_out)s %(ramdisk_addr)x %(ramdisk_size)x
+sb save hostfs 0 %(kernel_addr)x %(kernel_out)s %(kernel_size)x
+sb save hostfs 0 %(fdt_addr)x %(fdt_out)s %(fdt_size)x
+sb save hostfs 0 %(ramdisk_addr)x %(ramdisk_out)s %(ramdisk_size)x
reset
'''
+def debug_stdout(stdout):
+ if DEBUG:
+ print stdout
+
def make_fname(leaf):
"""Make a temporary filename
@@ -328,6 +335,7 @@
# We could perhaps reduce duplication with some loss of readability
set_test('Kernel load')
stdout = command.Output(u_boot, '-d', control_dtb, '-c', cmd)
+ debug_stdout(stdout)
if read_file(kernel) != read_file(kernel_out):
fail('Kernel not loaded', stdout)
if read_file(control_dtb) == read_file(fdt_out):
@@ -352,6 +360,7 @@
params['fdt_load'] = 'load = <%#x>;' % params['fdt_addr']
fit = make_fit(mkimage, params)
stdout = command.Output(u_boot, '-d', control_dtb, '-c', cmd)
+ debug_stdout(stdout)
if read_file(kernel) != read_file(kernel_out):
fail('Kernel not loaded', stdout)
if read_file(control_dtb) != read_file(fdt_out):
@@ -365,6 +374,7 @@
params['ramdisk_load'] = 'load = <%#x>;' % params['ramdisk_addr']
fit = make_fit(mkimage, params)
stdout = command.Output(u_boot, '-d', control_dtb, '-c', cmd)
+ debug_stdout(stdout)
if read_file(ramdisk) != read_file(ramdisk_out):
fail('Ramdisk not loaded', stdout)
diff --git a/tools/buildman/README b/tools/buildman/README
index 0f8ea20..cf7bf5c 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -141,8 +141,8 @@
$ git checkout -b my-branch origin/master
$ # Add some commits to the branch, reading for testing
-2. Create ~/.buildman to tell buildman where to find tool chains. As an
-example:
+2. Create ~/.buildman to tell buildman where to find tool chains (see 'The
+.buildman file' later for details). As an example:
# Buildman settings file
@@ -171,7 +171,16 @@
to build x86 commits.
-2. Check the available toolchains
+3. Make sure you have the require Python pre-requisites
+
+Buildman uses multiprocessing, Queue, shutil, StringIO, ConfigParser and
+urllib2. These should normally be available, but if you get an error like
+this then you will need to obtain those modules:
+
+ ImportError: No module named multiprocessing
+
+
+4. Check the available toolchains
Run this check to make sure that you have a toolchain for every architecture.
@@ -301,6 +310,47 @@
be used (c88 and c99). This is a feature.
+5. Install new toolchains if needed
+
+You can download toolchains and update the [toolchain] section of the
+settings file to find them.
+
+To make this easier, buildman can automatically download and install
+toolchains from kernel.org. First list the available architectures:
+
+$ ./tools/buildman/buildman sandbox --fetch-arch list
+Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/
+Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.2/
+Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1/
+Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.2.4/
+Available architectures: alpha am33_2.0 arm avr32 bfin cris crisv32 frv h8300
+hppa hppa64 i386 ia64 m32r m68k mips mips64 or32 powerpc powerpc64 s390x sh4
+sparc sparc64 tilegx x86_64 xtensa
+
+Then pick one and download it:
+
+$ ./tools/buildman/buildman sandbox --fetch-arch or32
+Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/
+Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.2/
+Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1/
+Downloading: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.5.1//x86_64-gcc-4.5.1-nolibc_or32-linux.tar.xz
+Unpacking to: /home/sjg/.buildman-toolchains
+Testing
+ - looking in '/home/sjg/.buildman-toolchains/gcc-4.5.1-nolibc/or32-linux/.'
+ - looking in '/home/sjg/.buildman-toolchains/gcc-4.5.1-nolibc/or32-linux/bin'
+ - found '/home/sjg/.buildman-toolchains/gcc-4.5.1-nolibc/or32-linux/bin/or32-linux-gcc'
+Tool chain test: OK
+
+Buildman should now be set up to use your new toolchain.
+
+At the time of writing, U-Boot has these architectures:
+
+ arc, arm, avr32, blackfin, m68k, microblaze, mips, nds32, nios2, openrisc
+ powerpc, sandbox, sh, sparc, x86
+
+Of these, only arc, microblaze and nds32 are not available at kernel.org..
+
+
How to run it
=============
@@ -310,8 +360,9 @@
$ ./tools/buildman/buildman -b <branch> -n
If it can't detect the upstream branch, try checking out the branch, and
-doing something like 'git branch --set-upstream <branch> upstream/master'
-or something similar.
+doing something like 'git branch --set-upstream-to upstream/master'
+or something similar. Buildman will try to guess a suitable upstream branch
+if it can't find one (you will see a message like" Guessing upstream as ...).
As an example:
@@ -665,28 +716,62 @@
increases, and vice versa.
-Providing 'make' flags
-======================
+The .buildman file
+==================
-U-Boot's build system supports a few flags (such as BUILD_TAG) which affect
-the build product. These flags can be specified in the buildman settings
-file. They can also be useful when building U-Boot against other open source
-software.
+The .buildman file provides information about the available toolchains and
+also allows build flags to be passed to 'make'. It consists of several
+sections, with the section name in square brackets. Within each section are
+a set of (tag, value) pairs.
-[make-flags]
-at91-boards=ENABLE_AT91_TEST=1
-snapper9260=${at91-boards} BUILD_TAG=442
-snapper9g45=${at91-boards} BUILD_TAG=443
+'[toolchain]' section
-This will use 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9260
-and 'make ENABLE_AT91_TEST=1 BUILD_TAG=443' for snapper9g45. A special
-variable ${target} is available to access the target name (snapper9260 and
-snapper9g20 in this case). Variables are resolved recursively. Note that
-variables can only contain the characters A-Z, a-z, 0-9, hyphen (-) and
-underscore (_).
+ This lists the available toolchains. The tag here doesn't matter, but
+ make sure it is unique. The value is the path to the toolchain. Buildman
+ will look in that path for a file ending in 'gcc'. It will then execute
+ it to check that it is a C compiler, passing only the --version flag to
+ it. If the return code is 0, buildman assumes that it is a valid C
+ compiler. It uses the first part of the name as the architecture and
+ strips off the last part when setting the CROSS_COMPILE environment
+ variable (parts are delimited with a hyphen).
-It is expected that any variables added are dealt with in U-Boot's
-config.mk file and documented in the README.
+ For example powerpc-linux-gcc will be noted as a toolchain for 'powerpc'
+ and CROSS_COMPILE will be set to powerpc-linux- when using it.
+
+'[toolchain-alias]' section
+
+ This converts toolchain architecture names to U-Boot names. For example,
+ if an x86 toolchains is called i386-linux-gcc it will not normally be
+ used for architecture 'x86'. Adding 'x86: i386 x86_64' to this section
+ will tell buildman that the i386 and x86_64 toolchains can be used for
+ the x86 architecture.
+
+'[make-flags]' section
+
+ U-Boot's build system supports a few flags (such as BUILD_TAG) which
+ affect the build product. These flags can be specified in the buildman
+ settings file. They can also be useful when building U-Boot against other
+ open source software.
+
+ [make-flags]
+ at91-boards=ENABLE_AT91_TEST=1
+ snapper9260=${at91-boards} BUILD_TAG=442
+ snapper9g45=${at91-boards} BUILD_TAG=443
+
+ This will use 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9260
+ and 'make ENABLE_AT91_TEST=1 BUILD_TAG=443' for snapper9g45. A special
+ variable ${target} is available to access the target name (snapper9260
+ and snapper9g20 in this case). Variables are resolved recursively. Note
+ that variables can only contain the characters A-Z, a-z, 0-9, hyphen (-)
+ and underscore (_).
+
+ It is expected that any variables added are dealt with in U-Boot's
+ config.mk file and documented in the README.
+
+ Note that you can pass ad-hoc options to the build using environment
+ variables, for example:
+
+ SOME_OPTION=1234 ./tools/buildman/buildman my_board
Quick Sanity Check
@@ -698,6 +783,17 @@
enabled automatically). Use -e to see errors/warnings as well.
+Building Ranges
+===============
+
+You can build a range of commits by specifying a range instead of a branch
+when using the -b flag. For example:
+
+ upstream/master..us-buildman
+
+will build commits in us-buildman that are not in upstream/master.
+
+
Other options
=============
diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py
index fdd875b..b361469 100644
--- a/tools/buildman/bsettings.py
+++ b/tools/buildman/bsettings.py
@@ -40,7 +40,16 @@
try:
return settings.items(section)
except ConfigParser.NoSectionError as e:
- print e
return []
except:
raise
+
+def SetItem(section, tag, value):
+ """Set an item and write it back to the settings file"""
+ global settings
+ global config_fname
+
+ settings.set(section, tag, value)
+ if config_fname is not None:
+ with open(config_fname, 'w') as fd:
+ settings.write(fd)
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 7002034..1b0ad99 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -174,7 +174,8 @@
self.func_sizes = func_sizes
def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs,
- gnu_make='make', checkout=True, show_unknown=True, step=1):
+ gnu_make='make', checkout=True, show_unknown=True, step=1,
+ no_subdirs=False, full_path=False, verbose_build=False):
"""Create a new Builder object
Args:
@@ -188,6 +189,11 @@
This is used for testing.
show_unknown: Show unknown boards (those not built) in summary
step: 1 to process every commit, n to process every nth commit
+ no_subdirs: Don't create subdirectories when building current
+ source for a single board
+ full_path: Return the full path in CROSS_COMPILE and don't set
+ PATH
+ verbose_build: Run build with V=1 and don't use 'make -s'
"""
self.toolchains = toolchains
self.base_dir = base_dir
@@ -213,6 +219,9 @@
self._step = step
self.in_tree = False
self._error_lines = 0
+ self.no_subdirs = no_subdirs
+ self.full_path = full_path
+ self.verbose_build = verbose_build
self.col = terminal.Color()
@@ -392,15 +401,17 @@
Args:
commit_upto: Commit number to use (0..self.count-1)
"""
+ commit_dir = None
if self.commits:
commit = self.commits[commit_upto]
subject = commit.subject.translate(trans_valid_chars)
commit_dir = ('%02d_of_%02d_g%s_%s' % (commit_upto + 1,
self.commit_count, commit.hash, subject[:20]))
- else:
+ elif not self.no_subdirs:
commit_dir = 'current'
- output_dir = os.path.join(self.base_dir, commit_dir)
- return output_dir
+ if not commit_dir:
+ return self.base_dir
+ return os.path.join(self.base_dir, commit_dir)
def GetBuildDir(self, commit_upto, target):
"""Get the name of the build directory for a commit number
@@ -1115,6 +1126,8 @@
create. Having left over directories is confusing when the user wants
to check the output manually.
"""
+ if not self.commits:
+ return
dir_list = []
for commit_upto in range(self.commit_count):
dir_list.append(self._GetOutputDir(commit_upto))
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index bc4541c..efb62f1 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -177,7 +177,7 @@
commit = 'current'
# Set up the environment and command line
- env = self.toolchain.MakeEnvironment()
+ env = self.toolchain.MakeEnvironment(self.builder.full_path)
Mkdir(out_dir)
args = []
cwd = work_dir
@@ -197,7 +197,8 @@
src_dir = os.getcwd()
else:
args.append('O=build')
- args.append('-s')
+ if not self.builder.verbose_build:
+ args.append('-s')
if self.builder.num_jobs is not None:
args.extend(['-j', str(self.builder.num_jobs)])
config_args = ['%s_defconfig' % brd.target]
@@ -284,7 +285,7 @@
print >>fd, 'path', result.toolchain.path
# Write out the image and function size information and an objdump
- env = result.toolchain.MakeEnvironment()
+ env = result.toolchain.MakeEnvironment(self.builder.full_path)
lines = []
for fname in ['u-boot', 'spl/u-boot-spl']:
cmd = ['%snm' % self.toolchain.cross, '--size-sort', fname]
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 27d3c70..e8a6dad 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -36,6 +36,10 @@
parser.add_option('-F', '--force-build-failures', dest='force_build_failures',
action='store_true', default=False,
help='Force build of previously-failed build')
+ parser.add_option('--fetch-arch', type='string',
+ help="Fetch a toolchain for architecture FETCH_ARCH ('list' to list)."
+ ' You can also fetch several toolchains separate by comma, or'
+ " 'all' to download all")
parser.add_option('-g', '--git', type='string',
help='Git repo containing branch to build', default='.')
parser.add_option('-G', '--config-file', type='string',
@@ -55,11 +59,15 @@
help='List available tool chains')
parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run',
default=False, help="Do a dry run (describe actions, but do nothing)")
+ parser.add_option('-N', '--no-subdirs', action='store_true', dest='no_subdirs',
+ default=False, help="Don't create subdirectories when building current source for a single board")
parser.add_option('-o', '--output-dir', type='string',
dest='output_dir', default='..',
help='Directory where all builds happen and buildman has its workspace (default is ../)')
parser.add_option('-Q', '--quick', action='store_true',
default=False, help='Do a rough build, with limited warning resolution')
+ parser.add_option('-p', '--full-path', action='store_true',
+ default=False, help="Use full toolchain path in CROSS_COMPILE")
parser.add_option('-s', '--summary', action='store_true',
default=False, help='Show a build summary')
parser.add_option('-S', '--show-sizes', action='store_true',
@@ -74,6 +82,8 @@
default=False, help='Show boards with unknown build result')
parser.add_option('-v', '--verbose', action='store_true',
default=False, help='Show build results while the build progresses')
+ parser.add_option('-V', '--verbose-build', action='store_true',
+ default=False, help='Run make with V=1, showing all output')
parser.add_option('-x', '--exclude', dest='exclude',
type='string', action='append',
help='Specify a list of boards to exclude, separated by comma')
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 2c3ba8b..720b978 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -118,21 +118,45 @@
print
return 0
+ if options.fetch_arch:
+ if options.fetch_arch == 'list':
+ sorted_list = toolchains.ListArchs()
+ print 'Available architectures: %s\n' % ' '.join(sorted_list)
+ return 0
+ else:
+ fetch_arch = options.fetch_arch
+ if fetch_arch == 'all':
+ fetch_arch = ','.join(toolchains.ListArchs())
+ print 'Downloading toolchains: %s\n' % fetch_arch
+ for arch in fetch_arch.split(','):
+ ret = toolchains.FetchAndInstall(arch)
+ if ret:
+ return ret
+ return 0
+
# Work out how many commits to build. We want to build everything on the
# branch. We also build the upstream commit as a control so we can see
# problems introduced by the first commit on the branch.
col = terminal.Color()
count = options.count
+ has_range = options.branch and '..' in options.branch
if count == -1:
if not options.branch:
count = 1
else:
- count = gitutil.CountCommitsInBranch(options.git_dir,
- options.branch)
+ if has_range:
+ count, msg = gitutil.CountCommitsInRange(options.git_dir,
+ options.branch)
+ else:
+ count, msg = gitutil.CountCommitsInBranch(options.git_dir,
+ options.branch)
if count is None:
- str = ("Branch '%s' not found or has no upstream" %
- options.branch)
- sys.exit(col.Color(col.RED, str))
+ sys.exit(col.Color(col.RED, msg))
+ elif count == 0:
+ sys.exit(col.Color(col.RED, "Range '%s' has no commits" %
+ options.branch))
+ if msg:
+ print col.Color(col.YELLOW, msg)
count += 1 # Build upstream commit also
if not count:
@@ -172,8 +196,11 @@
# to overwrite earlier ones by setting allow_overwrite=True
if options.branch:
if count == -1:
- range_expr = gitutil.GetRangeInBranch(options.git_dir,
- options.branch)
+ if has_range:
+ range_expr = options.branch
+ else:
+ range_expr = gitutil.GetRangeInBranch(options.git_dir,
+ options.branch)
upstream_commit = gitutil.GetUpstream(options.git_dir,
options.branch)
series = patchstream.GetMetaDataForList(upstream_commit,
@@ -188,6 +215,8 @@
else:
series = None
options.verbose = True
+ if not options.summary:
+ options.show_errors = True
# By default we have one thread per CPU. But if there are not enough jobs
# we can have fewer threads and use a high '-j' value for make.
@@ -205,17 +234,22 @@
if not gnu_make:
sys.exit('GNU Make not found')
- # Create a new builder with the selected options
+ # Create a new builder with the selected options.
+ output_dir = options.output_dir
if options.branch:
dirname = options.branch.replace('/', '_')
- else:
- dirname = 'current'
- output_dir = os.path.join(options.output_dir, dirname)
- if clean_dir and os.path.exists(output_dir):
+ # As a special case allow the board directory to be placed in the
+ # output directory itself rather than any subdirectory.
+ if not options.no_subdirs:
+ output_dir = os.path.join(options.output_dir, dirname)
+ if (clean_dir and output_dir != options.output_dir and
+ os.path.exists(output_dir)):
shutil.rmtree(output_dir)
builder = Builder(toolchains, output_dir, options.git_dir,
options.threads, options.jobs, gnu_make=gnu_make, checkout=True,
- show_unknown=options.show_unknown, step=options.step)
+ show_unknown=options.show_unknown, step=options.step,
+ no_subdirs=options.no_subdirs, full_path=options.full_path,
+ verbose_build=options.verbose_build)
builder.force_config_on_failure = not options.quick
if make_func:
builder.do_make = make_func
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index a2a85ac..c0ad5d0 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -24,6 +24,16 @@
import terminal
import toolchain
+settings_data = '''
+# Buildman settings file
+
+[toolchain]
+main: /usr/sbin
+
+[toolchain-alias]
+x86: i386 x86_64
+'''
+
errors = [
'''main.c: In function 'main_loop':
main.c:260:6: warning: unused variable 'joe' [-Wunused-variable]
@@ -83,6 +93,8 @@
['Active', 'sandbox', 'sandbox', '', 'Tester', 'Sandbox board', 'board4', ''],
]
+BASE_DIR = 'base'
+
class Options:
"""Class that holds build options"""
pass
@@ -111,8 +123,11 @@
self.boards.AddBoard(board.Board(*brd))
self.boards.SelectBoards([])
+ # Add some test settings
+ bsettings.Setup(None)
+ bsettings.AddFile(settings_data)
+
# Set up the toolchains
- bsettings.Setup()
self.toolchains = toolchain.Toolchains()
self.toolchains.Add('arm-linux-gcc', test=False)
self.toolchains.Add('sparc-linux-gcc', test=False)
@@ -341,6 +356,64 @@
self.assertEqual(self.boards.SelectBoards(['sandbox sandbox',
'sandbox']),
{'all': 1, 'sandbox': 1})
+ def CheckDirs(self, build, dirname):
+ self.assertEqual('base%s' % dirname, build._GetOutputDir(1))
+ self.assertEqual('base%s/fred' % dirname,
+ build.GetBuildDir(1, 'fred'))
+ self.assertEqual('base%s/fred/done' % dirname,
+ build.GetDoneFile(1, 'fred'))
+ self.assertEqual('base%s/fred/u-boot.sizes' % dirname,
+ build.GetFuncSizesFile(1, 'fred', 'u-boot'))
+ self.assertEqual('base%s/fred/u-boot.objdump' % dirname,
+ build.GetObjdumpFile(1, 'fred', 'u-boot'))
+ self.assertEqual('base%s/fred/err' % dirname,
+ build.GetErrFile(1, 'fred'))
+
+ def testOutputDir(self):
+ build = builder.Builder(self.toolchains, BASE_DIR, None, 1, 2,
+ checkout=False, show_unknown=False)
+ build.commits = self.commits
+ build.commit_count = len(self.commits)
+ subject = self.commits[1].subject.translate(builder.trans_valid_chars)
+ dirname ='/%02d_of_%02d_g%s_%s' % (2, build.commit_count, commits[1][0],
+ subject[:20])
+ self.CheckDirs(build, dirname)
+
+ def testOutputDirCurrent(self):
+ build = builder.Builder(self.toolchains, BASE_DIR, None, 1, 2,
+ checkout=False, show_unknown=False)
+ build.commits = None
+ build.commit_count = 0
+ self.CheckDirs(build, '/current')
+
+ def testOutputDirNoSubdirs(self):
+ build = builder.Builder(self.toolchains, BASE_DIR, None, 1, 2,
+ checkout=False, show_unknown=False,
+ no_subdirs=True)
+ build.commits = None
+ build.commit_count = 0
+ self.CheckDirs(build, '')
+
+ def testToolchainAliases(self):
+ self.assertTrue(self.toolchains.Select('arm') != None)
+ with self.assertRaises(ValueError):
+ self.toolchains.Select('no-arch')
+ with self.assertRaises(ValueError):
+ self.toolchains.Select('x86')
+
+ self.toolchains = toolchain.Toolchains()
+ self.toolchains.Add('x86_64-linux-gcc', test=False)
+ self.assertTrue(self.toolchains.Select('x86') != None)
+
+ self.toolchains = toolchain.Toolchains()
+ self.toolchains.Add('i386-linux-gcc', test=False)
+ self.assertTrue(self.toolchains.Select('x86') != None)
+
+ def testToolchainDownload(self):
+ """Test that we can download toolchains"""
+ self.assertEqual('https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/x86_64-gcc-4.6.3-nolibc_arm-unknown-linux-gnueabi.tar.xz',
+ self.toolchains.LocateArchUrl('arm'))
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 27dc318..d4c5d4a 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -5,11 +5,42 @@
import re
import glob
+from HTMLParser import HTMLParser
import os
+import sys
+import tempfile
+import urllib2
import bsettings
import command
+# Simple class to collect links from a page
+class MyHTMLParser(HTMLParser):
+ def __init__(self, arch):
+ """Create a new parser
+
+ After the parser runs, self.links will be set to a list of the links
+ to .xz archives found in the page, and self.arch_link will be set to
+ the one for the given architecture (or None if not found).
+
+ Args:
+ arch: Architecture to search for
+ """
+ HTMLParser.__init__(self)
+ self.arch_link = None
+ self.links = []
+ self._match = '_%s-' % arch
+
+ def handle_starttag(self, tag, attrs):
+ if tag == 'a':
+ for tag, value in attrs:
+ if tag == 'href':
+ if value and value.endswith('.xz'):
+ self.links.append(value)
+ if self._match in value:
+ self.arch_link = value
+
+
class Toolchain:
"""A single toolchain
@@ -20,7 +51,6 @@
arch: Architecture of toolchain as determined from the first
component of the filename. E.g. arm-linux-gcc becomes arm
"""
-
def __init__(self, fname, test, verbose=False):
"""Create a new toolchain object.
@@ -30,11 +60,18 @@
"""
self.gcc = fname
self.path = os.path.dirname(fname)
- self.cross = os.path.basename(fname)[:-3]
+
+ # Find the CROSS_COMPILE prefix to use for U-Boot. For example,
+ # 'arm-linux-gnueabihf-gcc' turns into 'arm-linux-gnueabihf-'.
+ basename = os.path.basename(fname)
+ pos = basename.rfind('-')
+ self.cross = basename[:pos + 1] if pos != -1 else ''
+
+ # The architecture is the first part of the name
pos = self.cross.find('-')
self.arch = self.cross[:pos] if pos != -1 else 'sandbox'
- env = self.MakeEnvironment()
+ env = self.MakeEnvironment(False)
# As a basic sanity check, run the C compiler with --version
cmd = [fname, '--version']
@@ -74,15 +111,23 @@
return prio
return prio
- def MakeEnvironment(self):
+ def MakeEnvironment(self, full_path):
"""Returns an environment for using the toolchain.
- Thie takes the current environment, adds CROSS_COMPILE and
- augments PATH so that the toolchain will operate correctly.
+ Thie takes the current environment and adds CROSS_COMPILE so that
+ the tool chain will operate correctly.
+
+ Args:
+ full_path: Return the full path in CROSS_COMPILE and don't set
+ PATH
"""
env = dict(os.environ)
- env['CROSS_COMPILE'] = self.cross
- env['PATH'] += (':' + self.path)
+ if full_path:
+ env['CROSS_COMPILE'] = os.path.join(self.path, self.cross)
+ else:
+ env['CROSS_COMPILE'] = self.cross
+ env['PATH'] = self.path + ':' + env['PATH']
+
return env
@@ -101,18 +146,29 @@
self.paths = []
self._make_flags = dict(bsettings.GetItems('make-flags'))
- def GetSettings(self):
+ def GetPathList(self):
+ """Get a list of available toolchain paths
+
+ Returns:
+ List of strings, each a path to a toolchain mentioned in the
+ [toolchain] section of the settings file.
+ """
toolchains = bsettings.GetItems('toolchain')
if not toolchains:
print ("Warning: No tool chains - please add a [toolchain] section"
" to your buildman config file %s. See README for details" %
bsettings.config_fname)
+ paths = []
for name, value in toolchains:
if '*' in value:
- self.paths += glob.glob(value)
+ paths += glob.glob(value)
else:
- self.paths.append(value)
+ paths.append(value)
+ return paths
+
+ def GetSettings(self):
+ self.paths += self.GetPathList()
def Add(self, fname, test=True, verbose=False):
"""Add a toolchain to our list
@@ -132,6 +188,24 @@
if add_it:
self.toolchains[toolchain.arch] = toolchain
+ def ScanPath(self, path, verbose):
+ """Scan a path for a valid toolchain
+
+ Args:
+ path: Path to scan
+ verbose: True to print out progress information
+ Returns:
+ Filename of C compiler if found, else None
+ """
+ for subdir in ['.', 'bin', 'usr/bin']:
+ dirname = os.path.join(path, subdir)
+ if verbose: print " - looking in '%s'" % dirname
+ for fname in glob.glob(dirname + '/*gcc'):
+ if verbose: print " - found '%s'" % fname
+ return fname
+ return None
+
+
def Scan(self, verbose):
"""Scan for available toolchains and select the best for each arch.
@@ -145,12 +219,9 @@
if verbose: print 'Scanning for tool chains'
for path in self.paths:
if verbose: print " - scanning path '%s'" % path
- for subdir in ['.', 'bin', 'usr/bin']:
- dirname = os.path.join(path, subdir)
- if verbose: print " - looking in '%s'" % dirname
- for fname in glob.glob(dirname + '/*gcc'):
- if verbose: print " - found '%s'" % fname
- self.Add(fname, True, verbose)
+ fname = self.ScanPath(path, verbose)
+ if fname:
+ self.Add(fname, True, verbose)
def List(self):
"""List out the selected toolchains for each architecture"""
@@ -170,9 +241,11 @@
returns:
toolchain object, or None if none found
"""
- for name, value in bsettings.GetItems('toolchain-alias'):
- if arch == name:
- arch = value
+ for tag, value in bsettings.GetItems('toolchain-alias'):
+ if arch == tag:
+ for alias in value.split():
+ if alias in self.toolchains:
+ return self.toolchains[alias]
if not arch in self.toolchains:
raise ValueError, ("No tool chain found for arch '%s'" % arch)
@@ -247,3 +320,160 @@
else:
i += 1
return args
+
+ def LocateArchUrl(self, fetch_arch):
+ """Find a toolchain available online
+
+ Look in standard places for available toolchains. At present the
+ only standard place is at kernel.org.
+
+ Args:
+ arch: Architecture to look for, or 'list' for all
+ Returns:
+ If fetch_arch is 'list', a tuple:
+ Machine architecture (e.g. x86_64)
+ List of toolchains
+ else
+ URL containing this toolchain, if avaialble, else None
+ """
+ arch = command.OutputOneLine('uname', '-m')
+ base = 'https://www.kernel.org/pub/tools/crosstool/files/bin'
+ versions = ['4.6.3', '4.6.2', '4.5.1', '4.2.4']
+ links = []
+ for version in versions:
+ url = '%s/%s/%s/' % (base, arch, version)
+ print 'Checking: %s' % url
+ response = urllib2.urlopen(url)
+ html = response.read()
+ parser = MyHTMLParser(fetch_arch)
+ parser.feed(html)
+ if fetch_arch == 'list':
+ links += parser.links
+ elif parser.arch_link:
+ return url + parser.arch_link
+ if fetch_arch == 'list':
+ return arch, links
+ return None
+
+ def Download(self, url):
+ """Download a file to a temporary directory
+
+ Args:
+ url: URL to download
+ Returns:
+ Tuple:
+ Temporary directory name
+ Full path to the downloaded archive file in that directory,
+ or None if there was an error while downloading
+ """
+ print "Downloading: %s" % url
+ leaf = url.split('/')[-1]
+ tmpdir = tempfile.mkdtemp('.buildman')
+ response = urllib2.urlopen(url)
+ fname = os.path.join(tmpdir, leaf)
+ fd = open(fname, 'wb')
+ meta = response.info()
+ size = int(meta.getheaders("Content-Length")[0])
+ done = 0
+ block_size = 1 << 16
+ status = ''
+
+ # Read the file in chunks and show progress as we go
+ while True:
+ buffer = response.read(block_size)
+ if not buffer:
+ print chr(8) * (len(status) + 1), '\r',
+ break
+
+ done += len(buffer)
+ fd.write(buffer)
+ status = r"%10d MiB [%3d%%]" % (done / 1024 / 1024,
+ done * 100 / size)
+ status = status + chr(8) * (len(status) + 1)
+ print status,
+ sys.stdout.flush()
+ fd.close()
+ if done != size:
+ print 'Error, failed to download'
+ os.remove(fname)
+ fname = None
+ return tmpdir, fname
+
+ def Unpack(self, fname, dest):
+ """Unpack a tar file
+
+ Args:
+ fname: Filename to unpack
+ dest: Destination directory
+ Returns:
+ Directory name of the first entry in the archive, without the
+ trailing /
+ """
+ stdout = command.Output('tar', 'xvfJ', fname, '-C', dest)
+ return stdout.splitlines()[0][:-1]
+
+ def TestSettingsHasPath(self, path):
+ """Check if builmand will find this toolchain
+
+ Returns:
+ True if the path is in settings, False if not
+ """
+ paths = self.GetPathList()
+ return path in paths
+
+ def ListArchs(self):
+ """List architectures with available toolchains to download"""
+ host_arch, archives = self.LocateArchUrl('list')
+ re_arch = re.compile('[-a-z0-9.]*_([^-]*)-.*')
+ arch_set = set()
+ for archive in archives:
+ # Remove the host architecture from the start
+ arch = re_arch.match(archive[len(host_arch):])
+ if arch:
+ arch_set.add(arch.group(1))
+ return sorted(arch_set)
+
+ def FetchAndInstall(self, arch):
+ """Fetch and install a new toolchain
+
+ arch:
+ Architecture to fetch, or 'list' to list
+ """
+ # Fist get the URL for this architecture
+ url = self.LocateArchUrl(arch)
+ if not url:
+ print ("Cannot find toolchain for arch '%s' - use 'list' to list" %
+ arch)
+ return 2
+ home = os.environ['HOME']
+ dest = os.path.join(home, '.buildman-toolchains')
+ if not os.path.exists(dest):
+ os.mkdir(dest)
+
+ # Download the tar file for this toolchain and unpack it
+ tmpdir, tarfile = self.Download(url)
+ if not tarfile:
+ return 1
+ print 'Unpacking to: %s' % dest,
+ sys.stdout.flush()
+ path = self.Unpack(tarfile, dest)
+ os.remove(tarfile)
+ os.rmdir(tmpdir)
+ print
+
+ # Check that the toolchain works
+ print 'Testing'
+ dirpath = os.path.join(dest, path)
+ compiler_fname = self.ScanPath(dirpath, True)
+ if not compiler_fname:
+ print 'Could not locate C compiler - fetch failed.'
+ return 1
+ toolchain = Toolchain(compiler_fname, True, True)
+
+ # Make sure that it will be found by buildman
+ if not self.TestSettingsHasPath(dirpath):
+ print ("Adding 'download' to config file '%s'" %
+ bsettings.config_fname)
+ tools_dir = os.path.dirname(dirpath)
+ bsettings.SetItem('toolchain', 'download', '%s/*' % tools_dir)
+ return 0
diff --git a/tools/ifdtool.c b/tools/ifdtool.c
index fe8366b..590ccc9 100644
--- a/tools/ifdtool.c
+++ b/tools/ifdtool.c
@@ -788,9 +788,9 @@
fdt_strerror(data_size));
return -ENOENT;
}
- offset = ucode_ptr - uboot->addr;
+ offset = (uint32_t)(ucode_ptr + size);
ptr = (void *)image + offset;
- ptr[0] = uboot->addr + (data - image);
+ ptr[0] = (data - image) - size;
ptr[1] = data_size;
debug("Wrote microcode pointer at %x: addr=%x, size=%x\n",
ucode_ptr, ptr[0], ptr[1]);
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index b68df5d..cc5a55a 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -61,6 +61,52 @@
patch_count = int(stdout)
return patch_count
+def NameRevision(commit_hash):
+ """Gets the revision name for a commit
+
+ Args:
+ commit_hash: Commit hash to look up
+
+ Return:
+ Name of revision, if any, else None
+ """
+ pipe = ['git', 'name-rev', commit_hash]
+ stdout = command.RunPipe([pipe], capture=True, oneline=True).stdout
+
+ # We expect a commit, a space, then a revision name
+ name = stdout.split(' ')[1].strip()
+ return name
+
+def GuessUpstream(git_dir, branch):
+ """Tries to guess the upstream for a branch
+
+ This lists out top commits on a branch and tries to find a suitable
+ upstream. It does this by looking for the first commit where
+ 'git name-rev' returns a plain branch name, with no ! or ^ modifiers.
+
+ Args:
+ git_dir: Git directory containing repo
+ branch: Name of branch
+
+ Returns:
+ Tuple:
+ Name of upstream branch (e.g. 'upstream/master') or None if none
+ Warning/error message, or None if none
+ """
+ pipe = [LogCmd(branch, git_dir=git_dir, oneline=True, count=100)]
+ result = command.RunPipe(pipe, capture=True, capture_stderr=True,
+ raise_on_error=False)
+ if result.return_code:
+ return None, "Branch '%s' not found" % branch
+ for line in result.stdout.splitlines()[1:]:
+ commit_hash = line.split(' ')[0]
+ name = NameRevision(commit_hash)
+ if '~' not in name and '^' not in name:
+ if name.startswith('remotes/'):
+ name = name[8:]
+ return name, "Guessing upstream as '%s'" % name
+ return None, "Cannot find a suitable upstream for branch '%s'" % branch
+
def GetUpstream(git_dir, branch):
"""Returns the name of the upstream for a branch
@@ -69,7 +115,9 @@
branch: Name of branch
Returns:
- Name of upstream branch (e.g. 'upstream/master') or None if none
+ Tuple:
+ Name of upstream branch (e.g. 'upstream/master') or None if none
+ Warning/error message, or None if none
"""
try:
remote = command.OutputOneLine('git', '--git-dir', git_dir, 'config',
@@ -77,13 +125,14 @@
merge = command.OutputOneLine('git', '--git-dir', git_dir, 'config',
'branch.%s.merge' % branch)
except:
- return None
+ upstream, msg = GuessUpstream(git_dir, branch)
+ return upstream, msg
if remote == '.':
return merge
elif remote and merge:
leaf = merge.split('/')[-1]
- return '%s/%s' % (remote, leaf)
+ return '%s/%s' % (remote, leaf), None
else:
raise ValueError, ("Cannot determine upstream branch for branch "
"'%s' remote='%s', merge='%s'" % (branch, remote, merge))
@@ -99,10 +148,29 @@
Expression in the form 'upstream..branch' which can be used to
access the commits. If the branch does not exist, returns None.
"""
- upstream = GetUpstream(git_dir, branch)
+ upstream, msg = GetUpstream(git_dir, branch)
if not upstream:
- return None
- return '%s%s..%s' % (upstream, '~' if include_upstream else '', branch)
+ return None, msg
+ rstr = '%s%s..%s' % (upstream, '~' if include_upstream else '', branch)
+ return rstr, msg
+
+def CountCommitsInRange(git_dir, range_expr):
+ """Returns the number of commits in the given range.
+
+ Args:
+ git_dir: Directory containing git repo
+ range_expr: Range to check
+ Return:
+ Number of patches that exist in the supplied rangem or None if none
+ were found
+ """
+ pipe = [LogCmd(range_expr, git_dir=git_dir, oneline=True)]
+ result = command.RunPipe(pipe, capture=True, capture_stderr=True,
+ raise_on_error=False)
+ if result.return_code:
+ return None, "Range '%s' not found or is invalid" % range_expr
+ patch_count = len(result.stdout.splitlines())
+ return patch_count, None
def CountCommitsInBranch(git_dir, branch, include_upstream=False):
"""Returns the number of commits in the given branch.
@@ -114,14 +182,10 @@
Number of patches that exist on top of the branch, or None if the
branch does not exist.
"""
- range_expr = GetRangeInBranch(git_dir, branch, include_upstream)
+ range_expr, msg = GetRangeInBranch(git_dir, branch, include_upstream)
if not range_expr:
- return None
- pipe = [LogCmd(range_expr, git_dir=git_dir, oneline=True),
- ['wc', '-l']]
- result = command.RunPipe(pipe, capture=True, oneline=True)
- patch_count = int(result.stdout)
- return patch_count
+ return None, msg
+ return CountCommitsInRange(git_dir, range_expr)
def CountCommits(commit_range):
"""Returns the number of commits in the given range.