qca: ipq6018: Adding support for IPQ6018
Added config, dts and initial board support code for ipq6018
Change-Id: I8cdc6d43f936179733c2c27e2b52dcf3477a892e
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
diff --git a/include/common.h b/include/common.h
index 64c82ce..1e74c7e 100644
--- a/include/common.h
+++ b/include/common.h
@@ -35,6 +35,9 @@
#elif defined(CONFIG_IPQ806X)
#include <../board/qca/arm/ipq806x/ipq806x.h>
+#elif defined(CONFIG_IPQ6018)
+#include <../board/qca/arm/ipq6018/ipq6018.h>
+
#elif defined(CONFIG_IPQ_RUMI)
#include <../board/qca/arm/ipq807x/ipq807x.h>
#endif
@@ -403,7 +406,7 @@
* Return -1 if variable does not exist (default to true)
*/
int getenv_yesno(const char *var);
-#if defined(CONFIG_IPQ40XX_ENV) || defined(CONFIG_IPQ807X_ENV) || defined(CONFIG_IPQ806X_ENV)
+#if defined(CONFIG_IPQ40XX_ENV) || defined(CONFIG_IPQ807X_ENV) || defined(CONFIG_IPQ806X_ENV) || defined(CONFIG_IPQ6018_ENV)
extern int (*saveenv)(void);
#else
int saveenv (void);
diff --git a/include/configs/ipq6018.h b/include/configs/ipq6018.h
new file mode 100644
index 0000000..f3a42a0
--- /dev/null
+++ b/include/configs/ipq6018.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _IPQ6018_H
+#define _IPQ6018_H
+
+#ifndef DO_DEPS_ONLY
+#include <generated/asm-offsets.h>
+#endif
+
+#define CONFIG_IPQ6018
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#define CONFIG_IPQ6018_UART
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000
+
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (256 << 10))
+
+#define CONFIG_ENV_IS_NOWHERE 1
+/*
+ * Size of malloc() pool
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */
+
+/*
+
+ svc_sp --> --------------
+ irq_sp --> | |
+ fiq_sp --> | |
+ bd --> | |
+ gd --> | |
+ pgt --> | |
+ malloc --> | |
+ text_base --> |------------|
+*/
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\
+ CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\
+ GENERATED_BD_INFO_SIZE)
+
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define TLMM_BASE 0x01000000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x4A900000
+#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20))
+
+#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE
+#define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE
+#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100)
+
+#define CONFIG_OF_COMBINE 1
+
+#define CONFIG_QCA_SMEM_BASE 0x4AB00000
+
+#define CONFIG_IPQ_FDT_HIGH 0x4A400000
+#define CONFIG_IPQ_NO_MACS 6
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+/*
+ * IPQ_TFTP_MIN_ADDR: Starting address of Linux HLOS region.
+ * CONFIG_TZ_END_ADDR: Ending address of Trust Zone and starting
+ * address of WLAN Area.
+ * TFTP file can only be written in Linux HLOS region and WLAN AREA.
+ */
+#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20))
+#define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21))
+#define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size)
+
+#ifndef __ASSEMBLY__
+#include <compiler.h>
+extern loff_t board_env_offset;
+extern loff_t board_env_range;
+extern loff_t board_env_size;
+#endif
+
+#define CONFIG_IPQ6018_ENV 1
+#define CONFIG_ENV_OFFSET board_env_offset
+#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX
+#define CONFIG_ENV_RANGE board_env_range
+#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (1024 << 10))
+
+#define CONFIG_ENV_IS_IN_NAND 1
+
+/*
+ * NAND Flash Configs
+ */
+
+/* CONFIG_QPIC_NAND: QPIC NAND in BAM mode
+ * CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode.
+ * BAM is enabled by default.
+ */
+#define CONFIG_QPIC_NAND
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_YAFFS
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * Expose SPI driver as a pseudo NAND driver to make use
+ * of U-Boot's MTD framework.
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \
+ CONFIG_IPQ_MAX_SPI_DEVICE
+
+#define CONFIG_IPQ_MAX_NAND_DEVICE 1
+#define CONFIG_IPQ_MAX_SPI_DEVICE 1
+
+#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
+#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
+
+#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX
+#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
+
+#define QCA_SPI_NOR_DEVICE "spi0.0"
+#define CONFIG_QUP_SPI_USE_DMA 1
+
+/*
+ * U-Boot Env Configs
+ */
+#define CONFIG_OF_LIBFDT 1
+
+/* NSS firmware loaded using bootm */
+#define CONFIG_BOOTCOMMAND "bootm"
+#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8"
+#define QCA_ROOT_FS_PART_NAME "rootfs"
+
+#define CONFIG_BOOTDELAY 2
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define NUM_ALT_PARTITION 16
+
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+
+#define CONFIG_CMD_BOOTZ
+
+/*
+ * Below Configs need to be updated after enabling reset_crashdump
+ * Included now to avoid build failure
+ */
+#define SET_MAGIC 0x1
+#define CLEAR_MAGIC 0x0
+#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9
+#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10
+#define SCM_CMD_TZ_PSHOLD 0x15
+/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
+ * Cache flush and invalidation based on L1 cache, so the cache line
+ * size is configured to 64 */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+/*#define CONFIG_SYS_DCACHE_OFF*/
+
+/* Enabling this flag will report any L2 errors.
+ * By default we are disabling it */
+/*#define CONFIG_IPQ_REPORT_L2ERR*/
+
+#endif /* _IPQ6018_H */
diff --git a/include/dt-bindings/qcom/gpio-ipq6018.h b/include/dt-bindings/qcom/gpio-ipq6018.h
new file mode 100644
index 0000000..0e5db3b
--- /dev/null
+++ b/include/dt-bindings/qcom/gpio-ipq6018.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_IPQ6018_GPIO_H__
+#define __DT_BINDINGS_IPQ6018_GPIO_H__
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+/* GPIO TLMM: Output value */
+#define GPIO_OUT_LOW 0
+#define GPIO_OUT_HIGH 1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_OE_DISABLE 0
+#define GPIO_OE_ENABLE 1
+
+/* GPIO VM */
+#define GPIO_VM_ENABLE 1
+#define GPIO_VM_DISABLE 0
+
+/* GPIO OD */
+#define GPIO_OD_ENABLE 1
+#define GPIO_OD_DISABLE 0
+
+/* GPIO PULLUP RES */
+#define GPIO_PULL_RES0 0
+#define GPIO_PULL_RES1 1
+#define GPIO_PULL_RES2 2
+#define GPIO_PULL_RES3 3
+
+#endif