Merge "ipq6018: Skip uboot relocation and setup CP15 barrier"
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 45b86f7..bb7b4fd 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -48,7 +48,7 @@
msr cpsr,r0
/* Setup CP15 barrier */
-#if defined (CONFIG_ARCH_IPQ807x) || defined (CONFIG_ARCH_IPQ806x)
+#if defined (CONFIG_ARCH_IPQ807x) || defined (CONFIG_ARCH_IPQ806x) || defined (CONFIG_ARCH_IPQ6018)
mrc p15, 0, r0, c1, c0, 0 @Read SCTLR to r0
orr r0, r0, #0x20 @set the cp15 barrier enable bit
mcr p15, 0, r0, c1, c0, 0 @write back to SCTLR
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 2a11530..0f7f8e2 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -62,7 +62,7 @@
mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
}
-#if defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ807x)
+#if defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ6018)
#define UBOOT_CACHE_SETUP 0x100e
#define GEN_CACHE_SETUP 0x101e
diff --git a/common/board_f.c b/common/board_f.c
index a5042f5..e48b92b 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -1062,7 +1062,7 @@
gd->flags = boot_flags;
gd->have_console = 0;
-#if defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ40xx)
+#if defined(CONFIG_ARCH_IPQ807x) || defined(CONFIG_ARCH_IPQ40xx) || defined(CONFIG_ARCH_IPQ6018)
gd->flags |= GD_FLG_SKIP_RELOC;
#endif