tree 5305b0d6ff370d753de1a217d08cd33efec0c765
parent f9f6686ff8ad3cbc860a51aa2b6b6def4188f15b
author SRICHARAN R <r.sricharan@ti.com> 1382007938 +0530
committer Tom Rini <trini@ti.com> 1383335760 -0400

ARM: OMAP5: DDR3: Change io settings

The change from 0x64656465 to 0x64646464 is to remove the weak pull
enabled on DQS, nDQS lines. This pulls the differential signals in the
same direction which is not intended. So disabling the weak pulls improves
signal integrity.

On the uEVM there are 4 DDR3 devices.  The VREF for 2 of the devices is powered by
the OMAP's VREF_CA_OUT pins.  The VREF on the other 2 devices is powered by the OMAP's
VREF_DQ_OUT pins.  So the net effect here is that only half of the DDR3 devices were being
supplied a VREF!  This was clearly a mistake.  The second change improves the robustness of
the interface and was specifically seen to cure corruption observed at high temperatures
on some boards.

With the above two changes better memory stability was observed with extended
temperature ranges around 100C.

Signed-off-by: Sricharan R <r.sricharan@ti.com>