| commit | 4442f45b0e1cbad35aa22d4cad22b90a57e3f32d | [log] [tgz] |
|---|---|---|
| author | Peter Tyser <ptyser@xes-inc.com> | Mon Oct 27 16:42:00 2008 -0500 |
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | Mon Oct 27 16:45:43 2008 -0500 |
| tree | 30016ac1c44a431c4356dd17a3de4cd274d1a472 | |
| parent | cd4251624205cb97104f6e32679dc7754934f711 [diff] |
85xx: Update MPC85xx_PORDEVSR_IO_SEL mask The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx processors have a 3-bit wide IO_SEL field but have the most significant bit is wired to 0 so this change should not affect them. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>