Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx
diff --git a/MAINTAINERS b/MAINTAINERS
index 14075af..7820375 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -897,6 +897,10 @@
omap3_overo ARM ARMV7 (OMAP3xx SoC)
+Leo Sartre <lsartre@adeneo-embedded.com>
+
+ cgtqmx6qeval i.MX6Q
+
Jens Scharsig <esw@bus-elektronik.de>
eb_cpux9k2 ARM920T (AT91RM9200 SoC)
@@ -969,6 +973,10 @@
SFFSDR ARM926EJS
+Lokesh Vutla <lokeshvutla@ti.com>
+
+ dra7xx_evm ARM ARMV7 (DRA7xx Soc)
+
Matt Waddel <matt.waddel@linaro.org>
vexpress_ca9x4 ARM ARMV7 (Quad Core)
@@ -1025,10 +1033,6 @@
jadecpu ARM926EJS (MB86R01 SoC)
zmx25 ARM926EJS (imx25 SoC)
-Richard Woodruff <r-woodruff2@ti.com>
-
- omap2420h4 ARM1136EJS
-
Josh Wu <josh.wu@atmel.com>
at91sam9n12ek ARM926EJS (AT91SAM9N12 SoC)
@@ -1066,6 +1070,14 @@
nitrogen6s i.MX6S 512MB
nitrogen6s1g i.MX6S 1GB
+Alison Wang <b18965@freescale.com>
+
+ vf610twr VF610
+
+Sergey Yanovich <ynvich@gmail.com>
+
+ lp8x4x xscale/pxa
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/Makefile b/Makefile
index ef154aa..fdaddb9 100644
--- a/Makefile
+++ b/Makefile
@@ -22,9 +22,9 @@
#
VERSION = 2013
-PATCHLEVEL = 04
+PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
@@ -341,7 +341,7 @@
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
@@ -743,6 +743,13 @@
$(MAKE) -C $@ all
endif # config.mk
+# ARM relocations should all be R_ARM_RELATIVE.
+checkarmreloc: $(obj)u-boot
+ @if test "R_ARM_RELATIVE" != \
+ "`readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \
+ then echo "$< contains relocations other than \
+ R_ARM_RELATIVE"; false; fi
+
$(VERSION_FILE):
@mkdir -p $(dir $(VERSION_FILE))
@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
diff --git a/README b/README
index 33bda8c..137e8cb 100644
--- a/README
+++ b/README
@@ -413,11 +413,22 @@
See Freescale App Note 4493 for more information about
this erratum.
+ CONFIG_A003399_NOR_WORKAROUND
+ Enables a workaround for IFC erratum A003399. It is only
+ requred during NOR boot.
+
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
+ CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
+ This value denotes start offset of M2 memory
+ which is directly connected to the DSP core.
+
+ CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+ This value denotes start offset of DSP CCSR space.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
@@ -1261,6 +1272,9 @@
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
txfilltuning field in the EHCI controller on reset.
+ CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
+ interval for usb hub power-on delay.(minimum 100msec)
+
- USB Device:
Define the below if you wish to use the USB console.
Once firmware is rebuilt from a serial console issue the
@@ -2506,6 +2520,11 @@
Define this option to include a destructive SPI flash
test ('sf test').
+ CONFIG_SPI_FLASH_BAR Ban/Extended Addr Reg
+
+ Define this option to use the Bank addr/Extended addr
+ support on SPI flashes which has size > 16Mbytes.
+
- SystemACE Support:
CONFIG_SYSTEMACE
@@ -3019,6 +3038,14 @@
CONFIG_SPL_LIBGENERIC_SUPPORT
Support for lib/libgeneric.o in SPL binary
+ CONFIG_SPL_ENV_SUPPORT
+ Support for the environment operating in SPL binary
+
+ CONFIG_SPL_NET_SUPPORT
+ Support for the net/libnet.o in SPL binary.
+ It conflicts with SPL env from storage medium specified by
+ CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
+
CONFIG_SPL_PAD_TO
Image offset to which the SPL should be padded before appending
the SPL payload. By default, this is defined as
@@ -3645,6 +3672,57 @@
You will probably want to define these to avoid a really noisy system
when storing the env in UBI.
+- CONFIG_ENV_IS_IN_MMC:
+
+ Define this if you have an MMC device which you want to use for the
+ environment.
+
+ - CONFIG_SYS_MMC_ENV_DEV:
+
+ Specifies which MMC device the environment is stored in.
+
+ - CONFIG_SYS_MMC_ENV_PART (optional):
+
+ Specifies which MMC partition the environment is stored in. If not
+ set, defaults to partition 0, the user area. Common values might be
+ 1 (first MMC boot partition), 2 (second MMC boot partition).
+
+ - CONFIG_ENV_OFFSET:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the offset and size of the environment
+ area within the specified MMC device.
+
+ If offset is positive (the usual case), it is treated as relative to
+ the start of the MMC partition. If offset is negative, it is treated
+ as relative to the end of the MMC partition. This can be useful if
+ your board may be fitted with different MMC devices, which have
+ different sizes for the MMC partitions, and you always want the
+ environment placed at the very end of the partition, to leave the
+ maximum possible space before it, to store other data.
+
+ These two values are in units of bytes, but must be aligned to an
+ MMC sector boundary.
+
+ - CONFIG_ENV_OFFSET_REDUND (optional):
+
+ Specifies a second storage area, of CONFIG_ENV_SIZE size, used to
+ hold a redundant copy of the environment data. This provides a
+ valid backup copy in case the other copy is corrupted, e.g. due
+ to a power failure during a "saveenv" operation.
+
+ This value may also be positive or negative; this is handled in the
+ same way as CONFIG_ENV_OFFSET.
+
+ This value is also in units of bytes, but must also be aligned to
+ an MMC sector boundary.
+
+ - CONFIG_ENV_SIZE_REDUND (optional):
+
+ This value need not be set, even when CONFIG_ENV_OFFSET_REDUND is
+ set. If this value is set, it must be set to the same value as
+ CONFIG_ENV_SIZE.
+
- CONFIG_SYS_SPI_INIT_OFFSET
Defines offset to the initial SPI buffer area in DPRAM. The
@@ -3910,6 +3988,9 @@
- CONFIG_SRIO2:
Board has SRIO 2 port available
+- CONFIG_SRIO_PCIE_BOOT_MASTER
+ Board can support master function for Boot from SRIO and PCIE
+
- CONFIG_SYS_SRIOn_MEM_VIRT:
Virtual Address of SRIO port 'n' memory region
@@ -4020,6 +4101,11 @@
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
+- CONFIG_SYS_MPC85XX_NO_RESETVEC
+ Only for 85xx systems. If this variable is specified, the section
+ .resetvec is not kept and the section .bootpg is placed in the
+ previous 4k of the .text section.
+
- CONFIG_ARCH_MAP_SYSMEM
Generally U-Boot (and in particular the md command) uses
effective address. It is therefore not necessary to regard
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index dc64160..e80e1ed 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -109,3 +109,8 @@
PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
endif
endif
+
+# check that only R_ARM_RELATIVE relocations are generated
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-y += checkarmreloc
+endif
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index edf249d..a7e0c28 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -142,24 +142,6 @@
orr r0,r0,#0xd3
msr cpsr,r0
-#ifdef CONFIG_OMAP2420H4
- /* Copy vectors to mask ROM indirect addr */
- adr r0, _start /* r0 <- current position of code */
- add r0, r0, #4 /* skip reset vector */
- mov r2, #64 /* r2 <- size to copy */
- add r2, r0, r2 /* r2 <- source end address */
- mov r1, #SRAM_OFFSET0 /* build vect addr */
- mov r3, #SRAM_OFFSET1
- add r1, r1, r3
- mov r3, #SRAM_OFFSET2
- add r1, r1, r3
-next:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next /* loop until equal */
- bl cpy_clk_code /* put dpll adjust code behind vectors */
-#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index cf55bf7..367c805 100644
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -31,6 +31,7 @@
. = ALIGN(4);
.text :
{
+ *(.__image_copy_start)
arch/arm/cpu/arm920t/start.o (.text*)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
@@ -56,7 +57,10 @@
. = ALIGN(4);
- __image_copy_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
__bss_start = .;
.bss : { *(.bss*) }
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index dec7bfb..bba4671 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -33,6 +33,7 @@
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
COBJS-$(CONFIG_SOC_DM646X) += dm646x.o
+COBJS-$(CONFIG_SOC_DA830) += da830_pinmux.o
COBJS-$(CONFIG_SOC_DA850) += da850_pinmux.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
new file mode 100644
index 0000000..d0c964a
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
@@ -0,0 +1,151 @@
+/*
+ * Pinmux configurations for the DA830 SoCs
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+
+/* SPI0 pin muxer settings */
+const struct pinmux_config spi0_pins_base[] = {
+ { pinmux(7), 1, 3 }, /* SPI0_SOMI */
+ { pinmux(7), 1, 4 }, /* SPI0_SIMO */
+ { pinmux(7), 1, 6 } /* SPI0_CLK */
+};
+
+const struct pinmux_config spi0_pins_scs0[] = {
+ { pinmux(7), 1, 7 } /* SPI0_SCS[0] */
+};
+
+const struct pinmux_config spi0_pins_ena[] = {
+ { pinmux(7), 1, 5 } /* SPI0_ENA */
+};
+
+/* NAND pin muxer settings */
+const struct pinmux_config emifa_pins_cs0[] = {
+ { pinmux(18), 1, 2 } /* EMA_CS[0] */
+};
+
+const struct pinmux_config emifa_pins_cs2[] = {
+ { pinmux(18), 1, 3 } /* EMA_CS[2] */
+};
+
+const struct pinmux_config emifa_pins_cs3[] = {
+ { pinmux(18), 1, 4 } /* EMA_CS[3] */
+};
+
+#ifdef CONFIG_USE_NAND
+const struct pinmux_config emifa_pins[] = {
+ { pinmux(13), 1, 6 }, /* EMA_D[0] */
+ { pinmux(13), 1, 7 }, /* EMA_D[1] */
+ { pinmux(14), 1, 0 }, /* EMA_D[2] */
+ { pinmux(14), 1, 1 }, /* EMA_D[3] */
+ { pinmux(14), 1, 2 }, /* EMA_D[4] */
+ { pinmux(14), 1, 3 }, /* EMA_D[5] */
+ { pinmux(14), 1, 4 }, /* EMA_D[6] */
+ { pinmux(14), 1, 5 }, /* EMA_D[7] */
+ { pinmux(14), 1, 6 }, /* EMA_D[8] */
+ { pinmux(14), 1, 7 }, /* EMA_D[9] */
+ { pinmux(15), 1, 0 }, /* EMA_D[10] */
+ { pinmux(15), 1, 1 }, /* EMA_D[11] */
+ { pinmux(15), 1, 2 }, /* EMA_D[12] */
+ { pinmux(15), 1, 3 }, /* EMA_D[13] */
+ { pinmux(15), 1, 4 }, /* EMA_D[14] */
+ { pinmux(15), 1, 5 }, /* EMA_D[15] */
+ { pinmux(15), 1, 6 }, /* EMA_A[0] */
+ { pinmux(15), 1, 7 }, /* EMA_A[1] */
+ { pinmux(16), 1, 0 }, /* EMA_A[2] */
+ { pinmux(16), 1, 1 }, /* EMA_A[3] */
+ { pinmux(16), 1, 2 }, /* EMA_A[4] */
+ { pinmux(16), 1, 3 }, /* EMA_A[5] */
+ { pinmux(16), 1, 4 }, /* EMA_A[6] */
+ { pinmux(16), 1, 5 }, /* EMA_A[7] */
+ { pinmux(16), 1, 6 }, /* EMA_A[8] */
+ { pinmux(16), 1, 7 }, /* EMA_A[9] */
+ { pinmux(17), 1, 0 }, /* EMA_A[10] */
+ { pinmux(17), 1, 1 }, /* EMA_A[11] */
+ { pinmux(17), 1, 2 }, /* EMA_A[12] */
+ { pinmux(17), 1, 3 }, /* EMA_BA[1] */
+ { pinmux(17), 1, 4 }, /* EMA_BA[0] */
+ { pinmux(17), 1, 5 }, /* EMA_CLK */
+ { pinmux(17), 1, 6 }, /* EMA_SDCKE */
+ { pinmux(17), 1, 7 }, /* EMA_CAS */
+ { pinmux(18), 1, 0 }, /* EMA_CAS */
+ { pinmux(18), 1, 1 }, /* EMA_WE */
+ { pinmux(18), 1, 5 }, /* EMA_OE */
+ { pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */
+ { pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */
+ { pinmux(10), 1, 0 } /* Tristate */
+};
+#endif
+
+/* EMAC PHY interface pins */
+const struct pinmux_config emac_pins_rmii[] = {
+ { pinmux(10), 2, 1 }, /* RMII_TXD[0] */
+ { pinmux(10), 2, 2 }, /* RMII_TXD[1] */
+ { pinmux(10), 2, 3 }, /* RMII_TXEN */
+ { pinmux(10), 2, 4 }, /* RMII_CRS_DV */
+ { pinmux(10), 2, 5 }, /* RMII_RXD[0] */
+ { pinmux(10), 2, 6 }, /* RMII_RXD[1] */
+ { pinmux(10), 2, 7 } /* RMII_RXER */
+};
+
+const struct pinmux_config emac_pins_mdio[] = {
+ { pinmux(11), 2, 0 }, /* MDIO_CLK */
+ { pinmux(11), 2, 1 } /* MDIO_D */
+};
+
+const struct pinmux_config emac_pins_rmii_clk_source[] = {
+ { pinmux(9), 0, 5 } /* ref.clk from external source */
+};
+
+/* UART2 pin muxer settings */
+const struct pinmux_config uart2_pins_txrx[] = {
+ { pinmux(8), 2, 7 }, /* UART2_RXD */
+ { pinmux(9), 2, 0 } /* UART2_TXD */
+};
+
+/* I2C0 pin muxer settings */
+const struct pinmux_config i2c0_pins[] = {
+ { pinmux(8), 2, 3 }, /* I2C0_SDA */
+ { pinmux(8), 2, 4 } /* I2C0_SCL */
+};
+
+/* USB0_DRVVBUS pin muxer settings */
+const struct pinmux_config usb_pins[] = {
+ { pinmux(9), 1, 1 } /* USB0_DRVVBUS */
+};
+
+#ifdef CONFIG_DAVINCI_MMC
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins_8bit[] = {
+ { pinmux(15), 2, 7 }, /* MMCSD0_CLK */
+ { pinmux(16), 2, 0 }, /* MMCSD0_CMD */
+ { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */
+ { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */
+ { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */
+ { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */
+ { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */
+ { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */
+ { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */
+ { pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */
+ /* DA830 supports 8-bit mode */
+};
+#endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index a5e388b..45667bd 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -76,13 +76,32 @@
#endif
}
+/*
+ * This function will craft a jumptable at 0x0 which will redirect interrupt
+ * vectoring to proper location of U-Boot in RAM.
+ *
+ * The structure of the jumptable will be as follows:
+ * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
+ * <destination address> ... for each previous ldr, thus also repeated 8 times
+ *
+ * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
+ * offset 0x18 from current value of PC register. Note that PC is already
+ * incremented by 4 when computing the offset, so the effective offset is
+ * actually 0x20, this the associated <destination address>. Loading the PC
+ * register with an address performs a jump to that address.
+ */
void mx28_fixup_vt(uint32_t start_addr)
{
- uint32_t *vt = (uint32_t *)0x20;
+ /* ldr pc, [pc, #0x18] */
+ const uint32_t ldr_pc = 0xe59ff018;
+ /* Jumptable location is 0x0 */
+ uint32_t *vt = (uint32_t *)0x0;
int i;
- for (i = 0; i < 8; i++)
- vt[i] = start_addr + (4 * i);
+ for (i = 0; i < 8; i++) {
+ vt[i] = ldr_pc;
+ vt[i + 8] = start_addr + (4 * i);
+ }
}
#ifdef CONFIG_ARCH_MISC_INIT
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index 673c725..f4e7525 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -57,11 +57,6 @@
__rel_dyn_end = .;
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
.bss : {
. = ALIGN(4);
__bss_start = .;
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index 967a135..446d095 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -57,11 +57,6 @@
__rel_dyn_end = .;
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
.bss : {
. = ALIGN(4);
__bss_start = .;
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 885fb2d..b935a29 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -149,3 +149,43 @@
#endif
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+void rtc32k_enable(void)
+{
+ struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+ /*
+ * Unlock the RTC's registers. For more details please see the
+ * RTC_SS section of the TRM. In order to unlock we need to
+ * write these specific values (keys) in this order.
+ */
+ writel(0x83e70b13, &rtc->kick0r);
+ writel(0x95a4f1e0, &rtc->kick1r);
+
+ /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+ writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+void uart_soft_reset(void)
+{
+ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+ u32 regval;
+
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_RESET;
+ writel(regval, &uart_base->uartsyscfg);
+ while ((readl(&uart_base->uartsyssts) &
+ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+ ;
+
+ /* Disable smart idle */
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_SMART_IDLE_EN;
+ writel(regval, &uart_base->uartsyscfg);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index a1efc75..9c4d0b4 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -246,7 +246,7 @@
;
}
-static void mpu_pll_config(void)
+void mpu_pll_config_val(int mpull_m)
{
u32 clkmode, clksel, div_m2;
@@ -260,7 +260,7 @@
;
clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
+ clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
writel(clksel, &cmwkup->clkseldpllmpu);
div_m2 = div_m2 & ~CLK_DIV_MASK;
@@ -274,6 +274,11 @@
;
}
+static void mpu_pll_config(void)
+{
+ mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+}
+
static void core_pll_config(void)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
index 9119961..b2f9152 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -22,7 +22,7 @@
LIB = $(obj)lib$(SOC).o
-COBJS += clock.o power.o soc.o system.o pinmux.o
+COBJS += clock.o power.o soc.o system.o pinmux.o tzpc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 223660a..e1c4246 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -116,10 +116,8 @@
/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 1024) * (freq / (p * (1 << s)));
} else {
- if (s < 1)
- s = 1;
- /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
- fout = m * (freq / (p * (1 << (s - 1))));
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ fout = m * (freq / (p * (1 << s)));
}
return fout;
@@ -613,7 +611,7 @@
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel, ratio, pre_ratio;
- int shift;
+ int shift = 0;
sel = readl(&clk->src_fsys);
sel = (sel >> (dev_index << 2)) & 0xf;
@@ -662,7 +660,7 @@
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel, ratio, pre_ratio;
- int shift;
+ int shift = 0;
sel = readl(&clk->src_fsys);
sel = (sel >> (dev_index << 2)) & 0xf;
diff --git a/board/samsung/smdk5250/tzpc_init.c b/arch/arm/cpu/armv7/exynos/tzpc.c
similarity index 69%
rename from board/samsung/smdk5250/tzpc_init.c
rename to arch/arm/cpu/armv7/exynos/tzpc.c
index c833541..f5e8e9c 100644
--- a/board/samsung/smdk5250/tzpc_init.c
+++ b/arch/arm/cpu/armv7/exynos/tzpc.c
@@ -22,27 +22,36 @@
* MA 02111-1307 USA
*/
+#include <common.h>
#include <asm/arch/tzpc.h>
-#include"setup.h"
+#include <asm/io.h>
/* Setting TZPC[TrustZone Protection Controller] */
void tzpc_init(void)
{
struct exynos_tzpc *tzpc;
- unsigned int addr;
+ unsigned int addr, start = 0, end = 0;
- for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
+ start = samsung_get_base_tzpc();
+
+ if (cpu_is_exynos5())
+ end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+ else if (cpu_is_exynos4())
+ end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+
+ for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) {
tzpc = (struct exynos_tzpc *)addr;
- if (addr == TZPC0_BASE)
+ if (addr == start)
writel(R0SIZE, &tzpc->r0size);
writel(DECPROTXSET, &tzpc->decprot0set);
writel(DECPROTXSET, &tzpc->decprot1set);
- if (addr != TZPC9_BASE) {
- writel(DECPROTXSET, &tzpc->decprot2set);
- writel(DECPROTXSET, &tzpc->decprot3set);
- }
+ if (cpu_is_exynos5() && (addr == end))
+ break;
+
+ writel(DECPROTXSET, &tzpc->decprot2set);
+ writel(DECPROTXSET, &tzpc->decprot3set);
}
}
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 55e82ba..c4b9809 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -34,6 +34,7 @@
COBJS += clocks-common.o
COBJS += emif-common.o
COBJS += vc.o
+COBJS += abb.o
endif
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c
new file mode 100644
index 0000000..87d1fb8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/abb.c
@@ -0,0 +1,137 @@
+/*
+ *
+ * Adaptive Body Bias programming sequence for OMAP family
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
+{
+ return -1;
+}
+
+static void abb_setup_timings(u32 setup)
+{
+ u32 sys_rate, sr2_cnt, clk_cycles;
+
+ /*
+ * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
+ * transition and must be programmed with the correct time at boot.
+ * The value programmed into the register is the number of SYS_CLK
+ * clock cycles that match a given wall time profiled for the ldo.
+ * This value depends on:
+ * settling time of ldo in micro-seconds (varies per OMAP family),
+ * of clock cycles per SYS_CLK period (varies per OMAP family),
+ * the SYS_CLK frequency in MHz (varies per board)
+ * The formula is:
+ *
+ * ldo settling time (in micro-seconds)
+ * SR2_WTCNT_VALUE = ------------------------------------------
+ * (# system clock cycles) * (sys_clk period)
+ *
+ * Put another way:
+ *
+ * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
+ *
+ * To avoid dividing by zero multiply both "# clock cycles" and
+ * "settling time" by 10 such that the final result is the one we want.
+ */
+
+ /* calculate SR2_WTCNT_VALUE */
+ sys_rate = DIV_ROUND(V_OSCK, 1000000);
+ clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
+ sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
+
+ setbits_le32(setup,
+ sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
+}
+
+void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
+ u32 txdone, u32 txdone_mask, u32 opp)
+{
+ u32 abb_type_mask, opp_sel_mask;
+
+ /* sanity check */
+ if (!setup || !control || !txdone)
+ return;
+
+ /* setup ABB only in case of Fast or Slow OPP */
+ switch (opp) {
+ case OMAP_ABB_FAST_OPP:
+ abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK;
+ opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK;
+ break;
+ case OMAP_ABB_SLOW_OPP:
+ abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK;
+ opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK;
+ break;
+ default:
+ return;
+ }
+
+ /*
+ * For some OMAP silicons additional setup for LDOVBB register is
+ * required. This is determined by data retrieved from corresponding
+ * OPP EFUSE register. Data, which is retrieved from EFUSE - is
+ * ABB enable/disable flag and VSET value, which must be copied
+ * to LDOVBB register. If function call fails - return quietly,
+ * it means no ABB is required for such silicon.
+ *
+ * For silicons, which don't require LDOVBB setup "fuse" and
+ * "ldovbb" offsets are not defined. ABB will be initialized in
+ * the common way for them.
+ */
+ if (fuse && ldovbb) {
+ if (abb_setup_ldovbb(fuse, ldovbb))
+ return;
+ }
+
+ /* clear ABB registers */
+ writel(0, setup);
+ writel(0, control);
+
+ /* configure timings, based on oscillator value */
+ abb_setup_timings(setup);
+
+ /* clear pending interrupts before setup */
+ setbits_le32(txdone, txdone_mask);
+
+ /* select ABB type */
+ setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK);
+
+ /* initiate ABB ldo change */
+ setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK);
+
+ /* wait until transition complete */
+ if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY))
+ puts("Error: ABB txdone is not set\n");
+
+ /* clear ABB tranxdone */
+ setbits_le32(txdone, txdone_mask);
+}
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 99910cd..ef23127 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -30,9 +30,10 @@
* MA 02111-1307 USA
*/
#include <common.h>
+#include <i2c.h>
#include <asm/omap_common.h>
#include <asm/gpio.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
@@ -49,13 +50,12 @@
const u32 sys_clk_array[8] = {
12000000, /* 12 MHz */
- 13000000, /* 13 MHz */
+ 20000000, /* 20 MHz */
16800000, /* 16.8 MHz */
19200000, /* 19.2 MHz */
26000000, /* 26 MHz */
27000000, /* 27 MHz */
38400000, /* 38.4 MHz */
- 20000000, /* 20 MHz */
};
static inline u32 __get_sys_clk_index(void)
@@ -74,13 +74,6 @@
/* SYS_CLKSEL - 1 to match the dpll param array indices */
ind = (readl((*prcm)->cm_sys_clksel) &
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
- /*
- * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
- * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
- * NUM_SYS_CLK. So considering the last 3 bits as the index
- * for the dpll param array.
- */
- ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
}
return ind;
}
@@ -440,6 +433,12 @@
params = get_abe_dpll_params(*dplls_data);
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
+
+ if (omap_revision() == DRA752_ES1_0)
+ /* Select the sys clk for dpll_abe */
+ clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
+ CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
+ CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
#else
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
/*
@@ -487,6 +486,10 @@
u32 offset = volt_mv;
int ret = 0;
+ if (!volt_mv)
+ return;
+
+ pmic->pmic_bus_init();
/* See if we can first get the GPIO if needed */
if (pmic->gpio_en)
ret = gpio_request(pmic->gpio, "PMIC_GPIO");
@@ -509,14 +512,45 @@
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
offset_code);
- if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
- vcore_reg, offset_code))
+ if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 1);
}
+static u32 optimize_vcore_voltage(struct volts const *v)
+{
+ u32 val;
+ if (!v->value)
+ return 0;
+ if (!v->efuse.reg)
+ return v->value;
+
+ switch (v->efuse.reg_bits) {
+ case 16:
+ val = readw(v->efuse.reg);
+ break;
+ case 32:
+ val = readl(v->efuse.reg);
+ break;
+ default:
+ printf("Error: efuse 0x%08x bits=%d unknown\n",
+ v->efuse.reg, v->efuse.reg_bits);
+ return v->value;
+ }
+
+ if (!val) {
+ printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
+ v->efuse.reg, v->efuse.reg_bits, v->value);
+ return v->value;
+ }
+
+ debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
+ __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
+ return val;
+}
+
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
@@ -525,16 +559,34 @@
*/
void scale_vcores(struct vcores_data const *vcores)
{
- omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+ u32 val;
- do_scale_vcore(vcores->core.addr, vcores->core.value,
- vcores->core.pmic);
+ val = optimize_vcore_voltage(&vcores->core);
+ do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
- do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
- vcores->mpu.pmic);
+ val = optimize_vcore_voltage(&vcores->mpu);
+ do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
- do_scale_vcore(vcores->mm.addr, vcores->mm.value,
- vcores->mm.pmic);
+ /* Configure MPU ABB LDO after scale */
+ abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+ (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
+ (*prcm)->prm_abbldo_mpu_setup,
+ (*prcm)->prm_abbldo_mpu_ctrl,
+ (*prcm)->prm_irqstatus_mpu_2,
+ OMAP_ABB_MPU_TXDONE_MASK,
+ OMAP_ABB_FAST_OPP);
+
+ val = optimize_vcore_voltage(&vcores->mm);
+ do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
+
+ val = optimize_vcore_voltage(&vcores->gpu);
+ do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
+
+ val = optimize_vcore_voltage(&vcores->eve);
+ do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
+
+ val = optimize_vcore_voltage(&vcores->iva);
+ do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM "magic" bits */
@@ -710,6 +762,7 @@
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
enable_basic_clocks();
+ timer_init();
scale_vcores(*omap_vcores);
setup_dplls();
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
@@ -725,3 +778,13 @@
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
enable_basic_uboot_clocks();
}
+
+void gpi2c_init(void)
+{
+ static int gpi2c = 1;
+
+ if (gpi2c) {
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ gpi2c = 0;
+ }
+}
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 11e830a..652e5a7 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -27,7 +27,7 @@
#include <common.h>
#include <asm/emif.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/utils.h>
@@ -209,7 +209,8 @@
writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
- if (omap_revision() >= OMAP5430_ES1_0) {
+ if ((omap_revision() >= OMAP5430_ES1_0) ||
+ (omap_revision() == DRA752_ES1_0)) {
writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
&emif->emif_l3_config);
} else if (omap_revision() >= OMAP4460_ES1_0) {
@@ -263,6 +264,18 @@
__udelay(130);
}
+static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+ config_data_eye_leveling_samples(base);
+
+ writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
+ writel(regs->sdram_config, &emif->emif_sdram_config);
+}
+
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -273,6 +286,7 @@
* defined, contents of mode Registers must be fully initialized.
* H/W takes care of this initialization
*/
+ writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
@@ -290,7 +304,10 @@
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
- ddr3_leveling(base, regs);
+ if (omap_revision() == DRA752_ES1_0)
+ ddr3_sw_leveling(base, regs);
+ else
+ ddr3_leveling(base, regs);
}
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1078,7 +1095,10 @@
if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
- ddr3_leveling(base, regs);
+ if (omap_revision() == DRA752_ES1_0)
+ ddr3_sw_leveling(base, regs);
+ else
+ ddr3_leveling(base, regs);
}
/* Write to the shadow registers */
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 0776d5c..5df116e 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -166,8 +166,6 @@
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
- timer_init();
-
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
#endif
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
index 507f687..5926a5a 100644
--- a/arch/arm/cpu/armv7/omap-common/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -35,6 +35,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c
index e6e5f78..a68f1d1 100644
--- a/arch/arm/cpu/armv7/omap-common/vc.c
+++ b/arch/arm/cpu/armv7/omap-common/vc.c
@@ -17,6 +17,7 @@
#include <common.h>
#include <asm/omap_common.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
/*
* Define Master code if there are multiple masters on the I2C_SR bus.
@@ -57,7 +58,7 @@
* omap_vc_init() - Initialization for Voltage controller
* @speed_khz: I2C buspeed in KHz
*/
-void omap_vc_init(u16 speed_khz)
+static void omap_vc_init(u16 speed_khz)
{
u32 val;
u32 sys_clk_khz, cycles_hi, cycles_low;
@@ -137,3 +138,14 @@
/* All good.. */
return 0;
}
+
+void sri2c_init(void)
+{
+ static int sri2c = 1;
+
+ if (sri2c) {
+ omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+ sri2c = 0;
+ }
+ return;
+}
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 09c51f6..81cc859 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -27,7 +27,7 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/clocks_omap3.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 06a2fc8..b97cad4 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -29,7 +29,7 @@
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
@@ -219,6 +219,9 @@
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct pmic_data twl6030 = {
@@ -226,6 +229,9 @@
.step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct pmic_data tps62361 = {
@@ -233,7 +239,10 @@
.step = 10000, /* 10 mV represented in uV */
.start_code = 0,
.gpio = TPS62361_VSEL0_GPIO,
- .gpio_en = 1
+ .gpio_en = 1,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
};
struct vcores_data omap4430_volts_es1 = {
diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index 7225a30..7e71ca0 100644
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -301,6 +301,8 @@
.control_ldosram_iva_voltage_ctrl = 0x4A002320,
.control_ldosram_mpu_voltage_ctrl = 0x4A002324,
.control_ldosram_core_voltage_ctrl = 0x4A002328,
+ .control_usbotghs_ctrl = 0x4A00233C,
+ .control_padconf_core_base = 0x4A100000,
.control_pbiaslite = 0x4A100600,
.control_lpddr2io1_0 = 0x4A100638,
.control_lpddr2io1_1 = 0x4A10063C,
@@ -312,4 +314,5 @@
.control_lpddr2io2_3 = 0x4A100654,
.control_efuse_1 = 0x4A100700,
.control_efuse_2 = 0x4A100704,
+ .control_padconf_wkup_base = 0x4A31E000,
};
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
index ce00e2c..6ff8dbb 100644
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -30,6 +30,7 @@
COBJS += sdram.o
COBJS += prcm-regs.o
COBJS += hw_data.o
+COBJS += abb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c
new file mode 100644
index 0000000..92470be
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/abb.c
@@ -0,0 +1,67 @@
+/*
+ *
+ * Adaptive Body Bias programming sequence for OMAP5 family
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/io.h>
+
+/*
+ * Setup LDOVBB for OMAP5.
+ * On OMAP5+ some ABB settings are fused. They are handled
+ * in the following way:
+ *
+ * 1. corresponding EFUSE register contains ABB enable bit
+ * and VSET value
+ * 2. If ABB enable bit is set to 1, than ABB should be
+ * enabled, otherwise ABB should be disabled
+ * 3. If ABB is enabled, than VSET value should be copied
+ * to corresponding MUX control register
+ */
+s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
+{
+ u32 vset;
+
+ /*
+ * ABB parameters must be properly fused
+ * otherwise ABB should be disabled
+ */
+ vset = readl(fuse);
+ if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK))
+ return -1;
+
+ /* prepare VSET value for LDOVBB mux register */
+ vset &= OMAP5_ABB_FUSE_VSET_MASK;
+ vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1;
+ vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
+ vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
+
+ /* setup LDOVBB using fused value */
+ clrsetbits_le32(ldovbb, OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 604fa42..56cf1f8 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -26,10 +26,11 @@
* MA 02111-1307 USA
*/
#include <common.h>
+#include <palmas.h>
#include <asm/arch/omap.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/omap_gpio.h>
#include <asm/io.h>
#include <asm/emif.h>
@@ -99,14 +100,13 @@
};
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
- {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
- {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+ {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params
@@ -132,15 +132,14 @@
};
static const struct dpll_params
- core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
- {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
- {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
- {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
+ core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
+ {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
+ {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
+ {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
+ {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
+ {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
- {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
+ {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
};
static const struct dpll_params
@@ -186,14 +185,13 @@
};
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
- {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
- {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
+ {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
@@ -206,6 +204,16 @@
{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
+static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
+ {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
/* ABE M & N values with sys_clk as source */
static const struct dpll_params
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
@@ -223,26 +231,36 @@
750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
};
+/* ABE M & N values with sysclk2(22.5792 MHz) as input */
+static const struct dpll_params
+ abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
- {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
};
-static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
- {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
+ {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
- {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+ {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
struct dplls omap5_dplls_es1 = {
@@ -275,10 +293,12 @@
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
- .core = core_dpll_params_2128mhz_ddr532_dra7xx,
+ .core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra7xx,
+ .abe = abe_dpll_params_sysclk2_361267khz,
+ .iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
- .ddr = ddr_dpll_params_1066mhz,
+ .ddr = ddr_dpll_params_2128mhz,
};
struct pmic_data palmas = {
@@ -289,6 +309,22 @@
* Offset code 0 switches OFF the SMPS
*/
.start_code = 6,
+ .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
+ .pmic_bus_init = sri2c_init,
+ .pmic_write = omap_vc_bypass_send_value,
+};
+
+struct pmic_data tps659038 = {
+ .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+ .step = 10000, /* 10 mV represented in uV */
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ .start_code = 6,
+ .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
+ .pmic_bus_init = gpi2c_init,
+ .pmic_write = palmas_i2c_write_u8,
};
struct vcores_data omap5430_volts = {
@@ -319,6 +355,38 @@
.mm.pmic = &palmas,
};
+struct vcores_data dra752_volts = {
+ .mpu.value = VDD_MPU_DRA752,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
+ .mpu.pmic = &tps659038,
+
+ .eve.value = VDD_EVE_DRA752,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
+ .eve.pmic = &tps659038,
+
+ .gpu.value = VDD_GPU_DRA752,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
+ .gpu.pmic = &tps659038,
+
+ .core.value = VDD_CORE_DRA752,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA752,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
+ .iva.pmic = &tps659038,
+};
+
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
@@ -383,12 +451,6 @@
clk_modules_explicit_en_essential,
1);
- /* Select 384Mhz for GPU as its the POR for ES1.0 */
- setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
- CLKSEL_GPU_HYD_GCLK_MASK);
- setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
- CLKSEL_GPU_CORE_GCLK_MASK);
-
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
@@ -540,6 +602,17 @@
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};
+const struct ctrl_ioregs ioregs_dra7xx_es1 = {
+ .ctrl_ddrch = 0x40404040,
+ .ctrl_lpddr2ch = 0x40404040,
+ .ctrl_ddr3ch = 0x80808080,
+ .ctrl_ddrio_0 = 0xbae8c631,
+ .ctrl_ddrio_1 = 0xb46318d8,
+ .ctrl_ddrio_2 = 0x84210000,
+ .ctrl_emif_sdram_config_ext = 0xb2c00000,
+ .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
@@ -565,7 +638,7 @@
case DRA752_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
- *omap_vcores = &omap5430_volts_es2;
+ *omap_vcores = &dra752_volts;
*ctrl = &dra7xx_ctrl;
break;
@@ -582,14 +655,16 @@
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = &ioregs_omap5430;
- break;
+ break;
case OMAP5432_ES1_0:
*regs = &ioregs_omap5432_es1;
- break;
+ break;
case OMAP5432_ES2_0:
- case DRA752_ES1_0:
*regs = &ioregs_omap5432_es2;
- break;
+ break;
+ case DRA752_ES1_0:
+ *regs = &ioregs_dra7xx_es1;
+ break;
default:
printf("\n INVALID OMAP REVISION ");
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index e192fea..daf124e 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -32,7 +32,7 @@
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
@@ -100,16 +100,21 @@
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif2_sdram_config_ext);
- /* Disable DLL select */
- io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
+ if (is_omap54xx()) {
+ /* Disable DLL select */
+ io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
- writel(io_settings,
- (*ctrl)->control_port_emif1_sdram_config);
+ writel(io_settings,
+ (*ctrl)->control_port_emif1_sdram_config);
- io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
+ io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
- writel(io_settings,
- (*ctrl)->control_port_emif2_sdram_config);
+ writel(io_settings,
+ (*ctrl)->control_port_emif2_sdram_config);
+ } else {
+ writel(ioregs->ctrl_ddr_ctrl_ext_0,
+ (*ctrl)->control_ddr_control_ext_0);
+ }
}
/*
@@ -201,6 +206,9 @@
u32 sysclk_ind = get_sys_clk_index();
u32 omap_rev = omap_revision();
+ if (!is_omap54xx())
+ return;
+
mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
div_factor = srcomp_parameters[sysclk_ind].divide_factor;
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index e9f6a32..e839ff5 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -298,6 +298,7 @@
.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
.prm_rstctrl = 0x4ae07b00,
.prm_rstst = 0x4ae07b04,
+ .prm_rsttime = 0x4ae07b08,
.prm_vc_val_bypass = 0x4ae07ba0,
.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
@@ -307,10 +308,16 @@
.prm_sldo_mpu_ctrl = 0x4ae07bd0,
.prm_sldo_mm_setup = 0x4ae07bd4,
.prm_sldo_mm_ctrl = 0x4ae07bd8,
+
+ /* SCRM stuff, used by some boards */
+ .scrm_auxclk0 = 0x4ae0a310,
+ .scrm_auxclk1 = 0x4ae0a314,
};
struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_status = 0x4A002134,
+ .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
+ .control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode = 0x4A002DA4,
.control_smart1io_padconf_0 = 0x4A002DA8,
@@ -358,6 +365,8 @@
.control_port_emif2_sdram_config = 0x4AE0C118,
.control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148,
+ .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318,
+ .control_padconf_wkup_base = 0x4AE0C800,
.control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
.control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
.control_padconf_mode = 0x4AE0CDA8,
@@ -434,6 +443,7 @@
.control_srcomp_east_side = 0x4A002E7C,
.control_srcomp_west_side = 0x4A002E80,
.control_srcomp_code_latch = 0x4A002E84,
+ .control_ddr_control_ext_0 = 0x4A002E88,
.control_padconf_core_base = 0x4A003400,
.control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
@@ -709,6 +719,9 @@
.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
+ /* prm irqstatus regs */
+ .prm_irqstatus_mpu_2 = 0x4ae06014,
+
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
.cm_sys_clksel = 0x4ae06110,
@@ -740,6 +753,12 @@
.prm_sldo_mpu_ctrl = 0x4ae07cd0,
.prm_sldo_mm_setup = 0x4ae07cd4,
.prm_sldo_mm_ctrl = 0x4ae07cd8,
+ .prm_abbldo_mpu_setup = 0x4ae07cdc,
+ .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
+
+ /* SCRM stuff, used by some boards */
+ .scrm_auxclk0 = 0x4ae0a310,
+ .scrm_auxclk1 = 0x4ae0a314,
};
struct prcm_regs const dra7xx_prcm = {
@@ -941,6 +960,7 @@
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
.cm_sys_clksel = 0x4ae06110,
+ .cm_abe_pll_sys_clksel = 0x4ae06118,
.cm_wkup_clkstctrl = 0x4ae07800,
.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 6b461e4..1b445a6 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -108,6 +108,7 @@
const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
+ .sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
@@ -131,6 +132,7 @@
const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
+ .sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
@@ -151,6 +153,54 @@
.emif_rd_wr_exec_thresh = 0x40000305
};
+const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
+ .sdram_config_init = 0x61851ab2,
+ .sdram_config = 0x61851ab2,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x0007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0E20400A,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x009E009E,
+ .emif_ddr_ext_phy_ctrl_3 = 0x009E009E,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009E009E,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
+ .sdram_config_init = 0x61851B32,
+ .sdram_config = 0x61851B32,
+ .sdram_config2 = 0x08000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x0007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0020400A,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x009D009D,
+ .emif_ddr_ext_phy_ctrl_3 = 0x009D009D,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009D009D,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009D009D,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
@@ -159,11 +209,39 @@
.is_ma_present = 0x1
};
-const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
+/*
+ * DRA752 EVM board has 1.5 GB of memory
+ * EMIF1 --> 2Gb * 2 = 512MB
+ * EMIF2 --> 2Gb * 4 = 1GB
+ * so mapping 1GB interleaved and 512MB non-interleaved
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x80640300,
+ .dmm_lisa_map_2 = 0xC0500220,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+/*
+ * DRA752 EVM EMIF1 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x0,
- .dmm_lisa_map_3 = 0x80500100,
+ .dmm_lisa_map_2 = 0x80500100,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+/*
+ * DRA752 EVM EMIF2 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x80600200,
+ .dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
@@ -180,9 +258,20 @@
*regs = &emif_regs_532_mhz_2cs_es2;
break;
case OMAP5432_ES2_0:
- case DRA752_ES1_0:
- default:
*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
+ break;
+ case DRA752_ES1_0:
+ switch (emif_nr) {
+ case 1:
+ *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
+ break;
+ case 2:
+ *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
+ break;
+ }
+ break;
+ default:
+ *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
}
}
@@ -201,7 +290,7 @@
break;
case DRA752_ES1_0:
default:
- *dmm_lisa_regs = &lisa_map_512M_x_1;
+ *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
}
}
@@ -252,7 +341,8 @@
0x00000000,
0x00000000,
0x00000000,
- 0x00000077
+ 0x00000077,
+ 0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@@ -274,7 +364,8 @@
0x00000000,
0x00000000,
0x00000000,
- 0x00000057
+ 0x00000057,
+ 0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@@ -296,7 +387,56 @@
0x00000000,
0x00000000,
0x00000000,
- 0x00000057
+ 0x00000057,
+ 0x0
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x009E009E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x002E002E,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x004D004D,
+ 0x0,
+ 0x600020,
+ 0x40010080,
+ 0x8102040
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x009D009D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x002D002D,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x00570057,
+ 0x0,
+ 0x600020,
+ 0x40010080,
+ 0x8102040
};
const struct lpddr2_mr_regs mr_regs = {
@@ -307,7 +447,7 @@
.mr16 = MR16_REF_FULL_ARRAY
};
-static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
+static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
@@ -318,7 +458,14 @@
*regs = ddr3_ext_phy_ctrl_const_base_es1;
break;
case OMAP5432_ES2_0:
+ *regs = ddr3_ext_phy_ctrl_const_base_es2;
+ break;
case DRA752_ES1_0:
+ if (emif_nr == 1)
+ *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
+ else
+ *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
+ break;
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
@@ -334,9 +481,12 @@
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
+ u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
+ emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
@@ -353,7 +503,7 @@
* external phy 6-24 registers do not change with
* ddr frequency
*/
- emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
+ emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile
index 1705399..0c38bd0 100644
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ b/arch/arm/cpu/armv7/s5p-common/Makefile
@@ -26,9 +26,11 @@
LIB = $(obj)libs5p-common.o
COBJS-y += cpu_info.o
+ifndef CONFIG_SPL_BUILD
COBJS-y += timer.o
COBJS-y += sromc.o
COBJS-$(CONFIG_PWM) += pwm.o
+endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
diff --git a/board/ti/omap2420h4/Makefile b/arch/arm/cpu/armv7/vf610/Makefile
similarity index 71%
copy from board/ti/omap2420h4/Makefile
copy to arch/arm/cpu/armv7/vf610/Makefile
index cddd7e6..9232cd4 100644
--- a/board/ti/omap2420h4/Makefile
+++ b/arch/arm/cpu/armv7/vf610/Makefile
@@ -1,9 +1,5 @@
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright 2013 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -23,17 +19,18 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)lib$(SOC).o
-COBJS := omap2420h4.o mem.o sys_info.o
-SOBJS := lowlevel_init.o
+COBJS += generic.o
+COBJS += timer.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
new file mode 100644
index 0000000..87f2a86
--- /dev/null
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <netdev.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&ccm->ccgr6);
+ if (enable)
+ reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
+ else
+ reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
+ writel(reg, &ccm->ccgr6);
+}
+#endif
+
+static u32 get_mcu_main_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_ccsr, ccm_cacrr, armclk_div;
+ u32 sysclk_sel, pll_pfd_sel = 0;
+ u32 freq = 0;
+
+ ccm_ccsr = readl(&ccm->ccsr);
+ sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
+ sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+ armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
+ armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
+ armclk_div += 1;
+
+ switch (sysclk_sel) {
+ case 0:
+ freq = FASE_CLK_FREQ;
+ break;
+ case 1:
+ freq = SLOW_CLK_FREQ;
+ break;
+ case 2:
+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
+ pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
+ if (pll_pfd_sel == 0)
+ freq = PLL2_MAIN_FREQ;
+ else if (pll_pfd_sel == 1)
+ freq = PLL2_PFD1_FREQ;
+ else if (pll_pfd_sel == 2)
+ freq = PLL2_PFD2_FREQ;
+ else if (pll_pfd_sel == 3)
+ freq = PLL2_PFD3_FREQ;
+ else if (pll_pfd_sel == 4)
+ freq = PLL2_PFD4_FREQ;
+ break;
+ case 3:
+ freq = PLL2_MAIN_FREQ;
+ break;
+ case 4:
+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
+ pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
+ if (pll_pfd_sel == 0)
+ freq = PLL1_MAIN_FREQ;
+ else if (pll_pfd_sel == 1)
+ freq = PLL1_PFD1_FREQ;
+ else if (pll_pfd_sel == 2)
+ freq = PLL1_PFD2_FREQ;
+ else if (pll_pfd_sel == 3)
+ freq = PLL1_PFD3_FREQ;
+ else if (pll_pfd_sel == 4)
+ freq = PLL1_PFD4_FREQ;
+ break;
+ case 5:
+ freq = PLL3_MAIN_FREQ;
+ break;
+ default:
+ printf("unsupported system clock select\n");
+ }
+
+ return freq / armclk_div;
+}
+
+static u32 get_bus_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cacrr, busclk_div;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+
+ busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
+ busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
+ busclk_div += 1;
+
+ return get_mcu_main_clk() / busclk_div;
+}
+
+static u32 get_ipg_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cacrr, ipgclk_div;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+
+ ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
+ ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
+ ipgclk_div += 1;
+
+ return get_bus_clk() / ipgclk_div;
+}
+
+static u32 get_uart_clk(void)
+{
+ return get_ipg_clk();
+}
+
+static u32 get_sdhc_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
+ u32 freq = 0;
+
+ ccm_cscmr1 = readl(&ccm->cscmr1);
+ sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
+ sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
+
+ ccm_cscdr2 = readl(&ccm->cscdr2);
+ sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
+ sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
+ sdhc_clk_div += 1;
+
+ switch (sdhc_clk_sel) {
+ case 0:
+ freq = PLL3_MAIN_FREQ;
+ break;
+ case 1:
+ freq = PLL3_PFD3_FREQ;
+ break;
+ case 2:
+ freq = PLL1_PFD3_FREQ;
+ break;
+ case 3:
+ freq = get_bus_clk();
+ break;
+ }
+
+ return freq / sdhc_clk_div;
+}
+
+u32 get_fec_clk(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ u32 ccm_cscmr2, rmii_clk_sel;
+ u32 freq = 0;
+
+ ccm_cscmr2 = readl(&ccm->cscmr2);
+ rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
+ rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
+
+ switch (rmii_clk_sel) {
+ case 0:
+ freq = ENET_EXTERNAL_CLK;
+ break;
+ case 1:
+ freq = AUDIO_EXTERNAL_CLK;
+ break;
+ case 2:
+ freq = PLL5_MAIN_FREQ;
+ break;
+ case 3:
+ freq = PLL5_MAIN_FREQ / 2;
+ break;
+ }
+
+ return freq;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_mcu_main_clk();
+ case MXC_BUS_CLK:
+ return get_bus_clk();
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_UART_CLK:
+ return get_uart_clk();
+ case MXC_ESDHC_CLK:
+ return get_sdhc_clk();
+ case MXC_FEC_CLK:
+ return get_fec_clk();
+ default:
+ break;
+ }
+ return -1;
+}
+
+/* Dump some core clocks */
+int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ printf("\n");
+ printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
+ printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
+ "display clocks",
+ ""
+);
+
+#ifdef CONFIG_FEC_MXC
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+
+ u32 value = readl(&fuse->mac_addr0);
+ mac[0] = (value >> 8);
+ mac[1] = value;
+
+ value = readl(&fuse->mac_addr1);
+ mac[2] = value >> 24;
+ mac[3] = value >> 16;
+ mac[4] = value >> 8;
+ mac[5] = value;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+ u32 cause;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ cause = readl(&src_regs->srsr);
+ writel(cause, &src_regs->srsr);
+ cause &= 0xff;
+
+ switch (cause) {
+ case 0x08:
+ return "WDOG";
+ case 0x20:
+ return "JTAG HIGH-Z";
+ case 0x80:
+ return "EXTERNAL RESET";
+ case 0xfd:
+ return "POR";
+ default:
+ return "unknown reset";
+ }
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: Freescale Vybrid VF610 at %d MHz\n",
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ printf("Reset cause: %s\n", get_reset_cause());
+
+ return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+ rc = fecmxc_initialize(bis);
+#endif
+
+ return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+ return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/vf610/timer.c b/arch/arm/cpu/armv7/vf610/timer.c
new file mode 100644
index 0000000..f8fbed7
--- /dev/null
+++ b/arch/arm/cpu/armv7/vf610/timer.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+static struct pit_reg *cur_pit = (struct pit_reg *)PIT_BASE_ADDR;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, mxc_get_clock(MXC_IPG_CLK));
+
+ return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+ usec = usec * mxc_get_clock(MXC_IPG_CLK) + 999999;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+int timer_init(void)
+{
+ __raw_writel(0, &cur_pit->mcr);
+
+ __raw_writel(TIMER_LOAD_VAL, &cur_pit->ldval1);
+ __raw_writel(0, &cur_pit->tctrl1);
+ __raw_writel(1, &cur_pit->tctrl1);
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ ulong now = TIMER_LOAD_VAL - __raw_readl(&cur_pit->cval1);
+
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+ unsigned long long start;
+ ulong tmo;
+
+ start = get_ticks(); /* get current timestamp */
+ tmo = us_to_tick(usec); /* convert usecs to ticks */
+ while ((get_ticks() - start) < tmo)
+ ; /* loop till time has passed */
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return mxc_get_clock(MXC_IPG_CLK);
+}
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index 553589c..54bafda 100644
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -31,6 +31,7 @@
. = ALIGN(4);
.text :
{
+ *(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
*(.text*)
}
@@ -54,17 +55,23 @@
. = ALIGN(4);
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
}
_end = .;
@@ -88,6 +95,7 @@
KEEP(*(.__bss_end));
}
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index 0c18610..f07dc67 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -244,7 +244,7 @@
{
writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR);
- asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2));
+ asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
/* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC);
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index e099683..9e6d51d 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -109,6 +109,10 @@
struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
u32 reg;
+ /* Only enable the SCU on T20/T25 */
+ if (tegra_get_chip() != CHIPID_TEGRA20)
+ return;
+
/* If SCU already setup/enabled, return */
if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
return;
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 1408f03..b6ed25f 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -58,11 +58,6 @@
__rel_dyn_end = .;
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
@@ -72,6 +67,7 @@
__bss_end = .;
}
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index d9bbee3..3037885 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -33,7 +33,7 @@
. = ALIGN(4);
.text :
{
- __image_copy_start = .;
+ *(.__image_copy_start)
CPUDIR/start.o (.text*)
*(.text*)
}
@@ -57,17 +57,23 @@
. = ALIGN(4);
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
}
_end = .;
@@ -101,6 +107,7 @@
KEEP(*(.__bss_end));
}
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index df4b231..cee4fe8 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -169,4 +169,37 @@
#address-cells = <1>;
#size-cells = <1>;
};
+
+ mmc@12200000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5250-dwmmc";
+ reg = <0x12200000 0x1000>;
+ interrupts = <0 75 0>;
+ };
+
+ mmc@12210000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5250-dwmmc";
+ reg = <0x12210000 0x1000>;
+ interrupts = <0 76 0>;
+ };
+
+ mmc@12220000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5250-dwmmc";
+ reg = <0x12220000 0x1000>;
+ interrupts = <0 77 0>;
+ };
+
+ mmc@12230000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos5250-dwmmc";
+ reg = <0x12230000 0x1000>;
+ interrupts = <0 78 0>;
+ };
+
};
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 8bba8a5..9492326 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -27,7 +27,7 @@
LIB = $(obj)libimx-common.o
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
COBJS-y = iomux-v3.o
endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 7fe5ce7..35880c7 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -48,8 +48,14 @@
if (sel_input_ofs)
__raw_writel(sel_input, base + sel_input_ofs);
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+ if (!(pad_ctrl & NO_PAD_CTRL))
+ __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
+ base + pad_ctrl_ofs);
+#else
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#endif
}
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index fedc674..307ac28 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -32,6 +32,7 @@
u32 get_device_type(void);
void save_omap_boot_params(void);
void setup_clocks_for_console(void);
+void mpu_pll_config_val(int mpull_m);
void ddr_pll_config(unsigned int ddrpll_M);
void sdelay(unsigned long);
@@ -41,4 +42,7 @@
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size);
void omap_nand_switch_ecc(uint32_t, uint32_t);
+
+void rtc32k_enable(void);
+void uart_soft_reset(void);
#endif
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
index a851f1f..beaf0d6 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -22,8 +22,14 @@
#define __ASM_ARCH_PINMUX_DEFS_H
#include <asm/arch/davinci_misc.h>
+#include <config.h>
-/* SPI pin muxer settings */
+/* SPI0 pin muxer settings */
+extern const struct pinmux_config spi0_pins_base[3];
+extern const struct pinmux_config spi0_pins_scs0[1];
+extern const struct pinmux_config spi0_pins_ena[1];
+
+/* SPI1 pin muxer settings */
extern const struct pinmux_config spi1_pins_base[3];
extern const struct pinmux_config spi1_pins_scs0[1];
@@ -35,6 +41,7 @@
/* EMAC pin muxer settings*/
extern const struct pinmux_config emac_pins_rmii[7];
+extern const struct pinmux_config emac_pins_rmii_clk_source[1];
extern const struct pinmux_config emac_pins_mii[15];
extern const struct pinmux_config emac_pins_mdio[2];
@@ -43,13 +50,19 @@
extern const struct pinmux_config i2c1_pins[2];
/* EMIFA pin muxer settings */
+extern const struct pinmux_config emifa_pins[40];
+extern const struct pinmux_config emifa_pins_cs0[1];
extern const struct pinmux_config emifa_pins_cs2[1];
extern const struct pinmux_config emifa_pins_cs3[1];
extern const struct pinmux_config emifa_pins_cs4[1];
extern const struct pinmux_config emifa_pins_nand[12];
extern const struct pinmux_config emifa_pins_nor[43];
+/* USB pin mux setting */
+extern const struct pinmux_config usb_pins[1];
+
/* MMC pin muxer settings */
+extern const struct pinmux_config mmc0_pins_8bit[10];
extern const struct pinmux_config mmc0_pins[6];
#endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index f76e489..36b98c8 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -38,6 +38,7 @@
#define EXYNOS4_CLOCK_BASE 0x10030000
#define EXYNOS4_SYSTIMER_BASE 0x10050000
#define EXYNOS4_WATCHDOG_BASE 0x10060000
+#define EXYNOS4_TZPC_BASE 0x10110000
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_DMC0_BASE 0x10400000
#define EXYNOS4_DMC1_BASE 0x10410000
@@ -74,6 +75,7 @@
#define EXYNOS4X12_CLOCK_BASE 0x10030000
#define EXYNOS4X12_SYSTIMER_BASE 0x10050000
#define EXYNOS4X12_WATCHDOG_BASE 0x10060000
+#define EXYNOS4X12_TZPC_BASE 0x10110000
#define EXYNOS4X12_DMC0_BASE 0x10600000
#define EXYNOS4X12_DMC1_BASE 0x10610000
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
@@ -107,6 +109,7 @@
#define EXYNOS5_POWER_BASE 0x10040000
#define EXYNOS5_SWRESET 0x10040400
#define EXYNOS5_SYSREG_BASE 0x10050000
+#define EXYNOS5_TZPC_BASE 0x10100000
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
@@ -233,6 +236,7 @@
SAMSUNG_BASE(power, POWER_BASE)
SAMSUNG_BASE(spi, SPI_BASE)
SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+SAMSUNG_BASE(tzpc, TZPC_BASE)
#endif
#endif /* _EXYNOS4_CPU_H */
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 8acdf9b..3b147b8 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -27,10 +27,7 @@
#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
- unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
- return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);
diff --git a/arch/arm/include/asm/arch-exynos/tmu.h b/arch/arm/include/asm/arch-exynos/tmu.h
index 7e0158e..cad3569 100644
--- a/arch/arm/include/asm/arch-exynos/tmu.h
+++ b/arch/arm/include/asm/arch-exynos/tmu.h
@@ -21,38 +21,30 @@
#define __ASM_ARCH_TMU_H
struct exynos5_tmu_reg {
- unsigned triminfo;
- unsigned rsvd1;
- unsigned rsvd2;
- unsigned rsvd3;
- unsigned rsvd4;
- unsigned triminfo_control;
- unsigned rsvd5;
- unsigned rsvd6;
- unsigned tmu_control;
- unsigned rsvd7;
- unsigned tmu_status;
- unsigned sampling_internal;
- unsigned counter_value0;
- unsigned counter_value1;
- unsigned rsvd8;
- unsigned rsvd9;
- unsigned current_temp;
- unsigned rsvd10;
- unsigned rsvd11;
- unsigned rsvd12;
- unsigned threshold_temp_rise;
- unsigned threshold_temp_fall;
- unsigned rsvd13;
- unsigned rsvd14;
- unsigned past_temp3_0;
- unsigned past_temp7_4;
- unsigned past_temp11_8;
- unsigned past_temp15_12;
- unsigned inten;
- unsigned intstat;
- unsigned intclear;
- unsigned rsvd15;
- unsigned emul_con;
+ u32 triminfo;
+ u32 rsvd1[4];
+ u32 triminfo_control;
+ u32 rsvd5[2];
+ u32 tmu_control;
+ u32 rsvd7;
+ u32 tmu_status;
+ u32 sampling_internal;
+ u32 counter_value0;
+ u32 counter_value1;
+ u32 rsvd8[2];
+ u32 current_temp;
+ u32 rsvd10[3];
+ u32 threshold_temp_rise;
+ u32 threshold_temp_fall;
+ u32 rsvd13[2];
+ u32 past_temp3_0;
+ u32 past_temp7_4;
+ u32 past_temp11_8;
+ u32 past_temp15_12;
+ u32 inten;
+ u32 intstat;
+ u32 intclear;
+ u32 rsvd15;
+ u32 emul_con;
};
#endif /* __ASM_ARCH_TMU_H */
diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h
index c5eb4b1..4d9c3a3 100644
--- a/arch/arm/include/asm/arch-exynos/tzpc.h
+++ b/arch/arm/include/asm/arch-exynos/tzpc.h
@@ -47,6 +47,26 @@
unsigned int pcellid2;
unsigned int pcellid3;
};
+
+#define EXYNOS4_NR_TZPC_BANKS 6
+#define EXYNOS5_NR_TZPC_BANKS 10
+
+/* TZPC : Register Offsets */
+#define TZPC_BASE_OFFSET 0x10000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET 0xFF
+void tzpc_init(void);
+
#endif
#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/bits.h b/arch/arm/include/asm/arch-omap24xx/bits.h
deleted file mode 100644
index 8522335..0000000
--- a/arch/arm/include/asm/arch-omap24xx/bits.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* bits.h
- * Copyright (c) 2004 Texas Instruments
- *
- * This package is free software; you can redistribute it and/or
- * modify it under the terms of the license found in the file
- * named COPYING that should have accompanied this file.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-#ifndef __bits_h
-#define __bits_h 1
-
-#define BIT0 (1<<0)
-#define BIT1 (1<<1)
-#define BIT2 (1<<2)
-#define BIT3 (1<<3)
-#define BIT4 (1<<4)
-#define BIT5 (1<<5)
-#define BIT6 (1<<6)
-#define BIT7 (1<<7)
-#define BIT8 (1<<8)
-#define BIT9 (1<<9)
-#define BIT10 (1<<10)
-#define BIT11 (1<<11)
-#define BIT12 (1<<12)
-#define BIT13 (1<<13)
-#define BIT14 (1<<14)
-#define BIT15 (1<<15)
-#define BIT16 (1<<16)
-#define BIT17 (1<<17)
-#define BIT18 (1<<18)
-#define BIT19 (1<<19)
-#define BIT20 (1<<20)
-#define BIT21 (1<<21)
-#define BIT22 (1<<22)
-#define BIT23 (1<<23)
-#define BIT24 (1<<24)
-#define BIT25 (1<<25)
-#define BIT26 (1<<26)
-#define BIT27 (1<<27)
-#define BIT28 (1<<28)
-#define BIT29 (1<<29)
-#define BIT30 (1<<30)
-#define BIT31 (1<<31)
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/clocks.h b/arch/arm/include/asm/arch-omap24xx/clocks.h
deleted file mode 100644
index 2e92569..0000000
--- a/arch/arm/include/asm/arch-omap24xx/clocks.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_CLOCKS_H_
-#define _OMAP24XX_CLOCKS_H_
-
-#define COMMIT_DIVIDERS 0x1
-
-#define MODE_BYPASS_FAST 0x2
-#define APLL_LOCK 0xc
-#ifdef CONFIG_APTIX
-#define DPLL_LOCK 0x1 /* stay in bypass mode */
-#else
-#define DPLL_LOCK 0x3 /* DPLL lock */
-#endif
-
-/****************************************************************************;
-; PRCM Scheme II
-;
-; Enable clocks and DPLL for:
-; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50
-; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0]
-; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0]
-; DSPI=100 6 CM_CLKSEL_DSP[6:5]
-; DSP_S bypass CM_CLKSEL_DSP[7]
-; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8]
-; IVAF=100 auto
-; IVAI auto
-; IVA_MPU auto
-; IVA_S bypass CM_CLKSEL_DSP[13]
-; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0]
-; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20]
-; SSI_SSTF=100 auto
-; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0]
-; L4=100Mhz 6
-; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define II_DPLL_OUT_X2 0x2 /* x2 core out */
-#define II_MPU_DIV 0x2 /* mpu = core/2 */
-#define II_DSP_DIV 0x343 /* dsp & iva divider */
-#define II_GFX_DIV 0x2
-#define II_BUS_DIV 0x04601026
-#define II_DPLL_300 0x01832100
-
-/****************************************************************************;
-; PRCM Scheme III
-;
-; Enable clocks and DPLL for:
-; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266
-; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0]
-; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0]
-; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0]
-; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5]
-; DSP_S ACTIVATED CM_CLKSEL_DSP[7]
-; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8]
-; IVAF=88.67 auto
-; IVAI auto
-; IVA_MPU auto
-; IVA_S ACTIVATED CM_CLKSEL_DSP[13]
-; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]:
-; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20]
-; SSI_SSTF=88.67 auto
-; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0]
-; L4=66.5Mhz /8
-; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5]
-***************************************************************************/
-#define III_DPLL_OUT_X2 0x2 /* x2 core out */
-#define III_MPU_DIV 0x2 /* mpu = core/2 */
-#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/
-#define III_GFX_DIV 0x2
-#define III_BUS_DIV 0x08301044
-#define III_DPLL_266 0x01885500
-
-/* set defaults for boot up */
-#ifdef PRCM_CONFIG_II
-# define DPLL_OUT II_DPLL_OUT_X2
-# define MPU_DIV II_MPU_DIV
-# define DSP_DIV II_DSP_DIV
-# define GFX_DIV II_GFX_DIV
-# define BUS_DIV II_BUS_DIV
-# define DPLL_VAL II_DPLL_300
-#elif PRCM_CONFIG_III
-# define DPLL_OUT III_DPLL_OUT_X2
-# define MPU_DIV III_MPU_DIV
-# define DSP_DIV III_DSP_DIV
-# define GFX_DIV III_GFX_DIV
-# define BUS_DIV III_BUS_DIV
-# define DPLL_VAL III_DPLL_266
-#endif
-
-/* lock delay time out */
-#define LDELAY 12000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h
deleted file mode 100644
index 6f64519..0000000
--- a/arch/arm/include/asm/arch-omap24xx/i2c.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_I2C_H_
-#define _OMAP24XX_I2C_H_
-
-#define I2C_BASE1 0x48070000
-#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */
-
-#define I2C_DEFAULT_BASE I2C_BASE1
-
-struct i2c {
- unsigned short rev; /* 0x00 */
- unsigned short res1;
- unsigned short ie; /* 0x04 */
- unsigned short res2;
- unsigned short stat; /* 0x08 */
- unsigned short res3;
- unsigned short iv; /* 0x0C */
- unsigned short res4;
- unsigned short syss; /* 0x10 */
- unsigned short res4p1;
- unsigned short buf; /* 0x14 */
- unsigned short res5;
- unsigned short cnt; /* 0x18 */
- unsigned short res6;
- unsigned short data; /* 0x1C */
- unsigned short res7;
- unsigned short sysc; /* 0x20 */
- unsigned short res8;
- unsigned short con; /* 0x24 */
- unsigned short res9;
- unsigned short oa; /* 0x28 */
- unsigned short res10;
- unsigned short sa; /* 0x2C */
- unsigned short res11;
- unsigned short psc; /* 0x30 */
- unsigned short res12;
- unsigned short scll; /* 0x34 */
- unsigned short res13;
- unsigned short sclh; /* 0x38 */
- unsigned short res14;
- unsigned short systest; /* 0x3c */
- unsigned short res15;
-};
-
-#define I2C_BUS_MAX 2
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/mem.h b/arch/arm/include/asm/arch-omap24xx/mem.h
deleted file mode 100644
index 42e8ab2..0000000
--- a/arch/arm/include/asm/arch-omap24xx/mem.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_MEM_H_
-#define _OMAP24XX_MEM_H_
-
-#define SDRC_CS0_OSET 0x0
-#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
-
-#ifndef __ASSEMBLY__
-/* struct's for holding data tables for current boards, they are getting used
- early in init when NO global access are there */
-struct sdrc_data_s {
- u32 sdrc_sharing;
- u32 sdrc_mdcfg_0_ddr;
- u32 sdrc_mdcfg_0_sdr;
- u32 sdrc_actim_ctrla_0;
- u32 sdrc_actim_ctrlb_0;
- u32 sdrc_rfr_ctrl;
- u32 sdrc_mr_0_ddr;
- u32 sdrc_mr_0_sdr;
- u32 sdrc_dllab_ctrl;
-} /*__attribute__ ((packed))*/;
-typedef struct sdrc_data_s sdrc_data_t;
-
-typedef enum {
- STACKED = 0,
- IP_DDR = 1,
- COMBO_DDR = 2,
- IP_SDR = 3,
-} mem_t;
-
-#endif
-
-/* Slower full frequency range default timings for x32 operation*/
-#define H4_2420_SDRC_SHARING 0x00000100
-#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
-#define H4_2420_SDRC_MR_0_SDR 0x00000031
-#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
-#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
-#define H4_2420_SDRC_MR_0_DDR 0x00000032
-
-#define H4_2422_SDRC_SHARING 0x00004b00
-#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */
-#define H4_2422_SDRC_MR_0_DDR 0x00000032
-
-/* ES1 work around timings */
-#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */
-#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020
-#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */
-
-/* optimized timings good for current shipping parts */
-#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
-#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
-#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */
-#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
-#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01
-#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
-#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/
-#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */
-
-#ifdef PRCM_CONFIG_II
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
-#elif PRCM_CONFIG_III
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz
-# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
-#endif
-
-
-/* GPMC settings */
-#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
-# ifdef CONFIG_SYS_NAND_BOOT
-# define H4_24XX_GPMC_CONFIG1_0 0x0
-# define H4_24XX_GPMC_CONFIG2_0 0x00141400
-# define H4_24XX_GPMC_CONFIG3_0 0x00141400
-# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
-# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
-# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
-# else /* else NOR */
-# define H4_24XX_GPMC_CONFIG1_0 0x3
-# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
-# define H4_24XX_GPMC_CONFIG3_0 0x00050502
-# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
-# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
-# endif /* endif CONFIG_SYS_NAND_BOOT */
-# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
-# define H4_24XX_GPMC_CONFIG1_1 0x00011000
-# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00
-# define H4_24XX_GPMC_CONFIG3_1 0x00080802
-# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
-# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F
-# define H4_24XX_GPMC_CONFIG6_1 0x000003C2
-# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
-#endif /* endif PRCM_CONFIG_II */
-
-#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
-# ifdef CONFIG_SYS_NAND_BOOT
-# define H4_24XX_GPMC_CONFIG1_0 0x0
-# define H4_24XX_GPMC_CONFIG2_0 0x00141400
-# define H4_24XX_GPMC_CONFIG3_0 0x00141400
-# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
-# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
-# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
-# else /* NOR boot */
-# define H4_24XX_GPMC_CONFIG1_0 0x3
-# define H4_24XX_GPMC_CONFIG2_0 0x00151501
-# define H4_24XX_GPMC_CONFIG3_0 0x00060602
-# define H4_24XX_GPMC_CONFIG4_0 0x10081008
-# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
-# define H4_24XX_GPMC_CONFIG6_0 0x000004c4
-# endif /* endif CONFIG_SYS_NAND_BOOT */
-# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
-# define H4_24XX_GPMC_CONFIG1_1 0x00011000
-# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
-# define H4_24XX_GPMC_CONFIG3_1 0x00080803
-# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
-# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
-# define H4_24XX_GPMC_CONFIG6_1 0x000004C4
-# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
-#endif /* endif CONFIG_SYS_PRCM_III */
-
-#endif /* endif _OMAP24XX_MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap24xx/mux.h b/arch/arm/include/asm/arch-omap24xx/mux.h
deleted file mode 100644
index 4fdb9c6..0000000
--- a/arch/arm/include/asm/arch-omap24xx/mux.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP2420_MUX_H_
-#define _OMAP2420_MUX_H_
-
-#ifndef __ASSEMBLY__
-typedef unsigned char uint8;
-typedef unsigned int uint32;
-
-void muxSetupSDRC(void);
-void muxSetupGPMC(void);
-void muxSetupUsb0(void);
-void muxSetupUsbHost(void);
-void muxSetupUart3(void);
-void muxSetupI2C1(void);
-void muxSetupUART1(void);
-void muxSetupLCD(void);
-void muxSetupCamera(void);
-void muxSetupMMCSD(void) ;
-void muxSetupTouchScreen(void) ;
-void muxSetupHDQ(void);
-#endif
-
-#define USB_OTG_CTRL ((volatile uint32 *)0x4805E30C)
-
-/* Pin Muxing registers used for HDQ (Smart battery) */
-#define CONTROL_PADCONF_HDQ_SIO ((volatile unsigned char *)0x48000115)
-
-/* Pin Muxing registers used for GPMC */
-#define CONTROL_PADCONF_GPMC_D2_BYTE0 ((volatile unsigned char *)0x48000088)
-#define CONTROL_PADCONF_GPMC_D2_BYTE1 ((volatile unsigned char *)0x48000089)
-#define CONTROL_PADCONF_GPMC_D2_BYTE2 ((volatile unsigned char *)0x4800008A)
-#define CONTROL_PADCONF_GPMC_D2_BYTE3 ((volatile unsigned char *)0x4800008B)
-
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE0 ((volatile unsigned char *)0x4800008C)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE4 (0x48000090)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE5 (0x48000091)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE6 (0x48000092)
-#define CONTROL_PADCONF_GPMC_NCS0_BYTE7 (0x48000093)
-
-/* Pin Muxing registers used for SDRC */
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2)
-#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3)
-
-#define CONTROL_PADCONF_SDRC_A14_BYTE0 ((volatile unsigned char *)0x48000030)
-#define CONTROL_PADCONF_SDRC_A14_BYTE1 ((volatile unsigned char *)0x48000031)
-#define CONTROL_PADCONF_SDRC_A14_BYTE2 ((volatile unsigned char *)0x48000032)
-#define CONTROL_PADCONF_SDRC_A14_BYTE3 ((volatile unsigned char *)0x48000033)
-
-/* Pin Muxing registers used for Touch Screen (SPI) */
-#define CONTROL_PADCONF_SPI1_CLK ((volatile unsigned char *)0x480000FF)
-#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100)
-#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101)
-#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102)
-#define CONTROL_PADCONF_SPI1_NCS1 (0x48000103)
-
-#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B)
-
-/* Pin Muxing registers used for MMCSD */
-#define CONTROL_PADCONF_MMC_CLKI ((volatile unsigned char *)0x480000FE)
-#define CONTROL_PADCONF_MMC_CLKO ((volatile unsigned char *)0x480000F3)
-#define CONTROL_PADCONF_MMC_CMD ((volatile unsigned char *)0x480000F4)
-#define CONTROL_PADCONF_MMC_DAT0 ((volatile unsigned char *)0x480000F5)
-#define CONTROL_PADCONF_MMC_DAT1 ((volatile unsigned char *)0x480000F6)
-#define CONTROL_PADCONF_MMC_DAT2 ((volatile unsigned char *)0x480000F7)
-#define CONTROL_PADCONF_MMC_DAT3 ((volatile unsigned char *)0x480000F8)
-#define CONTROL_PADCONF_MMC_DAT_DIR0 ((volatile unsigned char *)0x480000F9)
-#define CONTROL_PADCONF_MMC_DAT_DIR1 ((volatile unsigned char *)0x480000FA)
-#define CONTROL_PADCONF_MMC_DAT_DIR2 ((volatile unsigned char *)0x480000FB)
-#define CONTROL_PADCONF_MMC_DAT_DIR3 ((volatile unsigned char *)0x480000FC)
-#define CONTROL_PADCONF_MMC_CMD_DIR ((volatile unsigned char *)0x480000FD)
-
-#define CONTROL_PADCONF_SDRC_A14 ((volatile unsigned char *)0x48000030)
-#define CONTROL_PADCONF_SDRC_A13 ((volatile unsigned char *)0x48000031)
-
-/* Pin Muxing registers used for CAMERA */
-#define CONTROL_PADCONF_SYS_NRESWARM ((volatile unsigned char *)0x4800012B)
-
-#define CONTROL_PADCONF_CAM_XCLK ((volatile unsigned char *)0x480000DC)
-#define CONTROL_PADCONF_CAM_LCLK ((volatile unsigned char *)0x480000DB)
-#define CONTROL_PADCONF_CAM_VS ((volatile unsigned char *)0x480000DA)
-#define CONTROL_PADCONF_CAM_HS ((volatile unsigned char *)0x480000D9)
-#define CONTROL_PADCONF_CAM_D0 ((volatile unsigned char *)0x480000D8)
-#define CONTROL_PADCONF_CAM_D1 ((volatile unsigned char *)0x480000D7)
-#define CONTROL_PADCONF_CAM_D2 ((volatile unsigned char *)0x480000D6)
-#define CONTROL_PADCONF_CAM_D3 ((volatile unsigned char *)0x480000D5)
-#define CONTROL_PADCONF_CAM_D4 ((volatile unsigned char *)0x480000D4)
-#define CONTROL_PADCONF_CAM_D5 ((volatile unsigned char *)0x480000D3)
-#define CONTROL_PADCONF_CAM_D6 ((volatile unsigned char *)0x480000D2)
-#define CONTROL_PADCONF_CAM_D7 ((volatile unsigned char *)0x480000D1)
-#define CONTROL_PADCONF_CAM_D8 ((volatile unsigned char *)0x480000D0)
-#define CONTROL_PADCONF_CAM_D9 ((volatile unsigned char *)0x480000CF)
-
-/* Pin Muxing registers used for LCD */
-#define CONTROL_PADCONF_DSS_D0 ((volatile unsigned char *)0x480000B3)
-#define CONTROL_PADCONF_DSS_D1 ((volatile unsigned char *)0x480000B4)
-#define CONTROL_PADCONF_DSS_D2 ((volatile unsigned char *)0x480000B5)
-#define CONTROL_PADCONF_DSS_D3 ((volatile unsigned char *)0x480000B6)
-#define CONTROL_PADCONF_DSS_D4 ((volatile unsigned char *)0x480000B7)
-#define CONTROL_PADCONF_DSS_D5 ((volatile unsigned char *)0x480000B8)
-#define CONTROL_PADCONF_DSS_D6 ((volatile unsigned char *)0x480000B9)
-#define CONTROL_PADCONF_DSS_D7 ((volatile unsigned char *)0x480000BA)
-#define CONTROL_PADCONF_DSS_D8 ((volatile unsigned char *)0x480000BB)
-#define CONTROL_PADCONF_DSS_D9 ((volatile unsigned char *)0x480000BC)
-#define CONTROL_PADCONF_DSS_D10 ((volatile unsigned char *)0x480000BD)
-#define CONTROL_PADCONF_DSS_D11 ((volatile unsigned char *)0x480000BE)
-#define CONTROL_PADCONF_DSS_D12 ((volatile unsigned char *)0x480000BF)
-#define CONTROL_PADCONF_DSS_D13 ((volatile unsigned char *)0x480000C0)
-#define CONTROL_PADCONF_DSS_D14 ((volatile unsigned char *)0x480000C1)
-#define CONTROL_PADCONF_DSS_D15 ((volatile unsigned char *)0x480000C2)
-#define CONTROL_PADCONF_DSS_D16 ((volatile unsigned char *)0x480000C3)
-#define CONTROL_PADCONF_DSS_D17 ((volatile unsigned char *)0x480000C4)
-#define CONTROL_PADCONF_DSS_PCLK ((volatile unsigned char *)0x480000CB)
-#define CONTROL_PADCONF_DSS_VSYNC ((volatile unsigned char *)0x480000CC)
-#define CONTROL_PADCONF_DSS_HSYNC ((volatile unsigned char *)0x480000CD)
-#define CONTROL_PADCONF_DSS_ACBIAS ((volatile unsigned char *)0x480000CE)
-
-/* Pin Muxing registers used for UART1 */
-#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5)
-#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6)
-#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7)
-#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8)
-
-/* Pin Muxing registers used for I2C1 */
-#define CONTROL_PADCONF_I2C1_SCL ((volatile unsigned char *)0x48000111)
-#define CONTROL_PADCONF_I2C1_SDA ((volatile unsigned char *)0x48000112)
-
-/* Pin Muxing registres used for USB0. */
-#define CONTROL_PADCONF_USB0_PUEN ((volatile uint8 *)0x4800011D)
-#define CONTROL_PADCONF_USB0_VP ((volatile uint8 *)0x4800011E)
-#define CONTROL_PADCONF_USB0_VM ((volatile uint8 *)0x4800011F)
-#define CONTROL_PADCONF_USB0_RCV ((volatile uint8 *)0x48000120)
-#define CONTROL_PADCONF_USB0_TXEN ((volatile uint8 *)0x48000121)
-#define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122)
-#define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123)
-
-/* Pin Muxing registres used for USB1. */
-#define CONTROL_PADCONF_USB1_RCV (0x480000EB)
-#define CONTROL_PADCONF_USB1_TXEN (0x480000EC)
-
-/* Pin Muxing registers used for UART3/IRDA */
-#define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118)
-#define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119)
-
-/* Pin Muxing registers used for GPIO */
-#define CONTROL_PADCONF_GPIO69 (0x480000ED)
-#define CONTROL_PADCONF_GPIO70 (0x480000EE)
-#define CONTROL_PADCONF_GPIO102 (0x48000116)
-#define CONTROL_PADCONF_GPIO103 (0x48000117)
-#define CONTROL_PADCONF_GPIO104 (0x48000118)
-#define CONTROL_PADCONF_GPIO105 (0x48000119)
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h
deleted file mode 100644
index 5724f5d..0000000
--- a/arch/arm/include/asm/arch-omap24xx/omap2420.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP2420_SYS_H_
-#define _OMAP2420_SYS_H_
-
-#include <asm/sizes.h>
-
-/*
- * 2420 specific Section
- */
-
-/* L3 Firewall */
-#define A_REQINFOPERM0 0x68005048
-#define A_READPERM0 0x68005050
-#define A_WRITEPERM0 0x68005058
-/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */
-
-/* L3 Firewall */
-#define A_REQINFOPERM0 0x68005048
-#define A_READPERM0 0x68005050
-#define A_WRITEPERM0 0x68005058
-
-/* CONTROL */
-#define OMAP2420_CTRL_BASE (0x48000000)
-#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8)
-
-/* device type */
-#define TST_DEVICE 0x0
-#define EMU_DEVICE 0x1
-#define HS_DEVICE 0x2
-#define GP_DEVICE 0x3
-
-/* TAP information */
-#define OMAP2420_TAP_BASE (0x48014000)
-#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204)
-#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208)
-
-/* GPMC */
-#define OMAP2420_GPMC_BASE (0x6800A000)
-#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10)
-#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C)
-#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40)
-#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50)
-#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60)
-#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64)
-#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68)
-#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C)
-#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70)
-#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74)
-#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78)
-#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90)
-#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94)
-#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98)
-#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C)
-#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0)
-#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4)
-#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8)
-#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0)
-#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4)
-#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8)
-#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC)
-#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0)
-#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4)
-#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8)
-#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0)
-#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4)
-#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8)
-#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC)
-#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100)
-#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104)
-#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108)
-
-/* SMS */
-#define OMAP2420_SMS_BASE 0x68008000
-#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10)
-#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0)
-# define BURSTCOMPLETE_GROUP7 BIT31
-
-/* SDRC */
-#define OMAP2420_SDRC_BASE 0x68009000
-#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10)
-#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14)
-#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40)
-#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44)
-#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60)
-#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68)
-#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70)
-#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80)
-#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84)
-#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
-#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
-#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
-#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
-#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4)
-#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8)
-#define OMAP2420_SDRC_CS0 0x80000000
-#define OMAP2420_SDRC_CS1 0xA0000000
-#define CMD_NOP 0x0
-#define CMD_PRECHARGE 0x1
-#define CMD_AUTOREFRESH 0x2
-#define CMD_ENTR_PWRDOWN 0x3
-#define CMD_EXIT_PWRDOWN 0x4
-#define CMD_ENTR_SRFRSH 0x5
-#define CMD_CKE_HIGH 0x6
-#define CMD_CKE_LOW 0x7
-#define SOFTRESET BIT1
-#define SMART_IDLE (0x2 << 3)
-#define REF_ON_IDLE (0x1 << 6)
-
-
-/* UART */
-#define OMAP2420_UART1 0x4806A000
-#define OMAP2420_UART2 0x4806C000
-#define OMAP2420_UART3 0x4806E000
-
-/* General Purpose Timers */
-#define OMAP2420_GPT1 0x48028000
-#define OMAP2420_GPT2 0x4802A000
-#define OMAP2420_GPT3 0x48078000
-#define OMAP2420_GPT4 0x4807A000
-#define OMAP2420_GPT5 0x4807C000
-#define OMAP2420_GPT6 0x4807E000
-#define OMAP2420_GPT7 0x48080000
-#define OMAP2420_GPT8 0x48082000
-#define OMAP2420_GPT9 0x48084000
-#define OMAP2420_GPT10 0x48086000
-#define OMAP2420_GPT11 0x48088000
-#define OMAP2420_GPT12 0x4808A000
-
-/* timer regs offsets (32 bit regs) */
-#define TIDR 0x0 /* r */
-#define TIOCP_CFG 0x10 /* rw */
-#define TISTAT 0x14 /* r */
-#define TISR 0x18 /* rw */
-#define TIER 0x1C /* rw */
-#define TWER 0x20 /* rw */
-#define TCLR 0x24 /* rw */
-#define TCRR 0x28 /* rw */
-#define TLDR 0x2C /* rw */
-#define TTGR 0x30 /* rw */
-#define TWPS 0x34 /* r */
-#define TMAR 0x38 /* rw */
-#define TCAR1 0x3c /* r */
-#define TSICR 0x40 /* rw */
-#define TCAR2 0x44 /* r */
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE 0x48020000
-#define WD2_BASE 0x48022000
-#define WD3_BASE 0x48024000
-#define WD4_BASE 0x48026000
-#define WWPS 0x34 /* r */
-#define WSPR 0x48 /* rw */
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-/* PRCM */
-#define OMAP2420_CM_BASE 0x48008000
-#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
-#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140)
-#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200)
-#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204)
-#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210)
-#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214)
-#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240)
-#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440)
-#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244)
-#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340)
-#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450)
-#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500)
-#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520)
-#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540)
-#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544)
-#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840)
-
-/*
- * H4 specific Section
- */
-
-/*
- * The 2420's chip selects are programmable. The mask ROM
- * does configure CS0 to 0x08000000 before dispatch. So, if
- * you want your code to live below that address, you have to
- * be prepared to jump though hoops, to reset the base address.
- */
-#if defined(CONFIG_OMAP2420H4)
-/* GPMC */
-#ifdef CONFIG_VIRTIO_A /* Pre version B */
-# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
-# define H4_CS1_BASE 0x04000000 /* debug board */
-# define H4_CS2_BASE 0x0A000000 /* wifi board */
-#else
-# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */
-# define H4_CS1_BASE 0x04000000 /* debug board */
-# define H4_CS2_BASE 0x0C000000 /* wifi board */
-#endif
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0 0x40000000
-#define SRAM_OFFSET1 0x00200000
-#define SRAM_OFFSET2 0x0000F800
-#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-
-/* FPGA on Debug board.*/
-#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b)
-#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c)
-#endif /* endif CONFIG_2420H4 */
-
-/* Common */
-#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
-
-#define PERIFERAL_PORT_BASE 0x480FE003
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/sys_info.h b/arch/arm/include/asm/arch-omap24xx/sys_info.h
deleted file mode 100644
index 53c231a..0000000
--- a/arch/arm/include/asm/arch-omap24xx/sys_info.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _OMAP24XX_SYS_INFO_H_
-#define _OMAP24XX_SYS_INFO_H_
-
-typedef struct h4_system_data {
- /* base board info */
- u32 base_b_rev; /* rev from base board i2c */
- /* cpu board info */
- u32 cpu_b_rev; /* rev from cpu board i2c */
- u32 cpu_b_mux; /* mux type on daughter board */
- u32 cpu_b_ddr_type; /* mem type */
- u32 cpu_b_ddr_speed; /* ddr speed rating */
- u32 cpu_b_switches; /* boot ctrl switch settings */
- /* cpu info */
- u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/
- u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
-} h4_sys_data;
-
-#define XDR_POP 5 /* package on package part */
-#define SDR_DISCRETE 4 /* 128M memory SDR module*/
-#define DDR_STACKED 3 /* stacked part on 2422 */
-#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
-#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
-
-#define DDR_100 100 /* type found on most mem d-boards */
-#define DDR_111 111 /* some combo parts */
-#define DDR_133 133 /* most combo, some mem d-boards */
-#define DDR_165 165 /* future parts */
-
-#define CPU_2420 0x2420
-#define CPU_2422 0x2422 /* 2420 + 64M stacked */
-#define CPU_2423 0x2423 /* 2420 + 96M stacked */
-
-#define CPU_2422_ES1 1
-#define CPU_2422_ES2 2
-#define CPU_2420_ES1 1
-#define CPU_2420_ES2 2
-#define CPU_2420_2422_ES1 1
-
-#define CPU_2420_CHIPID 0x0B5D9000
-#define CPU_24XX_ID_MASK 0x0FFFF000
-#define CPU_242X_REV_MASK 0xF0000000
-#define CPU_242X_PID_MASK 0x000F0000
-
-#define BOARD_H4_MENELAUS 1
-#define BOARD_H4_SDP 2
-
-#define GPMC_MUXED 1
-#define GPMC_NONMUXED 0
-
-#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */
-#define TYPE_NOR 0x000
-
-#define WIDTH_8BIT 0x0000
-#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
-
-#define I2C_MENELAUS 0x72 /* i2c id for companion chip */
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap24xx/sys_proto.h b/arch/arm/include/asm/arch-omap24xx/sys_proto.h
deleted file mode 100644
index 9d8e5b2..0000000
--- a/arch/arm/include/asm/arch-omap24xx/sys_proto.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _OMAP24XX_SYS_PROTO_H_
-#define _OMAP24XX_SYS_PROTO_H_
-
-void prcm_init(void);
-void memif_init(void);
-void sdrc_init(void);
-void do_sdrc_init(u32,u32);
-void gpmc_init(void);
-
-void ether_init(void);
-void watchdog_init(void);
-void set_muxconf_regs(void);
-void peripheral_enable(void);
-
-u32 get_cpu_type(void);
-u32 get_cpu_rev(void);
-u32 get_mem_type(void);
-u32 get_sysboot_value(void);
-u32 get_gpmc0_base(void);
-u32 is_gpmc_muxed(void);
-u32 get_gpmc0_type(void);
-u32 get_gpmc0_width(void);
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
-u32 get_board_type(void);
-void display_board_info(u32);
-void update_mux(u32,u32);
-u32 get_sdr_cs_size(u32 offset);
-
-u32 running_in_sdram(void);
-u32 running_in_sram(void);
-u32 running_in_flash(void);
-u32 running_from_internal_boot(void);
-u32 get_device_type(void);
-#endif
diff --git a/arch/arm/include/asm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clock.h
similarity index 100%
rename from arch/arm/include/asm/arch-omap3/clocks.h
rename to arch/arm/include/asm/arch-omap3/clock.h
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index 2b5e9ae..c57599a 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -253,4 +253,11 @@
#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME 30
+#define OMAP_ABB_CLOCK_CYCLES 8
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26)
+
#endif
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clock.h
similarity index 89%
rename from arch/arm/include/asm/arch-omap4/clocks.h
rename to arch/arm/include/asm/arch-omap4/clock.h
index ed7a1c8..d14d8fb 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clock.h
@@ -34,25 +34,6 @@
*/
#define LDELAY 1000000
-#define CM_CLKMODE_DPLL_CORE 0x4A004120
-#define CM_CLKMODE_DPLL_PER 0x4A008140
-#define CM_CLKMODE_DPLL_MPU 0x4A004160
-#define CM_CLKSEL_CORE 0x4A004100
-
-/* DPLL register offsets */
-#define CM_CLKMODE_DPLL 0
-#define CM_IDLEST_DPLL 0x4
-#define CM_AUTOIDLE_DPLL 0x8
-#define CM_CLKSEL_DPLL 0xC
-#define CM_DIV_M2_DPLL 0x10
-#define CM_DIV_M3_DPLL 0x14
-#define CM_DIV_M4_DPLL 0x18
-#define CM_DIV_M5_DPLL 0x1C
-#define CM_DIV_M6_DPLL 0x20
-#define CM_DIV_M7_DPLL 0x24
-
-#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
-
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
@@ -94,10 +75,8 @@
#define CM_CLKSEL_DCC_EN_SHIFT 22
#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
-#define OMAP4_DPLL_MAX_N 127
-
/* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT 0
@@ -181,9 +160,7 @@
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
/* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
-#define OMAP_32K_CLK_FREQ 32768
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
@@ -234,14 +211,13 @@
#define ALTCLKSRC_MODE_ACTIVE 1
-/* Defines for DPLL setup */
-#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
-#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
-#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
-
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
+/* Clock Defines */
+#define V_OSCK 38400000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
struct omap4_scrm_regs {
u32 revision; /* 0x0000 */
u32 pad00[63];
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 3a0bfbf..311c6ff 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -115,18 +115,6 @@
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
-#define SYSCLKDIV_1 (0x1 << 6)
-#define SYSCLKDIV_2 (0x1 << 7)
-
-#define CLKSEL_GPT1 (0x1 << 0)
-
-#define EN_GPT1 (0x1 << 0)
-#define EN_32KSYNC (0x1 << 2)
-
-#define ST_WDT2 (0x1 << 5)
-
-#define RESETDONE (0x1 << 0)
-
#define TCLR_ST (0x1 << 0)
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 44353a4..9fd00ff 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -47,14 +47,6 @@
#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
-/* CONTROL */
-#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
-#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
-
-/* LPDDR2 IO regs */
-#define LPDDR2_IO_REGS_BASE 0x4A100638
-
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
@@ -79,15 +71,9 @@
/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
-
/* GPMC */
#define OMAP44XX_GPMC_BASE 0x50000000
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
-
/*
* Hardware Register Details
*/
@@ -144,4 +130,12 @@
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME 50
+#define OMAP_ABB_CLOCK_CYCLES 16
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
+
#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index ef85594..e413466 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -22,7 +22,7 @@
#define _SYS_PROTO_H_
#include <asm/arch/omap.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/omap_common.h>
#include <asm/arch/mux_omap4.h>
@@ -57,7 +57,8 @@
void save_omap_boot_params(void);
void init_omap_revision(void);
void do_io_settings(void);
-void omap_vc_init(u16 speed_khz);
+void sri2c_init(void);
+void gpi2c_init(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clock.h
similarity index 73%
rename from arch/arm/include/asm/arch-omap5/clocks.h
rename to arch/arm/include/asm/arch-omap5/clock.h
index 68afa76..4d2765d 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -35,19 +35,6 @@
*/
#define LDELAY 1000000
-#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120)
-#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140)
-#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
-#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
-
-/* DPLL register offsets */
-#define CM_CLKMODE_DPLL 0
-#define CM_IDLEST_DPLL 0x4
-#define CM_AUTOIDLE_DPLL 0x8
-#define CM_CLKSEL_DPLL 0xC
-
-#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
-
/* CM_DLL_CTRL */
#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
@@ -93,10 +80,8 @@
#define CM_CLKSEL_DCC_EN_SHIFT 22
#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
-#define OMAP4_DPLL_MAX_N 127
-
/* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT 0
@@ -113,6 +98,12 @@
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
+/* CM_CLKSEL_ABE_PLL_SYS */
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1
+
/* CM_BYPCLK_DPLL_IVA */
#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
@@ -195,9 +186,7 @@
#define RSTTIME1_MASK (0x3ff << 0)
/* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
-#define OMAP_32K_CLK_FREQ 32768
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
@@ -229,9 +218,54 @@
#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880
+/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
+#define VDD_MPU_DRA752 1090
+#define VDD_EVE_DRA752 1060
+#define VDD_GPU_DRA752 1060
+#define VDD_CORE_DRA752 1030
+#define VDD_IVA_DRA752 1060
+
+/* Efuse register offsets for DRA7xx platform */
+#define DRA752_EFUSE_BASE 0x4A002000
+#define DRA752_EFUSE_REGBITS 16
+/* STD_FUSE_OPP_VMIN_IVA_2 */
+#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC)
+/* STD_FUSE_OPP_VMIN_IVA_3 */
+#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0)
+/* STD_FUSE_OPP_VMIN_IVA_4 */
+#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_2 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0)
+/* STD_FUSE_OPP_VMIN_DSPEVE_3 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_4 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8)
+/* STD_FUSE_OPP_VMIN_CORE_2 */
+#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4)
+/* STD_FUSE_OPP_VMIN_GPU_2 */
+#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08)
+/* STD_FUSE_OPP_VMIN_GPU_3 */
+#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C)
+/* STD_FUSE_OPP_VMIN_GPU_4 */
+#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10)
+/* STD_FUSE_OPP_VMIN_MPU_2 */
+#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20)
+/* STD_FUSE_OPP_VMIN_MPU_3 */
+#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24)
+/* STD_FUSE_OPP_VMIN_MPU_4 */
+#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
+
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
+/* TPS659038 */
+#define TPS659038_I2C_SLAVE_ADDR 0x58
+#define TPS659038_REG_ADDR_SMPS12_MPU 0x23
+#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B
+#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F
+#define TPS659038_REG_ADDR_SMPS7_CORE 0x33
+#define TPS659038_REG_ADDR_SMPS8_IVA 0x37
+
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
#define TPS62361_REG_ADDR_SET0 0x0
@@ -261,4 +295,25 @@
* into microsec and passing the value.
*/
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
+
+#ifdef CONFIG_DRA7XX
+#define V_OSCK 20000000 /* Clock output from T2 */
+#else
+#define V_OSCK 19200000 /* Clock output from T2 */
+#endif
+
+#define V_SCLK V_OSCK
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK (1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT 1
+#define AUXCLK_SRCSELECT_MASK (3 << 1)
+#define AUXCLK_CLKDIV_SHIFT 16
+#define AUXCLK_CLKDIV_MASK (0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK 0
+#define AUXCLK_SRCSELECT_CORE_DPLL 1
+#define AUXCLK_SRCSELECT_PER_DPLL 2
+#define AUXCLK_SRCSELECT_ALTERNATE 3
+
#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 044ab55..4753f46 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -119,18 +119,6 @@
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
-#define SYSCLKDIV_1 (0x1 << 6)
-#define SYSCLKDIV_2 (0x1 << 7)
-
-#define CLKSEL_GPT1 (0x1 << 0)
-
-#define EN_GPT1 (0x1 << 0)
-#define EN_32KSYNC (0x1 << 2)
-
-#define ST_WDT2 (0x1 << 5)
-
-#define RESETDONE (0x1 << 0)
-
#define TCLR_ST (0x1 << 0)
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
index 55e9de6..5f2b0f9 100644
--- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
+++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
@@ -28,11 +28,14 @@
#include <asm/types.h>
+#define FSC (1 << 19)
+#define SSC (0 << 19)
+
#define IEN (1 << 18)
#define IDIS (0 << 18)
-#define PTU (3 << 16)
-#define PTD (1 << 16)
+#define PTU (1 << 17)
+#define PTD (0 << 17)
#define PEN (1 << 16)
#define PDIS (0 << 16)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 04af227..5e6d82e 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -44,16 +44,15 @@
#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
-/* CONTROL */
-#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800)
-#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800)
+/* CONTROL ID CODE */
+#define CONTROL_CORE_ID_CODE 0x4A002204
+#define CONTROL_WKUP_ID_CODE 0x4AE0C204
-/* LPDDR2 IO regs. To be verified */
-#define LPDDR2_IO_REGS_BASE 0x4A100638
-
-/* CONTROL_ID_CODE */
-#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
+#ifdef CONFIG_DRA7XX
+#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
+#else
+#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
+#endif
/* To be verified */
#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
@@ -62,11 +61,6 @@
#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
-/* STD_FUSE_PROD_ID_1 */
-#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
-#define PROD_ID_1_SILICON_TYPE_SHIFT 16
-#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16)
-
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
@@ -80,15 +74,9 @@
/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000)
-
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x50000000
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
-
/*
* Hardware Register Details
*/
@@ -118,9 +106,9 @@
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 << 27)
#define SDCARD_PWRDNZ (1 << 26)
#define SDCARD_BIAS_HIZ_MODE (1 << 25)
-#define SDCARD_BIAS_PWRDNZ (1 << 22)
#define SDCARD_PBIASLITE_VMODE (1 << 21)
#ifndef __ASSEMBLY__
@@ -181,27 +169,18 @@
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
-/*
- * Non-secure SRAM Addresses
- * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
- * at 0x40304000(EMU base) so that our code works for both EMU and GP
- */
+#ifdef CONFIG_DRA7XX
+#define NON_SECURE_SRAM_START 0x40300000
+#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
+#else
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
+#endif
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
-/* Silicon revisions */
-#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
-#define OMAP4430_ES1_0 0x44300100
-#define OMAP4430_ES2_0 0x44300200
-#define OMAP4430_ES2_1 0x44300210
-#define OMAP4430_ES2_2 0x44300220
-#define OMAP4430_ES2_3 0x44300230
-#define OMAP4460_ES1_0 0x44600100
-#define OMAP4460_ES1_1 0x44600110
-
/* CONTROL_SRCOMP_XXX_SIDE */
#define OVERRIDE_XS_SHIFT 30
#define OVERRIDE_XS_MASK (1 << 30)
@@ -216,6 +195,19 @@
#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME 50
+#define OMAP_ABB_CLOCK_CYCLES 16
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
+
+/* ABB efuse masks */
+#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24)
+#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29)
+#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
+#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)
+
#ifndef __ASSEMBLY__
struct srcomp_params {
s8 divide_factor;
@@ -230,6 +222,7 @@
u32 ctrl_ddrio_1;
u32 ctrl_ddrio_2;
u32 ctrl_emif_sdram_config_ext;
+ u32 ctrl_ddr_ctrl_ext_0;
};
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 4d99db9..0bb59d8 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -23,9 +23,9 @@
#include <asm/arch/omap.h>
#include <asm/io.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -61,7 +61,8 @@
void save_omap_boot_params(void);
void init_omap_revision(void);
void do_io_settings(void);
-void omap_vc_init(u16 speed_khz);
+void sri2c_init(void);
+void gpi2c_init(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
new file mode 100644
index 0000000..04e418c
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_BUS_CLK,
+ MXC_IPG_CLK,
+ MXC_UART_CLK,
+ MXC_ESDHC_CLK,
+ MXC_FEC_CLK,
+};
+
+void enable_ocotp_clk(unsigned char enable);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
new file mode 100644
index 0000000..e3f703d
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* Clock Controller Module (CCM) */
+struct ccm_reg {
+ u32 ccr;
+ u32 csr;
+ u32 ccsr;
+ u32 cacrr;
+ u32 cscmr1;
+ u32 cscdr1;
+ u32 cscdr2;
+ u32 cscdr3;
+ u32 cscmr2;
+ u32 cscdr4;
+ u32 ctor;
+ u32 clpcr;
+ u32 cisr;
+ u32 cimr;
+ u32 ccosr;
+ u32 cgpr;
+ u32 ccgr0;
+ u32 ccgr1;
+ u32 ccgr2;
+ u32 ccgr3;
+ u32 ccgr4;
+ u32 ccgr5;
+ u32 ccgr6;
+ u32 ccgr7;
+ u32 ccgr8;
+ u32 ccgr9;
+ u32 ccgr10;
+ u32 ccgr11;
+ u32 cmeor0;
+ u32 cmeor1;
+ u32 cmeor2;
+ u32 cmeor3;
+ u32 cmeor4;
+ u32 cmeor5;
+ u32 cppdsr;
+ u32 ccowr;
+ u32 ccpgr0;
+ u32 ccpgr1;
+ u32 ccpgr2;
+ u32 ccpgr3;
+};
+
+/* Analog components control digital interface (ANADIG) */
+struct anadig_reg {
+ u32 pll3_ctrl;
+ u32 resv0[3];
+ u32 pll7_ctrl;
+ u32 resv1[3];
+ u32 pll2_ctrl;
+ u32 resv2[3];
+ u32 pll2_ss;
+ u32 resv3[3];
+ u32 pll2_num;
+ u32 resv4[3];
+ u32 pll2_denom;
+ u32 resv5[3];
+ u32 pll4_ctrl;
+ u32 resv6[3];
+ u32 pll4_num;
+ u32 resv7[3];
+ u32 pll4_denom;
+ u32 pll6_ctrl;
+ u32 resv8[3];
+ u32 pll6_num;
+ u32 resv9[3];
+ u32 pll6_denom;
+ u32 resv10[3];
+ u32 pll5_ctrl;
+ u32 resv11[3];
+ u32 pll3_pfd;
+ u32 resv12[3];
+ u32 pll2_pfd;
+ u32 resv13[3];
+ u32 reg_1p1;
+ u32 resv14[3];
+ u32 reg_3p0;
+ u32 resv15[3];
+ u32 reg_2p5;
+ u32 resv16[7];
+ u32 ana_misc0;
+ u32 resv17[3];
+ u32 ana_misc1;
+ u32 resv18[63];
+ u32 anadig_digprog;
+ u32 resv19[3];
+ u32 pll1_ctrl;
+ u32 resv20[3];
+ u32 pll1_ss;
+ u32 resv21[3];
+ u32 pll1_num;
+ u32 resv22[3];
+ u32 pll1_denom;
+ u32 resv23[3];
+ u32 pll1_pdf;
+ u32 resv24[3];
+ u32 pll_lock;
+};
+#endif
+
+#define CCM_CCR_FIRC_EN (1 << 16)
+#define CCM_CCR_OSCNT_MASK 0xff
+#define CCM_CCR_OSCNT(v) ((v) & 0xff)
+
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
+#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
+
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
+#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
+
+#define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
+#define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
+#define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
+#define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
+#define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
+#define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
+#define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
+#define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
+
+#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
+#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
+
+#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
+#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
+#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
+
+#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
+#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
+#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
+#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
+#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
+#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
+#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
+#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
+#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
+
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
+#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
+
+#define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
+
+#define CCM_CSCDR2_ESDHC1_EN (1 << 29)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+
+#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
+#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
+#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
+
+#define CCM_REG_CTRL_MASK 0xffffffff
+#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
+#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
+#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
+#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
+#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
+#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
+#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
+#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
+#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
+#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
+#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
+#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
+#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
+#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
+#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
+#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
+
+#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL2_CTRL_DIV_SELECT 1
+#define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL1_CTRL_DIV_SELECT 1
+
+#define FASE_CLK_FREQ 24000000
+#define SLOW_CLK_FREQ 32000
+#define PLL1_PFD1_FREQ 500000000
+#define PLL1_PFD2_FREQ 452000000
+#define PLL1_PFD3_FREQ 396000000
+#define PLL1_PFD4_FREQ 528000000
+#define PLL1_MAIN_FREQ 528000000
+#define PLL2_PFD1_FREQ 500000000
+#define PLL2_PFD2_FREQ 396000000
+#define PLL2_PFD3_FREQ 339000000
+#define PLL2_PFD4_FREQ 413000000
+#define PLL2_MAIN_FREQ 528000000
+#define PLL3_MAIN_FREQ 480000000
+#define PLL3_PFD3_FREQ 298000000
+#define PLL5_MAIN_FREQ 500000000
+
+#define ENET_EXTERNAL_CLK 50000000
+#define AUDIO_EXTERNAL_CLK 24576000
+
+#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
new file mode 100644
index 0000000..c9df32a
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -0,0 +1,419 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
+#define IRAM_SIZE 0x00080000 /* 512 KB */
+
+#define AIPS0_BASE_ADDR 0x40000000
+#define AIPS1_BASE_ADDR 0x40080000
+
+/* AIPS 0 */
+#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
+#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
+#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
+#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
+#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
+#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
+#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
+#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
+#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
+#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
+#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
+#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
+#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
+#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
+#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
+#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
+#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
+#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
+#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
+#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
+#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
+#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
+#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
+#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
+#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
+#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
+#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
+#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
+#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
+#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
+#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
+#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
+#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
+#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
+#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
+#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
+#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
+#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
+#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
+#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
+#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
+#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
+#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
+#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
+#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
+#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
+#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
+#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
+#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
+#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
+#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
+#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
+#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
+#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
+#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
+#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
+#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
+#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
+#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
+
+/* AIPS 1 */
+#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
+#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
+#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
+#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
+
+/* MUX mode and PAD ctrl are in one register */
+#define CONFIG_IOMUX_SHARE_CONF_REG
+
+#define FEC_QUIRK_ENET_MAC
+
+/* MSCM interrupt rounter */
+#define MSCM_IRSPRC_CP0_EN 1
+#define MSCM_IRSPRC_NUM 112
+
+/* DDRMC */
+#define DDRMC_PHY_DQ_TIMING 0x00002613
+#define DDRMC_PHY_DQS_TIMING 0x00002615
+#define DDRMC_PHY_CTRL 0x01210080
+#define DDRMC_PHY_MASTER_CTRL 0x0001012a
+#define DDRMC_PHY_SLAVE_CTRL 0x00012020
+
+#define DDRMC_PHY50_DDR3_MODE (1 << 12)
+#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8)
+
+#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8)
+#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8)
+#define DDRMC_CR00_START 1
+#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff)
+#define DDRMC_CR10_TRST_PWRON(v) (v)
+#define DDRMC_CR11_CKE_INACTIVE(v) (v)
+#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f)
+#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24)
+#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16)
+#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7)
+#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24)
+#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16)
+#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8)
+#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff)
+#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24)
+#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16)
+#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8)
+#define DDRMC_CR17_TMOD(v) ((v) & 0xff)
+#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR18_TCKE(v) ((v) & 0x7)
+#define DDRMC_CR20_AP_EN (1 << 24)
+#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
+#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
+#define DDRMC_CR21_CCMAP_EN 1
+#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
+#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
+#define DDRMC_CR23_TDLL(v) ((v) & 0xff)
+#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f)
+#define DDRMC_CR25_TREF_EN (1 << 16)
+#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff)
+#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff)
+#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff)
+#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff)
+#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR31_TXSR(v) ((v) & 0xffff)
+#define DDRMC_CR33_EN_QK_SREF (1 << 16)
+#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16)
+#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8)
+#define DDRMC_CR38_FREQ_CHG_EN (1 << 8)
+#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8)
+#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3)
+#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1
+#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff)
+#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16)
+#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff)
+#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff)
+#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8)
+#define DDRMC_CR70_REF_PER_ZQ(v) (v)
+#define DDRMC_CR72_ZQCS_ROTATE (1 << 24)
+#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24)
+#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16)
+#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8)
+#define DDRMC_CR74_BANKSPLT_EN (1 << 24)
+#define DDRMC_CR74_ADDR_CMP_EN (1 << 16)
+#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8)
+#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff)
+#define DDRMC_CR75_RW_PG_EN (1 << 24)
+#define DDRMC_CR75_RW_EN (1 << 16)
+#define DDRMC_CR75_PRI_EN (1 << 8)
+#define DDRMC_CR75_PLEN 1
+#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24)
+#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16)
+#define DDRMC_CR76_W2R_SPLT_EN (1 << 8)
+#define DDRMC_CR76_CS_EN 1
+#define DDRMC_CR77_CS_MAP (1 << 24)
+#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8)
+#define DDRMC_CR77_SWAP_EN 1
+#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
+#define DDRMC_CR79_CTLUPD_AREF (1 << 24)
+#define DDRMC_CR82_INT_MASK 0x1fffffff
+#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
+#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
+#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
+#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
+#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
+#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
+#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
+#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff)
+#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8)
+#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8)
+#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3)
+#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24)
+#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16)
+#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24)
+#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16)
+#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8)
+#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf)
+#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24)
+#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16)
+#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff)
+#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8)
+#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf)
+#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff)
+#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8)
+#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
+#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
+#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
+#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)
+#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff)
+#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27)
+#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21)
+#define DDRMC_CR155_AXI0_AWCACHE (1 << 10)
+#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7)
+#define DDRMC_CR158_TWR(v) ((v) & 0x3f)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr;
+ u32 sbmr1;
+ u32 srsr;
+ u32 secr;
+ u32 gpsr;
+ u32 sicr;
+ u32 simr;
+ u32 sbmr2;
+ u32 gpr0;
+ u32 gpr1;
+ u32 gpr2;
+ u32 gpr3;
+ u32 gpr4;
+ u32 hab0;
+ u32 hab1;
+ u32 hab2;
+ u32 hab3;
+ u32 hab4;
+ u32 hab5;
+ u32 misc0;
+ u32 misc1;
+ u32 misc2;
+ u32 misc3;
+};
+
+/* Periodic Interrupt Timer (PIT) */
+struct pit_reg {
+ u32 mcr;
+ u32 recv0[55];
+ u32 ltmr64h;
+ u32 ltmr64l;
+ u32 recv1[6];
+ u32 ldval0;
+ u32 cval0;
+ u32 tctrl0;
+ u32 tflg0;
+ u32 ldval1;
+ u32 cval1;
+ u32 tctrl1;
+ u32 tflg1;
+ u32 ldval2;
+ u32 cval2;
+ u32 tctrl2;
+ u32 tflg2;
+ u32 ldval3;
+ u32 cval3;
+ u32 tctrl3;
+ u32 tflg3;
+ u32 ldval4;
+ u32 cval4;
+ u32 tctrl4;
+ u32 tflg4;
+ u32 ldval5;
+ u32 cval5;
+ u32 tctrl5;
+ u32 tflg5;
+ u32 ldval6;
+ u32 cval6;
+ u32 tctrl6;
+ u32 tflg6;
+ u32 ldval7;
+ u32 cval7;
+ u32 tctrl7;
+ u32 tflg7;
+};
+
+/* Watchdog Timer (WDOG) */
+struct wdog_regs {
+ u16 wcr;
+ u16 wsr;
+ u16 wrsr;
+ u16 wicr;
+ u16 wmcr;
+};
+
+/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
+struct ddrmr_regs {
+ u32 cr[162];
+ u32 rsvd[94];
+ u32 phy[53];
+};
+
+/* On-Chip One Time Programmable Controller (OCOTP) */
+struct ocotp_regs {
+ u32 ctrl;
+ u32 ctrl_set;
+ u32 ctrl_clr;
+ u32 ctrl_tog;
+ u32 timing;
+ u32 rsvd0[3];
+ u32 data;
+ u32 rsvd1[3];
+ u32 read_ctrl;
+ u32 rsvd2[3];
+ u32 read_fuse_data;
+ u32 rsvd3[7];
+ u32 scs;
+ u32 scs_set;
+ u32 scs_clr;
+ u32 scs_tog;
+ u32 crc_addr;
+ u32 rsvd4[3];
+ u32 crc_value;
+ u32 rsvd5[3];
+ u32 version;
+ u32 rsvd6[0xdb];
+
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ } bank[16];
+};
+
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[3];
+ u32 uid_low;
+ u32 rsvd1[3];
+ u32 uid_high;
+ u32 rsvd2[0x17];
+};
+
+struct fuse_bank4_regs {
+ u32 sjc_resp0;
+ u32 rsvd0[3];
+ u32 sjc_resp1;
+ u32 rsvd1[3];
+ u32 mac_addr0;
+ u32 rsvd2[3];
+ u32 mac_addr1;
+ u32 rsvd3[3];
+ u32 mac_addr2;
+ u32 rsvd4[3];
+ u32 mac_addr3;
+ u32 rsvd5[3];
+ u32 gp1;
+ u32 rsvd6[3];
+ u32 gp2;
+ u32 rsvd7[3];
+};
+
+/* UART */
+struct lpuart_fsl {
+ u8 ubdh;
+ u8 ubdl;
+ u8 uc1;
+ u8 uc2;
+ u8 us1;
+ u8 us2;
+ u8 uc3;
+ u8 ud;
+ u8 uma1;
+ u8 uma2;
+ u8 uc4;
+ u8 uc5;
+ u8 ued;
+ u8 umodem;
+ u8 uir;
+ u8 reserved;
+ u8 upfifo;
+ u8 ucfifo;
+ u8 usfifo;
+ u8 utwfifo;
+ u8 utcfifo;
+ u8 urwfifo;
+ u8 urcfifo;
+ u8 rsvd[28];
+};
+
+/* MSCM Interrupt Router */
+struct mscm_ir {
+ u32 ircp0ir;
+ u32 ircp1ir;
+ u32 rsvd1[6];
+ u32 ircpgir;
+ u32 rsvd2[23];
+ u16 irsprc[112];
+ u16 rsvd3[848];
+};
+
+#endif /* __ASSEMBLER__*/
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
new file mode 100644
index 0000000..1c728fa
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_VF610_H__
+#define __IOMUX_VF610_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm
+
+enum {
+ VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
+ VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
+ VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+};
+
+#endif /* __IOMUX_VF610_H__ */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 5f11d7b..1b94a99 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -581,7 +581,7 @@
(0xFF << EMIF_SYS_ADDR_SHIFT))
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
-#define EMIF_EXT_PHY_CTRL_CONST_REG 0x13
+#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14
/* Reg mapping structure */
struct emif_reg_struct {
@@ -855,13 +855,10 @@
#define DPD_ENABLE 1
/* Maximum delay before Low Power Modes */
-#ifndef CONFIG_OMAP54XX
-#define REG_CS_TIM 0xF
-#else
#define REG_CS_TIM 0x0
-#endif
-#define REG_SR_TIM 0xF
-#define REG_PD_TIM 0xF
+#define REG_SR_TIM 0x0
+#define REG_PD_TIM 0x0
+
/* EMIF_PWR_MGMT_CTRL register */
#define EMIF_PWR_MGMT_CTRL (\
@@ -1113,6 +1110,7 @@
u32 freq;
u32 sdram_config_init;
u32 sdram_config;
+ u32 sdram_config2;
u32 ref_ctrl;
u32 sdram_tim1;
u32 sdram_tim2;
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 0b4e763..ebf54cf 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -121,6 +121,24 @@
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
+#elif defined(CONFIG_VF610)
+
+#define PAD_MUX_MODE_SHIFT 20
+
+#define PAD_CTL_SPEED_MED (1 << 12)
+#define PAD_CTL_SPEED_HIGH (3 << 12)
+
+#define PAD_CTL_DSE_50ohm (3 << 6)
+#define PAD_CTL_DSE_25ohm (6 << 6)
+#define PAD_CTL_DSE_20ohm (7 << 6)
+
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PKE (1 << 3)
+#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
+
+#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
+
#else
#define PAD_CTL_DVS (1 << 13)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index baeef4e..0dbe81b 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -29,7 +29,7 @@
#include <common.h>
-#define NUM_SYS_CLKS 8
+#define NUM_SYS_CLKS 7
struct prcm_regs {
/* cm1.ckgen */
@@ -242,6 +242,8 @@
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
+ u32 prm_irqstatus_mpu_2;
+
/* cm2.l4per */
u32 cm_l4per_clkstctrl;
u32 cm_l4per_dynamicdep;
@@ -301,6 +303,7 @@
/* l4 wkup regs */
u32 cm_abe_pll_ref_clksel;
u32 cm_sys_clksel;
+ u32 cm_abe_pll_sys_clksel;
u32 cm_wkup_clkstctrl;
u32 cm_wkup_l4wkup_clkctrl;
u32 cm_wkup_wdtimer1_clkctrl;
@@ -328,6 +331,8 @@
u32 prm_sldo_mpu_ctrl;
u32 prm_sldo_mm_setup;
u32 prm_sldo_mm_ctrl;
+ u32 prm_abbldo_mpu_setup;
+ u32 prm_abbldo_mpu_ctrl;
u32 cm_div_m4_dpll_core;
u32 cm_div_m5_dpll_core;
@@ -346,10 +351,15 @@
u32 cm_l3init_usbphy_clkctrl;
u32 cm_l4per_mcbsp4_clkctrl;
u32 prm_vc_cfg_channel;
+
+ /* SCRM stuff, used by some boards */
+ u32 scrm_auxclk0;
+ u32 scrm_auxclk1;
};
struct omap_sys_ctrl_regs {
u32 control_status;
+ u32 control_std_fuse_opp_vdd_mpu_2;
u32 control_core_mmr_lock1;
u32 control_core_mmr_lock2;
u32 control_core_mmr_lock3;
@@ -362,6 +372,7 @@
u32 control_ldosram_iva_voltage_ctrl;
u32 control_ldosram_mpu_voltage_ctrl;
u32 control_ldosram_core_voltage_ctrl;
+ u32 control_usbotghs_ctrl;
u32 control_padconf_core_base;
u32 control_paconf_global;
u32 control_paconf_mode;
@@ -394,6 +405,7 @@
u32 control_ddrio_0;
u32 control_ddrio_1;
u32 control_ddrio_2;
+ u32 control_ddr_control_ext_0;
u32 control_lpddr2io1_0;
u32 control_lpddr2io1_1;
u32 control_lpddr2io1_2;
@@ -419,6 +431,7 @@
u32 control_port_emif2_sdram_config;
u32 control_emif1_sdram_config_ext;
u32 control_emif2_sdram_config_ext;
+ u32 control_wkup_ldovbb_mpu_voltage_ctrl;
u32 control_smart1nopmio_padconf_0;
u32 control_smart1nopmio_padconf_1;
u32 control_padconf_mode;
@@ -494,11 +507,25 @@
u32 start_code;
unsigned gpio;
int gpio_en;
+ u32 i2c_slave_addr;
+ void (*pmic_bus_init)(void);
+ int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
+};
+
+/**
+ * struct volts_efuse_data - efuse definition for voltage
+ * @reg: register address for efuse
+ * @reg_bits: Number of bits in a register address, mandatory.
+ */
+struct volts_efuse_data {
+ u32 reg;
+ u8 reg_bits;
};
struct volts {
u32 value;
u32 addr;
+ struct volts_efuse_data efuse;
struct pmic_data *pmic;
};
@@ -506,6 +533,9 @@
struct volts mpu;
struct volts core;
struct volts mm;
+ struct volts gpu;
+ struct volts eve;
+ struct volts iva;
};
extern struct prcm_regs const **prcm;
@@ -545,9 +575,9 @@
void scale_vcores(struct vcores_data const *);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
-
-/* Max value for DPLL multiplier M */
-#define OMAP_DPLL_MAX_N 127
+void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
+ u32 txdone, u32 txdone_mask, u32 opp);
+s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
/* HW Init Context */
#define OMAP_INIT_CONTEXT_SPL 0
@@ -555,11 +585,32 @@
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3
+/* ABB */
+#define OMAP_ABB_NOMINAL_OPP 0
+#define OMAP_ABB_FAST_OPP 1
+#define OMAP_ABB_SLOW_OPP 3
+#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0)
+#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1)
+#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2)
+#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6)
+#define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0)
+#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2)
+#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1)
+#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8)
+
static inline u32 omap_revision(void)
{
extern u32 *const omap_si_rev;
return *omap_si_rev;
}
+
+#define OMAP54xx 0x54000000
+
+static inline u8 is_omap54xx(void)
+{
+ extern u32 *const omap_si_rev;
+ return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
+}
#endif
/*
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 8ad9f66..9ecafb2 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -43,7 +43,7 @@
ifndef CONFIG_SYS_GENERIC_BOARD
COBJS-y += board.o
endif
-COBJS-y += bss.o
+COBJS-y += sections.o
COBJS-y += bootm.o
COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index b545fb7..8b1c8ed 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -27,7 +27,7 @@
void __flush_cache(unsigned long start, unsigned long size)
{
-#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
+#if defined(CONFIG_ARM1136)
void arm1136_cache_flush(void);
arm1136_cache_flush();
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index a9657d1..a5bffb8 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -97,13 +97,13 @@
* 'here' but relocated.
*/
- ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */
+ ldr sp, [r8, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r8, [r8, #GD_BD] /* r8 = gd->bd */
sub r8, r8, #GD_SIZE /* new GD is below bd */
adr lr, here
- ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */
+ ldr r0, [r8, #GD_RELOC_OFF] /* r0 = gd->reloc_off */
add lr, lr, r0
ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */
b relocate_code
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 4446da9..949b9e8 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -37,56 +37,34 @@
*/
ENTRY(relocate_code)
- mov r6, r0 /* save addr of destination */
-
- ldr r0, =_start /* r0 <- SRC &_start */
- subs r9, r6, r0 /* r9 <- relocation offset */
+ ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */
+ subs r9, r0, r1 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy loop */
- adr r7, relocate_code /* r7 <- SRC &relocate_code */
- ldr r3, _image_copy_end_ofs /* r3 <- __image_copy_end local ofs */
- add r2, r7, r3 /* r2 <- SRC &__image_copy_end */
+ ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */
copy_loop:
- ldmia r0!, {r10-r11} /* copy from source address [r0] */
- stmia r1!, {r10-r11} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
+ ldmia r1!, {r10-r11} /* copy from source address [r1] */
+ stmia r0!, {r10-r11} /* copy to target address [r0] */
+ cmp r1, r2 /* until source end address [r2] */
blo copy_loop
/*
* fix .rel.dyn relocations
*/
- ldr r10, _dynsym_start_ofs /* r10 <- __dynsym_start local ofs */
- add r10, r10, r7 /* r10 <- SRC &__dynsym_start */
- ldr r2, _rel_dyn_start_ofs /* r2 <- __rel_dyn_start local ofs */
- add r2, r2, r7 /* r2 <- SRC &__rel_dyn_start */
- ldr r3, _rel_dyn_end_ofs /* r3 <- __rel_dyn_end local ofs */
- add r3, r3, r7 /* r3 <- SRC &__rel_dyn_end */
+ ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */
+ ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */
fixloop:
- ldr r0, [r2] /* r0 <- SRC location to fix up */
- add r0, r0, r9 /* r0 <- DST location to fix up */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
+ ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */
+ and r1, r1, #0xff
+ cmp r1, #23 /* relative fixup? */
+ bne fixnext
+
/* relative fix: increase location by offset */
+ add r0, r0, r9
ldr r1, [r0]
add r1, r1, r9
-fixnext:
str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
+fixnext:
cmp r2, r3
blo fixloop
@@ -100,13 +78,4 @@
bx lr
#endif
-_image_copy_end_ofs:
- .word __image_copy_end - relocate_code
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - relocate_code
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - relocate_code
-_dynsym_start_ofs:
- .word __dynsym_start - relocate_code
-
ENDPROC(relocate_code)
diff --git a/arch/arm/lib/bss.c b/arch/arm/lib/sections.c
similarity index 79%
rename from arch/arm/lib/bss.c
rename to arch/arm/lib/sections.c
index 99eda59..5921dd8 100644
--- a/arch/arm/lib/bss.c
+++ b/arch/arm/lib/sections.c
@@ -35,5 +35,9 @@
* aliasing warnings.
*/
-char __bss_start[0] __attribute__((used, section(".__bss_start")));
-char __bss_end[0] __attribute__((used, section(".__bss_end")));
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c
index 22cef3e..484bd17 100644
--- a/arch/powerpc/cpu/mpc8260/commproc.c
+++ b/arch/powerpc/cpu/mpc8260/commproc.c
@@ -43,7 +43,7 @@
} while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000);
#ifdef CONFIG_HARD_I2C
- *((unsigned short*)(&immr->im_dprambase[PROFF_I2C_BASE])) = 0;
+ immr->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)] = 0;
#endif
}
diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c
index f8bc5a9..22e1a23 100644
--- a/arch/powerpc/cpu/mpc8260/cpu.c
+++ b/arch/powerpc/cpu/mpc8260/cpu.c
@@ -106,7 +106,7 @@
* in the mask.
*/
m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
- k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
+ k = immap->im_dprambase16[PROFF_REVNUM / sizeof(u16)];
switch (m) {
case 0x0000:
diff --git a/arch/powerpc/cpu/mpc8260/i2c.c b/arch/powerpc/cpu/mpc8260/i2c.c
index b720b1f..e2341e9 100644
--- a/arch/powerpc/cpu/mpc8260/i2c.c
+++ b/arch/powerpc/cpu/mpc8260/i2c.c
@@ -221,14 +221,14 @@
i2c_init_board();
#endif
- dpaddr = *((unsigned short *) (&immap->im_dprambase[PROFF_I2C_BASE]));
+ dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
if (dpaddr == 0) {
/* need to allocate dual port ram */
dpaddr = m8260_cpm_dpalloc(64 +
(NUM_RX_BDS * sizeof(I2C_BD)) +
(NUM_TX_BDS * sizeof(I2C_BD)) +
MAX_TX_SPACE, 64);
- *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE])) =
+ immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)] =
dpaddr;
}
@@ -305,7 +305,7 @@
debug("[I2C] i2c_newio\n");
- dpaddr = *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE]));
+ dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
iip = (iic_t *)&immap->im_dprambase[dpaddr];
state->rx_idx = 0;
state->tx_idx = 0;
@@ -480,7 +480,7 @@
return I2CERR_QUEUE_EMPTY;
}
- dpaddr = *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE]));
+ dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
iip = (iic_t *)&immap->im_dprambase[dpaddr];
iip->iic_rbptr = iip->iic_rbase;
iip->iic_tbptr = iip->iic_tbase;
diff --git a/arch/powerpc/cpu/mpc8260/serial_smc.c b/arch/powerpc/cpu/mpc8260/serial_smc.c
index feba1f6..9410e4c 100644
--- a/arch/powerpc/cpu/mpc8260/serial_smc.c
+++ b/arch/powerpc/cpu/mpc8260/serial_smc.c
@@ -105,7 +105,7 @@
/* initialize pointers to SMC */
sp = (smc_t *) &(im->im_smc[SMC_INDEX]);
- *(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC;
+ im->im_dprambase16[PROFF_SMC_BASE / sizeof(u16)] = PROFF_SMC;
up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
/* Disable transmitter/receiver. */
@@ -331,7 +331,7 @@
/* initialize pointers to SMC */
sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]);
- *(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC;
+ im->im_dprambase16[KGDB_PROFF_SMC_BASE / sizeof(u16)] = KGDB_PROFF_SMC;
up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
/* Disable transmitter/receiver. */
diff --git a/arch/powerpc/cpu/mpc8260/spi.c b/arch/powerpc/cpu/mpc8260/spi.c
index dc98ea7..01b492e 100644
--- a/arch/powerpc/cpu/mpc8260/spi.c
+++ b/arch/powerpc/cpu/mpc8260/spi.c
@@ -146,7 +146,7 @@
immr = (immap_t *) CONFIG_SYS_IMMR;
cp = (cpm8260_t *) &immr->im_cpm;
- *(ushort *)(&immr->im_dprambase[PROFF_SPI_BASE]) = PROFF_SPI;
+ immr->im_dprambase16[PROFF_SPI_BASE / sizeof(u16)] = PROFF_SPI;
spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
/* 1 */
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 2318064..4669883 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -73,6 +73,7 @@
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
+COBJS-$(CONFIG_P1023) += ddr-gen3.o
COBJS-$(CONFIG_P1024) += ddr-gen3.o
COBJS-$(CONFIG_P1025) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 422782c..a7ed877 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -258,6 +258,9 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
+ puts("Work-around for Erratum A006593 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 6ce483e..fbee753 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -121,16 +121,16 @@
switch(ver) {
case PVR_VER_E500_V1:
case PVR_VER_E500_V2:
- puts("E500");
+ puts("e500");
break;
case PVR_VER_E500MC:
- puts("E500MC");
+ puts("e500mc");
break;
case PVR_VER_E5500:
- puts("E5500");
+ puts("e5500");
break;
case PVR_VER_E6500:
- puts("E6500");
+ puts("e6500");
break;
default:
puts("Unknown");
@@ -341,7 +341,7 @@
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
return fsl_ddr_sdram_size();
#else
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
}
#else /* CONFIG_SYS_RAMBOOT */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4067f05..3c8f59c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -172,6 +172,9 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
+ setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
+#endif
out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
/* Read back to sync write */
@@ -564,7 +567,7 @@
#ifdef CONFIG_SYS_SRIO
srio_init();
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
char *s = getenv("bootmaster");
if (s) {
if (!strcmp(s, "SRIO1")) {
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 234fde4..837c034 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -25,7 +25,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_A003399_NOR_WORKAROUND
void setup_ifc(void)
{
struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
@@ -99,7 +99,7 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
-#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_A003399_NOR_WORKAROUND
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
u32 *dst, *src;
void (*setup_ifc_sram)(void);
@@ -138,7 +138,7 @@
* Work Around for IFC Erratum A003399, issue will hit only when execution
* from NOR Flash
*/
-#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_A003399_NOR_WORKAROUND
#define SRAM_BASE_ADDR (0x00000000)
/* TLB for SRAM */
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
@@ -180,5 +180,9 @@
invalidate_tlb(1);
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL)
+ disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
+#endif
+
init_tlbs();
}
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 288f7b2..bb95f3d 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -663,7 +663,7 @@
#ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
- do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2",
+ do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
do_fixup_by_compat_u32(blob, "fsl,mpic",
"clock-frequency", get_bus_freq(0)/2, 1);
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index 6dadeb8..ec96e81 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -228,7 +228,7 @@
break;
}
- if (srds1_io_sel > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds1_io_sel >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
return;
}
@@ -237,7 +237,7 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
- if (srds2_io_sel > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
index 7c49097..3483366 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
@@ -68,7 +68,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
@@ -77,7 +77,7 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
- if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
index 76288cd..c9eea15 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -53,7 +53,7 @@
debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
- if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
return ;
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
index 2582637..49a0290 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
@@ -53,7 +53,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
index f480c26..7af6aff 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
@@ -62,7 +62,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
index 2ff5d9a..fcccb52 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
@@ -57,7 +57,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
index e8a0387..1f7dba0 100644
--- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
@@ -54,7 +54,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
@@ -63,7 +63,7 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
- if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
index 1849c16..d6d2696 100644
--- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
@@ -73,7 +73,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
index e4c9c22..ed49920 100644
--- a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
@@ -93,7 +93,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
@@ -102,7 +102,7 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
- if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
index c8ab5d6..0b4ae90 100644
--- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -41,7 +41,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
index 389ff6b..01af333 100644
--- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
@@ -61,7 +61,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
index eec4ffe..87335c9 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
@@ -90,7 +90,7 @@
u32 svr = get_svr();
u32 ver = SVR_SOC_VER(svr);
- if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
/* P2040[e] does not support XAUI */
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
index fba9ff2..a36dcd5 100644
--- a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
@@ -139,7 +139,7 @@
int is_serdes_prtcl_valid(u32 prtcl) {
int i;
- if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
index 87bd795..94ec445 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
@@ -86,7 +86,7 @@
int is_serdes_prtcl_valid(u32 prtcl) {
int i;
- if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c
index fba9ff2..a36dcd5 100644
--- a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c
@@ -139,7 +139,7 @@
int is_serdes_prtcl_valid(u32 prtcl) {
int i;
- if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
index 890b88e..d646e85 100644
--- a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
@@ -105,7 +105,7 @@
{
int i;
- if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 4f0480b..2657982 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1795,7 +1795,7 @@
stw r0,0(r3)
addi r3,r3,4
cmplw 0,r3,r4
- bne 5b
+ blt 5b
6:
mr r3,r9 /* Init Data pointer */
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
index 8261e03..19add9f 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -81,7 +81,7 @@
{
int i;
- if (prtcl > (ARRAY_SIZE(serdes_cfg_tbl[serdes])))
+ if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes]))
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index f2b7bff..20284ed 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -26,6 +26,13 @@
#include "config.h" /* CONFIG_BOARDDIR */
OUTPUT_ARCH(powerpc)
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+#endif
SECTIONS
{
. = CONFIG_SPL_TEXT_BASE;
@@ -60,7 +67,7 @@
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
- start.o (.bootpg)
+ arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
}
#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
#elif defined(CONFIG_FSL_ELBC)
@@ -68,9 +75,16 @@
#else
#error unknown NAND controller
#endif
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ KEEP(*(.bootpg))
+ } :text = 0xffff
+#else
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
+#endif
/*
* Make sure that the bss segment isn't linked at 0x0, otherwise its
@@ -78,10 +92,12 @@
*/
. |= 0x10;
+ . = ALIGN(4);
__bss_start = .;
.bss : {
*(.sbss*)
*(.bss*)
}
+ . = ALIGN(4);
__bss_end = .;
}
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 0503dce..2643563 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -95,6 +95,13 @@
. = ALIGN(256);
__init_end = .;
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
+ } :text = 0xffff
+ . = ADDR(.text) + 0x80000;
+#else
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
@@ -117,6 +124,7 @@
#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
. |= 0x10;
#endif
+#endif
__bss_start = .;
.bss (NOLOAD) :
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
index c553415..5ed3eb2 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu.c
@@ -78,7 +78,7 @@
major = PVR_E600_MAJ(pvr);
minor = PVR_E600_MIN(pvr);
- printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
+ printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
puts("\n Core1Translation Enabled");
debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
index 0dc1975..0342e34 100644
--- a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
+++ b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
@@ -64,7 +64,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
@@ -73,7 +73,7 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
- if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
index 3ae9069..21c5ddb 100644
--- a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
+++ b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
@@ -73,7 +73,7 @@
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
- if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
@@ -82,7 +82,7 @@
serdes1_prtcl_map |= (1 << lane_prtcl);
}
- if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+ if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index b6b733d..dc33eb3 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -78,7 +78,8 @@
if ((pvr >> 16) != 0x0050)
return -1;
- k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
+ k = (immr << 16) |
+ immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
m = 0;
suf = "";
@@ -194,7 +195,8 @@
if ((pvr >> 16) != 0x0050)
return -1;
- k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
+ k = (immr << 16) |
+ immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
m = 0;
switch (k) {
@@ -253,7 +255,8 @@
if ((pvr >> 16) != 0x0050)
return -1;
- k = (immr << 16) | in_be16((ushort *)&immap->im_cpm.cp_dparam[0xB0]);
+ k = (immr << 16) |
+ in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
m = 0;
switch (k) {
@@ -312,7 +315,8 @@
if ((pvr >> 16) != 0x0050)
return -1;
- k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
+ k = (immr << 16) |
+ immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
m = 0;
switch (k) {
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index 56b319f..4e8a441 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -26,7 +26,7 @@
int i, j;
printf("IFC Controller Registers\n");
- for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
+ for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
i, get_ifc_cspr(i), i, get_ifc_amask(i),
i, get_ifc_csor(i));
@@ -43,7 +43,7 @@
set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
-#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT)
+#ifndef CONFIG_A003399_NOR_WORKAROUND
#ifdef CONFIG_SYS_CSPR0_EXT
set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
#endif
@@ -94,4 +94,60 @@
set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
#endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+ set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+ set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+
+ set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
+ set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
+ set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#endif
+
+#ifdef CONFIG_SYS_CSPR5_EXT
+ set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+ set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
+
+ set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
+ set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
+ set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#endif
+
+#ifdef CONFIG_SYS_CSPR6_EXT
+ set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+ set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+
+ set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
+ set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
+ set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#endif
+
+#ifdef CONFIG_SYS_CSPR7_EXT
+ set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+ set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+
+ set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
+ set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
+ set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+#endif
}
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 6e6f7dc..90d1065 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -24,7 +24,7 @@
#include <asm/fsl_srio.h>
#include <asm/errno.h>
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
#define SRIO_PORT_ACCEPT_ALL 0x10000001
#define SRIO_IB_ATMU_AR 0x80f55000
#define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -299,7 +299,7 @@
}
}
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h
index 40679cb..01129ed 100644
--- a/arch/powerpc/include/asm/8xx_immap.h
+++ b/arch/powerpc/include/asm/8xx_immap.h
@@ -485,7 +485,12 @@
* Some processors don't have all of it populated.
*/
u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
- u_char cp_dparam[0x400]; /* Parameter RAM */
+
+ /* Parameter RAM */
+ union {
+ u_char cp_dparam[0x400];
+ u16 cp_dparam16[0x200];
+ };
} cpm8xx_t;
/* Internal memory map.
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 1009a31..1d46b14 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -139,6 +139,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -337,7 +338,6 @@
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -371,7 +371,6 @@
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -413,7 +412,6 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -449,7 +447,6 @@
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -494,6 +491,9 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -506,6 +506,7 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -541,6 +542,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -553,6 +555,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004468
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -566,6 +569,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -573,6 +577,7 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#ifdef CONFIG_PPC_B4860
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index ba41b73..3baf4cc 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -21,6 +21,7 @@
#ifndef __ASM_PPC_FSL_IFC_H
#define __ASM_PPC_FSL_IFC_H
+#ifdef CONFIG_FSL_IFC
#include <config.h>
#include <common.h>
@@ -798,13 +799,15 @@
#define set_ifc_ftim(i, j, v) \
(out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
-#define FSL_IFC_BANK_COUNT 4
-
enum ifc_chip_sel {
IFC_CS0,
IFC_CS1,
IFC_CS2,
IFC_CS3,
+ IFC_CS4,
+ IFC_CS5,
+ IFC_CS6,
+ IFC_CS7,
};
enum ifc_ftims {
@@ -907,6 +910,49 @@
u32 res4[0x1F3];
};
+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define IFC_CSPR_REG_LEN 148
+#define IFC_AMASK_REG_LEN 144
+#define IFC_CSOR_REG_LEN 144
+#define IFC_FTIM_REG_LEN 576
+
+#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
+ CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
+ CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
+ CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
+ CONFIG_SYS_FSL_IFC_BANK_COUNT
+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif
+
+struct fsl_ifc_cspr {
+ u32 cspr_ext;
+ u32 cspr;
+ u32 res;
+};
+
+struct fsl_ifc_amask {
+ u32 amask;
+ u32 res[0x2];
+};
+
+struct fsl_ifc_csor {
+ u32 csor;
+ u32 csor_ext;
+ u32 res;
+};
+
+struct fsl_ifc_ftim {
+ u32 ftim[4];
+ u32 res[0x8];
+};
/*
* IFC Controller Registers
@@ -914,44 +960,30 @@
struct fsl_ifc {
u32 ifc_rev;
u32 res1[0x2];
- struct {
- u32 cspr_ext;
- u32 cspr;
- u32 res2;
- } cspr_cs[FSL_IFC_BANK_COUNT];
- u32 res3[0x19];
- struct {
- u32 amask;
- u32 res4[0x2];
- } amask_cs[FSL_IFC_BANK_COUNT];
- u32 res5[0x17];
- struct {
- u32 csor_ext;
- u32 csor;
- u32 res6;
- } csor_cs[FSL_IFC_BANK_COUNT];
- u32 res7[0x19];
- struct {
- u32 ftim[4];
- u32 res8[0x8];
- } ftim_cs[FSL_IFC_BANK_COUNT];
- u32 res9[0x60];
+ struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+ struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+ struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+ struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
u32 rb_stat;
- u32 res10[0x2];
+ u32 res6[0x2];
u32 ifc_gcr;
- u32 res11[0x2];
+ u32 res7[0x2];
u32 cm_evter_stat;
- u32 res12[0x2];
+ u32 res8[0x2];
u32 cm_evter_en;
- u32 res13[0x2];
+ u32 res9[0x2];
u32 cm_evter_intr_en;
- u32 res14[0x2];
+ u32 res10[0x2];
u32 cm_erattr0;
u32 cm_erattr1;
- u32 res15[0x2];
+ u32 res11[0x2];
u32 ifc_ccr;
u32 ifc_csr;
- u32 res16[0x2EB];
+ u32 res12[0x2EB];
struct fsl_ifc_nand ifc_nand;
struct fsl_ifc_nor ifc_nor;
struct fsl_ifc_gpcm ifc_gpcm;
@@ -961,6 +993,7 @@
#undef CSPR_MSEL_NOR
#define CSPR_MSEL_NOR CSPR_MSEL_GPCM
#endif
+#endif /* CONFIG_FSL_IFC */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_PPC_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 90b264d..bea1636 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -82,11 +82,16 @@
#ifndef CONFIG_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
+#if defined(CONFIG_BSC9131)
+ LAW_TRGT_IF_OCN_DSP = 0x03,
+#else
#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
+#endif
LAW_TRGT_IF_LBC = 0x04,
LAW_TRGT_IF_CCSR = 0x08,
+ LAW_TRGT_IF_DSP_CCSR = 0x09,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
LAW_TRGT_IF_RIO_2 = 0x0d,
diff --git a/arch/powerpc/include/asm/immap_8260.h b/arch/powerpc/include/asm/immap_8260.h
index 4974ae5..c7021a7 100644
--- a/arch/powerpc/include/asm/immap_8260.h
+++ b/arch/powerpc/include/asm/immap_8260.h
@@ -526,13 +526,18 @@
/* Some references are into the unique and known dpram spaces,
* others are from the generic base.
*/
-#define im_dprambase im_dpram1
- u_char im_dpram1[16*1024];
- char res1[16*1024];
- u_char im_dpram2[4*1024];
- char res2[8*1024];
- u_char im_dpram3[4*1024];
- char res3[16*1024];
+ union {
+ struct {
+ u_char im_dpram1[16 * 1024];
+ char res1[16 * 1024];
+ u_char im_dpram2[4 * 1024];
+ char res2[8 * 1024];
+ u_char im_dpram3[4 * 1024];
+ char res3[16 * 1024];
+ };
+ u8 im_dprambase[64 * 1024];
+ u16 im_dprambase16[32 * 1024];
+ };
sysconf8260_t im_siu_conf; /* SIU Configuration */
memctl8260_t im_memctl; /* Memory Controller */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 4052037..db70d04 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1839,11 +1839,13 @@
#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#elif defined(CONFIG_PPC_T1040)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
@@ -2160,7 +2162,7 @@
u32 porbmsr; /* POR boot mode status */
#define MPC85xx_PORBMSR_HA 0x00070000
#define MPC85xx_PORBMSR_HA_SHIFT 16
-#define MPC85XX_PORBMSR_ROMLOC_SHIFT 24
+#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
#define PORBMSR_ROMLOC_SPI 0x6
#define PORBMSR_ROMLOC_SDHC 0x7
#define PORBMSR_ROMLOC_NAND_2K 0x9
diff --git a/board/LaCie/common/cpld-gpio-bus.c b/board/LaCie/common/cpld-gpio-bus.c
new file mode 100644
index 0000000..fb9bf8d
--- /dev/null
+++ b/board/LaCie/common/cpld-gpio-bus.c
@@ -0,0 +1,50 @@
+/*
+ * cpld-gpio-bus.c: provides support for the CPLD GPIO bus found on some LaCie
+ * boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO
+ * bus exposes two registers (address and data). Each of this register is made
+ * up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that
+ * the registers have been updated.
+ *
+ * Mostly this bus is used to configure the LEDs on LaCie boards.
+ *
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <asm/arch/gpio.h>
+#include "cpld-gpio-bus.h"
+
+static void cpld_gpio_bus_set_addr(struct cpld_gpio_bus *bus, unsigned addr)
+{
+ int pin;
+
+ for (pin = 0; pin < bus->num_addr; pin++)
+ kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1);
+}
+
+static void cpld_gpio_bus_set_data(struct cpld_gpio_bus *bus, unsigned data)
+{
+ int pin;
+
+ for (pin = 0; pin < bus->num_data; pin++)
+ kw_gpio_set_value(bus->data[pin], (data >> pin) & 1);
+}
+
+static void cpld_gpio_bus_enable_select(struct cpld_gpio_bus *bus)
+{
+ /* The transfer is enabled on the raising edge. */
+ kw_gpio_set_value(bus->enable, 0);
+ kw_gpio_set_value(bus->enable, 1);
+}
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *bus,
+ unsigned addr, unsigned value)
+{
+ cpld_gpio_bus_set_addr(bus, addr);
+ cpld_gpio_bus_set_data(bus, value);
+ cpld_gpio_bus_enable_select(bus);
+}
diff --git a/board/LaCie/common/cpld-gpio-bus.h b/board/LaCie/common/cpld-gpio-bus.h
new file mode 100644
index 0000000..e9e9b96
--- /dev/null
+++ b/board/LaCie/common/cpld-gpio-bus.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _LACIE_CPLD_GPI0_BUS_H
+#define _LACIE_CPLD_GPI0_BUS_H
+
+struct cpld_gpio_bus {
+ unsigned *addr;
+ unsigned num_addr;
+ unsigned *data;
+ unsigned num_data;
+ unsigned enable;
+};
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus,
+ unsigned addr, unsigned value);
+
+#endif /* _LACIE_CPLD_GPI0_BUS_H */
diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile
index fbae48e..9a6dfb6 100644
--- a/board/LaCie/net2big_v2/Makefile
+++ b/board/LaCie/net2big_v2/Makefile
@@ -28,6 +28,9 @@
LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o ../common/common.o
+ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
+COBJS += ../common/cpld-gpio-bus.o
+endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
index e524f35..b133f7c 100644
--- a/board/LaCie/net2big_v2/net2big_v2.c
+++ b/board/LaCie/net2big_v2/net2big_v2.c
@@ -22,6 +22,7 @@
#include <common.h>
#include <command.h>
+#include <i2c.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
@@ -29,6 +30,7 @@
#include "net2big_v2.h"
#include "../common/common.h"
+#include "../common/cpld-gpio-bus.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -60,18 +62,18 @@
MPP24_GPIO, /* USB mode select */
MPP26_GPIO, /* USB device vbus */
MPP28_GPIO, /* USB enable host vbus */
- MPP29_GPIO, /* GPIO extension ALE */
+ MPP29_GPIO, /* CPLD GPIO bus ALE */
MPP34_GPIO, /* Rear Push button 0=on 1=off */
MPP35_GPIO, /* Inhibit switch power-off */
MPP36_GPIO, /* SATA HDD1 presence */
MPP37_GPIO, /* SATA HDD2 presence */
MPP40_GPIO, /* eSATA presence */
- MPP44_GPIO, /* GPIO extension (data 0) */
- MPP45_GPIO, /* GPIO extension (data 1) */
- MPP46_GPIO, /* GPIO extension (data 2) */
- MPP47_GPIO, /* GPIO extension (addr 0) */
- MPP48_GPIO, /* GPIO extension (addr 1) */
- MPP49_GPIO, /* GPIO extension (addr 2) */
+ MPP44_GPIO, /* CPLD GPIO bus (data 0) */
+ MPP45_GPIO, /* CPLD GPIO bus (data 1) */
+ MPP46_GPIO, /* CPLD GPIO bus (data 2) */
+ MPP47_GPIO, /* CPLD GPIO bus (addr 0) */
+ MPP48_GPIO, /* CPLD GPIO bus (addr 1) */
+ MPP49_GPIO, /* CPLD GPIO bus (addr 2) */
0
};
@@ -92,8 +94,142 @@
}
#if defined(CONFIG_MISC_INIT_R)
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
+/*
+ * Start I2C fan (GMT G762 controller)
+ */
+static void init_fan(void)
+{
+ u8 data;
+
+ i2c_set_bus_num(0);
+
+ /* Enable open-loop and PWM modes */
+ data = 0x20;
+ if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+ G762_REG_FAN_CMD1, 1, &data, 1) != 0)
+ goto err;
+ data = 0;
+ if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+ G762_REG_SET_CNT, 1, &data, 1) != 0)
+ goto err;
+ /*
+ * RPM to PWM (set_out register) fan speed conversion array:
+ * 0 0x00
+ * 1500 0x04
+ * 2800 0x08
+ * 3400 0x0C
+ * 3700 0x10
+ * 4400 0x20
+ * 4700 0x30
+ * 4800 0x50
+ * 5200 0x80
+ * 5400 0xC0
+ * 5500 0xFF
+ *
+ * Start fan at low speed (2800 RPM):
+ */
+ data = 0x08;
+ if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+ G762_REG_SET_OUT, 1, &data, 1) != 0)
+ goto err;
+
+ return;
+err:
+ printf("Error: failed to start I2C fan @%02x\n",
+ CONFIG_SYS_I2C_G762_ADDR);
+}
+#else
+static void init_fan(void) {}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
+
+#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
+/*
+ * CPLD GPIO bus:
+ *
+ * - address register : bit [0-2] -> GPIO [47-49]
+ * - data register : bit [0-2] -> GPIO [44-46]
+ * - enable register : GPIO 29
+ */
+static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
+static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
+
+static struct cpld_gpio_bus cpld_gpio_bus = {
+ .addr = cpld_gpio_bus_addr,
+ .num_addr = ARRAY_SIZE(cpld_gpio_bus_addr),
+ .data = cpld_gpio_bus_data,
+ .num_data = ARRAY_SIZE(cpld_gpio_bus_data),
+ .enable = 29,
+};
+
+/*
+ * LEDs configuration:
+ *
+ * The LEDs are controlled by a CPLD and can be configured through
+ * the CPLD GPIO bus.
+ *
+ * Address register selection:
+ *
+ * addr | register
+ * ----------------------------
+ * 0 | front LED
+ * 1 | front LED brightness
+ * 2 | SATA LED brightness
+ * 3 | SATA0 LED
+ * 4 | SATA1 LED
+ * 5 | SATA2 LED
+ * 6 | SATA3 LED
+ * 7 | SATA4 LED
+ *
+ * Data register configuration:
+ *
+ * data | LED brightness
+ * -------------------------------------------------
+ * 0 | min (off)
+ * - | -
+ * 7 | max
+ *
+ * data | front LED mode
+ * -------------------------------------------------
+ * 0 | fix off
+ * 1 | fix blue on
+ * 2 | fix red on
+ * 3 | blink blue on=1 sec and blue off=1 sec
+ * 4 | blink red on=1 sec and red off=1 sec
+ * 5 | blink blue on=2.5 sec and red on=0.5 sec
+ * 6 | blink blue on=1 sec and red on=1 sec
+ * 7 | blink blue on=0.5 sec and blue off=2.5 sec
+ *
+ * data | SATA LED mode
+ * -------------------------------------------------
+ * 0 | fix off
+ * 1 | SATA activity blink
+ * 2 | fix red on
+ * 3 | blink blue on=1 sec and blue off=1 sec
+ * 4 | blink red on=1 sec and red off=1 sec
+ * 5 | blink blue on=2.5 sec and red on=0.5 sec
+ * 6 | blink blue on=1 sec and red on=1 sec
+ * 7 | fix blue on
+ */
+static void init_leds(void)
+{
+ /* Enable the front blue LED */
+ cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
+ cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
+
+ /* Configure SATA LEDs to blink in relation with the SATA activity */
+ cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
+ cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
+ cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
+}
+#else
+static void init_leds(void) {}
+#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
+
int misc_init_r(void)
{
+ init_fan();
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
if (!getenv("ethaddr")) {
uchar mac[6];
@@ -101,9 +237,11 @@
eth_setenv_enetaddr("ethaddr", mac);
}
#endif
+ init_leds();
+
return 0;
}
-#endif
+#endif /* CONFIG_MISC_INIT_R */
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
/* Configure and initialize PHY */
diff --git a/board/LaCie/net2big_v2/net2big_v2.h b/board/LaCie/net2big_v2/net2big_v2.h
index f9778f4..83537d6 100644
--- a/board/LaCie/net2big_v2/net2big_v2.h
+++ b/board/LaCie/net2big_v2/net2big_v2.h
@@ -32,4 +32,9 @@
/* Buttons */
#define NET2BIG_V2_GPIO_PUSH_BUTTON 34
+/* GMT G762 registers (I2C fan controller) */
+#define G762_REG_SET_CNT 0x00
+#define G762_REG_SET_OUT 0x03
+#define G762_REG_FAN_CMD1 0x04
+
#endif /* NET2BIG_V2_H */
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
index ef4a25b..74aec5f 100644
--- a/board/actux1/u-boot.lds
+++ b/board/actux1/u-boot.lds
@@ -30,6 +30,7 @@
. = ALIGN (4);
.text : {
+ *(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
net/libnet.o(.text*)
board/actux1/libactux1.o(.text*)
@@ -62,17 +63,23 @@
. = ALIGN (4);
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
}
_end = .;
@@ -96,6 +103,7 @@
KEEP(*(.__bss_end));
}
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
index 00ad8b7..c276501 100644
--- a/board/actux2/u-boot.lds
+++ b/board/actux2/u-boot.lds
@@ -30,6 +30,7 @@
. = ALIGN (4);
.text : {
+ *(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
net/libnet.o(.text*)
board/actux2/libactux2.o(.text*)
@@ -62,17 +63,23 @@
. = ALIGN (4);
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
}
_end = .;
@@ -96,6 +103,7 @@
KEEP(*(.__bss_end));
}
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
index 44b990e..5610644 100644
--- a/board/actux3/u-boot.lds
+++ b/board/actux3/u-boot.lds
@@ -30,6 +30,7 @@
. = ALIGN (4);
.text : {
+ *(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
net/libnet.o(.text*)
board/actux3/libactux3.o(.text*)
@@ -62,17 +63,23 @@
. = ALIGN (4);
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
}
_end = .;
@@ -96,6 +103,7 @@
KEEP(*(.__bss_end));
}
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
index 1daa1b3..3972685 100644
--- a/board/ait/cam_enc_4xx/u-boot-spl.lds
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -54,11 +54,6 @@
__rel_dyn_end = .;
} >.sram
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- } >.sram
-
.bss :
{
. = ALIGN(4);
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index e155556..8f0f9b8 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -336,7 +336,6 @@
void setup_spi(void)
{
- gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
ARRAY_SIZE(ecspi1_pads));
}
diff --git a/board/ti/omap2420h4/Makefile b/board/congatec/cgtqmx6eval/Makefile
similarity index 68%
copy from board/ti/omap2420h4/Makefile
copy to board/congatec/cgtqmx6eval/Makefile
index cddd7e6..ac16c1f 100644
--- a/board/ti/omap2420h4/Makefile
+++ b/board/congatec/cgtqmx6eval/Makefile
@@ -1,9 +1,8 @@
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2013 Adeneo Embedded <www.adeneo-embedded.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -23,17 +22,15 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)lib$(BOARD).o
-COBJS := omap2420h4.o mem.o sys_info.o
-SOBJS := lowlevel_init.o
+COBJS := cgtqmx6eval.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README
new file mode 100644
index 0000000..bbf0f75
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/README
@@ -0,0 +1,29 @@
+U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board with
+qmx6 quad module.
+
+This file contains information for the port of U-Boot to the Congatec
+Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
+
+1. Boot source, boot from SD card
+---------------------------------
+
+This version of u-boot works only on the SD card. By default, the
+Congatec board can boot only from the SPI-NOR.
+But, with the u-boot version provided with the board you can write boot
+registers to force the board to reboot and boot from the SD slot. If
+"bmode" command is not available from your pre-installed u-boot, these
+instruction will produce the same effect:
+
+conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850
+conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000
+conga-QMX6 U-Boot > reset
+resetting ...
+
+The the board will reboot and, if you have written your SD correctly
+the board will use u-boot that live into the SD
+
+To copy the resulting u-boot.imx to the SD card:
+
+ dd if=u-boot.imx of=/dev/xxx bs=512 seek=2
+
+Note: Replace xxx with the device representing the SD card in your system.
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
new file mode 100644
index 0000000..f70f674
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Based on mx6qsabrelite.c file
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Leo Sartre, <lsartre@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ gpio_direction_input(IMX_GPIO_NR(1, 4));
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
+ break;
+ case USDHC4_BASE_ADDR:
+ gpio_direction_input(IMX_GPIO_NR(2, 6));
+ ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
+ break;
+ default:
+ printf("Bad USDHC interface\n");
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+
+ status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
+ fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+
+ return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Conga-QEVAL QMX6 Quad\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c
index c45c94b..a4e9254 100644
--- a/board/davinci/da8xxevm/da830evm.c
+++ b/board/davinci/da8xxevm/da830evm.c
@@ -39,135 +39,43 @@
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
+#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/davinci_misc.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-/* SPI0 pin muxer settings */
-static const struct pinmux_config spi0_pins[] = {
- { pinmux(7), 1, 3 },
- { pinmux(7), 1, 4 },
- { pinmux(7), 1, 5 },
- { pinmux(7), 1, 6 },
- { pinmux(7), 1, 7 }
-};
-
-/* EMIF-A bus pins for 8-bit NAND support on CS3 */
-static const struct pinmux_config emifa_nand_pins[] = {
- { pinmux(13), 1, 6 },
- { pinmux(13), 1, 7 },
- { pinmux(14), 1, 0 },
- { pinmux(14), 1, 1 },
- { pinmux(14), 1, 2 },
- { pinmux(14), 1, 3 },
- { pinmux(14), 1, 4 },
- { pinmux(14), 1, 5 },
- { pinmux(15), 1, 7 },
- { pinmux(16), 1, 0 },
- { pinmux(18), 1, 1 },
- { pinmux(18), 1, 4 },
- { pinmux(18), 1, 5 },
-};
-
-/* EMAC PHY interface pins */
-static const struct pinmux_config emac_pins[] = {
- { pinmux(9), 0, 5 },
- { pinmux(10), 2, 1 },
- { pinmux(10), 2, 2 },
- { pinmux(10), 2, 3 },
- { pinmux(10), 2, 4 },
- { pinmux(10), 2, 5 },
- { pinmux(10), 2, 6 },
- { pinmux(10), 2, 7 },
- { pinmux(11), 2, 0 },
- { pinmux(11), 2, 1 },
-};
-
-/* UART pin muxer settings */
-static const struct pinmux_config uart_pins[] = {
- { pinmux(8), 2, 7 },
- { pinmux(9), 2, 0 }
-};
-
-/* I2C pin muxer settings */
-static const struct pinmux_config i2c_pins[] = {
- { pinmux(8), 2, 3 },
- { pinmux(8), 2, 4 }
-};
-
-#ifdef CONFIG_USE_NAND
-/* NAND pin muxer settings */
-const struct pinmux_config aemif_pins[] = {
- { pinmux(13), 1, 6 },
- { pinmux(13), 1, 7 },
- { pinmux(14), 1, 0 },
- { pinmux(14), 1, 1 },
- { pinmux(14), 1, 2 },
- { pinmux(14), 1, 3 },
- { pinmux(14), 1, 4 },
- { pinmux(14), 1, 5 },
- { pinmux(14), 1, 6 },
- { pinmux(14), 1, 7 },
- { pinmux(15), 1, 0 },
- { pinmux(15), 1, 1 },
- { pinmux(15), 1, 2 },
- { pinmux(15), 1, 3 },
- { pinmux(15), 1, 4 },
- { pinmux(15), 1, 5 },
- { pinmux(15), 1, 6 },
- { pinmux(15), 1, 7 },
- { pinmux(16), 1, 0 },
- { pinmux(16), 1, 1 },
- { pinmux(16), 1, 2 },
- { pinmux(16), 1, 3 },
- { pinmux(16), 1, 4 },
- { pinmux(16), 1, 5 },
- { pinmux(16), 1, 6 },
- { pinmux(16), 1, 7 },
- { pinmux(17), 1, 0 },
- { pinmux(17), 1, 1 },
- { pinmux(17), 1, 2 },
- { pinmux(17), 1, 3 },
- { pinmux(17), 1, 4 },
- { pinmux(17), 1, 5 },
- { pinmux(17), 1, 6 },
- { pinmux(17), 1, 7 },
- { pinmux(18), 1, 0 },
- { pinmux(18), 1, 1 },
- { pinmux(18), 1, 2 },
- { pinmux(18), 1, 3 },
- { pinmux(18), 1, 4 },
- { pinmux(18), 1, 5 },
- { pinmux(18), 1, 6 },
- { pinmux(18), 1, 7 },
- { pinmux(10), 1, 0 }
-};
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
#endif
-
-/* USB0_DRVVBUS pin muxer settings */
-static const struct pinmux_config usb_pins[] = {
- { pinmux(9), 1, 1 }
-};
+DECLARE_GLOBAL_DATA_PTR;
static const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_SPI_FLASH
- PINMUX_ITEM(spi0_pins),
+ PINMUX_ITEM(spi0_pins_base),
+ PINMUX_ITEM(spi0_pins_scs0),
+ PINMUX_ITEM(spi0_pins_ena),
#endif
- PINMUX_ITEM(uart_pins),
- PINMUX_ITEM(i2c_pins),
+ PINMUX_ITEM(uart2_pins_txrx),
+ PINMUX_ITEM(i2c0_pins),
#ifdef CONFIG_USB_DA8XX
PINMUX_ITEM(usb_pins),
#endif
#ifdef CONFIG_USE_NAND
- PINMUX_ITEM(emifa_nand_pins),
- PINMUX_ITEM(aemif_pins),
+ PINMUX_ITEM(emifa_pins),
+ PINMUX_ITEM(emifa_pins_cs0),
+ PINMUX_ITEM(emifa_pins_cs2),
+ PINMUX_ITEM(emifa_pins_cs3),
#endif
#if defined(CONFIG_DRIVER_TI_EMAC)
- PINMUX_ITEM(emac_pins),
+ PINMUX_ITEM(emac_pins_rmii),
+ PINMUX_ITEM(emac_pins_mdio),
+ PINMUX_ITEM(emac_pins_rmii_clk_source),
+#endif
+#ifdef CONFIG_DAVINCI_MMC
+ PINMUX_ITEM(mmc0_pins_8bit)
#endif
};
@@ -177,8 +85,31 @@
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_DAVINCI_MMC
+ { DAVINCI_LPSC_MMC_SD },
+#endif
+
};
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .host_caps = MMC_MODE_8BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+ printf("%x\n", mmc_sd0.input_clk);
+
+ /* Add slot-0 to mmc subsystem */
+ return davinci_mmc_init(bis, &mmc_sd0);
+}
+#endif
+
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index b1b8701..6fa4509 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -55,11 +55,6 @@
__rel_dyn_end = .;
} >.sram
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- } >.sram
-
.bss :
{
. = ALIGN(4);
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
index 596a9e0..b452f20 100644
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -61,7 +61,6 @@
__image_copy_end = .;
__rel_dyn_start = .;
__rel_dyn_end = .;
- __dynsym_start = .;
__got_start = .;
. = ALIGN(4);
diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
index 6d4b187..f359112 100644
--- a/board/dvlhost/u-boot.lds
+++ b/board/dvlhost/u-boot.lds
@@ -30,6 +30,7 @@
. = ALIGN (4);
.text : {
+ *(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
net/libnet.o(.text*)
board/dvlhost/libdvlhost.o(.text*)
@@ -62,17 +63,23 @@
. = ALIGN (4);
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
}
_end = .;
@@ -96,6 +103,7 @@
KEEP(*(.__bss_end));
}
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 29cc41b..1416f98 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -52,6 +52,15 @@
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -137,6 +146,16 @@
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_256M, 1),
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
index 6f4cb26..2e829ad 100644
--- a/board/freescale/bsc9131rdb/Makefile
+++ b/board/freescale/bsc9131rdb/Makefile
@@ -24,12 +24,28 @@
LIB = $(obj)lib$(BOARD).o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y += spl_minimal.o tlb.o law.o
+
+else
+
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
#COBJS-y += bsc9131rdb_mux.o
+endif
+
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README
index 065faa3..4902b98 100644
--- a/board/freescale/bsc9131rdb/README
+++ b/board/freescale/bsc9131rdb/README
@@ -89,10 +89,14 @@
Building U-boot
--------------
To build the u-boot for BSC9131RDB:
-1. NAND Flash
+1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
make BSC9131RDB_NAND
-2. SPI Flash
+2. NAND Flash with sysclk 100MHz(J16 on RDB open)
+ make BSC9131RDB_NAND_SYSCLK100
+3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
make BSC9131RDB_SPIFLASH
+4. SPI Flash with sysclk 100MHz(J16 on RDB open)
+ make BSC9131RDB_SPIFLASH_SYSCLK100
Memory map
-----------
@@ -107,6 +111,16 @@
0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
+DDR Memory map
+---------------
+ 0x0000_0000 0x36FF_FFFF Memory passed onto Linux
+ 0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
+ 0x3800_0000 0x4FFF_FFFF DSP Private area
+
+ Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
+ data communcation between PowerPC and DSP core.
+ Rest is PowerPC private area.
+
Flashing Images
---------------
To place a new u-boot image in the NAND flash and then boot
diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c
index 201c147..0432780 100644
--- a/board/freescale/bsc9131rdb/law.c
+++ b/board/freescale/bsc9131rdb/law.c
@@ -26,6 +26,10 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
+ LAW_TRGT_IF_DSP_CCSR),
+ SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
+ LAW_TRGT_IF_OCN_DSP),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
new file mode 100644
index 0000000..301115e
--- /dev/null
+++ b/board/freescale/bsc9131rdb/spl_minimal.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+static void sdram_init(void)
+{
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+
+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+ __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+#endif
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+
+ /* Set, but do not enable the memory */
+ __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+ set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* Initialize the DDR3 */
+ sdram_init();
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
index 5b68f4a..c05a556 100644
--- a/board/freescale/bsc9131rdb/tlb.c
+++ b/board/freescale/bsc9131rdb/tlb.c
@@ -44,15 +44,26 @@
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+ SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
/* *I*G* - CCSRBAR (PA) */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT)
+ /* CCSRBAR (DSP) */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
+ CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
index 267400b..72b1917 100644
--- a/board/freescale/bsc9132qds/Makefile
+++ b/board/freescale/bsc9132qds/Makefile
@@ -24,11 +24,28 @@
LIB = $(obj)lib$(BOARD).o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y += spl_minimal.o tlb.o law.o
+
+else
+
+
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
+endif
+
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index 6e1b558..ddc9d0a 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -258,7 +258,7 @@
u8 val;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 porbmsr = in_be32(&gur->porbmsr);
- u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+ u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
/*Configure 1588 clock-in source from RF Card*/
val = QIXIS_READ_I2C(brdcfg[5]);
@@ -360,7 +360,7 @@
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 porbmsr = in_be32(&gur->porbmsr);
- u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+ u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
if (!(hwconfig("uart2") && hwconfig("usb1"))) {
/* If uart2 is there in hwconfig remove usb node from
diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c
index dc23658..b4bce99 100644
--- a/board/freescale/bsc9132qds/law.c
+++ b/board/freescale/bsc9132qds/law.c
@@ -25,11 +25,13 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
-#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_FPGA_BASE_PHYS
SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
new file mode 100644
index 0000000..62dee52
--- /dev/null
+++ b/board/freescale/bsc9132qds/spl_minimal.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_init(void)
+{
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+#if CONFIG_DDR_CLK_FREQ == 100000000
+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+#elif CONFIG_DDR_CLK_FREQ == 133000000
+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+#else
+ puts("Not a valid DDR Freq Found! Please Reset\n");
+#endif
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+ set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* Initialize the DDR3 */
+ sdram_init();
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 0e4545f..0ec9a85 100644
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -44,14 +44,20 @@
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+ SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
/* *I*G* - CCSRBAR (PA) */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 3, BOOKE_PAGESZ_64M, 1),
@@ -61,12 +67,6 @@
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
-#if defined(CONFIG_SYS_RAMBOOT)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
#ifdef CONFIG_PCI
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
@@ -78,15 +78,26 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_64K, 1),
#endif
+#endif
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_FPGA_BASE
/* *I*G - Board FPGA */
SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_256K, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 72bb56c..37236d0 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -29,6 +29,15 @@
LIB = $(obj)libfreescale.o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifndef MINIMAL
COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o
COBJS-$(CONFIG_FSL_VIA) += cds_via.o
COBJS-$(CONFIG_FMAN_ENET) += fman.o
@@ -68,6 +77,7 @@
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o
+endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index 8d07061..fbb709d 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -480,6 +480,7 @@
|| unknown_param) {
#ifdef CONFIG_SYS_LONGHELP
puts(cmdtp->help);
+ putc('\n');
#endif
return 1;
}
@@ -512,6 +513,7 @@
&& set_px_mpxpll(mpxpll))) {
#ifdef CONFIG_SYS_LONGHELP
puts(cmdtp->help);
+ putc('\n');
#endif
return 1;
}
diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c
index 41ba303..d25e2b3 100644
--- a/board/freescale/mx23evk/mx23evk.c
+++ b/board/freescale/mx23evk/mx23evk.c
@@ -43,6 +43,12 @@
/* SSP0 clock at 96MHz */
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+ /* Power on LCD */
+ gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1);
+
+ /* Set contrast to maximum */
+ gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
return 0;
}
diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c
index 6be8c8d..fd71f7d 100644
--- a/board/freescale/mx23evk/spl_boot.c
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -27,6 +27,7 @@
#define MUX_CONFIG_SSP1 (MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_LCD (MXS_PAD_4MA | MXS_PAD_NOPULL)
const iomux_cfg_t iomux_setup[] = {
/* DUART */
@@ -96,6 +97,37 @@
/* Slot Power Enable */
MX23_PAD_PWM3__GPIO_1_29 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ /* LCD */
+ MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */
+ MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */
};
#define HW_DRAM_CTL14 (0x38 >> 2)
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index ae6eda3..beae0e6 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -30,6 +30,7 @@
#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
const iomux_cfg_t iomux_setup[] = {
/* DUART */
@@ -162,6 +163,38 @@
/* I2C */
MX28_PAD_I2C0_SCL__I2C0_SCL,
MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* LCD */
+ MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */
+ MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */
};
#define HW_DRAM_CTL29 (0x74 >> 2)
diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c
index de7231b..4edd9f4 100644
--- a/board/freescale/mx28evk/mx28evk.c
+++ b/board/freescale/mx28evk/mx28evk.c
@@ -59,6 +59,12 @@
gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
#endif
+ /* Power on LCD */
+ gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
+
+ /* Set contrast to maximum */
+ gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
+
return 0;
}
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 4969960..963d29f 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -34,6 +34,7 @@
. = ALIGN(4);
.text :
{
+ *(.__image_copy_start)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
@@ -65,17 +66,23 @@
. = ALIGN(4);
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
}
_end = .;
@@ -100,6 +107,7 @@
}
/DISCARD/ : { *(.bss*) }
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynsym*) }
/DISCARD/ : { *(.dynamic*) }
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index bfe4868..2a6e3a9 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -26,12 +26,14 @@
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
+#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -46,6 +48,12 @@
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -76,6 +84,45 @@
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
+/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+/*
+ * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
+ * Compass Sensor, Accelerometer, Res Touch
+ */
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+iomux_v3_cfg_t const i2c3_pads[] = {
+ MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const port_exp[] = {
+ MX6_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
@@ -216,6 +263,16 @@
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ /* I2C 3 Steer */
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+ imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+ gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+ imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
+
return 0;
}
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 8ce054e..862bc30 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -308,7 +308,6 @@
void setup_spi(void)
{
- gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
ARRAY_SIZE(ecspi1_pads));
}
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index 4c705b6..e6563be 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -24,11 +24,27 @@
LIB = $(obj)lib$(BOARD).o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y += spl_minimal.o tlb.o law.o
+
+else
+
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
+endif
+
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/board/freescale/p1010rdb/spl_minimal.c
similarity index 94%
rename from nand_spl/board/freescale/p1010rdb/nand_boot.c
rename to board/freescale/p1010rdb/spl_minimal.c
index 3c7bc2b..c909e0e 100644
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -31,11 +31,18 @@
DECLARE_GLOBAL_DATA_PTR;
-unsigned long ddr_freq_mhz;
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 ddr_ratio;
+ unsigned long ddr_freq_mhz;
+
+ ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+ ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+ ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
+
/* mask off E bit */
u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
@@ -81,6 +88,7 @@
__raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
}
+ asm volatile("sync;isync");
udelay(500);
/* Let the controller go */
@@ -91,7 +99,7 @@
void board_init_f(ulong bootflag)
{
- u32 plat_ratio, ddr_ratio;
+ u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* initialize selected port with appropriate baud rate */
@@ -99,10 +107,6 @@
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
- ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
-
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
@@ -115,8 +119,8 @@
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 4256bf4..078717a 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -44,15 +44,20 @@
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+ SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_SDCARD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
@@ -88,7 +93,7 @@
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1)
diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile
new file mode 100644
index 0000000..45c4f8b
--- /dev/null
+++ b/board/freescale/p1023rdb/Makefile
@@ -0,0 +1,33 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
new file mode 100644
index 0000000..7ed275a
--- /dev/null
+++ b/board/freescale/p1023rdb/ddr.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Hynix H5TQ1G83TFR-H9C
+ */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 536870912u,
+ .capacity = 536870912u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tCKmin_X_ps = 1875,
+ .caslat_X = 0x1e << 4, /* 5,6,7,8 */
+ .tAA_ps = 13125,
+ .tWR_ps = 18000,
+ .tRCD_ps = 13125,
+ .tRRD_ps = 7500,
+ .tRP_ps = 13125,
+ .tRAS_ps = 37500,
+ .tRC_ps = 50625,
+ .tRFC_ps = 160000,
+ .tWTR_ps = 7500,
+ .tRTP_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tFAW_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+ popts->clk_adjust = 6;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x8;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
+
diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c
new file mode 100644
index 0000000..331662c
--- /dev/null
+++ b/board/freescale/p1023rdb/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
+ LAW_TRGT_IF_DPAA_SWP_SRAM),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
new file mode 100644
index 0000000..918398b
--- /dev/null
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors: Roy Zang <tie-fei.zang@freescale.com>
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_portals.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ /* Set ABSWP to implement conversion of addresses in the LBC */
+ setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: P1023 RDB\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ setup_portals();
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ return gd->bus_clk;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ return gd->mem_clk;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+
+ /*
+ * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
+ * is not correct.
+ */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
+
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+
+ fm_info_set_mdio(FM1_DTSEC1,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ fm_info_set_mdio(FM1_DTSEC2,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+#ifdef CONFIG_FMAN_ENET
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+ fdt_fixup_fman_ethernet(blob);
+}
+#endif
diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
new file mode 100644
index 0000000..3417c0f
--- /dev/null
+++ b/board/freescale/p1023rdb/tlb.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_4M, 1),
+
+ /* W**G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 9, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_1M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_16K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+ CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 92c01cf..a138d5a 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -55,6 +55,15 @@
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -130,6 +139,16 @@
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 17, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
};
diff --git a/board/ti/omap2420h4/Makefile b/board/freescale/vf610twr/Makefile
similarity index 72%
copy from board/ti/omap2420h4/Makefile
copy to board/freescale/vf610twr/Makefile
index cddd7e6..7416228 100644
--- a/board/ti/omap2420h4/Makefile
+++ b/board/freescale/vf610twr/Makefile
@@ -1,9 +1,5 @@
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright 2013 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -25,15 +21,13 @@
LIB = $(obj)lib$(BOARD).o
-COBJS := omap2420h4.o mem.o sys_info.o
-SOBJS := lowlevel_init.o
+COBJS := $(BOARD).o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg
new file mode 100644
index 0000000..b00d4c1
--- /dev/null
+++ b/board/freescale/vf610twr/imximage.cfg
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET FLASH_OFFSET_STANDARD
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
new file mode 100644
index 0000000..f14df8b
--- /dev/null
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -0,0 +1,407 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+void setup_iomux_ddr(void)
+{
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A14__DDR_A_14,
+ VF610_PAD_DDR_A13__DDR_A_13,
+ VF610_PAD_DDR_A12__DDR_A_12,
+ VF610_PAD_DDR_A11__DDR_A_11,
+ VF610_PAD_DDR_A10__DDR_A_10,
+ VF610_PAD_DDR_A9__DDR_A_9,
+ VF610_PAD_DDR_A8__DDR_A_8,
+ VF610_PAD_DDR_A7__DDR_A_7,
+ VF610_PAD_DDR_A6__DDR_A_6,
+ VF610_PAD_DDR_A5__DDR_A_5,
+ VF610_PAD_DDR_A4__DDR_A_4,
+ VF610_PAD_DDR_A3__DDR_A_3,
+ VF610_PAD_DDR_A2__DDR_A_2,
+ VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_BA2__DDR_BA_2,
+ VF610_PAD_DDR_BA1__DDR_BA_1,
+ VF610_PAD_DDR_BA0__DDR_BA_0,
+ VF610_PAD_DDR_CAS__DDR_CAS_B,
+ VF610_PAD_DDR_CKE__DDR_CKE_0,
+ VF610_PAD_DDR_CLK__DDR_CLK_0,
+ VF610_PAD_DDR_CS__DDR_CS_B_0,
+ VF610_PAD_DDR_D15__DDR_D_15,
+ VF610_PAD_DDR_D14__DDR_D_14,
+ VF610_PAD_DDR_D13__DDR_D_13,
+ VF610_PAD_DDR_D12__DDR_D_12,
+ VF610_PAD_DDR_D11__DDR_D_11,
+ VF610_PAD_DDR_D10__DDR_D_10,
+ VF610_PAD_DDR_D9__DDR_D_9,
+ VF610_PAD_DDR_D8__DDR_D_8,
+ VF610_PAD_DDR_D7__DDR_D_7,
+ VF610_PAD_DDR_D6__DDR_D_6,
+ VF610_PAD_DDR_D5__DDR_D_5,
+ VF610_PAD_DDR_D4__DDR_D_4,
+ VF610_PAD_DDR_D3__DDR_D_3,
+ VF610_PAD_DDR_D2__DDR_D_2,
+ VF610_PAD_DDR_D1__DDR_D_1,
+ VF610_PAD_DDR_D0__DDR_D_0,
+ VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ VF610_PAD_DDR_RAS__DDR_RAS_B,
+ VF610_PAD_DDR_WE__DDR_WE_B,
+ VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddr_phy_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
+
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
+
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
+
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
+
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
+
+ writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
+ &ddrmr->phy[50]);
+}
+
+void ddr_ctrl_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+ writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
+ writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
+
+ writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
+ writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
+ writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
+ DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
+ writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
+ DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
+ writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
+ writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
+ &ddrmr->cr[17]);
+ writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
+
+ writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+ writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
+ DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+
+ writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
+ writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
+ writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
+
+ writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+ writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
+ writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
+ writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
+
+ writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
+ writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
+ writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+ writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
+
+ writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
+ writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+ DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+ writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+ writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
+ &ddrmr->cr[48]);
+
+ writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
+ writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
+ writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+ writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
+ writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
+
+ writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
+ DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
+ writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+ DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
+ &ddrmr->cr[74]);
+ writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+ DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+ writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+ DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
+ writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+ DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+ writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
+ writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
+
+ writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+ writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
+ &ddrmr->cr[87]);
+ writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+ writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+ writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+ writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
+
+ writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
+ writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
+ writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
+
+ writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
+ &ddrmr->cr[117]);
+ writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
+ &ddrmr->cr[118]);
+
+ writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
+ &ddrmr->cr[120]);
+ writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
+ &ddrmr->cr[121]);
+ writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+ DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
+ writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
+ &ddrmr->cr[123]);
+ writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
+
+ writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
+ writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
+ &ddrmr->cr[132]);
+ writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+ DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
+ &ddrmr->cr[139]);
+
+ writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+ DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
+ writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
+ &ddrmr->cr[155]);
+ writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+
+ ddr_phy_init();
+
+ writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+ udelay(200);
+}
+
+int dram_init(void)
+{
+ setup_iomux_ddr();
+
+ ddr_ctrl_init();
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart1_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+ static const iomux_v3_cfg_t enet0_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* eSDHC1 is always present */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t esdhc1_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+ };
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(
+ esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static void clock_init(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+ clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+ CCM_CCGR0_UART1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+ CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+ CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+ CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+ CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+ CCM_CCGR3_ANADIG_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+ CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+ CCM_CCGR4_GPC_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+ CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+ CCM_CCGR7_SDHC1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+ CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+
+ clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+ ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+ clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+ ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+ clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+ CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+ clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+ CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
+ CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+ CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+ CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+ CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
+ CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+ clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+ CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+ CCM_CACRR_ARM_CLK_DIV(0));
+ clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+ CCM_CSCMR1_ESDHC1_CLK_SEL(3));
+ clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+ CCM_CSCDR1_RMII_CLK_EN);
+ clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+ CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+ clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+ CCM_CSCMR2_RMII_CLK_SEL(0));
+}
+
+static void mscm_init(void)
+{
+ struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ clock_init();
+ mscm_init();
+
+ setup_iomux_uart();
+ setup_iomux_enet();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: vf610twr\n");
+
+ return 0;
+}
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index 923461a..7f0330d 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -28,7 +28,7 @@
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/arch/dss.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include "errno.h"
#include <i2c.h>
#ifdef CONFIG_USB_EHCI
diff --git a/board/ti/omap2420h4/Makefile b/board/icpdas/lp8x4x/Makefile
similarity index 73%
rename from board/ti/omap2420h4/Makefile
rename to board/icpdas/lp8x4x/Makefile
index cddd7e6..cbe6aa9 100644
--- a/board/ti/omap2420h4/Makefile
+++ b/board/icpdas/lp8x4x/Makefile
@@ -1,9 +1,7 @@
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# ICPDAS LP-8x4x Support
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -25,15 +23,13 @@
LIB = $(obj)lib$(BOARD).o
-COBJS := omap2420h4.o mem.o sys_info.o
-SOBJS := lowlevel_init.o
+COBJS := lp8x4x.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c
new file mode 100644
index 0000000..76f0700
--- /dev/null
+++ b/board/icpdas/lp8x4x/lp8x4x.c
@@ -0,0 +1,147 @@
+/*
+ * ICP DAS LP-8x4x Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * adapted from Voipac PXA270 Support by
+ * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/pxa.h>
+#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+int usb_board_init(void)
+{
+ writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ continue; /* required by checkpath.pl */
+
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+ /* Clear any OTG Pin Hold */
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+ /* Set port power control mask bits, only 3 ports. */
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+ /* enable port 2 */
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+ return 0;
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
+ udelay(10);
+
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+ return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+void lp8x4x_eth1_mac_init(void)
+{
+ u8 eth1addr[8];
+ int i;
+ u8 reg;
+
+ eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
+ if (!is_valid_ether_addr(eth1addr))
+ return;
+
+ for (i = 0, reg = 0x10; i < 6; i++, reg++) {
+ writeb(reg, (u8 *)(DM9000_IO_2));
+ writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+ lp8x4x_eth1_mac_init();
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 826cead..ea3bea5 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -36,37 +36,13 @@
DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
/* MII mode defines */
#define RMII_MODE_ENABLE 0x4D
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-/* UART Defines */
#ifdef CONFIG_SPL_BUILD
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
- struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
- /*
- * Unlock the RTC's registers. For more details please see the
- * RTC_SS section of the TRM. In order to unlock we need to
- * write these specific values (keys) in this order.
- */
- writel(0x83e70b13, &rtc->kick0r);
- writel(0x95a4f1e0, &rtc->kick1r);
-
- /* Enable the RTC 32K OSC by setting bits 3 and 6. */
- writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
static const struct ddr_data ddr3_data = {
.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
@@ -131,23 +107,9 @@
/* Enable RTC32K clock */
rtc32k_enable();
- /* UART softreset */
- u32 regval;
-
enable_uart0_pin_mux();
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_RESET;
- writel(regval, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
- ;
-
- /* Disable smart idle */
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_SMART_IDLE_EN;
- writel(regval, &uart_base->uartsyscfg);
-
+ uart_soft_reset();
gd = &gdata;
preloader_console_init();
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index eda9199..b944887 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -160,7 +160,7 @@
}
#endif
-int initialize_unit_leds(void)
+static int initialize_unit_leds(void)
{
/*
* Init the unit LEDs per default they all are
@@ -181,7 +181,7 @@
}
#if defined(CONFIG_BOOTCOUNT_LIMIT)
-void set_bootcount_addr(void)
+static void set_bootcount_addr(void)
{
uchar buf[32];
unsigned int bootcountaddr;
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 93c611d..0cca8d7 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -39,9 +39,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
@@ -50,31 +47,11 @@
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-/* UART defines */
#ifdef CONFIG_SPL_BUILD
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
/* DDR RAM defines */
#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
-static void rtc32k_enable(void)
-{
- struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
- /*
- * Unlock the RTC's registers. For more details please see the
- * RTC_SS section of the TRM. In order to unlock we need to
- * write these specific values (keys) in this order.
- */
- writel(0x83e70b13, &rtc->kick0r);
- writel(0x95a4f1e0, &rtc->kick1r);
-
- /* Enable the RTC 32K OSC by setting bits 3 and 6. */
- writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J256M8HX15E_RD_DQS,
.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
@@ -141,22 +118,8 @@
/* Enable RTC32K clock */
rtc32k_enable();
- /* UART softreset */
- u32 regval;
-
enable_uart0_pin_mux();
-
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_RESET;
- writel(regval, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
- != UART_CLK_RUNNING_MASK)
- ;
-
- /* Disable smart idle */
- regval = readl(&uart_base->uartsyscfg);
- regval |= UART_SMART_IDLE_EN;
- writel(regval, &uart_base->uartsyscfg);
+ uart_soft_reset();
gd = &gdata;
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts
index 8da973b..93375a6 100644
--- a/board/samsung/dts/exynos5250-smdk5250.dts
+++ b/board/samsung/dts/exynos5250-smdk5250.dts
@@ -30,6 +30,10 @@
spi2 = "/spi@12d40000";
spi3 = "/spi@131a0000";
spi4 = "/spi@131b0000";
+ mmc0 = "/mmc@12200000";
+ mmc1 = "/mmc@12210000";
+ mmc2 = "/mmc@12220000";
+ mmc3 = "/mmc@12230000";
};
sromc@12250000 {
@@ -119,4 +123,24 @@
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
};
+
+ mmc@12200000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ samsung,removable = <0>;
+ };
+
+ mmc@12210000 {
+ status = "disabled";
+ };
+
+ mmc@12220000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ samsung,removable = <1>;
+ };
+
+ mmc@12230000 {
+ status = "disabled";
+ };
};
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index 9daa0da..be9d418 100644
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -87,12 +87,14 @@
1:
/* for UART */
bl uart_asm_init
+ bl arch_cpu_init
bl tzpc_init
pop {pc}
wakeup_reset:
bl system_clock_init
bl mem_ctrl_asm_init
+ bl arch_cpu_init
bl tzpc_init
exit_wakeup:
@@ -353,45 +355,3 @@
nop
nop
-/* Setting TZPC[TrustZone Protection Controller] */
-tzpc_init:
- ldr r0, =TZPC0_BASE
- mov r1, #R0SIZE
- str r1, [r0]
- mov r1, #DECPROTXSET
- str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
- ldr r0, =TZPC1_BASE
- str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
- ldr r0, =TZPC2_BASE
- str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
- ldr r0, =TZPC3_BASE
- str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
- ldr r0, =TZPC4_BASE
- str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
- ldr r0, =TZPC5_BASE
- str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
- str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
- mov pc, lr
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index 930b948..926a4cc 100644
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -121,19 +121,6 @@
#define UBRDIV_OFFSET 0x28
#define UFRACVAL_OFFSET 0x2C
-/* TZPC : Register Offsets */
-#define TZPC0_BASE 0x10110000
-#define TZPC1_BASE 0x10120000
-#define TZPC2_BASE 0x10130000
-#define TZPC3_BASE 0x10140000
-#define TZPC4_BASE 0x10150000
-#define TZPC5_BASE 0x10160000
-
-#define TZPC_DECPROT0SET_OFFSET 0x804
-#define TZPC_DECPROT1SET_OFFSET 0x810
-#define TZPC_DECPROT2SET_OFFSET 0x81C
-#define TZPC_DECPROT3SET_OFFSET 0x828
-
/* CLK_SRC_CPU */
#define MUX_HPM_SEL_MOUTAPLL 0x0
#define MUX_HPM_SEL_SCLKMPLL 0x1
@@ -617,16 +604,4 @@
* UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
*/
#define UFRACVAL_VAL 0x4
-
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE 0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET 0xFF
#endif
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 47c6a5a..f2c32ee 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -28,12 +28,15 @@
COBJS := clock_init.o
COBJS += dmc_common.o dmc_init_ddr3.o
-COBJS += tzpc_init.o
COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_OF_CONTROL
+COBJS += exynos5-dt.o
+else
COBJS += smdk5250.o
endif
+endif
ifdef CONFIG_SPL_BUILD
COBJS += spl_boot.o
diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c
index 5b9e82f..b288e66 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -28,10 +28,14 @@
#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
#include <asm/arch/spl.h>
+#include <asm/arch/dwmmc.h>
#include "clock_init.h"
#include "setup.h"
+#define FSYS1_MMC0_DIV_MASK 0xff0f
+#define FSYS1_MMC0_DIV_VAL 0x0701
+
DECLARE_GLOBAL_DATA_PTR;
struct arm_clk_ratios arm_clk_ratios[] = {
@@ -664,3 +668,17 @@
/* We run DP at 267 Mhz */
setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
}
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
+ */
+void emmc_boot_clk_div_set(void)
+{
+ struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+ unsigned int div_mmc;
+
+ div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
+ div_mmc |= FSYS1_MMC0_DIV_VAL;
+ writel(div_mmc, (unsigned int) &clk->div_fsys1);
+}
diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h
index f751bcb..20a1d47 100644
--- a/board/samsung/smdk5250/clock_init.h
+++ b/board/samsung/smdk5250/clock_init.h
@@ -146,4 +146,9 @@
* Initialize clock for the device
*/
void system_clock_init(void);
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ */
+void emmc_boot_clk_div_set(void);
#endif
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
new file mode 100644
index 0000000..8131505
--- /dev/null
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -0,0 +1,423 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <spi.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/sromc.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <tmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined CONFIG_EXYNOS_TMU
+/*
+ * Boot Time Thermal Analysis for SoC temperature threshold breach
+ */
+static void boot_temp_check(void)
+{
+ int temp;
+
+ switch (tmu_monitor(&temp)) {
+ /* Status TRIPPED ans WARNING means corresponding threshold breach */
+ case TMU_STATUS_TRIPPED:
+ puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
+ set_ps_hold_ctrl();
+ hang();
+ break;
+ case TMU_STATUS_WARNING:
+ puts("EXYNOS_TMU: WARNING! Temperature very high\n");
+ break;
+ /*
+ * TMU_STATUS_INIT means something is wrong with temperature sensing
+ * and TMU status was changed back from NORMAL to INIT.
+ */
+ case TMU_STATUS_INIT:
+ default:
+ debug("EXYNOS_TMU: Unknown TMU state\n");
+ }
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_vbus_init(void)
+{
+ struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+ samsung_get_base_gpio_part1();
+
+ /* Enable VBUS power switch */
+ s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+
+ /* VBUS turn ON time */
+ mdelay(3);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SOUND_MAX98095
+static void board_enable_audio_codec(void)
+{
+ struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+ samsung_get_base_gpio_part1();
+
+ /* Enable MAX98095 Codec */
+ s5p_gpio_direction_output(&gpio1->x1, 7, 1);
+ s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+}
+#endif
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+
+#if defined CONFIG_EXYNOS_TMU
+ if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
+ debug("%s: Failed to init TMU\n", __func__);
+ return -1;
+ }
+ boot_temp_check();
+#endif
+
+#ifdef CONFIG_EXYNOS_SPI
+ spi_init();
+#endif
+#ifdef CONFIG_USB_EHCI_EXYNOS
+ board_usb_vbus_init();
+#endif
+#ifdef CONFIG_SOUND_MAX98095
+ board_enable_audio_codec();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ int i;
+ u32 addr;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ }
+ return 0;
+}
+
+#if defined(CONFIG_POWER)
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
+{
+ u32 val;
+ int ret = 0;
+
+ ret = pmic_reg_read(p, reg, &val);
+ if (ret) {
+ debug("%s: PMIC %d register read failed\n", __func__, reg);
+ return -1;
+ }
+ val |= regval;
+ ret = pmic_reg_write(p, reg, val);
+ if (ret) {
+ debug("%s: PMIC %d register write failed\n", __func__, reg);
+ return -1;
+ }
+ return 0;
+}
+
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ set_ps_hold_ctrl();
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ if (pmic_init(I2C_PMIC))
+ return -1;
+
+ p = pmic_get("MAX77686_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+ MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+ return -1;
+
+ /* VDD_MIF */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+ MAX77686_BUCK1OUT_1V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK1OUT);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+ MAX77686_BUCK1CTRL_EN))
+ return -1;
+
+ /* VDD_ARM */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+ MAX77686_BUCK2DVS1_1_3V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK2DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+ MAX77686_BUCK2CTRL_ON))
+ return -1;
+
+ /* VDD_INT */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+ MAX77686_BUCK3DVS1_1_0125V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK3DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_G3D */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+ MAX77686_BUCK4DVS1_1_2V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK4DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_LDO2 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+ MAX77686_LD02CTRL1_1_5V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO3 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+ MAX77686_LD03CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO5 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+ MAX77686_LD05CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO10 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+ MAX77686_LD10CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ return 0;
+}
+#endif
+
+void dram_init_banksize(void)
+{
+ int i;
+ u32 addr, size;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+ gd->bd->bi_dram[i].start = addr;
+ gd->bd->bi_dram[i].size = size;
+ }
+}
+
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+ int err;
+ int node;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+ if (node < 0) {
+ debug("Could not find SROMC node\n");
+ return node;
+ }
+
+ config->bank = fdtdec_get_int(blob, node, "bank", 0);
+ config->width = fdtdec_get_int(blob, node, "width", 2);
+
+ err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+ FDT_SROM_TIMING_COUNT);
+ if (err < 0) {
+ debug("Could not decode SROMC configuration Error: %s\n",
+ fdt_strerror(err));
+ return -FDT_ERR_NOTFOUND;
+ }
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+ u32 smc_bw_conf, smc_bc_conf;
+ struct fdt_sromc config;
+ fdt_addr_t base_addr;
+ int node;
+
+ node = decode_sromc(gd->fdt_blob, &config);
+ if (node < 0) {
+ debug("%s: Could not find sromc configuration\n", __func__);
+ return 0;
+ }
+ node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+ if (node < 0) {
+ debug("%s: Could not find lan9215 configuration\n", __func__);
+ return 0;
+ }
+
+ /* We now have a node, so any problems from now on are errors */
+ base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (base_addr == FDT_ADDR_T_NONE) {
+ debug("%s: Could not find lan9215 address\n", __func__);
+ return -1;
+ }
+
+ /* Ethernet needs data bus width of 16 bits */
+ if (config.width != 2) {
+ debug("%s: Unsupported bus width %d\n", __func__,
+ config.width);
+ return -1;
+ }
+ smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+ | SROMC_BYTE_ENABLE(config.bank);
+
+ smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
+ SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
+ SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
+ SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
+ SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
+ SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
+ SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+ /* Select and configure the SROMC bank */
+ exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+ s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+ return smc911x_initialize(0, base_addr);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ const char *board_name;
+
+ board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ if (board_name == NULL)
+ printf("\nUnknown Board\n");
+ else
+ printf("\nBoard: %s\n", board_name);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ /* dwmmc initializattion for available channels */
+ ret = exynos_dwmmc_init(gd->fdt_blob);
+ if (ret)
+ debug("dwmmc init failed\n");
+
+ return ret;
+}
+#endif
+
+static int board_uart_init(void)
+{
+ int err, uart_id, ret = 0;
+
+ for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+ err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART%d not configured\n",
+ (uart_id - PERIPH_ID_UART0));
+ ret |= err;
+ }
+ }
+ return ret;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int err;
+ err = board_uart_init();
+ if (err) {
+ debug("UART init failed\n");
+ return err;
+ }
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ board_i2c_init(gd->fdt_blob);
+#endif
+ return err;
+}
+#endif
+
+#ifdef CONFIG_LCD
+void exynos_cfg_lcd_gpio(void)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+
+ /* For Backlight */
+ s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+ s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+ /* LCD power on */
+ s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+ s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+ /* Set Hotplug detect for DP */
+ s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+void exynos_set_dp_phy(unsigned int onoff)
+{
+ set_dp_phy_ctrl(onoff);
+}
+#endif
diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S
index bc6cb6f..edc565e 100644
--- a/board/samsung/smdk5250/lowlevel_init.S
+++ b/board/samsung/smdk5250/lowlevel_init.S
@@ -75,12 +75,14 @@
bl mem_ctrl_init
1:
+ bl arch_cpu_init
bl tzpc_init
ldmia r13!, {ip,pc}
wakeup_reset:
bl system_clock_init
bl mem_ctrl_init
+ bl arch_cpu_init
bl tzpc_init
exit_wakeup:
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
index 34d8bc31..eb91d13 100644
--- a/board/samsung/smdk5250/setup.h
+++ b/board/samsung/smdk5250/setup.h
@@ -28,18 +28,6 @@
#include <config.h>
#include <asm/arch/dmc.h>
-/* TZPC : Register Offsets */
-#define TZPC0_BASE 0x10100000
-#define TZPC1_BASE 0x10110000
-#define TZPC2_BASE 0x10120000
-#define TZPC3_BASE 0x10130000
-#define TZPC4_BASE 0x10140000
-#define TZPC5_BASE 0x10150000
-#define TZPC6_BASE 0x10160000
-#define TZPC7_BASE 0x10170000
-#define TZPC8_BASE 0x10180000
-#define TZPC9_BASE 0x10190000
-
/* APLL_CON1 */
#define APLL_CON1_VAL (0x00203800)
@@ -458,18 +446,6 @@
/* CLK_GATE_IP_DISP1 */
#define CLK_GATE_DP1_ALLOW (1 << 4)
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE 0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET 0xFF
-
#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
@@ -590,5 +566,4 @@
void sdelay(unsigned long);
void mem_ctrl_init(void);
void system_clock_init(void);
-void tzpc_init(void);
#endif
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 8b09e1d..276fd41 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -29,6 +29,7 @@
#include <netdev.h>
#include <spi.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
@@ -37,39 +38,9 @@
#include <asm/arch/dp_info.h>
#include <power/pmic.h>
#include <power/max77686_pmic.h>
-#include <tmu.h>
DECLARE_GLOBAL_DATA_PTR;
-#if defined CONFIG_EXYNOS_TMU
-/*
- * Boot Time Thermal Analysis for SoC temperature threshold breach
- */
-static void boot_temp_check(void)
-{
- int temp;
-
- switch (tmu_monitor(&temp)) {
- /* Status TRIPPED ans WARNING means corresponding threshold breach */
- case TMU_STATUS_TRIPPED:
- puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
- set_ps_hold_ctrl();
- hang();
- break;
- case TMU_STATUS_WARNING:
- puts("EXYNOS_TMU: WARNING! Temperature very high\n");
- break;
- /*
- * TMU_STATUS_INIT means something is wrong with temperature sensing
- * and TMU status was changed back from NORMAL to INIT.
- */
- case TMU_STATUS_INIT:
- default:
- debug("EXYNOS_TMU: Unknown TMU state\n");
- }
-}
-#endif
-
#ifdef CONFIG_USB_EHCI_EXYNOS
int board_usb_vbus_init(void)
{
@@ -102,14 +73,6 @@
{
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
-#if defined CONFIG_EXYNOS_TMU
- if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
- debug("%s: Failed to init TMU\n", __func__);
- return -1;
- }
- boot_temp_check();
-#endif
-
#ifdef CONFIG_EXYNOS_SPI
spi_init();
#endif
@@ -124,14 +87,13 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
- + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
+ int i;
+ u32 addr;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ }
return 0;
}
@@ -254,57 +216,15 @@
void dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
- PHYS_SDRAM_2_SIZE);
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
- PHYS_SDRAM_3_SIZE);
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
- PHYS_SDRAM_4_SIZE);
- gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
- gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
- PHYS_SDRAM_5_SIZE);
- gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
- gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
- PHYS_SDRAM_6_SIZE);
- gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
- gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
- PHYS_SDRAM_7_SIZE);
- gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
- gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
- PHYS_SDRAM_8_SIZE);
-}
-
-#ifdef CONFIG_OF_CONTROL
-static int decode_sromc(const void *blob, struct fdt_sromc *config)
-{
- int err;
- int node;
-
- node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
- if (node < 0) {
- debug("Could not find SROMC node\n");
- return node;
+ int i;
+ u32 addr, size;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ gd->bd->bi_dram[i].start = addr;
+ gd->bd->bi_dram[i].size = size;
}
-
- config->bank = fdtdec_get_int(blob, node, "bank", 0);
- config->width = fdtdec_get_int(blob, node, "width", 2);
-
- err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
- FDT_SROM_TIMING_COUNT);
- if (err < 0) {
- debug("Could not decode SROMC configuration\n");
- return -FDT_ERR_NOTFOUND;
- }
-
- return 0;
}
-#endif
int board_eth_init(bd_t *bis)
{
@@ -313,27 +233,6 @@
struct fdt_sromc config;
fdt_addr_t base_addr;
-#ifdef CONFIG_OF_CONTROL
- int node;
-
- node = decode_sromc(gd->fdt_blob, &config);
- if (node < 0) {
- debug("%s: Could not find sromc configuration\n", __func__);
- return 0;
- }
- node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
- if (node < 0) {
- debug("%s: Could not find lan9215 configuration\n", __func__);
- return 0;
- }
-
- /* We now have a node, so any problems from now on are errors */
- base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
- if (base_addr == FDT_ADDR_T_NONE) {
- debug("%s: Could not find lan9215 address\n", __func__);
- return -1;
- }
-#else
/* Non-FDT configuration - bank number and timing parameters*/
config.bank = CONFIG_ENV_SROM_BANK;
config.width = 2;
@@ -346,7 +245,6 @@
config.timing[FDT_SROM_TACP] = 0x09;
config.timing[FDT_SROM_PMC] = 0x01;
base_addr = CONFIG_SMC911X_BASE;
-#endif
/* Ethernet needs data bus width of 16 bits */
if (config.width != 2) {
@@ -376,17 +274,7 @@
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
-#ifdef CONFIG_OF_CONTROL
- const char *board_name;
-
- board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- if (board_name == NULL)
- printf("\nUnknown Board\n");
- else
- printf("\nBoard: %s\n", board_name);
-#else
printf("\nBoard: SMDK5250\n");
-#endif
return 0;
}
#endif
@@ -394,48 +282,54 @@
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- int err;
+ int err, ret = 0, index, bus_width;
+ u32 base;
err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
- if (err) {
+ if (err)
debug("SDMMC0 not configured\n");
- return err;
- }
+ ret |= err;
- err = s5p_mmc_init(0, 8);
- return err;
+ /*EMMC: dwmmc Channel-0 with 8 bit bus width */
+ index = 0;
+ base = samsung_get_base_mmc() + (0x10000 * index);
+ bus_width = 8;
+ err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
+ if (err)
+ debug("dwmmc Channel-0 init failed\n");
+ ret |= err;
+
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err)
+ debug("SDMMC2 not configured\n");
+ ret |= err;
+
+ /*SD: dwmmc Channel-2 with 4 bit bus width */
+ index = 2;
+ base = samsung_get_base_mmc() + (0x10000 * index);
+ bus_width = 4;
+ err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
+ if (err)
+ debug("dwmmc Channel-2 init failed\n");
+ ret |= err;
+
+ return ret;
}
#endif
static int board_uart_init(void)
{
- int err;
+ int err, uart_id, ret = 0;
- err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART0 not configured\n");
- return err;
+ for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+ err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART%d not configured\n",
+ (uart_id - PERIPH_ID_UART0));
+ ret |= err;
+ }
}
-
- err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART1 not configured\n");
- return err;
- }
-
- err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART2 not configured\n");
- return err;
- }
-
- err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
- if (err) {
- debug("UART3 not configured\n");
- return err;
- }
-
- return 0;
+ return ret;
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
@@ -448,7 +342,7 @@
return err;
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
- board_i2c_init(gd->fdt_blob);
+ board_i2c_init(NULL);
#endif
return err;
}
@@ -477,7 +371,6 @@
set_dp_phy_ctrl(onoff);
}
-#ifndef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
.vl_freq = 60,
.vl_col = 2560,
@@ -543,13 +436,9 @@
.edp_dev_info = &edp_info,
};
-#endif
void init_panel_info(vidinfo_t *vid)
{
-#ifndef CONFIG_OF_CONTROL
- vid->rgb_mode = MODE_RGB_P,
-
+ vid->rgb_mode = MODE_RGB_P;
exynos_set_dp_platform_data(&dp_platform_data);
-#endif
}
#endif
diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c
index c0bcf46..98f2286 100644
--- a/board/samsung/smdk5250/spl_boot.c
+++ b/board/samsung/smdk5250/spl_boot.c
@@ -23,16 +23,44 @@
#include<common.h>
#include<config.h>
+#include <asm/arch-exynos/dmc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+
+#include "clock_init.h"
+
+/* Index into irom ptr table */
+enum index {
+ MMC_INDEX,
+ EMMC44_INDEX,
+ EMMC44_END_INDEX,
+ SPI_INDEX,
+ USB_INDEX,
+};
+
+/* IROM Function Pointers Table */
+u32 irom_ptr_table[] = {
+ [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
+ [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
+ [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
+ -EMMC4.4 end boot operation */
+ [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
+ [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
+ };
+
enum boot_mode {
BOOT_MODE_MMC = 4,
BOOT_MODE_SERIAL = 20,
+ BOOT_MODE_EMMC = 8, /* EMMC4.4 */
/* Boot based on Operating Mode pin settings */
BOOT_MODE_OM = 32,
BOOT_MODE_USB, /* Boot using USB download */
};
- typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst);
- typedef u32 (*usb_copy_func_t)(void);
+void *get_irom_func(int index)
+{
+ return (void *)*(u32 *)irom_ptr_table[index];
+}
/*
* Set/clear program flow prediction and return the previous state.
@@ -55,13 +83,15 @@
*/
void copy_uboot_to_ram(void)
{
- spi_copy_func_t spi_copy;
- usb_copy_func_t usb_copy;
-
int is_cr_z_set;
unsigned int sec_boot_check;
enum boot_mode bootmode = BOOT_MODE_OM;
- u32 (*copy_bl2)(u32, u32, u32);
+
+ u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst);
+ u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst);
+ u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
+ void (*end_bootop_from_emmc)(void);
+ u32 (*usb_copy)(void);
/* Read iRAM location to check for secondary USB boot mode */
sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
@@ -73,14 +103,24 @@
switch (bootmode) {
case BOOT_MODE_SERIAL:
- spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR;
+ spi_copy = get_irom_func(SPI_INDEX);
spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
- CONFIG_SYS_TEXT_BASE);
+ CONFIG_SYS_TEXT_BASE);
break;
case BOOT_MODE_MMC:
- copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+ copy_bl2 = get_irom_func(MMC_INDEX);
copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
- CONFIG_SYS_TEXT_BASE);
+ CONFIG_SYS_TEXT_BASE);
+ break;
+ case BOOT_MODE_EMMC:
+ /* Set the FSYS1 clock divisor value for EMMC boot */
+ emmc_boot_clk_div_set();
+
+ copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
+ end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
+
+ copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
+ end_bootop_from_emmc();
break;
case BOOT_MODE_USB:
/*
@@ -88,8 +128,7 @@
* before copy from USB device to RAM
*/
is_cr_z_set = config_branch_prediction(0);
- usb_copy = *(usb_copy_func_t *)
- EXYNOS_COPY_USB_FNPTR_ADDR;
+ usb_copy = get_irom_func(USB_INDEX);
usb_copy();
config_branch_prediction(is_cr_z_set);
break;
@@ -117,5 +156,4 @@
while (1)
;
}
-
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
index 7a1ea98..31e0e2e 100644
--- a/board/samsung/smdkv310/lowlevel_init.S
+++ b/board/samsung/smdkv310/lowlevel_init.S
@@ -85,12 +85,14 @@
1:
/* for UART */
bl uart_asm_init
+ bl arch_cpu_init
bl tzpc_init
pop {pc}
wakeup_reset:
bl system_clock_init
bl mem_ctrl_asm_init
+ bl arch_cpu_init
bl tzpc_init
exit_wakeup:
@@ -410,61 +412,3 @@
nop
nop
nop
-
-/* Setting TZPC[TrustZone Protection Controller] */
-tzpc_init:
- ldr r0, =0x10110000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10120000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10130000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10140000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10150000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10160000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- mov pc, lr
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index 8347cf9..5c73098 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -31,7 +31,7 @@
#include <asm/omap_gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/dss.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <i2c.h>
#include <spartan3.h>
#include <asm/gpio.h>
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 73bf853..fdbe26c 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -38,9 +38,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
@@ -126,28 +123,7 @@
return 0;
}
-/* UART Defines */
#ifdef CONFIG_SPL_BUILD
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
- struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
- /*
- * Unlock the RTC's registers. For more details please see the
- * RTC_SS section of the TRM. In order to unlock we need to
- * write these specific values (keys) in this order.
- */
- writel(0x83e70b13, &rtc->kick0r);
- writel(0x95a4f1e0, &rtc->kick1r);
-
- /* Enable the RTC 32K OSC by setting bits 3 and 6. */
- writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
(MT47H128M16RT25E_RD_DQS<<20) |
@@ -339,9 +315,6 @@
/* Enable RTC32K clock */
rtc32k_enable();
- /* UART softreset */
- u32 regVal;
-
#ifdef CONFIG_SERIAL1
enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
@@ -361,17 +334,7 @@
enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_RESET;
- writel(regVal, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
- ;
-
- /* Disable smart idle */
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_SMART_IDLE_EN;
- writel(regVal, &uart_base->uartsyscfg);
+ uart_soft_reset();
gd = &gdata;
@@ -514,6 +477,7 @@
eth_setenv_enetaddr("ethaddr", mac_addr);
}
+#ifdef CONFIG_DRIVER_TI_CPSW
if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
@@ -529,6 +493,7 @@
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
+#endif
/*
*
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 04c95fd..338a241 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -29,19 +29,29 @@
#include <asm/arch/mux_dra7xx.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
- {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */
- {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */
- {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */
- {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */
- {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */
- {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */
- {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */
- {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */
- {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */
- {UART1_TXD, (M0)}, /* UART1_TXD */
- {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */
- {UART1_RTSN, (M0)}, /* UART1_RTSN */
- {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */
- {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */
+ {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
+ {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
+ {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
+ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
+ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
+ {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
+ {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
+ {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
+ {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
+ {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
+ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
+ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
+ {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
+ {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
+ {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
+ {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
+ {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/board/ti/omap2420h4/config.mk b/board/ti/omap2420h4/config.mk
deleted file mode 100644
index e5dff69..0000000
--- a/board/ti/omap2420h4/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-#
-# TI H4 board with OMAP2420 (ARM1136) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
-# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1) ES2 will be configurable
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-#CONFIG_SYS_TEXT_BASE = 0x80e80000
-
-# Used with full SRAM boot.
-# This is either with a GP system or a signed boot image.
-# easiest, and safest way to go if you can.
-#CONFIG_SYS_TEXT_BASE = 0x40270000
-
-
-# Handy to get symbols to debug ROM version.
-#CONFIG_SYS_TEXT_BASE = 0x0
-CONFIG_SYS_TEXT_BASE = 0x08000000
-#CONFIG_SYS_TEXT_BASE = 0x04000000
diff --git a/board/ti/omap2420h4/lowlevel_init.S b/board/ti/omap2420h4/lowlevel_init.S
deleted file mode 100644
index 731c552..0000000
--- a/board/ti/omap2420h4/lowlevel_init.S
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
-
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
-next2:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next2
- mov pc, lr /* back to caller */
-
-/* ****************************************************************************
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = PRCM_CLKCFG_CTRL - addr of valid reg
- * R1 = CM_CLKEN_PLL - addr dpll ctlr reg
- * R2 = dpll value
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
- sub sp, sp, #0x4 /* get some stack space */
- str r4, [sp] /* save r4's value */
-
- /* move into fast relock bypass */
- ldr r8, pll_ctl_add
- mov r4, #0x2
- str r4, [r8]
- ldr r4, pll_stat
-block:
- ldr r8, [r4] /* wait for bypass to take effect */
- and r8, r8, #0x3
- cmp r8, #0x1
- bne block
-
- /* set new dpll dividers _after_ in bypass */
- ldr r4, pll_div_add
- ldr r8, pll_div_val
- str r8, [r4]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r4, cfg3_0_addr
- ldr r8, cfg3_0_val
- str r8, [r4]
- ldr r4, cfg4_0_addr
- ldr r8, cfg4_0_val
- str r8, [r4]
- ldr r4, cfg1_0_addr
- ldr r8, [r4]
- orr r8, r8, #0x3 /* up gpmc divider */
- str r8, [r4]
-
- /* setup to 2x loop though code. The first loop pre-loads the
- * icache, the 2nd commits the prcm config, and locks the dpll
- */
- mov r4, #0x1000 /* spin spin spin */
- mov r8, #0x4 /* first pass condition & set registers */
- cmp r8, #0x4
-2:
- ldrne r8, [r3] /* DPLL lock check */
- and r8, r8, #0x7
- cmp r8, #0x2
- beq 4f
-3:
- subeq r8, r8, #0x1
- streq r8, [r0] /* commit dividers (2nd time) */
- nop
-lloop1:
- sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop1
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- streq r2, [r1] /* lock dpll (2nd time) */
- nop
-lloop2:
- sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop2
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- ldreq r8, [r3] /* get lock condition for dpll */
- cmp r8, #0x4 /* first time though? */
- bne 2b
- moveq r8, #0x2 /* set to dpll check condition. */
- beq 3b /* if condition not true branch */
-4:
- ldr r4, [sp]
- add sp, sp, #0x4 /* return stack space */
- mov pc, lr /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-cfg3_0_addr:
- .word GPMC_CONFIG3_0
-cfg3_0_val:
- .word H4_24XX_GPMC_CONFIG3_0
-cfg4_0_addr:
- .word GPMC_CONFIG4_0
-cfg4_0_val:
- .word H4_24XX_GPMC_CONFIG4_0
-cfg1_0_addr:
- .word GPMC_CONFIG1_0
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_stat:
- .word CM_IDLEST_CKGEN
-pll_div_add:
- .word CM_CLKSEL1_PLL
-pll_div_val:
- .word DPLL_VAL /* DPLL setting (300MHz default) */
-
-.globl lowlevel_init
-lowlevel_init:
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* map interrupt controller */
- ldr r0, VAL_INTH_SETUP
- mcr p15, 0, r0, c15, c2, 4
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-VAL_INTH_SETUP:
- .word PERIFERAL_PORT_BASE
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
diff --git a/board/ti/omap2420h4/mem.c b/board/ti/omap2420h4/mem.c
deleted file mode 100644
index ba3f12a..0000000
--- a/board/ti/omap2420h4/mem.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-
-/************************************************************
- * sdelay() - simple spin loop. Will be constant time as
- * its generally used in 12MHz bypass conditions only. This
- * is necessary until timers are accessible.
- *
- * not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay (unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*********************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
- * -- called from SRAM, or Flash (using temp SRAM stack).
- *********************************************************************************/
-void prcm_init(void)
-{
- u32 div;
- void (*f_lock_pll) (u32, u32, u32, u32);
- extern void *_end_vect, *_start;
-
- f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
-
- __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */
- __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */
- __raw_writel(0, CM_ICLKEN1_CORE);
- __raw_writel(0, CM_ICLKEN2_CORE);
-
- __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */
- __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */
- __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */
- __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */
-
- div = BUS_DIV;
- __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
- sdelay(1000);
-
- if(running_in_sram()){
- /* If running fully from SRAM this is OK. The Flash bus drops out for just a little.
- * but then comes back. If running from Flash this sequence kills you, thus you need
- * to run it using CONFIG_PARTIAL_SRAM.
- */
- __raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
- wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
- sdelay(1000);
- /* set clock selection and dpll dividers. */
- __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */
- __raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
- sdelay(10000);
- __raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
- sdelay(10000);
- wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */
- }else if(running_in_flash()){
- /* if running from flash, need to jump to small relocated code area in SRAM.
- * This is the only safe spot to do configurations from.
- */
- (*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
- }
-
- __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */
- wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */
- sdelay(1000);
-}
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- * command line mem=xyz use all memory with out discontigious support
- * compiled in. Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
- u32 size, a_add_low, a_add_high;
-
- size = get_sdr_cs_size(SDRC_CS0_OSET);
- size /= SZ_32M; /* find size to offset CS1 */
- a_add_high = (size & 3) << 8; /* set up low field */
- a_add_low = (size & 0x3C) >> 2; /* set up high field */
- __raw_writel((a_add_high|a_add_low),SDRC_CS_CFG);
-
-}
-
-/********************************************************
- * mem_ok() - test used to see if timings are correct
- * for a part. Helps in gussing which part
- * we are currently using.
- *******************************************************/
-u32 mem_ok(void)
-{
- u32 val1, val2;
- u32 pattern = 0x12345678;
-
- __raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */
- __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */
- __raw_writel(0x0,OMAP2420_SDRC_CS0+4); /* remove pattern off the bus */
- val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
- val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
-
- if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed*/
- return(0);
- else
- return(1);
-}
-
-
-/********************************************************
- * sdrc_init() - init the sdrc chip selects CS0 and CS1
- * - early init routines, called from flash or
- * SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
- #define EARLY_INIT 1
- do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- * -called from low level code with stack only.
- * -code sets up SDRAM timing and muxing for 2422 or 2420.
- * -optimal settings can be placed here, or redone after i2c
- * inspection of board info
- *
- * This is a bit ugly, but should handle all memory moduels
- * used with the H4. The first time though this code from s_init()
- * we configure the first chip select. Later on we come back and
- * will configure the 2nd chip select if it exists.
- *
- **************************************************************************/
-void do_sdrc_init(u32 offset, u32 early)
-{
- u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype;
- sdrc_data_t *sdata; /* do not change type */
- u32 a, b, r;
-
- static const sdrc_data_t sdrc_2422 =
- {
- H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0,
- H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR,
- 0, H4_2422_SDRC_DLLAB_CTRL
- };
- static const sdrc_data_t sdrc_2420 =
- {
- H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR,
- H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
- H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
- H4_2420_SDRC_DLLAB_CTRL
- };
-
- if (offset == SDRC_CS0_OSET)
- cs0 = common = 1; /* int regs shared between both chip select */
-
- cpu = get_cpu_type();
- rev = get_cpu_rev();
-
- /* warning generated, though code generation is correct. this may bite later,
- * but is ok for now. there is only so much C code you can do on stack only
- * operation.
- */
- if (cpu == CPU_2422){
- sdata = (sdrc_data_t *)&sdrc_2422;
- pass_type = STACKED;
- } else{
- sdata = (sdrc_data_t *)&sdrc_2420;
- pass_type = IP_DDR;
- }
-
- __asm__ __volatile__("": : :"memory"); /* limit compiler scope */
-
- if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
- if(mtype == DDR_COMBO){
- pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
- pass_type = COMBO_DDR; /* CS1 config */
- __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
- }
- if(rev != CPU_2420_2422_ES1) /* for es2 and above smooth things out */
- make_cs1_contiguous();
- }
-
-next_mem_type:
- if (common) { /* do a SDRC reset between types to clear regs*/
- __raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */
- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */
- __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */
- __raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
-#ifdef POWER_SAVE
- __raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
- __raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING);
- __raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER);
-#endif
- }
-
- if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */
- __raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset);
- else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */
- __raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset);
- } else if (pass_type == IP_SDR){ /* ip sdr-CS0 */
- __raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset);
- }
-
- a = sdata->sdrc_actim_ctrla_0;
- b = sdata->sdrc_actim_ctrlb_0;
- r = sdata->sdrc_dllab_ctrl;
-
- /* work around ES1 DDR issues */
- if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){
- a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1;
- b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1;
- r = H4_242x_SDRC_RFR_CTRL_ES1;
- }
-
- if (cs0) {
- __raw_writel(a, SDRC_ACTIM_CTRLA_0);
- __raw_writel(b, SDRC_ACTIM_CTRLB_0);
- } else {
- __raw_writel(a, SDRC_ACTIM_CTRLA_1);
- __raw_writel(b, SDRC_ACTIM_CTRLB_1);
- }
- __raw_writel(r, SDRC_RFR_CTRL+offset);
-
- /* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
- sdelay(5000); /* susposed to be 100us per design spec for mddr/msdr */
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
-
- /*
- * CSx SDRC Mode Register
- * Burst length = (4 - DDR) (2-SDR)
- * Serial mode
- * CAS latency = x
- */
- if(pass_type == IP_SDR)
- __raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset);
- else
- __raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset);
-
- /* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/
- if (rev == CPU_2420_2422_ES1){
- dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */
- __raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7)
- ,SMS_CLASS_ARB0);/* enable bust complete for lcd */
- }
- else
- dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */
-
- /* enable & load up DLL with good value for 75MHz, and set phase to 90
- * ES1 recommends 90 phase, ES2 recommends 72 phase.
- */
- if (common && (pass_type != IP_SDR)) {
- __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL);
- __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL);
- __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL);
- __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL);
- }
- sdelay(90000);
-
- if(mem_ok())
- return; /* STACKED, other configued type */
- ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */
- goto next_mem_type;
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
- u32 mux=0, mtype, mwidth, rev, tval;
-
- rev = get_cpu_rev();
- if (rev == CPU_2420_2422_ES1)
- tval = 1;
- else
- tval = 0; /* disable bit switched meaning */
-
- /* global settings */
- __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
- __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-#ifdef CONFIG_SYS_NAND_BOOT
- __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
-#else
- __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */
-#endif
-
- /* discover bus connection from sysboot */
- if (is_gpmc_muxed() == GPMC_MUXED)
- mux = BIT9;
- mtype = get_gpmc0_type();
- mwidth = get_gpmc0_width();
-
- /* setup cs0 */
- __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
- sdelay(1000);
-
-#ifdef CONFIG_SYS_NAND_BOOT
- __raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0);
-#else
- __raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
-#endif
-
-#ifdef PRCM_CONFIG_III
- __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
-#endif
- __raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
- __raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
-#ifdef PRCM_CONFIG_III
- __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
- __raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
-#endif
- __raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
- sdelay(2000);
-
- /* setup cs1 */
- __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
- sdelay(1000);
- __raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
- __raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
- __raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
- __raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
- __raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
- __raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
- __raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
- sdelay(2000);
-}
diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c
deleted file mode 100644
index 532e989..0000000
--- a/board/ti/omap2420h4/omap2420h4.c
+++ /dev/null
@@ -1,867 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/mem.h>
-#include <i2c.h>
-#include <asm/mach-types.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void wait_for_command_complete(unsigned int wd_base);
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
- gpmc_init(); /* in SRAM or SDRM, finish GPMC */
-
- gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
- gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */
-
- return 0;
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for
- * general use.
- ***********************************************************/
-void try_unlock_sram(void)
-{
- /* if GP device unlock device SRAM for general use */
- if (get_device_type() == GP_DEVICE) {
- __raw_writel(0xFF, A_REQINFOPERM0);
- __raw_writel(0xCFDE, A_READPERM0);
- __raw_writel(0xCFDE, A_WRITEPERM0);
- }
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called path is with sram stack.
- **********************************************************/
-void s_init(void)
-{
- int in_sdram = running_in_sdram();
-
- watchdog_init();
- set_muxconf_regs();
- delay(100);
- try_unlock_sram();
-
- if(!in_sdram)
- prcm_init();
-
- peripheral_enable();
- icache_enable();
- if (!in_sdram)
- sdrc_init();
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r (void)
-{
- ether_init(); /* better done here so timers are init'ed */
- return(0);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-void watchdog_init(void)
-{
- /* There are 4 watch dogs. 1 secure, and 3 general purpose.
- * The ROM takes care of the secure one. Of the 3 GP ones,
- * 1 can reset us directly, the other 2 only generate MPU interrupts.
- */
- __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
-
-#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
- __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
- wait_for_command_complete(WD3_BASE);
- __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
-
- __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
- wait_for_command_complete(WD4_BASE);
- __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
-#endif
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base+WWPS);
- } while (pending);
-}
-
-/*******************************************************************
- * Routine:ether_init
- * Description: take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
- ******************************************************************/
-void ether_init (void)
-{
-#ifdef CONFIG_LAN91C96
- int cnt = 20;
-
- __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
-
- __raw_writew(0x0, LAN_RESET_REGISTER);
- do {
- __raw_writew(0x1, LAN_RESET_REGISTER);
- udelay (100);
- if (cnt == 0)
- goto h4reset_err_out;
- --cnt;
- } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
-
- cnt = 20;
-
- do {
- __raw_writew(0x0, LAN_RESET_REGISTER);
- udelay (100);
- if (cnt == 0)
- goto h4reset_err_out;
- --cnt;
- } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
- udelay (1000);
-
- *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
- udelay (1000);
-
- h4reset_err_out:
- return;
-#endif
-}
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init(void)
-{
- unsigned int size0=0,size1=0;
- u32 mtype, btype;
- u8 chg_on = 0x5; /* enable charge of back up battery */
- u8 vmode_on = 0x8C;
- #define NOT_EARLY 0
-
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
-
- btype = get_board_type();
- mtype = get_mem_type();
-
- display_board_info(btype);
- if (btype == BOARD_H4_MENELAUS){
- update_mux(btype,mtype); /* combo part on menelaus */
- i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
- i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
- }
-
- if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
- do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
- }
- size0 = get_sdr_cs_size(SDRC_CS0_OSET);
- size1 = get_sdr_cs_size(SDRC_CS1_OSET);
-
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, size0 + size1);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- unsigned int size0, size1;
- u32 rev;
-
- rev = get_cpu_rev();
- size0 = get_sdr_cs_size(SDRC_CS0_OSET);
- size1 = get_sdr_cs_size(SDRC_CS1_OSET);
-
- if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- else /* ES2 and above can remap at 32MB granularity */
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
- gd->bd->bi_dram[1].size = size1;
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
-}
-
-/**********************************************************
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers
- * specific to the hardware
- *********************************************************/
-void set_muxconf_regs (void)
-{
- muxSetupSDRC();
- muxSetupGPMC();
- muxSetupUsb0();
- muxSetupUart3();
- muxSetupI2C1();
- muxSetupUART1();
- muxSetupLCD();
- muxSetupCamera();
- muxSetupMMCSD();
- muxSetupTouchScreen();
- muxSetupHDQ();
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-void peripheral_enable(void)
-{
- unsigned int v, if_clks=0, func_clks=0;
-
- /* Enable GP2 timer.*/
- if_clks |= BIT4;
- func_clks |= BIT4;
- v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
- __raw_writel(v, CM_CLKSEL2_CORE);
- __raw_writel(0x1, CM_CLKSEL_WKUP);
-
-#ifdef CONFIG_SYS_NS16550
- /* Enable UART1 clock */
- func_clks |= BIT21;
- if_clks |= BIT21;
-#endif
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
- __raw_writel(v,CM_ICLKEN1_CORE );
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
- __raw_writel(v, CM_FCLKEN1_CORE);
- delay(1000);
-
-#ifndef KERNEL_UPDATED
- {
-#define V1 0xffffffff
-#define V2 0x00000007
-
- __raw_writel(V1, CM_FCLKEN1_CORE);
- __raw_writel(V2, CM_FCLKEN2_CORE);
- __raw_writel(V1, CM_ICLKEN1_CORE);
- __raw_writel(V1, CM_ICLKEN2_CORE);
- }
-#endif
-}
-
-/****************************************
- * Routine: muxSetupUsb0 (ostboot)
- * Description: Setup usb muxing
- *****************************************/
-void muxSetupUsb0(void)
-{
- volatile uint8 *MuxConfigReg;
- volatile uint32 *otgCtrlReg;
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
- *MuxConfigReg &= (uint8)(~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
- *MuxConfigReg &= (uint8)(~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
- *MuxConfigReg &= (uint8)(~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
- *MuxConfigReg &= (uint8)(~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
- *MuxConfigReg &= (uint8)(~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
- *MuxConfigReg &= (uint8)(~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
- *MuxConfigReg &= (uint8)(~0x1F);
-
- /* setup for USB VBus detection */
- otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
- *otgCtrlReg |= 0x00040000; /* bit 18 */
-}
-
-/****************************************
- * Routine: muxSetupUart3 (ostboot)
- * Description: Setup uart3 muxing
- *****************************************/
-void muxSetupUart3(void)
-{
- volatile uint8 *MuxConfigReg;
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
- *MuxConfigReg &= (uint8)(~0x1F);
-
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
- *MuxConfigReg &= (uint8)(~0x1F);
-}
-
-/****************************************
- * Routine: muxSetupI2C1 (ostboot)
- * Description: Setup i2c muxing
- *****************************************/
-void muxSetupI2C1(void)
-{
- volatile unsigned char *MuxConfigReg;
-
- /* I2C1 Clock pin configuration, PIN = M19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* I2C1 Data pin configuration, PIN = L15 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* Pull-up required on data line */
- /* external pull-up already present. */
- /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
-}
-
-/****************************************
- * Routine: muxSetupUART1 (ostboot)
- * Description: Set up uart1 muxing
- *****************************************/
-void muxSetupUART1(void)
-{
- volatile unsigned char *MuxConfigReg;
-
- /* UART1_CTS pin configuration, PIN = D21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_RTS pin configuration, PIN = H21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_TX pin configuration, PIN = L20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_RX pin configuration, PIN = T21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupLCD (ostboot)
- * Description: Setup lcd muxing
- *****************************************/
-void muxSetupLCD(void)
-{
- volatile unsigned char *MuxConfigReg;
-
- /* LCD_D0 pin configuration, PIN = Y7 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D1 pin configuration, PIN = P10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D2 pin configuration, PIN = V8 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D3 pin configuration, PIN = Y8 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D4 pin configuration, PIN = W8 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D5 pin configuration, PIN = R10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D6 pin configuration, PIN = Y9 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D7 pin configuration, PIN = V9 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D8 pin configuration, PIN = W9 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D9 pin configuration, PIN = P11 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D10 pin configuration, PIN = V10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D11 pin configuration, PIN = Y10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D12 pin configuration, PIN = W10 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D13 pin configuration, PIN = R11 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D14 pin configuration, PIN = V11 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D15 pin configuration, PIN = W11 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D16 pin configuration, PIN = P12 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_D17 pin configuration, PIN = R12 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_PCLK pin configuration, PIN = W6 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_VSYNC pin configuration, PIN = V7 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_HSYNC pin configuration, PIN = Y6 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* LCD_ACBIAS pin configuration, PIN = W7 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupCamera (ostboot)
- * Description: Setup camera muxing
- *****************************************/
-void muxSetupCamera(void)
-{
- volatile unsigned char *MuxConfigReg;
-
- /* CAMERA_RSTZ pin configuration, PIN = Y16 */
- /* CAM_RST is connected through the I2C IO expander.*/
- /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
- /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */
-
- /* CAMERA_XCLK pin configuration, PIN = U3 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_LCLK pin configuration, PIN = V5 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_VSYNC pin configuration, PIN = U2 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_HSYNC pin configuration, PIN = T3 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT0 pin configuration, PIN = T4 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT1 pin configuration, PIN = V2 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT2 pin configuration, PIN = V3 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT3 pin configuration, PIN = U4 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT4 pin configuration, PIN = W2 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT5 pin configuration, PIN = V4 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT6 pin configuration, PIN = W3 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT7 pin configuration, PIN = Y2 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT8 pin configuration, PIN = Y4 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* CAMERA_DAT9 pin configuration, PIN = V6 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupMMCSD (ostboot)
- * Description: set up MMC muxing
- *****************************************/
-void muxSetupMMCSD(void)
-{
- volatile unsigned char *MuxConfigReg;
-
- /* SDMMC_CLKI pin configuration, PIN = H15 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_CLKO pin configuration, PIN = G19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_CMD pin configuration, PIN = H18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DAT0 pin configuration, PIN = F20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DAT1 pin configuration, PIN = H14 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DAT2 pin configuration, PIN = E19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DAT3 pin configuration, PIN = D19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
- /* External pull-ups are present. */
- /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
-
- /* SDMMC_DDIR0 pin configuration, PIN = F19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_DDIR1 pin configuration, PIN = E20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_DDIR2 pin configuration, PIN = F18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_DDIR3 pin configuration, PIN = E18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* SDMMC_CDIR pin configuration, PIN = G18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/
- /* MMC_CD for 2422IP=K1 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
- *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
-
- /* MMC_WP pin configuration, PIN = B4 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
- *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
-}
-
-/******************************************
- * Routine: muxSetupTouchScreen (ostboot)
- * Description: Set up touch screen muxing
- *******************************************/
-void muxSetupTouchScreen(void)
-{
- volatile unsigned char *MuxConfigReg;
-
- /* SPI1_CLK pin configuration, PIN = U18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* SPI1_MOSI pin configuration, PIN = V20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* SPI1_MISO pin configuration, PIN = T18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* SPI1_nCS0 pin configuration, PIN = U19 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* PEN_IRQ pin configuration, PIN = P20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
- *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
-}
-
-/****************************************
- * Routine: muxSetupHDQ (ostboot)
- * Description: setup 1wire mux
- *****************************************/
-void muxSetupHDQ(void)
-{
- volatile unsigned char *MuxConfigReg;
-
- /* HDQ_SIO pin configuration, PIN = N18 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-/***************************************************************
- * Routine: muxSetupGPMC (ostboot)
- * Description: Configures balls which cam up in protected mode
- ***************************************************************/
-void muxSetupGPMC(void)
-{
- volatile uint8 *MuxConfigReg;
- volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
-
- /* gpmc_io_dir */
- *MCR = 0x19000000;
-
- /* NOR FLASH CS0 */
- /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
- *MuxConfigReg = 0x00 ;
-
- /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
- *MuxConfigReg = 0x01 ;
-
- /* MPDB(Multi Port Debug Port) CS1 */
- /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
- *MuxConfigReg = 0x00 ;
-
- /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
- *MuxConfigReg = 0x00 ;
-}
-
-/****************************************************************
- * Routine: muxSetupSDRC (ostboot)
- * Description: Configures balls which come up in protected mode
- ****************************************************************/
-void muxSetupSDRC(void)
-{
- volatile uint8 *MuxConfigReg;
-
- /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
- *MuxConfigReg = 0x00 ;
-
- /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
- *MuxConfigReg = 0x00 ;
-
- /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3 Pull/up - N/A */
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
- *MuxConfigReg = 0x00;
-
- if (get_cpu_type() == CPU_2422) {
- MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
- *MuxConfigReg = 0x1b;
- }
-}
-
-/*****************************************************************************
- * Routine: update_mux()
- * Description: Update balls which are different beween boards. All should be
- * updated to match functionaly. However, I'm only updating ones
- * which I'll be using for now. When power comes into play they
- * all need updating.
- *****************************************************************************/
-void update_mux(u32 btype,u32 mtype)
-{
- u32 cpu, base = OMAP2420_CTRL_BASE;
- cpu = get_cpu_type();
-
- if (btype == BOARD_H4_MENELAUS) {
- if (cpu == CPU_2420) {
- /* PIN = B3, GPIO.0->KBR5, mode 3, (pun?),-DO-*/
- __raw_writeb(0x3, base+0x30);
- /* PIN = B13, GPIO.38->KBC6, mode 3, (pun?)-DO-*/
- __raw_writeb(0x3, base+0xa3);
- /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
- /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
- /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
- /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
- /* PIN = M1 (HSUSBOTG) */
- /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
- __raw_writeb(0x3, base+0x9d);
- /* PIN = U32, (WLAN_CLKREQ) */
- /* PIN = Y11, WLAN */
- /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
- __raw_writeb(0x3, base+0xe7);
- /* PIN = AA8, mDOC */
- /* PIN = AA10, BT */
- /* PIN = AA13, WLAN */
- /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
- __raw_writeb(0x3, base+0x10e);
- /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
- __raw_writeb(0x3, base+0x110);
- /* PIN = J15 HHUSB */
- /* PIN = H19 HSUSB */
- /* PIN = W13, P13, R13, W16 ... */
- /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
- __raw_writeb(0x3, base+0xde);
- /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
- __raw_writeb(0x0, base+0x12c);
- /* PIN = AA17->sys_clkreq mode 0 -DO- */
- __raw_writeb(0x0, base+0x136);
- } else if (cpu == CPU_2422) {
- /* PIN = B3, GPIO.0->nc, mode 3, set above (pun?)*/
- /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
- /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
- /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
- /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
- __raw_writeb(0x0, base+0x92);
- /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
- /* PIN = M1 (HSUSBOTG) */
- /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
- __raw_writeb(0x3, base+0x10c);
- /* PIN = U32, (WLAN_CLKREQ) */
- /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
- __raw_writeb(0x3, base+0x30);
- /* PIN = AA8, mDOC */
- /* PIN = AA10, BT */
- /* PIN = AA12, WLAN */
- /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
- __raw_writeb(0x3, base+0x10e);
- /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
- __raw_writeb(0x3, base+0x110);
- /* PIN = J15 HHUSB */
- /* PIN = H19 HSUSB */
- /* PIN = W13, P13, R13, W16 ... */
- /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
- __raw_writeb(0x3, base+0xde);
- /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
- __raw_writeb(0x0, base+0x12c);
- /* PIN = AA17->sys_clkreq mode 0 -DO- */
- __raw_writeb(0x0, base+0x136);
- }
-
- } else if (btype == BOARD_H4_SDP) {
- if (cpu == CPU_2420) {
- /* PIN = B3, GPIO.0->nc mode 3, set above (pun?)*/
- /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
- /* Pin = Y11 VLNQ */
- /* Pin = AA4 VLNQ */
- /* Pin = AA6 VLNQ */
- /* Pin = AA8 VLNQ */
- /* Pin = AA10 VLNQ */
- /* Pin = AA12 VLNQ */
- /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
- __raw_writeb(0x3, base+0x10e);
- /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
- __raw_writeb(0x3, base+0x110);
- /* PIN = J15 MDOC_nDMAREQ */
- /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
- __raw_writeb(0x3, base+0x114);
- /* PIN = W13, V12, P13, R13, W19, W16 ... */
- /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
- } else if (cpu == CPU_2422) {
- /* PIN = B3, GPIO.0->MMC_CD, mode 3, set above */
- /* PIN = B13, GPIO.38->wlan_int, mode 3, (pun?)*/
- /* Pin = Y11 VLNQ */
- /* Pin = AA4 VLNQ */
- /* Pin = AA6 VLNQ */
- /* Pin = AA8 VLNQ */
- /* Pin = AA10 VLNQ */
- /* Pin = AA12 VLNQ */
- /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
- __raw_writeb(0x3, base+0x10e);
- /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
- __raw_writeb(0x3, base+0x110);
- /* PIN = J15 MDOC_nDMAREQ */
- /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
- __raw_writeb(0x3, base+0x114);
- /* PIN = W13, V12, P13, R13, W19, W16 ... */
- /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
- }
- }
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/ti/omap2420h4/sys_info.c b/board/ti/omap2420h4/sys_info.c
deleted file mode 100644
index b12011e..0000000
--- a/board/ti/omap2420h4/sys_info.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/io.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mem.h> /* get mem tables */
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <i2c.h>
-
-/**************************************************************************
- * get_prod_id() - get id info from chips
- ***************************************************************************/
-static u32 get_prod_id(void)
-{
- u32 p;
- p = __raw_readl(PRODUCTION_ID); /* get production ID */
- return((p & CPU_242X_PID_MASK) >> 16);
-}
-
-/**************************************************************************
- * get_cpu_type() - low level get cpu type
- * - no C globals yet.
- * - just looking to say if this is a 2422 or 2420 or ...
- * - to start with we will look at switch settings..
- * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
- * (mux for 2420, non-mux for 2422).
- ***************************************************************************/
-u32 get_cpu_type(void)
-{
- u32 v;
-
- switch(get_prod_id()){
- case 1:;/* 2420 */
- case 2: return(CPU_2420); break; /* 2420 pop */
- case 4: return(CPU_2422); break;
- case 8: return(CPU_2423); break;
- default: break; /* early 2420/2422's unmarked */
- }
-
- v = __raw_readl(TAP_IDCODE_REG);
- v &= CPU_24XX_ID_MASK;
- if (v == CPU_2420_CHIPID) { /* currently 2420 and 2422 have same id */
- if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */
- return(CPU_2420);
- else
- return(CPU_2422);
- } else
- return(CPU_2420); /* don't know, say 2420 */
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 v;
- v = __raw_readl(TAP_IDCODE_REG);
- v = v >> 28;
- return(v+1); /* currently 2422 and 2420 match up */
-}
-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
- volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET);
- if(*burst == H4_2420_SDRC_MR_0_SDR)
- return(1);
- return(0);
-}
-
-/***********************************************************
- * get_mem_type() - identify type of mDDR part used.
- * 2422 uses stacked DDR, 2 parts CS0/CS1.
- * 2420 may have 1 or 2, no good way to know...only init 1...
- * when eeprom data is up we can select 1 more.
- *************************************************************/
-u32 get_mem_type(void)
-{
- u32 cpu, sdr = is_mem_sdr();
-
- cpu = get_cpu_type();
- if (cpu == CPU_2422 || cpu == CPU_2423)
- return(DDR_STACKED);
-
- if(get_prod_id() == 0x2)
- return(XDR_POP);
-
- if (get_board_type() == BOARD_H4_MENELAUS)
- if(sdr)
- return(SDR_DISCRETE);
- else
- return(DDR_COMBO);
- else
- if(sdr) /* SDP + SDR kit */
- return(SDR_DISCRETE);
- else
- return(DDR_DISCRETE); /* origional SDP */
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 offset)
-{
- u32 size;
- size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */
- size &= 0x2FF; /* remove unwanted bits */
- size *= SZ_2M; /* find size in MB */
- return(size);
-}
-
-/***********************************************************************
- * get_board_type() - get board type based on current production stats.
- * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
- * when they are available we can get info from there. This should
- * be correct of all known boards up until today.
- ************************************************************************/
-u32 get_board_type(void)
-{
- if (i2c_probe(I2C_MENELAUS) == 0)
- return(BOARD_H4_MENELAUS);
- else
- return(BOARD_H4_SDP);
-}
-
-/******************************************************************
- * get_sysboot_value() - get init word settings (dip switch on h4)
- ******************************************************************/
-inline u32 get_sysboot_value(void)
-{
- return(0x00000FFF & __raw_readl(CONTROL_STATUS));
-}
-
-/***************************************************************************
- * get_gpmc0_base() - Return current address hardware will be
- * fetching from. The below effectively gives what is correct, its a bit
- * mis-leading compared to the TRM. For the most general case the mask
- * needs to be also taken into account this does work in practice.
- * - for u-boot we currently map:
- * -- 0 to nothing,
- * -- 4 to flash
- * -- 8 to enent
- * -- c to wifi
- ****************************************************************************/
-u32 get_gpmc0_base(void)
-{
- u32 b;
-
- b = __raw_readl(GPMC_CONFIG7_0);
- b &= 0x1F; /* keep base [5:0] */
- b = b << 24; /* ret 0x0b000000 */
- return(b);
-}
-
-/*****************************************************************
- * is_gpmc_muxed() - tells if address/data lines are multiplexed
- *****************************************************************/
-u32 is_gpmc_muxed(void)
-{
- u32 mux;
- mux = get_sysboot_value();
- if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
- return(GPMC_MUXED); /* NAND Boot mode */
- if (mux & BIT1) /* if mux'ed */
- return(GPMC_MUXED);
- else
- return(GPMC_NONMUXED);
-}
-
-/************************************************************************
- * get_gpmc0_type() - read sysboot lines to see type of memory attached
- ************************************************************************/
-u32 get_gpmc0_type(void)
-{
- u32 type;
- type = get_sysboot_value();
- if ((type & (BIT3|BIT2)) == (BIT3|BIT2))
- return(TYPE_NAND);
- else
- return(TYPE_NOR);
-}
-
-/*******************************************************************
- * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
- *******************************************************************/
-u32 get_gpmc0_width(void)
-{
- u32 width;
- width = get_sysboot_value();
- if ((width & 0xF) == (BIT3|BIT2))
- return(WIDTH_8BIT);
- else
- return(WIDTH_16BIT);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- * volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = __raw_readl(read_addr) & read_bit_mask;
- if (val == match_value)
- return(1);
- if (i==bound)
- return(0);
- } while (1);
-}
-
-/*********************************************************************
- * display_board_info() - print banner with board info.
- *********************************************************************/
-void display_board_info(u32 btype)
-{
- static const char cpu_2420 [] = "2420"; /* cpu type */
- static const char cpu_2422 [] = "2422";
- static const char cpu_2423 [] = "2423";
- static const char db_men [] = "Menelaus"; /* board type */
- static const char db_ip [] = "IP";
- static const char mem_sdr [] = "mSDR"; /* memory type */
- static const char mem_ddr [] = "mDDR";
- static const char t_tst [] = "TST"; /* security level */
- static const char t_emu [] = "EMU";
- static const char t_hs [] = "HS";
- static const char t_gp [] = "GP";
- static const char unk [] = "?";
-
- const char *cpu_s, *db_s, *mem_s, *sec_s;
- u32 cpu, rev, sec;
-
- rev = get_cpu_rev();
- cpu = get_cpu_type();
- sec = get_device_type();
-
- if(is_mem_sdr())
- mem_s = mem_sdr;
- else
- mem_s = mem_ddr;
-
- if(cpu == CPU_2423)
- cpu_s = cpu_2423;
- else if (cpu == CPU_2422)
- cpu_s = cpu_2422;
- else
- cpu_s = cpu_2420;
-
- if(btype == BOARD_H4_MENELAUS)
- db_s = db_men;
- else
- db_s = db_ip;
-
- switch(sec){
- case TST_DEVICE: sec_s = t_tst; break;
- case EMU_DEVICE: sec_s = t_emu; break;
- case HS_DEVICE: sec_s = t_hs; break;
- case GP_DEVICE: sec_s = t_gp; break;
- default: sec_s = unk;
- }
-
- printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1);
- printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s);
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = 242x IP platform (first 2xx boards)
- * 1 = 242x Menelaus platfrom.
- *************************************************************************/
-u32 get_board_rev(void)
-{
- u32 rev = 0;
- u32 btype = get_board_type();
-
- if (btype == BOARD_H4_MENELAUS){
- rev = 1;
- }
- return(rev);
-}
-
-/********************************************************
- * get_base(); get upper addr of current execution
- *******************************************************/
-u32 get_base(void)
-{
- u32 val;
- __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
- val &= 0xF0000000;
- val >>= 28;
- return(val);
-}
-
-/********************************************************
- * get_base2(); get 2upper addr of current execution
- *******************************************************/
-u32 get_base2(void)
-{
- u32 val;
- __asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
- val &= 0xFF000000;
- val >>= 24;
- return(val);
-}
-
-/********************************************************
- * running_in_flash() - tell if currently running in
- * flash.
- *******************************************************/
-u32 running_in_flash(void)
-{
- if (get_base() < 4)
- return(1); /* in flash */
- return(0); /* running in SRAM or SDRAM */
-}
-
-/********************************************************
- * running_in_sram() - tell if currently running in
- * sram.
- *******************************************************/
-u32 running_in_sram(void)
-{
- if (get_base() == 4)
- return(1); /* in SRAM */
- return(0); /* running in FLASH or SDRAM */
-}
-/********************************************************
- * running_in_sdram() - tell if currently running in
- * flash.
- *******************************************************/
-u32 running_in_sdram(void)
-{
- if (get_base() > 4)
- return(1); /* in sdram */
- return(0); /* running in SRAM or FLASH */
-}
-
-/*************************************************************
- * running_from_internal_boot() - am I a signed NOR image.
- *************************************************************/
-u32 running_from_internal_boot(void)
-{
- u32 v, base;
-
- v = get_sysboot_value() & BIT3;
- base = get_base2();
- /* if running at mask rom flash address and
- * sysboot3 says this was an internal boot
- */
- if ((base == 0x08) && v)
- return(1);
- else
- return(0);
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
- return(mode >>= 8);
-}
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 46db1bf..90046e8 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -71,22 +71,26 @@
void set_muxconf_regs_essential(void)
{
- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
}
void set_muxconf_regs_non_essential(void)
{
- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_non_essential,
sizeof(core_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_non_essential,
sizeof(wkup_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
}
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 2bbe392..1da5b35 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
@@ -37,6 +37,11 @@
#endif
#define PANDA_ULPI_PHY_TYPE_GPIO 182
+#define PANDA_BOARD_ID_1_GPIO 101
+#define PANDA_ES_BOARD_ID_1_GPIO 48
+#define PANDA_BOARD_ID_2_GPIO 171
+#define PANDA_ES_BOARD_ID_3_GPIO 3
+#define PANDA_ES_BOARD_ID_4_GPIO 2
DECLARE_GLOBAL_DATA_PTR;
@@ -66,6 +71,73 @@
return 0;
}
+/*
+* Routine: get_board_revision
+* Description: Detect if we are running on a panda revision A1-A6,
+* or an ES panda board. This can be done by reading
+* the level of GPIOs and checking the processor revisions.
+* This should result in:
+* Panda 4430:
+* GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
+* GPIO171, GPIO101, GPIO182: 1 0 1 => A6
+* Panda ES:
+* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
+* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
+*/
+int get_board_revision(void)
+{
+ int board_id0, board_id1, board_id2;
+ int board_id3, board_id4;
+ int board_id;
+
+ int processor_rev = omap_revision();
+
+ /* Setup the mux for the common board ID pins (gpio 171 and 182) */
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
+
+ board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
+ board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+
+ if ((processor_rev >= OMAP4460_ES1_0 &&
+ processor_rev <= OMAP4460_ES1_1)) {
+ /*
+ * Setup the mux for the ES specific board ID pins (gpio 101,
+ * 2 and 3.
+ */
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+ GPMC_A24);
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+ UNIPRO_RY0);
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+ UNIPRO_RX1);
+
+ board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
+ board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
+ board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
+#endif
+ board_id = ((board_id4 << 4) | (board_id3 << 3) |
+ (board_id2 << 2) | (board_id1 << 1) | (board_id0));
+ } else {
+ /* Setup the mux for the Ax specific board ID pins (gpio 101) */
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+ FREF_CLK2_OUT);
+
+ board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
+ board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
+ setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
+#endif
+ }
+
+ return board_id;
+}
+
/**
* @brief misc_init_r - Configure Panda board specific configurations
* such as power configurations, ethernet initialization as phase2 of
@@ -82,11 +154,7 @@
if (omap_revision() == OMAP4430_ES1_0)
return 0;
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (omap_revision() >= OMAP4460_ES1_0 ||
- omap_revision() <= OMAP4460_ES1_1)
- setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
-#endif
+ get_board_revision();
gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
@@ -106,7 +174,7 @@
auxclk |= AUXCLK_ENABLE_MASK;
writel(auxclk, &scrm->auxclk3);
- } else {
+ } else {
/* ULPI PHY supplied by auxclk1 derived from PER dpll */
debug("ULPI PHY supplied by auxclk1\n");
@@ -139,47 +207,51 @@
void set_muxconf_regs_essential(void)
{
- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
if (omap_revision() >= OMAP4460_ES1_0)
- do_set_mux(CONTROL_PADCONF_WKUP,
- wkup_padconf_array_essential_4460,
- sizeof(wkup_padconf_array_essential_4460) /
- sizeof(struct pad_conf_entry));
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential_4460,
+ sizeof(wkup_padconf_array_essential_4460) /
+ sizeof(struct pad_conf_entry));
}
void set_muxconf_regs_non_essential(void)
{
- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_non_essential,
sizeof(core_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
if (omap_revision() < OMAP4460_ES1_0)
- do_set_mux(CONTROL_PADCONF_CORE,
- core_padconf_array_non_essential_4430,
- sizeof(core_padconf_array_non_essential_4430) /
- sizeof(struct pad_conf_entry));
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_non_essential_4430,
+ sizeof(core_padconf_array_non_essential_4430) /
+ sizeof(struct pad_conf_entry));
else
- do_set_mux(CONTROL_PADCONF_CORE,
- core_padconf_array_non_essential_4460,
- sizeof(core_padconf_array_non_essential_4460) /
- sizeof(struct pad_conf_entry));
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_non_essential_4460,
+ sizeof(core_padconf_array_non_essential_4460) /
+ sizeof(struct pad_conf_entry));
- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_non_essential,
sizeof(wkup_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
if (omap_revision() < OMAP4460_ES1_0)
- do_set_mux(CONTROL_PADCONF_WKUP,
- wkup_padconf_array_non_essential_4430,
- sizeof(wkup_padconf_array_non_essential_4430) /
- sizeof(struct pad_conf_entry));
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_non_essential_4430,
+ sizeof(wkup_padconf_array_non_essential_4430) /
+ sizeof(struct pad_conf_entry));
}
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 4c1a4f7..5dd1ba3 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -72,16 +72,18 @@
void set_muxconf_regs_essential(void)
{
- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
if (omap_revision() >= OMAP4460_ES1_0)
- do_set_mux(CONTROL_PADCONF_WKUP,
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential_4460,
sizeof(wkup_padconf_array_essential_4460) /
sizeof(struct pad_conf_entry));
@@ -89,16 +91,18 @@
void set_muxconf_regs_non_essential(void)
{
- do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_non_essential,
sizeof(core_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
- do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_non_essential,
sizeof(wkup_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
if (omap_revision() < OMAP4460_ES1_0) {
- do_set_mux(CONTROL_PADCONF_WKUP,
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_non_essential_4430,
sizeof(wkup_padconf_array_non_essential_4430) /
sizeof(struct pad_conf_entry));
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 4759b16..6ad3dd8 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -37,49 +37,16 @@
#ifdef CONFIG_SPL_BUILD
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
#endif
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/* UART Defines */
#ifdef CONFIG_SPL_BUILD
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
- struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
- /*
- * Unlock the RTC's registers. For more details please see the
- * RTC_SS section of the TRM. In order to unlock we need to
- * write these specific values (keys) in this order.
- */
- writel(0x83e70b13, &rtc->kick0r);
- writel(0x95a4f1e0, &rtc->kick1r);
-
- /* Enable the RTC 32K OSC by setting bits 3 and 6. */
- writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
static void uart_enable(void)
{
- u32 regVal;
-
/* UART softreset */
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_RESET;
- writel(regVal, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
- ;
-
- /* Disable smart idle */
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_SMART_IDLE_EN;
- writel(regVal, &uart_base->uartsyscfg);
+ uart_soft_reset();
}
static void wdt_disable(void)
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index 61d1154..1a3ef92 100644
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -67,11 +67,6 @@
__rel_dyn_end = .;
}
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
. = ALIGN(0x800);
_end = .;
@@ -84,6 +79,7 @@
}
/DISCARD/ : { *(.bss*) }
+ /DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynsym*) }
/DISCARD/ : { *(.dynamic*) }
diff --git a/board/wandboard/README b/board/wandboard/README
index e0b0b33..ce83bbe 100644
--- a/board/wandboard/README
+++ b/board/wandboard/README
@@ -14,12 +14,12 @@
To build U-Boot for the Wandboard Dual Lite version:
-$ make wanboard_dl_config
+$ make wandboard_dl_config
$ make
To build U-Boot for the Wandboard Solo version:
-$ make wanboard_solo_config
+$ make wandboard_solo_config
$ make
Flashing U-boot into the SD card
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index bb98352..5666cbf 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -10,9 +10,11 @@
*/
#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
@@ -21,9 +23,11 @@
#include <asm/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
+#include <ipu_pixfmt.h>
#include <mmc.h>
#include <miiphy.h>
#include <netdev.h>
+#include <linux/fb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -206,6 +210,88 @@
return 0;
}
+#if defined(CONFIG_VIDEO_IPUV3)
+static void enable_hdmi(void)
+{
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ u8 reg;
+ reg = readb(&hdmi->phy_conf0);
+ reg |= HDMI_PHY_CONF0_PDZ_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+ writeb(reg, &hdmi->phy_conf0);
+ writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+static struct fb_videomode const hdmi = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+int board_video_skip(void)
+{
+ int ret;
+
+ ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
+
+ if (ret)
+ printf("HDMI cannot be configured: %d\n", ret);
+
+ enable_hdmi();
+
+ return ret;
+}
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ int reg;
+
+ /* Turn on IPU clock */
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* Turn on HDMI PHY clock */
+ reg = readl(&mxc_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
+ | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+ writel(reg, &mxc_ccm->CCGR2);
+
+ /* clear HDMI PHY reset */
+ writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
+ | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
+ | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+ | (CHSCCDR_PODF_DIVIDE_BY_3
+ << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+ | (CHSCCDR_IPU_PRE_CLK_540M_PFD
+ << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
int board_eth_init(bd_t *bis)
{
int ret;
@@ -222,9 +308,21 @@
int board_early_init_f(void)
{
setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
return 0;
}
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
diff --git a/boards.cfg b/boards.cfg
index e2a8d42..c0c4282 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -52,7 +52,6 @@
mx35pdk arm arm1136 - freescale mx35
woodburn arm arm1136 - - mx35
woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
-omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
rpi_b arm arm1176 rpi_b raspberrypi bcm2835
integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T
@@ -266,12 +265,14 @@
mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
+cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
titanium arm armv7 titanium freescale mx6 titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
+vf610twr arm armv7 vf610twr freescale vf610 vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg
eco5pk arm armv7 eco5pk 8dtech omap3
nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
@@ -347,6 +348,7 @@
scpu arm ixp pdnb3 prodrive - pdnb3:SCPU
balloon3 arm pxa
h2200 arm pxa
+lp8x4x arm pxa lp8x4x icpdas
lubbock arm pxa
palmld arm pxa
palmtc arm pxa
@@ -829,6 +831,7 @@
P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD
P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SDCARD
P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT
+P1023RDB powerpc mpc85xx p1023rdb freescale - P1023RDB
P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS
P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND
P1024RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB
@@ -898,8 +901,13 @@
P5040DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P5040DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
+BSC9131RDB_SPIFLASH_SYSCLK100 powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100
+BSC9131RDB_NAND powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,NAND
+BSC9131RDB_NAND_SYSCLK100 powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100
BSC9132QDS_NOR_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100
BSC9132QDS_NOR_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133
+BSC9132QDS_NAND_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100
+BSC9132QDS_NAND_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133
BSC9132QDS_SDCARD_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100
BSC9132QDS_SDCARD_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133
BSC9132QDS_SPIFLASH_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100
@@ -910,12 +918,14 @@
T4240QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240
T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+T4240QDS_SRIO_PCIE_BOOT powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
T4160QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160
T4160QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
T4160QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860
B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+B4860QDS_SRIO_PCIE_BOOT powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
B4420QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420
B4420QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
B4420QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
diff --git a/common/Makefile b/common/Makefile
index 3ba4316..3581603 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -44,13 +44,11 @@
COBJS-y += cmd_boot.o
COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
COBJS-y += cmd_help.o
-COBJS-y += cmd_nvedit.o
COBJS-y += cmd_version.o
# environment
COBJS-y += env_attr.o
COBJS-y += env_callback.o
-COBJS-y += env_common.o
COBJS-y += env_flags.o
COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
@@ -191,14 +189,6 @@
COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o
# others
-ifdef CONFIG_DDR_SPD
-SPD := y
-endif
-ifdef CONFIG_SPD_EEPROM
-SPD := y
-endif
-COBJS-$(SPD) += ddr_spd.o
-COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
COBJS-$(CONFIG_BOOTSTAGE) += bootstage.o
COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
COBJS-y += flash.o
@@ -216,18 +206,36 @@
endif
ifdef CONFIG_SPL_BUILD
-COBJS-y += cmd_nvedit.o
-COBJS-y += env_common.o
COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += cmd_nvedit.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_attr.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_callback.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_flags.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
+# environment
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
+ifneq ($(CONFIG_SPL_NET_SUPPORT),y)
+COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
+COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
+COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
+else
+COBJS-y += env_nowhere.o
endif
+endif
+# core command
+COBJS-y += cmd_nvedit.o
+#environment
+COBJS-y += env_common.o
+#others
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+COBJS-$(SPD) += ddr_spd.o
+COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
COBJS-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
COBJS-y += console.o
COBJS-y += dlmalloc.o
diff --git a/common/cmd_immap.c b/common/cmd_immap.c
index fdf9489..bb15795 100644
--- a/common/cmd_immap.c
+++ b/common/cmd_immap.c
@@ -535,7 +535,7 @@
volatile iic_t *iip;
uint dpaddr;
- dpaddr = *((unsigned short *) (&immap->im_dprambase[PROFF_I2C_BASE]));
+ dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
if (dpaddr == 0)
iip = NULL;
else
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 7d82469..5f1ed43 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -147,6 +147,36 @@
"- display info of the current MMC device"
);
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+{
+ int err;
+ err = mmc_boot_part_access(mmc, ack, part_num, access);
+
+ if ((err == 0) && (access != 0)) {
+ printf("\t\t\t!!!Notice!!!\n");
+
+ printf("!You must close EMMC boot Partition");
+ printf("after all images are written\n");
+
+ printf("!EMMC boot partition has continuity");
+ printf("at image writing time.\n");
+
+ printf("!So, do not close the boot partition");
+ printf("before all images are written.\n");
+ return 0;
+ } else if ((err == 0) && (access == 0))
+ return 0;
+ else if ((err != 0) && (access != 0)) {
+ printf("EMMC boot partition-%d OPEN Failed.\n", part_num);
+ return 1;
+ } else {
+ printf("EMMC boot partition-%d CLOSE Failed.\n", part_num);
+ return 1;
+ }
+}
+#endif
+
static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
enum mmc_state state;
@@ -258,8 +288,74 @@
curr_device, mmc->part_num);
return 0;
- }
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ } else if ((strcmp(argv[1], "open") == 0) ||
+ (strcmp(argv[1], "close") == 0)) {
+ int dev;
+ struct mmc *mmc;
+ u8 part_num, access = 0;
+ if (argc == 4) {
+ dev = simple_strtoul(argv[2], NULL, 10);
+ part_num = simple_strtoul(argv[3], NULL, 10);
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ mmc = find_mmc_device(dev);
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", dev);
+ return 1;
+ }
+
+ if (IS_SD(mmc)) {
+ printf("SD device cannot be opened/closed\n");
+ return 1;
+ }
+
+ if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) {
+ printf("Invalid boot partition number:\n");
+ printf("Boot partition number cannot be <= 0\n");
+ printf("EMMC44 supports only 2 boot partitions\n");
+ return 1;
+ }
+
+ if (strcmp(argv[1], "open") == 0)
+ access = part_num; /* enable R/W access to boot part*/
+ else
+ access = 0; /* No access to boot partition */
+
+ /* acknowledge to be sent during boot operation */
+ return boot_part_access(mmc, 1, part_num, access);
+
+ } else if (strcmp(argv[1], "bootpart") == 0) {
+ int dev;
+ dev = simple_strtoul(argv[2], NULL, 10);
+
+ u32 bootsize = simple_strtoul(argv[3], NULL, 10);
+ u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);
+ struct mmc *mmc = find_mmc_device(dev);
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", dev);
+ return 1;
+ }
+
+ if (IS_SD(mmc)) {
+ printf("It is not a EMMC device\n");
+ return 1;
+ }
+
+ if (0 == mmc_boot_partition_size_change(mmc,
+ bootsize, rpmbsize)) {
+ printf("EMMC boot partition Size %d MB\n", bootsize);
+ printf("EMMC RPMB partition Size %d MB\n", rpmbsize);
+ return 0;
+ } else {
+ printf("EMMC boot partition Size change Failed.\n");
+ return 1;
+ }
+#endif /* CONFIG_SUPPORT_EMMC_BOOT */
+ }
state = MMC_INVALID;
if (argc == 5 && strcmp(argv[1], "read") == 0)
state = MMC_READ;
@@ -334,5 +430,14 @@
"mmc rescan\n"
"mmc part - lists available partition on current mmc device\n"
"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
- "mmc list - lists available devices");
+ "mmc list - lists available devices\n"
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ "mmc open <dev> <boot_partition>\n"
+ " - Enable boot_part for booting and enable R/W access of boot_part\n"
+ "mmc close <dev> <boot_partition>\n"
+ " - Enable boot_part for booting and disable access to boot_part\n"
+ "mmc bootpart <device num> <boot part size MB> <RPMB part size MB>\n"
+ " - change sizes of boot and RPMB partions of specified device\n"
#endif
+ );
+#endif /* !CONFIG_GENERIC_MMC */
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 0a17782..19b0dc9 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -234,7 +234,7 @@
unsigned long len;
void *buf;
char *endp;
- int ret;
+ int ret = 1;
if (argc < 4)
return -1;
@@ -264,19 +264,23 @@
if (strcmp(argv[0], "update") == 0)
ret = spi_flash_update(flash, offset, len, buf);
- else if (strcmp(argv[0], "read") == 0)
- ret = spi_flash_read(flash, offset, len, buf);
- else
- ret = spi_flash_write(flash, offset, len, buf);
+ else if (strncmp(argv[0], "read", 4) == 0 ||
+ strncmp(argv[0], "write", 5) == 0) {
+ int read;
+
+ read = strncmp(argv[0], "read", 4) == 0;
+ if (read)
+ ret = spi_flash_read(flash, offset, len, buf);
+ else
+ ret = spi_flash_write(flash, offset, len, buf);
+
+ printf("SF: %zu bytes @ %#x %s: %s\n", (size_t)len, (u32)offset,
+ read ? "Read" : "Written", ret ? "ERROR" : "OK");
+ }
unmap_physmem(buf, len);
- if (ret) {
- printf("SPI flash %s failed\n", argv[0]);
- return 1;
- }
-
- return 0;
+ return ret == 0 ? 0 : 1;
}
static int do_spi_flash_erase(int argc, char * const argv[])
@@ -305,12 +309,10 @@
}
ret = spi_flash_erase(flash, offset, len);
- if (ret) {
- printf("SPI flash %s failed\n", argv[0]);
- return 1;
- }
+ printf("SF: %zu bytes @ %#x Erased: %s\n", (size_t)len, (u32)offset,
+ ret ? "ERROR" : "OK");
- return 0;
+ return ret == 0 ? 0 : 1;
}
#ifdef CONFIG_CMD_SF_TEST
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 9ca098f..5d3a769 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -53,11 +53,19 @@
__weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
- *env_addr = CONFIG_ENV_OFFSET;
+ s64 offset;
+
+ offset = CONFIG_ENV_OFFSET;
#ifdef CONFIG_ENV_OFFSET_REDUND
if (copy)
- *env_addr = CONFIG_ENV_OFFSET_REDUND;
+ offset = CONFIG_ENV_OFFSET_REDUND;
#endif
+
+ if (offset < 0)
+ offset += mmc->capacity;
+
+ *env_addr = offset;
+
return 0;
}
diff --git a/common/image-fit.c b/common/image-fit.c
index 7bf82d3..f40f160 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1557,7 +1557,7 @@
if (fit_image_get_data(fit, noffset, &buf, &size)) {
printf("Could not find %s subimage data!\n", prop_name);
bootstage_error(bootstage_id + BOOTSTAGE_SUB_GET_DATA);
- return -ENOMEDIUM;
+ return -ENOENT;
}
len = (ulong)size;
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 0d79ec3..774ba63 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -53,6 +53,10 @@
#include <asm/4xx_pci.h>
#endif
+#ifndef CONFIG_USB_HUB_MIN_POWER_ON_DELAY
+#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 100
+#endif
+
#define USB_BUFSIZ 512
static struct usb_hub_device hub_dev[USB_MAX_HUB];
@@ -148,8 +152,8 @@
debug("port %d returns %lX\n", i + 1, dev->status);
}
- /* Wait at least 100 msec for power to become stable */
- mdelay(max(pgood_delay, (unsigned)100));
+ /* Wait for power to become stable */
+ mdelay(max(pgood_delay, CONFIG_USB_HUB_MIN_POWER_ON_DELAY));
}
void usb_hub_reset(void)
@@ -485,7 +489,11 @@
i + 1, portstatus);
usb_clear_port_feature(dev, i + 1,
USB_PORT_FEAT_C_ENABLE);
-
+ /*
+ * The following hack causes a ghost device problem
+ * to Faraday EHCI
+ */
+#ifndef CONFIG_USB_EHCI_FARADAY
/* EM interference sometimes causes bad shielded USB
* devices to be shutdown by the hub, this hack enables
* them again. Works at least with mouse driver */
@@ -497,6 +505,7 @@
"re-enabling...\n", i + 1);
usb_hub_port_connect_change(dev, i);
}
+#endif
}
if (portstatus & USB_PORT_STAT_SUSPEND) {
debug("port %d suspend change\n", i + 1);
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index b962849..3174b5e 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -461,8 +461,13 @@
usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE, 0);
debug("USB KBD: enable interrupt pipe...\n");
- usb_submit_int_msg(dev, pipe, data->new, maxp > 8 ? 8 : maxp,
- ep->bInterval);
+ if (usb_submit_int_msg(dev, pipe, data->new, maxp > 8 ? 8 : maxp,
+ ep->bInterval) < 0) {
+ printf("Failed to get keyboard state from device %04x:%04x\n",
+ dev->descriptor.idVendor, dev->descriptor.idProduct);
+ /* Abort, we don't want to use that non-functional keyboard. */
+ return 0;
+ }
/* Success. */
return 1;
@@ -496,6 +501,7 @@
if (old_dev) {
/* Already registered, just return ok. */
debug("USB KBD: is already registered.\n");
+ usb_kbd_deregister();
return 1;
}
diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp
index 9a53311..7a2863c 100644
--- a/doc/README.mxc_ocotp
+++ b/doc/README.mxc_ocotp
@@ -2,6 +2,7 @@
on MXC
This IP can be found on the following SoCs:
+ - Vybrid VF610,
- i.MX6.
Note that this IP is different from albeit similar to the IPs of the same name
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 9223f6e..a0f1fa3 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -96,3 +96,4 @@
CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk <wd@denx.de>
PCIPPC6 powerpc MPC740/MPC750 - - Wolfgang Denk <wd@denx.de>
+omap2420h4 arm omap24xx - 2013-06-04 Richard Woodruff <r-woodruff2@ti.com>
diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet
index cd7e7ee..2b1f76b 100644
--- a/doc/README.srio-pcie-boot-corenet
+++ b/doc/README.srio-pcie-boot-corenet
@@ -21,13 +21,13 @@
e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
the boot location to SRIO or PCIE, and holdoff all the cores.
- ---------- ----------- -----------
- | | | | | |
- | | | | | |
+ ----------- ----------- -----------
+ | | | | | |
+ | | | | | |
| NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
- | | | |<===========>| |
- | | | | | |
- ---------- ----------- -----------
+ | | | |<===========>| |
+ | | | | | |
+ ----------- ----------- -----------
The example based on P4080DS platform:
Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
@@ -87,26 +87,32 @@
Please refer to the examples given above.
2. U-Boot image's compilation.
- For master, U-Boot image should be generated normally.
+ For master, U-Boot image should be generated normally.
- For example, master U-Boot image used on P4080DS should be compiled with
+ For example, master U-Boot image used on P4080DS should be compiled with
make P4080DS_config.
- For slave, U-Boot image should be generated specifically by
+ For slave, U-Boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
- For example, slave U-Boot image used on P4080DS should be compiled with
+ For example, slave U-Boot image used on P4080DS should be compiled with
make P4080DS_SRIO_PCIE_BOOT_config.
3. Necessary modifications based on a specific environment.
- For a specific environment, the addresses of the slave's U-Boot image,
- UCode, ENV stored in master's NorFlash, and any other configurations
- can be modified in the file:
- include/configs/corenet_ds.h.
+ For a specific environment, the addresses of the slave's U-Boot image,
+ UCode, ENV stored in master's NorFlash, and any other configurations
+ can be modified in the file:
+ include/configs/corenet_ds.h.
4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
perform the role as a master for boot from SRIO or PCIE.
+
+NOTE: When the Slave's ENV parameters are stored in Master's NorFlash,
+ it can fetch them through PCIE or SRIO interface. But the ENV
+ parameters can not be modified by "saveenv" or other commands under
+ the Slave's u-boot environment, because the Slave can not erase,
+ write Master's NorFlash by PCIE or SRIO link.
diff --git a/doc/README.vf610 b/doc/README.vf610
new file mode 100644
index 0000000..38cf5cf
--- /dev/null
+++ b/doc/README.vf610
@@ -0,0 +1,10 @@
+U-Boot for Freescale Vybrid VF610
+
+This file contains information for the port of U-Boot to the Freescale Vybrid
+VF610 SoC.
+
+1. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+1.1 MAC Address: It is stored in fuse bank 4, with the 16 msbs in word 2 and the
+ 32 lsbs in word 3.
diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt b/doc/device-tree-bindings/exynos/dwmmc.txt
new file mode 100644
index 0000000..566da3b
--- /dev/null
+++ b/doc/device-tree-bindings/exynos/dwmmc.txt
@@ -0,0 +1,54 @@
+* Exynos 5250 DWC_mobile_storage
+
+The Exynos 5250 provides DWC_mobile_storage interface which supports
+. Embedded Multimedia Cards (EMMC-version 4.5)
+. Secure Digital memory (SD mem-version 2.0)
+. Secure Digital I/O (SDIO-version 3.0)
+. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
+
+The Exynos 5250 DWC_mobile_storage provides four channels.
+SOC specific and Board specific properties are channel specific.
+
+Required SoC Specific Properties:
+
+- compatible: should be
+ - samsung,exynos5250-dwmmc: for exynos5250 platforms
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- interrupts: The interrupt number to the cpu.
+
+Required Board Specific Properties:
+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- samsung,bus-width: The width of the bus used to interface the devices
+ supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
+ . Typically the bus width is 4 or 8.
+- samsung,timing: The timing values to be written into the
+ Drv/sample clock selection register of corresponding channel.
+ . It is comprised of 3 values corresponding to the 3 fileds
+ 'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register.
+ . SelClk_sample: Select sample clock among 8 shifted clocks.
+ . SelClk_drv: Select drv clock among 8 shifted clocks.
+ . DIVRATIO: Clock Divide ratio select.
+ . The above 3 values are used by the clock phase shifter.
+
+Example:
+
+mmc@12200000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ samsung,removable = <1>;
+}
+In the above example,
+ . The bus width is 8
+ . Timing is comprised of 3 values as explained below
+ 1 - SelClk_sample
+ 3 - SelClk_drv
+ 3 - DIVRATIO
+ . The 'removable' flag indicates whether the the particilar device
+ cannot be removed (always present) or it is a removable device.
+ 1 - Indicates that the device is removable.
+ 0 - Indicates that the device cannot be removed.
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 54e9b15..ef38d71 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -18,6 +18,20 @@
*
* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
*
+ * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
+ * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
+ * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
+ * OMAPs and derivatives as well. The only anticipated exception would
+ * be the OMAP2420, which shall require driver modification.
+ * - Rewritten i2c_read to operate correctly with all types of chips
+ * (old function could not read consistent data from some I2C slaves).
+ * - Optimized i2c_write.
+ * - New i2c_probe, performs write access vs read. The old probe could
+ * hang the system under certain conditions (e.g. unconfigured pads).
+ * - The read/write/probe functions try to identify unconfigured bus.
+ * - Status functions now read irqstatus_raw as per TRM guidelines
+ * (except for OMAP243X and OMAP34XX).
+ * - Driver now supports up to I2C5 (OMAP5).
*/
#include <common.h>
@@ -31,8 +45,11 @@
#define I2C_TIMEOUT 1000
+/* Absolutely safe for status update at 100 kHz I2C: */
+#define I2C_WAIT 200
+
static int wait_for_bb(void);
-static u16 wait_for_pin(void);
+static u16 wait_for_event(void);
static void flush_fifo(void);
/*
@@ -137,10 +154,14 @@
/* own address */
writew(slaveadd, &i2c_base->oa);
writew(I2C_CON_EN, &i2c_base->con);
-
- /* have to enable intrrupts or OMAP i2c module doesn't work */
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
+ /*
+ * Have to enable interrupts for OMAP2/3, these IPs don't have
+ * an 'irqstatus_raw' register and we shall have to poll 'stat'
+ */
writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
- I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
+ I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
+#endif
udelay(1000);
flush_fifo();
writew(0xFFFF, &i2c_base->stat);
@@ -150,88 +171,6 @@
bus_initialized[current_bus] = 1;
}
-static int i2c_read_byte(u8 devaddr, u16 regoffset, u8 alen, u8 *value)
-{
- int i2c_error = 0;
- u16 status;
- int i = 2 - alen;
- u8 tmpbuf[2] = {(regoffset) >> 8, regoffset & 0xff};
- u16 w;
-
- /* wait until bus not busy */
- if (wait_for_bb())
- return 1;
-
- /* one byte only */
- writew(alen, &i2c_base->cnt);
- /* set slave address */
- writew(devaddr, &i2c_base->sa);
- /* no stop bit needed here */
- writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
- I2C_CON_TRX, &i2c_base->con);
-
- /* send register offset */
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto read_exit;
- }
- if (status & I2C_STAT_XRDY) {
- w = tmpbuf[i++];
-#if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
- defined(CONFIG_OMAP54XX))
- w |= tmpbuf[i++] << 8;
-#endif
- writew(w, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
-
- /* set slave address */
- writew(devaddr, &i2c_base->sa);
- /* read one byte from slave */
- writew(1, &i2c_base->cnt);
- /* need stop bit here */
- writew(I2C_CON_EN | I2C_CON_MST |
- I2C_CON_STT | I2C_CON_STP,
- &i2c_base->con);
-
- /* receive data */
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto read_exit;
- }
- if (status & I2C_STAT_RRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
- defined(CONFIG_OMAP54XX)
- *value = readb(&i2c_base->data);
-#else
- *value = readw(&i2c_base->data);
-#endif
- writew(I2C_STAT_RRDY, &i2c_base->stat);
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
-
-read_exit:
- flush_fifo();
- writew(0xFFFF, &i2c_base->stat);
- writew(0, &i2c_base->cnt);
- return i2c_error;
-}
-
static void flush_fifo(void)
{ u16 stat;
@@ -241,13 +180,7 @@
while (1) {
stat = readw(&i2c_base->stat);
if (stat == I2C_STAT_RRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
- defined(CONFIG_OMAP54XX)
readb(&i2c_base->data);
-#else
- readw(&i2c_base->data);
-#endif
writew(I2C_STAT_RRDY, &i2c_base->stat);
udelay(1000);
} else
@@ -255,6 +188,10 @@
}
}
+/*
+ * i2c_probe: Use write access. Allows to identify addresses that are
+ * write-only (like the config register of dual-port EEPROMs)
+ */
int i2c_probe(uchar chip)
{
u16 status;
@@ -263,61 +200,81 @@
if (chip == readw(&i2c_base->oa))
return res;
- /* wait until bus not busy */
+ /* Wait until bus is free */
if (wait_for_bb())
return res;
- /* try to read one byte */
- writew(1, &i2c_base->cnt);
- /* set slave address */
+ /* No data transfer, slave addr only */
+ writew(0, &i2c_base->cnt);
+ /* Set slave address */
writew(chip, &i2c_base->sa);
- /* stop bit needed here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
+ /* Stop bit needed here */
+ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+ I2C_CON_STP, &i2c_base->con);
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_AL) {
- res = 1;
- goto probe_exit;
- }
- if (status & I2C_STAT_NACK) {
- res = 1;
- writew(0xff, &i2c_base->stat);
- writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
+ status = wait_for_event();
- if (wait_for_bb())
- res = 1;
+ if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
+ /*
+ * With current high-level command implementation, notifying
+ * the user shall flood the console with 127 messages. If
+ * silent exit is desired upon unconfigured bus, remove the
+ * following 'if' section:
+ */
+ if (status == I2C_STAT_XRDY)
+ printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
+ current_bus, status);
- break;
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- if (status & I2C_STAT_RRDY) {
- res = 0;
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
- defined(CONFIG_OMAP54XX)
- readb(&i2c_base->data);
-#else
- readw(&i2c_base->data);
-#endif
- writew(I2C_STAT_RRDY, &i2c_base->stat);
- }
+ goto pr_exit;
}
-probe_exit:
+ /* Check for ACK (!NAK) */
+ if (!(status & I2C_STAT_NACK)) {
+ res = 0; /* Device found */
+ udelay(I2C_WAIT); /* Required by AM335X in SPL */
+ /* Abort transfer (force idle state) */
+ writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
+ udelay(1000);
+ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
+ I2C_CON_STP, &i2c_base->con); /* STP */
+ }
+pr_exit:
flush_fifo();
- /* don't allow any more data in... we don't want it. */
- writew(0, &i2c_base->cnt);
writew(0xFFFF, &i2c_base->stat);
+ writew(0, &i2c_base->cnt);
return res;
}
+/*
+ * i2c_read: Function now uses a single I2C read transaction with bulk transfer
+ * of the requested number of bytes (note that the 'i2c md' command
+ * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
+ * defined in the board config header, this transaction shall be with
+ * Repeated Start (Sr) between the address and data phases; otherwise
+ * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
+ * The address (reg offset) may be 0, 1 or 2 bytes long.
+ * Function now reads correctly from chips that return more than one
+ * byte of data per addressed register (like TI temperature sensors),
+ * or that do not need a register address at all (such as some clock
+ * distributors).
+ */
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
- int i;
+ int i2c_error = 0;
+ u16 status;
+
+ if (alen < 0) {
+ puts("I2C read: addr len < 0\n");
+ return 1;
+ }
+ if (len < 0) {
+ puts("I2C read: data len < 0\n");
+ return 1;
+ }
+ if (buffer == NULL) {
+ puts("I2C read: NULL pointer passed\n");
+ return 1;
+ }
if (alen > 2) {
printf("I2C read: addr len %d not supported\n", alen);
@@ -329,24 +286,122 @@
return 1;
}
- for (i = 0; i < len; i++) {
- if (i2c_read_byte(chip, addr + i, alen, &buffer[i])) {
- puts("I2C read: I/O error\n");
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 1;
+ /* Wait until bus not busy */
+ if (wait_for_bb())
+ return 1;
+
+ /* Zero, one or two bytes reg address (offset) */
+ writew(alen, &i2c_base->cnt);
+ /* Set slave address */
+ writew(chip, &i2c_base->sa);
+
+ if (alen) {
+ /* Must write reg offset first */
+#ifdef CONFIG_I2C_REPEATED_START
+ /* No stop bit, use Repeated Start (Sr) */
+ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+ I2C_CON_TRX, &i2c_base->con);
+#else
+ /* Stop - Start (P-S) */
+ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
+ I2C_CON_TRX, &i2c_base->con);
+#endif
+ /* Send register offset */
+ while (1) {
+ status = wait_for_event();
+ /* Try to identify bus that is not padconf'd for I2C */
+ if (status == I2C_STAT_XRDY) {
+ i2c_error = 2;
+ printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
+ current_bus, status);
+ goto rd_exit;
+ }
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
+ status);
+ goto rd_exit;
+ }
+ if (alen) {
+ if (status & I2C_STAT_XRDY) {
+ alen--;
+ /* Do we have to use byte access? */
+ writeb((addr >> (8 * alen)) & 0xff,
+ &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ }
+ }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
+ }
+ }
+ }
+ /* Set slave address */
+ writew(chip, &i2c_base->sa);
+ /* Read len bytes from slave */
+ writew(len, &i2c_base->cnt);
+ /* Need stop bit here */
+ writew(I2C_CON_EN | I2C_CON_MST |
+ I2C_CON_STT | I2C_CON_STP,
+ &i2c_base->con);
+
+ /* Receive data */
+ while (1) {
+ status = wait_for_event();
+ /*
+ * Try to identify bus that is not padconf'd for I2C. This
+ * state could be left over from previous transactions if
+ * the address phase is skipped due to alen=0.
+ */
+ if (status == I2C_STAT_XRDY) {
+ i2c_error = 2;
+ printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
+ current_bus, status);
+ goto rd_exit;
+ }
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ goto rd_exit;
+ }
+ if (status & I2C_STAT_RRDY) {
+ *buffer++ = readb(&i2c_base->data);
+ writew(I2C_STAT_RRDY, &i2c_base->stat);
+ }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
}
}
- return 0;
+rd_exit:
+ flush_fifo();
+ writew(0xFFFF, &i2c_base->stat);
+ writew(0, &i2c_base->cnt);
+ return i2c_error;
}
+/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int i;
u16 status;
int i2c_error = 0;
- u16 w;
- u8 tmpbuf[2] = {addr >> 8, addr & 0xff};
+
+ if (alen < 0) {
+ puts("I2C write: addr len < 0\n");
+ return 1;
+ }
+
+ if (len < 0) {
+ puts("I2C write: data len < 0\n");
+ return 1;
+ }
+
+ if (buffer == NULL) {
+ puts("I2C write: NULL pointer passed\n");
+ return 1;
+ }
if (alen > 2) {
printf("I2C write: addr len %d not supported\n", alen);
@@ -355,92 +410,137 @@
if (addr + len > (1 << 16)) {
printf("I2C write: address 0x%x + 0x%x out of range\n",
- addr, len);
+ addr, len);
return 1;
}
- /* wait until bus not busy */
+ /* Wait until bus not busy */
if (wait_for_bb())
return 1;
- /* start address phase - will write regoffset + len bytes data */
- /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
+ /* Start address phase - will write regoffset + len bytes data */
writew(alen + len, &i2c_base->cnt);
- /* set slave address */
+ /* Set slave address */
writew(chip, &i2c_base->sa);
- /* stop bit needed here */
+ /* Stop bit needed here */
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
- I2C_CON_STP, &i2c_base->con);
+ I2C_CON_STP, &i2c_base->con);
- /* Send address and data */
- for (i = -alen; i < len; i++) {
- status = wait_for_pin();
-
+ while (alen) {
+ /* Must write reg offset (one or two bytes) */
+ status = wait_for_event();
+ /* Try to identify bus that is not padconf'd for I2C */
+ if (status == I2C_STAT_XRDY) {
+ i2c_error = 2;
+ printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
+ current_bus, status);
+ goto wr_exit;
+ }
if (status == 0 || status & I2C_STAT_NACK) {
i2c_error = 1;
- printf("i2c error waiting for data ACK (status=0x%x)\n",
- status);
- goto write_exit;
+ printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
+ status);
+ goto wr_exit;
}
-
if (status & I2C_STAT_XRDY) {
- w = (i < 0) ? tmpbuf[2+i] : buffer[i];
-#if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
- defined(CONFIG_OMAP54XX))
- w |= ((++i < 0) ? tmpbuf[2+i] : buffer[i]) << 8;
-#endif
- writew(w, &i2c_base->data);
+ alen--;
+ writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
writew(I2C_STAT_XRDY, &i2c_base->stat);
} else {
i2c_error = 1;
- printf("i2c bus not ready for Tx (i=%d)\n", i);
- goto write_exit;
+ printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
+ status);
+ goto wr_exit;
+ }
+ }
+ /* Address phase is over, now write data */
+ for (i = 0; i < len; i++) {
+ status = wait_for_event();
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
+ status);
+ goto wr_exit;
+ }
+ if (status & I2C_STAT_XRDY) {
+ writeb(buffer[i], &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ } else {
+ i2c_error = 1;
+ printf("i2c_write: bus not ready for data Tx (i=%d)\n",
+ i);
+ goto wr_exit;
}
}
-write_exit:
+wr_exit:
flush_fifo();
writew(0xFFFF, &i2c_base->stat);
+ writew(0, &i2c_base->cnt);
return i2c_error;
}
+/*
+ * Wait for the bus to be free by checking the Bus Busy (BB)
+ * bit to become clear
+ */
static int wait_for_bb(void)
{
int timeout = I2C_TIMEOUT;
u16 stat;
writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
+#else
+ /* Read RAW status */
+ while ((stat = readw(&i2c_base->irqstatus_raw) &
+ I2C_STAT_BB) && timeout--) {
+#endif
writew(stat, &i2c_base->stat);
- udelay(1000);
+ udelay(I2C_WAIT);
}
if (timeout <= 0) {
- printf("timed out in wait_for_bb: I2C_STAT=%x\n",
- readw(&i2c_base->stat));
+ printf("Timed out in wait_for_bb: status=%04x\n",
+ stat);
return 1;
}
writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
return 0;
}
-static u16 wait_for_pin(void)
+/*
+ * Wait for the I2C controller to complete current action
+ * and update status
+ */
+static u16 wait_for_event(void)
{
u16 status;
int timeout = I2C_TIMEOUT;
do {
- udelay(1000);
+ udelay(I2C_WAIT);
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
status = readw(&i2c_base->stat);
+#else
+ /* Read RAW status */
+ status = readw(&i2c_base->irqstatus_raw);
+#endif
} while (!(status &
(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
I2C_STAT_AL)) && timeout--);
if (timeout <= 0) {
- printf("timed out in wait_for_pin: I2C_STAT=%x\n",
- readw(&i2c_base->stat));
+ printf("Timed out in wait_for_event: status=%04x\n",
+ status);
+ /*
+ * If status is still 0 here, probably the bus pads have
+ * not been configured for I2C, and/or pull-ups are missing.
+ */
+ printf("Check if pads/pull-ups of bus %d are properly configured\n",
+ current_bus);
writew(0xFFFF, &i2c_base->stat);
status = 0;
}
@@ -450,28 +550,36 @@
int i2c_set_bus_num(unsigned int bus)
{
- if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
- printf("Bad bus: %d\n", bus);
+ if (bus >= I2C_BUS_MAX) {
+ printf("Bad bus: %x\n", bus);
return -1;
}
-#if I2C_BUS_MAX == 4
- if (bus == 3)
- i2c_base = (struct i2c *)I2C_BASE4;
- else
- if (bus == 2)
- i2c_base = (struct i2c *)I2C_BASE3;
- else
-#endif
-#if I2C_BUS_MAX == 3
- if (bus == 2)
- i2c_base = (struct i2c *)I2C_BASE3;
- else
-#endif
- if (bus == 1)
- i2c_base = (struct i2c *)I2C_BASE2;
- else
+ switch (bus) {
+ default:
+ bus = 0; /* Fall through */
+ case 0:
i2c_base = (struct i2c *)I2C_BASE1;
+ break;
+ case 1:
+ i2c_base = (struct i2c *)I2C_BASE2;
+ break;
+#if (I2C_BUS_MAX > 2)
+ case 2:
+ i2c_base = (struct i2c *)I2C_BASE3;
+ break;
+#if (I2C_BUS_MAX > 3)
+ case 3:
+ i2c_base = (struct i2c *)I2C_BASE4;
+ break;
+#if (I2C_BUS_MAX > 4)
+ case 4:
+ i2c_base = (struct i2c *)I2C_BASE5;
+ break;
+#endif
+#endif
+#endif
+ }
current_bus = bus;
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 4070d4e..5da20ed 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -129,13 +129,13 @@
unsigned int timeout = 100000;
u32 retry = 10000;
u32 mask, ctrl;
+ ulong start = get_timer(0);
while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
- if (timeout == 0) {
+ if (get_timer(start) > timeout) {
printf("Timeout on data busy\n");
return TIMEOUT;
}
- timeout--;
}
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
@@ -143,7 +143,6 @@
if (data)
dwmci_prepare_data(host, data);
-
dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
if (data)
@@ -231,9 +230,8 @@
int timeout = 10000;
unsigned long sclk;
- if (freq == host->clock)
+ if ((freq == host->clock) || (freq == 0))
return 0;
-
/*
* If host->mmc_clk didn't define,
* then assume that host->bus_hz is source clock value.
@@ -314,7 +312,7 @@
static int dwmci_init(struct mmc *mmc)
{
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
- u32 fifo_size, fifoth_val;
+ u32 fifo_size;
dwmci_writel(host, DWMCI_PWREN, 1);
@@ -323,6 +321,9 @@
return -1;
}
+ /* Enumerate at 400KHz */
+ dwmci_setup_bus(host, mmc->f_min);
+
dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
dwmci_writel(host, DWMCI_INTMASK, 0);
@@ -331,13 +332,13 @@
dwmci_writel(host, DWMCI_IDINTEN, 0);
dwmci_writel(host, DWMCI_BMOD, 1);
- fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
- if (host->fifoth_val)
- fifoth_val = host->fifoth_val;
- else
- fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
- TX_WMARK(fifo_size/2);
- dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
+ if (!host->fifoth_val) {
+ fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+ fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
+ host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+ TX_WMARK(fifo_size / 2);
+ }
+ dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
dwmci_writel(host, DWMCI_CLKENA, 0);
dwmci_writel(host, DWMCI_CLKSRC, 0);
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 72a31b7..4238dd9 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -19,39 +19,146 @@
*/
#include <common.h>
-#include <malloc.h>
#include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define DWMMC_MAX_CH_NUM 4
+#define DWMMC_MAX_FREQ 52000000
+#define DWMMC_MIN_FREQ 400000
+#define DWMMC_MMC0_CLKSEL_VAL 0x03030001
+#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
static void exynos_dwmci_clksel(struct dwmci_host *host)
{
- u32 val;
- val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
- DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
-
- dwmci_writel(host, DWMCI_CLKSEL, val);
+ dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
}
-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+ return get_mmc_clk(dev_index);
+}
+
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index - mmc channel number.
+ * regbase - register base address of mmc channel specified in 'index'.
+ * bus_width - operating bus width of mmc channel specified in 'index'.
+ * clksel - value to be written into CLKSEL register in case of FDT.
+ * NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
{
struct dwmci_host *host = NULL;
+ unsigned int div;
+ unsigned long freq, sclk;
host = malloc(sizeof(struct dwmci_host));
if (!host) {
printf("dwmci_host malloc fail!\n");
return 1;
}
+ /* request mmc clock vlaue of 52MHz. */
+ freq = 52000000;
+ sclk = get_mmc_clk(index);
+ div = DIV_ROUND_UP(sclk, freq);
+ /* set the clock divisor for mmc */
+ set_mmc_clk(index, div);
- host->name = EXYNOS_NAME;
+ host->name = "EXYNOS DWMMC";
host->ioaddr = (void *)regbase;
host->buswidth = bus_width;
+
+ if (clksel) {
+ host->clksel_val = clksel;
+ } else {
+ if (0 == index)
+ host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+ if (2 == index)
+ host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+ }
+
host->clksel = exynos_dwmci_clksel;
host->dev_index = index;
-
- add_dwmci(host, 52000000, 400000);
-
+ host->mmc_clk = exynos_dwmci_get_clk;
+ /* Add the mmc channel to be registered with mmc core */
+ if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+ debug("dwmmc%d registration failed\n", index);
+ return -1;
+ }
return 0;
}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+ int index, bus_width;
+ int node_list[DWMMC_MAX_CH_NUM];
+ int err = 0, dev_id, flag, count, i;
+ u32 clksel_val, base, timing[3];
+
+ count = fdtdec_find_aliases_for_id(blob, "mmc",
+ COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+ DWMMC_MAX_CH_NUM);
+
+ for (i = 0; i < count; i++) {
+ int node = node_list[i];
+
+ if (node <= 0)
+ continue;
+
+ /* Extract device id for each mmc channel */
+ dev_id = pinmux_decode_periph_id(blob, node);
+
+ /* Get the bus width from the device node */
+ bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+ if (bus_width <= 0) {
+ debug("DWMMC: Can't get bus-width\n");
+ return -1;
+ }
+ if (8 == bus_width)
+ flag = PINMUX_FLAG_8BIT_MODE;
+ else
+ flag = PINMUX_FLAG_NONE;
+
+ /* config pinmux for each mmc channel */
+ err = exynos_pinmux_config(dev_id, flag);
+ if (err) {
+ debug("DWMMC not configured\n");
+ return err;
+ }
+
+ index = dev_id - PERIPH_ID_SDMMC0;
+
+ /* Get the base address from the device node */
+ base = fdtdec_get_addr(blob, node, "reg");
+ if (!base) {
+ debug("DWMMC: Can't get base address\n");
+ return -1;
+ }
+ /* Extract the timing info from the node */
+ err = fdtdec_get_int_array(blob, node, "samsung,timing",
+ timing, 3);
+ if (err) {
+ debug("Can't get sdr-timings for divider\n");
+ return -1;
+ }
+
+ clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+ DWMCI_SET_DRV_CLK(timing[1]) |
+ DWMCI_SET_DIV_RATIO(timing[2]));
+ /* Initialise each mmc channel */
+ err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
+ if (err)
+ debug("dwmmc Channel-%d init failed\n", index);
+ }
+ return 0;
+}
+#endif
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 861f4b9..973b19f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -178,7 +178,7 @@
int timeout;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
uint wml_value;
wml_value = data->blocksize/4;
@@ -310,6 +310,9 @@
/* Figure out the transfer arguments */
xfertyp = esdhc_xfertyp(cmd, data);
+ /* Mask all irqs */
+ esdhc_write32(®s->irqsigen, 0);
+
/* Send the command */
esdhc_write32(®s->cmdarg, cmd->cmdarg);
#if defined(CONFIG_FSL_USDHC)
@@ -320,15 +323,11 @@
esdhc_write32(®s->xfertyp, xfertyp);
#endif
- /* Mask all irqs */
- esdhc_write32(®s->irqsigen, 0);
-
/* Wait for the command to complete */
while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
;
irqstat = esdhc_read32(®s->irqstat);
- esdhc_write32(®s->irqstat, irqstat);
/* Reset CMD and DATA portions on error */
if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 0a2f535..83d2df7 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -301,10 +301,12 @@
return 0;
}
- if (blkcnt > 1)
- cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
- else
+ if (blkcnt == 0)
+ return 0;
+ else if (blkcnt == 1)
cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
+ else
+ cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
if (mmc->high_capacity)
cmd.cmdarg = start;
@@ -700,16 +702,49 @@
return 0;
}
+static int mmc_set_capacity(struct mmc *mmc, int part_num)
+{
+ switch (part_num) {
+ case 0:
+ mmc->capacity = mmc->capacity_user;
+ break;
+ case 1:
+ case 2:
+ mmc->capacity = mmc->capacity_boot;
+ break;
+ case 3:
+ mmc->capacity = mmc->capacity_rpmb;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ mmc->capacity = mmc->capacity_gp[part_num - 4];
+ break;
+ default:
+ return -1;
+ }
+
+ mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
+
+ return 0;
+}
+
int mmc_switch_part(int dev_num, unsigned int part_num)
{
struct mmc *mmc = find_mmc_device(dev_num);
+ int ret;
if (!mmc)
return -1;
- return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
- (mmc->part_config & ~PART_ACCESS_MASK)
- | (part_num & PART_ACCESS_MASK));
+ ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
+ (mmc->part_config & ~PART_ACCESS_MASK)
+ | (part_num & PART_ACCESS_MASK));
+ if (ret)
+ return ret;
+
+ return mmc_set_capacity(mmc, part_num);
}
int mmc_getcd(struct mmc *mmc)
@@ -917,7 +952,7 @@
static int mmc_startup(struct mmc *mmc)
{
- int err;
+ int err, i;
uint mult, freq;
u64 cmult, csize, capacity;
struct mmc_cmd cmd;
@@ -1035,8 +1070,12 @@
cmult = (mmc->csd[2] & 0x00038000) >> 15;
}
- mmc->capacity = (csize + 1) << (cmult + 2);
- mmc->capacity *= mmc->read_bl_len;
+ mmc->capacity_user = (csize + 1) << (cmult + 2);
+ mmc->capacity_user *= mmc->read_bl_len;
+ mmc->capacity_boot = 0;
+ mmc->capacity_rpmb = 0;
+ for (i = 0; i < 4; i++)
+ mmc->capacity_gp[i] = 0;
if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
@@ -1075,7 +1114,7 @@
| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
capacity *= MMC_MAX_BLOCK_LEN;
if ((capacity >> 20) > 2 * 1024)
- mmc->capacity = capacity;
+ mmc->capacity_user = capacity;
}
switch (ext_csd[EXT_CSD_REV]) {
@@ -1117,8 +1156,25 @@
if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
ext_csd[EXT_CSD_BOOT_MULT])
mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
+
+ mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
+
+ mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
+
+ for (i = 0; i < 4; i++) {
+ int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
+ mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) +
+ (ext_csd[idx + 1] << 8) + ext_csd[idx];
+ mmc->capacity_gp[i] *=
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
+ mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+ }
}
+ err = mmc_set_capacity(mmc, mmc->part_num);
+ if (err)
+ return err;
+
if (IS_SD(mmc))
err = sd_change_freq(mmc);
else
@@ -1447,3 +1503,137 @@
do_preinit();
return 0;
}
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+/*
+ * This function changes the size of boot partition and the size of rpmb
+ * partition present on EMMC devices.
+ *
+ * Input Parameters:
+ * struct *mmc: pointer for the mmc device strcuture
+ * bootsize: size of boot partition
+ * rpmbsize: size of rpmb partition
+ *
+ * Returns 0 on success.
+ */
+
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+ unsigned long rpmbsize)
+{
+ int err;
+ struct mmc_cmd cmd;
+
+ /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = MMC_CMD62_ARG1;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err) {
+ debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
+ return err;
+ }
+
+ /* Boot partition changing mode */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = MMC_CMD62_ARG2;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err) {
+ debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
+ return err;
+ }
+ /* boot partition size is multiple of 128KB */
+ bootsize = (bootsize * 1024) / 128;
+
+ /* Arg: boot partition size */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = bootsize;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err) {
+ debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
+ return err;
+ }
+ /* RPMB partition size is multiple of 128KB */
+ rpmbsize = (rpmbsize * 1024) / 128;
+ /* Arg: RPMB partition size */
+ cmd.cmdidx = MMC_CMD_RES_MAN;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = rpmbsize;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err) {
+ debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
+ return err;
+ }
+ return 0;
+}
+
+/*
+ * This function shall form and send the commands to open / close the
+ * boot partition specified by user.
+ *
+ * Input Parameters:
+ * ack: 0x0 - No boot acknowledge sent (default)
+ * 0x1 - Boot acknowledge sent during boot operation
+ * part_num: User selects boot data that will be sent to master
+ * 0x0 - Device not boot enabled (default)
+ * 0x1 - Boot partition 1 enabled for boot
+ * 0x2 - Boot partition 2 enabled for boot
+ * access: User selects partitions to access
+ * 0x0 : No access to boot partition (default)
+ * 0x1 : R/W boot partition 1
+ * 0x2 : R/W boot partition 2
+ * 0x3 : R/W Replay Protected Memory Block (RPMB)
+ *
+ * Returns 0 on success.
+ */
+int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+{
+ int err;
+ struct mmc_cmd cmd;
+
+ /* Boot ack enable, boot partition enable , boot partition access */
+ cmd.cmdidx = MMC_CMD_SWITCH;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
+ (EXT_CSD_PART_CONF << 16) |
+ ((EXT_CSD_BOOT_ACK(ack) |
+ EXT_CSD_BOOT_PART_NUM(part_num) |
+ EXT_CSD_PARTITION_ACCESS(access)) << 8);
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err) {
+ if (access) {
+ debug("mmc boot partition#%d open fail:Error1 = %d\n",
+ part_num, err);
+ } else {
+ debug("mmc boot partition#%d close fail:Error = %d\n",
+ part_num, err);
+ }
+ return err;
+ }
+
+ if (access) {
+ /* 4bit transfer mode at booting time. */
+ cmd.cmdidx = MMC_CMD_SWITCH;
+ cmd.resp_type = MMC_RSP_R1b;
+
+ cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
+ (EXT_CSD_BOOT_BUS_WIDTH << 16) |
+ ((1 << 0) << 8);
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err) {
+ debug("mmc boot partition#%d open fail:Error2 = %d\n",
+ part_num, err);
+ return err;
+ }
+ }
+ return 0;
+}
+#endif
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index afdfa88..975b2c5 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -113,23 +113,21 @@
u32 value = 0;
value = readl((*ctrl)->control_pbias);
- value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
+ value &= ~SDCARD_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+ udelay(10); /* wait 10 us */
+ value &= ~SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)->control_pbias);
palmas_mmc1_poweron_ldo();
value = readl((*ctrl)->control_pbias);
- value &= ~SDCARD_BIAS_HIZ_MODE;
- value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
+ value |= SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)->control_pbias);
-
- value = readl((*ctrl)->control_pbias);
- if (value & (1 << 23)) {
- value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
- value |= SDCARD_BIAS_HIZ_MODE;
- writel(value, (*ctrl)->control_pbias);
- }
+ udelay(150); /* wait 150 us */
+ value |= SDCARD_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+ udelay(150); /* wait 150 us */
}
#endif
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 1eaea04..c5631bf 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -486,8 +486,10 @@
mmc->voltages |= host->voltages;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
- if (caps & SDHCI_CAN_DO_8BIT)
- mmc->host_caps |= MMC_MODE_8BIT;
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
+ if (caps & SDHCI_CAN_DO_8BIT)
+ mmc->host_caps |= MMC_MODE_8BIT;
+ }
if (host->host_caps)
mmc->host_caps |= host->host_caps;
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8821704..bb81e84 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -83,6 +83,7 @@
else # minimal SPL drivers
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
+COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
endif # drivers
diff --git a/nand_spl/nand_boot_fsl_ifc.c b/drivers/mtd/nand/fsl_ifc_spl.c
similarity index 88%
rename from nand_spl/nand_boot_fsl_ifc.c
rename to drivers/mtd/nand/fsl_ifc_spl.c
index 44972c5..8537c4c 100644
--- a/nand_spl/nand_boot_fsl_ifc.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -1,5 +1,5 @@
/*
- * NAND boot for FSL Integrated Flash Controller, NAND Flash Control Machine
+ * NAND boot for Freescale Integrated Flash Controller, NAND FCM
*
* Copyright 2011 Freescale Semiconductor, Inc.
* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
@@ -46,9 +46,9 @@
unsigned int bufnum, int page_size)
{
u32 reg = eccstat[bufnum / 4];
- int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
+ int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
- if (errors == 15) { /* uncorrectable */
+ if (errors == 0xf) { /* uncorrectable */
/* Blank pages fail hw ECC checks */
if (is_blank(buf, page_size))
return 1;
@@ -123,30 +123,17 @@
csor = CONFIG_SYS_NAND_CSOR;
cspr = CONFIG_SYS_NAND_CSPR;
- if (!(csor & CSOR_NAND_ECC_DEC_EN)) {
- /* soft ECC in SPL is unimplemented */
- puts("WARNING: soft ECC not checked in SPL\n");
- } else {
- u32 hwcsor;
-
- /* make sure board is configured with ECC on boot */
- hwcsor = in_be32(&ifc->csor_cs[0].csor);
- if (!(hwcsor & CSOR_NAND_ECC_DEC_EN))
- puts("WARNING: ECC not checked in SPL, "
- "check board cfg\n");
- }
-
port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
if (csor & CSOR_NAND_PGS_4K) {
page_size = 4096;
- bufnum_mask = 1;
+ bufnum_mask = 0x1;
} else if (csor & CSOR_NAND_PGS_2K) {
page_size = 2048;
- bufnum_mask = 3;
+ bufnum_mask = 0x3;
} else {
page_size = 512;
- bufnum_mask = 15;
+ bufnum_mask = 0xf;
if (port_size == 8)
bad_marker = 5;
@@ -174,8 +161,8 @@
out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
out_be32(&ifc->ifc_nand.nand_fcr0,
- (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
- (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+ (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+ (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
} else {
out_be32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
@@ -185,7 +172,7 @@
out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
out_be32(&ifc->ifc_nand.nand_fcr0,
- NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+ NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
}
/* Program FBCR = 0 for full page read */
@@ -206,7 +193,7 @@
out_be32(&ifc->ifc_nand.col0, 0);
/* start read */
out_be32(&ifc->ifc_nand.nandseq_strt,
- IFC_NAND_SEQ_STRT_FIR_STRT);
+ IFC_NAND_SEQ_STRT_FIR_STRT);
/* wait for read to complete */
nand_wait(&buf[sram_addr], bufnum, page_size);
@@ -241,7 +228,6 @@
void nand_boot(void)
{
__attribute__((noreturn)) void (*uboot)(void);
-
/*
* Load U-Boot image from NAND into RAM
*/
@@ -257,15 +243,16 @@
(uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
-
/*
* Jump to U-Boot image
*/
+#ifdef CONFIG_SPL_FLUSH_IMAGE
/*
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+#endif
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot();
}
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 90f8392..ecbb210 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -32,6 +32,7 @@
COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o
COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o
+COBJS-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.o
COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o
COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o
COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
diff --git a/drivers/mtd/spi/gigadevice.c b/drivers/mtd/spi/gigadevice.c
new file mode 100644
index 0000000..b5e1ebe
--- /dev/null
+++ b/drivers/mtd/spi/gigadevice.c
@@ -0,0 +1,81 @@
+/*
+ * Gigadevice SPI flash driver
+ * Copyright 2013, Samsung Electronics Co., Ltd.
+ * Author: Banajit Goswami <banajit.g@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#include "spi_flash_internal.h"
+
+struct gigadevice_spi_flash_params {
+ uint16_t id;
+ uint16_t nr_blocks;
+ const char *name;
+};
+
+static const struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] = {
+ {
+ .id = 0x6016,
+ .nr_blocks = 64,
+ .name = "GD25LQ",
+ },
+ {
+ .id = 0x4017,
+ .nr_blocks = 128,
+ .name = "GD25Q64B",
+ },
+};
+
+struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode)
+{
+ const struct gigadevice_spi_flash_params *params;
+ struct spi_flash *flash;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gigadevice_spi_flash_table); i++) {
+ params = &gigadevice_spi_flash_table[i];
+ if (params->id == ((idcode[1] << 8) | idcode[2]))
+ break;
+ }
+
+ if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) {
+ debug("SF: Unsupported Gigadevice ID %02x%02x\n",
+ idcode[1], idcode[2]);
+ return NULL;
+ }
+
+ flash = spi_flash_alloc_base(spi, params->name);
+ if (!flash) {
+ debug("SF: Failed to allocate memory\n");
+ return NULL;
+ }
+ /* page_size */
+ flash->page_size = 256;
+ /* sector_size = page_size * pages_per_sector */
+ flash->sector_size = flash->page_size * 16;
+ /* size = sector_size * sector_per_block * number of blocks */
+ flash->size = flash->sector_size * 16 * params->nr_blocks;
+
+ return flash;
+}
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index dad30b5..3ec2151 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -90,18 +90,32 @@
.name = "S25FL032P",
},
{
+ .idcode1 = 0x0216,
+ .idcode2 = 0x4d00,
+ .pages_per_sector = 256,
+ .nr_sectors = 128,
+ .name = "S25FL064P",
+ },
+ {
.idcode1 = 0x2018,
.idcode2 = 0x4d01,
.pages_per_sector = 256,
.nr_sectors = 256,
- .name = "S25FL129P_64K/S25FL128S",
+ .name = "S25FL129P_64K/S25FL128S_64K",
},
{
.idcode1 = 0x0219,
.idcode2 = 0x4d01,
.pages_per_sector = 256,
.nr_sectors = 512,
- .name = "S25FL256S",
+ .name = "S25FL256S_64K",
+ },
+ {
+ .idcode1 = 0x0220,
+ .idcode2 = 0x4d01,
+ .pages_per_sector = 256,
+ .nr_sectors = 1024,
+ .name = "S25FL512S_64K",
},
};
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 111185a..6a6fe37 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -68,109 +68,25 @@
return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
}
-int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
- size_t len, const void *buf)
-{
- unsigned long page_addr, byte_addr, page_size;
- size_t chunk_len, actual;
- int ret;
- u8 cmd[4];
-
- page_size = flash->page_size;
- page_addr = offset / page_size;
- byte_addr = offset % page_size;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: unable to claim SPI bus\n");
- return ret;
- }
-
- cmd[0] = CMD_PAGE_PROGRAM;
- for (actual = 0; actual < len; actual += chunk_len) {
- chunk_len = min(len - actual, page_size - byte_addr);
-
- if (flash->spi->max_write_size)
- chunk_len = min(chunk_len, flash->spi->max_write_size);
-
- cmd[1] = page_addr >> 8;
- cmd[2] = page_addr;
- cmd[3] = byte_addr;
-
- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-
- ret = spi_flash_cmd_write_enable(flash);
- if (ret < 0) {
- debug("SF: enabling write failed\n");
- break;
- }
-
- ret = spi_flash_cmd_write(flash->spi, cmd, 4,
- buf + actual, chunk_len);
- if (ret < 0) {
- debug("SF: write failed\n");
- break;
- }
-
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
- if (ret)
- break;
-
- byte_addr += chunk_len;
- if (byte_addr == page_size) {
- page_addr++;
- byte_addr = 0;
- }
- }
-
- debug("SF: program %s %zu bytes @ %#x\n",
- ret ? "failure" : "success", len, offset);
-
- spi_release_bus(flash->spi);
- return ret;
-}
-
-int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len)
-{
- struct spi_slave *spi = flash->spi;
- int ret;
-
- spi_claim_bus(spi);
- ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
- spi_release_bus(spi);
-
- return ret;
-}
-
-int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
- size_t len, void *data)
-{
- u8 cmd[5];
-
- /* Handle memory-mapped SPI */
- if (flash->memory_map)
- memcpy(data, flash->memory_map + offset, len);
-
- cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
- cmd[4] = 0x00;
-
- return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
-}
-
-int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
- u8 cmd, u8 poll_bit)
+int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
{
struct spi_slave *spi = flash->spi;
unsigned long timebase;
int ret;
u8 status;
+ u8 check_status = 0x0;
+ u8 poll_bit = STATUS_WIP;
+ u8 cmd = flash->poll_cmd;
+
+ if (cmd == CMD_FLAG_STATUS) {
+ poll_bit = STATUS_PEC;
+ check_status = poll_bit;
+ }
ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
if (ret) {
- debug("SF: Failed to send command %02x: %d\n", cmd, ret);
+ debug("SF: fail to read %s status register\n",
+ cmd == CMD_READ_STATUS ? "read" : "flag");
return ret;
}
@@ -182,14 +98,14 @@
if (ret)
return -1;
- if ((status & poll_bit) == 0)
+ if ((status & poll_bit) == check_status)
break;
} while (get_timer(timebase) < timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
- if ((status & poll_bit) == 0)
+ if ((status & poll_bit) == check_status)
return 0;
/* Timed out */
@@ -197,17 +113,52 @@
return -1;
}
-int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
+int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, const void *buf, size_t buf_len)
{
- return spi_flash_cmd_poll_bit(flash, timeout,
- CMD_READ_STATUS, STATUS_WIP);
+ struct spi_slave *spi = flash->spi;
+ unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
+ int ret;
+
+ if (buf == NULL)
+ timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
+ if (ret < 0) {
+ debug("SF: write cmd failed\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, timeout);
+ if (ret < 0) {
+ debug("SF: write %s timed out\n",
+ timeout == SPI_FLASH_PROG_TIMEOUT ?
+ "program" : "page erase");
+ return ret;
+ }
+
+ spi_release_bus(spi);
+
+ return ret;
}
int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
{
- u32 start, end, erase_size;
- int ret;
+ u32 erase_size;
u8 cmd[4];
+ int ret = -1;
erase_size = flash->sector_size;
if (offset % erase_size || len % erase_size) {
@@ -215,43 +166,157 @@
return -1;
}
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
if (erase_size == 4096)
cmd[0] = CMD_ERASE_4K;
else
cmd[0] = CMD_ERASE_64K;
- start = offset;
- end = start + len;
- while (offset < end) {
+ while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel;
+
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+#endif
spi_flash_addr(offset, cmd);
- offset += erase_size;
debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
cmd[2], cmd[3], offset);
- ret = spi_flash_cmd_write_enable(flash);
- if (ret)
- goto out;
+ ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
+ if (ret < 0) {
+ debug("SF: erase failed\n");
+ break;
+ }
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0);
- if (ret)
- goto out;
-
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
- if (ret)
- goto out;
+ offset += erase_size;
+ len -= erase_size;
}
- debug("SF: Successfully erased %zu bytes @ %#x\n", len, start);
+ return ret;
+}
- out:
- spi_release_bus(flash->spi);
+int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ unsigned long byte_addr, page_size;
+ size_t chunk_len, actual;
+ u8 cmd[4];
+ int ret = -1;
+
+ page_size = flash->page_size;
+
+ cmd[0] = CMD_PAGE_PROGRAM;
+ for (actual = 0; actual < len; actual += chunk_len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ u8 bank_sel;
+
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+#endif
+ byte_addr = offset % page_size;
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ if (flash->spi->max_write_size)
+ chunk_len = min(chunk_len, flash->spi->max_write_size);
+
+ spi_flash_addr(offset, cmd);
+
+ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+ ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ debug("SF: write failed\n");
+ break;
+ }
+
+ offset += chunk_len;
+ }
+
+ return ret;
+}
+
+int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len)
+{
+ struct spi_slave *spi = flash->spi;
+ int ret;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
+ if (ret < 0) {
+ debug("SF: read cmd failed\n");
+ return ret;
+ }
+
+ spi_release_bus(spi);
+
+ return ret;
+}
+
+int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
+ size_t len, void *data)
+{
+ u8 cmd[5], bank_sel = 0;
+ u32 remain_len, read_len;
+ int ret = -1;
+
+ /* Handle memory-mapped SPI */
+ if (flash->memory_map) {
+ memcpy(data, flash->memory_map + offset, len);
+ return 0;
+ }
+
+ cmd[0] = CMD_READ_ARRAY_FAST;
+ cmd[4] = 0x00;
+
+ while (len) {
+#ifdef CONFIG_SPI_FLASH_BAR
+ bank_sel = offset / SPI_FLASH_16MB_BOUN;
+
+ ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
+ if (ret) {
+ debug("SF: fail to set bank%d\n", bank_sel);
+ return ret;
+ }
+#endif
+ remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
+ if (len < remain_len)
+ read_len = len;
+ else
+ read_len = remain_len;
+
+ spi_flash_addr(offset, cmd);
+
+ ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+ data, read_len);
+ if (ret < 0) {
+ debug("SF: read failed\n");
+ break;
+ }
+
+ offset += read_len;
+ len -= read_len;
+ data += read_len;
+ }
+
return ret;
}
@@ -260,28 +325,75 @@
u8 cmd;
int ret;
- ret = spi_flash_cmd_write_enable(flash);
- if (ret < 0) {
- debug("SF: enabling write failed\n");
- return ret;
- }
-
cmd = CMD_WRITE_STATUS;
- ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1);
- if (ret) {
- debug("SF: fail to write status register\n");
- return ret;
- }
-
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
if (ret < 0) {
- debug("SF: write status register timed out\n");
+ debug("SF: fail to write status register\n");
return ret;
}
return 0;
}
+#ifdef CONFIG_SPI_FLASH_BAR
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
+{
+ u8 cmd;
+ int ret;
+
+ if (flash->bank_curr == bank_sel) {
+ debug("SF: not require to enable bank%d\n", bank_sel);
+ return 0;
+ }
+
+ cmd = flash->bank_write_cmd;
+ ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
+ if (ret < 0) {
+ debug("SF: fail to write bank register\n");
+ return ret;
+ }
+ flash->bank_curr = bank_sel;
+
+ return 0;
+}
+
+int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
+{
+ u8 cmd;
+ u8 curr_bank = 0;
+
+ /* discover bank cmds */
+ switch (idcode0) {
+ case SPI_FLASH_SPANSION_IDCODE0:
+ flash->bank_read_cmd = CMD_BANKADDR_BRRD;
+ flash->bank_write_cmd = CMD_BANKADDR_BRWR;
+ break;
+ case SPI_FLASH_STMICRO_IDCODE0:
+ case SPI_FLASH_WINBOND_IDCODE0:
+ flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
+ flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
+ break;
+ default:
+ printf("SF: Unsupported bank commands %02x\n", idcode0);
+ return -1;
+ }
+
+ /* read the bank reg - on which bank the flash is in currently */
+ cmd = flash->bank_read_cmd;
+ if (flash->size > SPI_FLASH_16MB_BOUN) {
+ if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) {
+ debug("SF: fail to read bank addr register\n");
+ return -1;
+ }
+ flash->bank_curr = curr_bank;
+ } else {
+ flash->bank_curr = curr_bank;
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_OF_CONTROL
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
{
@@ -346,6 +458,9 @@
#ifdef CONFIG_SPI_FLASH_EON
{ 0, 0x1c, spi_flash_probe_eon, },
#endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE
+ { 0, 0xc8, spi_flash_probe_gigadevice, },
+#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX
{ 0, 0xc2, spi_flash_probe_macronix, },
#endif
@@ -426,6 +541,13 @@
goto err_manufacturer_probe;
}
+#ifdef CONFIG_SPI_FLASH_BAR
+ /* Configure the BAR - disover bank cmds and read current bank */
+ ret = spi_flash_bank_config(flash, *idp);
+ if (ret < 0)
+ goto err_manufacturer_probe;
+#endif
+
#ifdef CONFIG_OF_CONTROL
if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
debug("SF: FDT decode error\n");
@@ -438,6 +560,12 @@
if (flash->memory_map)
printf(", mapped at %p", flash->memory_map);
puts("\n");
+#ifndef CONFIG_SPI_FLASH_BAR
+ if (flash->size > SPI_FLASH_16MB_BOUN) {
+ puts("SF: Warning - Only lower 16MiB accessible,");
+ puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
+ }
+#endif
spi_release_bus(spi);
@@ -468,6 +596,7 @@
/* Set up some basic fields - caller will sort out sizes */
flash->spi = spi;
flash->name = name;
+ flash->poll_cmd = CMD_READ_STATUS;
flash->read = spi_flash_cmd_read_fast;
flash->write = spi_flash_cmd_write_multi;
diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h
index 141cfa8..af1afa9 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -22,14 +22,31 @@
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS 0x05
+#define CMD_FLAG_STATUS 0x70
#define CMD_WRITE_ENABLE 0x06
#define CMD_ERASE_4K 0x20
#define CMD_ERASE_32K 0x52
#define CMD_ERASE_64K 0xd8
#define CMD_ERASE_CHIP 0xc7
+#define SPI_FLASH_16MB_BOUN 0x1000000
+
+/* Manufacture ID's */
+#define SPI_FLASH_SPANSION_IDCODE0 0x01
+#define SPI_FLASH_STMICRO_IDCODE0 0x20
+#define SPI_FLASH_WINBOND_IDCODE0 0xef
+
+#ifdef CONFIG_SPI_FLASH_BAR
+/* Bank addr access commands */
+# define CMD_BANKADDR_BRWR 0x17
+# define CMD_BANKADDR_BRRD 0x16
+# define CMD_EXTNADDR_WREAR 0xC5
+# define CMD_EXTNADDR_RDEAR 0xC8
+#endif
+
/* Common status */
#define STATUS_WIP 0x01
+#define STATUS_PEC 0x80
/* Send a single-byte command to the device and read the response */
int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
@@ -77,16 +94,30 @@
/* Program the status register. */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+#ifdef CONFIG_SPI_FLASH_BAR
+/* Program the bank address register */
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel);
+
+/* Configure the BAR - discover the bank cmds */
+int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0);
+#endif
+
/*
* Same as spi_flash_cmd_read() except it also claims/releases the SPI
* bus. Used as common part of the ->read() operation.
*/
int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len);
-
-/* Send a command to the device and wait for some bit to clear itself. */
-int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
- u8 cmd, u8 poll_bit);
+/*
+ * Used for spi_flash write operation
+ * - SPI claim
+ * - spi_flash_cmd_write_enable
+ * - spi_flash_cmd_write
+ * - spi_flash_cmd_wait_ready
+ * - SPI release
+ */
+int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
+ size_t cmd_len, const void *buf, size_t buf_len);
/*
* Send the read status command to the device and wait for the wip
@@ -106,3 +137,4 @@
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode);
diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c
index 2a9972b..7e41ee1 100644
--- a/drivers/mtd/spi/stmicro.c
+++ b/drivers/mtd/spi/stmicro.c
@@ -140,6 +140,30 @@
.nr_sectors = 512,
.name = "N25Q256A",
},
+ {
+ .id = 0xba20,
+ .pages_per_sector = 256,
+ .nr_sectors = 1024,
+ .name = "N25Q512",
+ },
+ {
+ .id = 0xbb20,
+ .pages_per_sector = 256,
+ .nr_sectors = 1024,
+ .name = "N25Q512A",
+ },
+ {
+ .id = 0xba21,
+ .pages_per_sector = 256,
+ .nr_sectors = 2048,
+ .name = "N25Q1024",
+ },
+ {
+ .id = 0xbb21,
+ .pages_per_sector = 256,
+ .nr_sectors = 2048,
+ .name = "N25Q1024A",
+ },
};
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
@@ -186,5 +210,9 @@
flash->sector_size = 256 * params->pages_per_sector;
flash->size = flash->sector_size * params->nr_sectors;
+ /* for >= 512MiB flashes, use flag status instead of read_status */
+ if (flash->size >= 0x4000000)
+ flash->poll_cmd = CMD_FLAG_STATUS;
+
return flash;
}
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index 2716209..c399bf1 100644
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -18,6 +18,21 @@
static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
{
+ .id = 0x2014,
+ .nr_blocks = 16,
+ .name = "W25P80",
+ },
+ {
+ .id = 0x2015,
+ .nr_blocks = 32,
+ .name = "W25P16",
+ },
+ {
+ .id = 0x2016,
+ .nr_blocks = 64,
+ .name = "W25P32",
+ },
+ {
.id = 0x3013,
.nr_blocks = 8,
.name = "W25X40",
@@ -40,42 +55,57 @@
{
.id = 0x4014,
.nr_blocks = 16,
- .name = "W25Q80BL",
+ .name = "W25Q80BL/W25Q80BV",
},
{
.id = 0x4015,
.nr_blocks = 32,
- .name = "W25Q16",
+ .name = "W25Q16CL/W25Q16DV",
},
{
.id = 0x4016,
.nr_blocks = 64,
- .name = "W25Q32",
+ .name = "W25Q32BV/W25Q32FV_SPI",
},
{
.id = 0x4017,
.nr_blocks = 128,
- .name = "W25Q64",
+ .name = "W25Q64CV/W25Q64FV_SPI",
},
{
.id = 0x4018,
.nr_blocks = 256,
- .name = "W25Q128",
+ .name = "W25Q128BV/W25Q128FV_SPI",
+ },
+ {
+ .id = 0x4019,
+ .nr_blocks = 512,
+ .name = "W25Q256",
},
{
.id = 0x5014,
- .nr_blocks = 128,
- .name = "W25Q80",
+ .nr_blocks = 16,
+ .name = "W25Q80BW",
+ },
+ {
+ .id = 0x6015,
+ .nr_blocks = 32,
+ .name = "W25Q16DW",
},
{
.id = 0x6016,
- .nr_blocks = 512,
- .name = "W25Q32DW",
+ .nr_blocks = 64,
+ .name = "W25Q32DW/W25Q32FV_QPI",
},
{
.id = 0x6017,
.nr_blocks = 128,
- .name = "W25Q64DW",
+ .name = "W25Q64DW/W25Q64FV_QPI",
+ },
+ {
+ .id = 0x6018,
+ .nr_blocks = 256,
+ .name = "W25Q128FW/W25Q128FV_QPI",
},
};
@@ -104,7 +134,7 @@
}
flash->page_size = 256;
- flash->sector_size = 4096;
+ flash->sector_size = (idcode[1] == 0x20) ? 65536 : 4096;
flash->size = 4096 * 16 * params->nr_blocks;
return flash;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4dbcdca..da95e28 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -516,9 +516,7 @@
#ifdef FEC_QUIRK_ENET_MAC
{
u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
- u32 rcr = (readl(&fec->eth->r_cntrl) &
- ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
- FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+ u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
if (speed == _1000BASET)
ecr |= FEC_ECNTRL_SPEED;
else if (speed != _100BASET)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 77ac1f7..621c899 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -211,7 +211,7 @@
return 1;
}
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
static void fsl_pcie_boot_master(pit_t *pi)
{
/* configure inbound window for slave's u-boot image */
@@ -388,7 +388,7 @@
/* see if we are a PCIe or PCI controller */
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
/* boot from PCIE --master */
char *s = getenv("bootmaster");
char pcie[6];
@@ -624,7 +624,7 @@
if (fsl_is_pci_agent(hose)) {
fsl_pci_config_unlock(hose);
hose->last_busno = hose->first_busno;
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
} else {
/* boot from PCIE --master releases slave's core 0 */
char *s = getenv("bootmaster");
diff --git a/drivers/power/exynos-tmu.c b/drivers/power/exynos-tmu.c
index d4b3e65..9a093a5 100644
--- a/drivers/power/exynos-tmu.c
+++ b/drivers/power/exynos-tmu.c
@@ -50,15 +50,15 @@
/* Tmeperature threshold values for various thermal events */
struct temperature_params {
/* minimum value in temperature code range */
- unsigned int min_val;
+ unsigned min_val;
/* maximum value in temperature code range */
- unsigned int max_val;
+ unsigned max_val;
/* temperature threshold to start warning */
- unsigned int start_warning;
+ unsigned start_warning;
/* temperature threshold CPU tripping */
- unsigned int start_tripping;
+ unsigned start_tripping;
/* temperature threshold for HW tripping */
- unsigned int hardware_tripping;
+ unsigned hardware_tripping;
};
/* Pre-defined values and thresholds for calibration of current temperature */
@@ -66,25 +66,27 @@
/* pre-defined temperature thresholds */
struct temperature_params ts;
/* pre-defined efuse range minimum value */
- unsigned int efuse_min_value;
+ unsigned efuse_min_value;
/* pre-defined efuse value for temperature calibration */
- unsigned int efuse_value;
+ unsigned efuse_value;
/* pre-defined efuse range maximum value */
- unsigned int efuse_max_value;
+ unsigned efuse_max_value;
/* current temperature sensing slope */
- unsigned int slope;
+ unsigned slope;
};
/* TMU device specific details and status */
struct tmu_info {
/* base Address for the TMU */
- unsigned tmu_base;
+ struct exynos5_tmu_reg *tmu_base;
+ /* mux Address for the TMU */
+ int tmu_mux;
/* pre-defined values for calibration and thresholds */
struct tmu_data data;
/* value required for triminfo_25 calibration */
- unsigned int te1;
+ unsigned te1;
/* value required for triminfo_85 calibration */
- unsigned int te2;
+ unsigned te2;
/* Value for measured data calibration */
int dc_value;
/* enum value indicating status of the TMU */
@@ -103,17 +105,24 @@
*/
static int get_cur_temp(struct tmu_info *info)
{
- int cur_temp;
- struct exynos5_tmu_reg *reg = (struct exynos5_tmu_reg *)info->tmu_base;
+ struct exynos5_tmu_reg *reg = info->tmu_base;
+ ulong start;
+ int cur_temp = 0;
/*
* Temperature code range between min 25 and max 125.
* May run more than once for first call as initial sensing
* has not yet happened.
*/
- do {
- cur_temp = readl(®->current_temp) & 0xff;
- } while (cur_temp == 0 && info->tmu_state == TMU_STATUS_NORMAL);
+ if (info->tmu_state == TMU_STATUS_NORMAL) {
+ start = get_timer(0);
+ do {
+ cur_temp = readl(®->current_temp) & 0xff;
+ } while ((cur_temp == 0) || (get_timer(start) > 100));
+ }
+
+ if (cur_temp == 0)
+ return cur_temp;
/* Calibrate current temperature */
cur_temp = cur_temp - info->te1 + info->dc_value;
@@ -137,23 +146,29 @@
/* Read current temperature of the SOC */
cur_temp = get_cur_temp(&gbl_info);
+
+ if (!cur_temp)
+ goto out;
+
*temp = cur_temp;
/* Temperature code lies between min 25 and max 125 */
- if (cur_temp >= data->ts.start_tripping &&
- cur_temp <= data->ts.max_val) {
+ if ((cur_temp >= data->ts.start_tripping) &&
+ (cur_temp <= data->ts.max_val))
return TMU_STATUS_TRIPPED;
- } else if (cur_temp >= data->ts.start_warning) {
+
+ if (cur_temp >= data->ts.start_warning)
return TMU_STATUS_WARNING;
- } else if (cur_temp < data->ts.start_warning &&
- cur_temp >= data->ts.min_val) {
+
+ if ((cur_temp < data->ts.start_warning) &&
+ (cur_temp >= data->ts.min_val))
return TMU_STATUS_NORMAL;
- } else {
- /* Temperature code does not lie between min 25 and max 125 */
- gbl_info.tmu_state = TMU_STATUS_INIT;
- debug("EXYNOS_TMU: Thermal reading failed\n");
- return TMU_STATUS_INIT;
- }
+
+ out:
+ /* Temperature code does not lie between min 25 and max 125 */
+ gbl_info.tmu_state = TMU_STATUS_INIT;
+ debug("EXYNOS_TMU: Thermal reading failed\n");
+ return TMU_STATUS_INIT;
}
/*
@@ -166,6 +181,7 @@
static int get_tmu_fdt_values(struct tmu_info *info, const void *blob)
{
#ifdef CONFIG_OF_CONTROL
+ fdt_addr_t addr;
int node;
int error = 0;
@@ -183,46 +199,58 @@
* miscalculation of register values in tmu_setup_parameters
* may result in misleading current temperature.
*/
- info->tmu_base = fdtdec_get_addr(blob, node, "reg");
- if (info->tmu_base == FDT_ADDR_T_NONE) {
+ addr = fdtdec_get_addr(blob, node, "reg");
+ if (addr == FDT_ADDR_T_NONE) {
debug("%s: Missing tmu-base\n", __func__);
return -1;
}
+ info->tmu_base = (struct exynos5_tmu_reg *)addr;
+
+ /* Optional field. */
+ info->tmu_mux = fdtdec_get_int(blob,
+ node, "samsung,mux", -1);
+ /* Take default value as per the user manual b(110) */
+ if (info->tmu_mux == -1)
+ info->tmu_mux = 0x6;
+
info->data.ts.min_val = fdtdec_get_int(blob,
node, "samsung,min-temp", -1);
- error |= info->data.ts.min_val;
+ error |= (info->data.ts.min_val == -1);
info->data.ts.max_val = fdtdec_get_int(blob,
node, "samsung,max-temp", -1);
- error |= info->data.ts.max_val;
+ error |= (info->data.ts.max_val == -1);
info->data.ts.start_warning = fdtdec_get_int(blob,
node, "samsung,start-warning", -1);
- error |= info->data.ts.start_warning;
+ error |= (info->data.ts.start_warning == -1);
info->data.ts.start_tripping = fdtdec_get_int(blob,
node, "samsung,start-tripping", -1);
- error |= info->data.ts.start_tripping;
+ error |= (info->data.ts.start_tripping == -1);
info->data.ts.hardware_tripping = fdtdec_get_int(blob,
node, "samsung,hw-tripping", -1);
- error |= info->data.ts.hardware_tripping;
+ error |= (info->data.ts.hardware_tripping == -1);
info->data.efuse_min_value = fdtdec_get_int(blob,
node, "samsung,efuse-min-value", -1);
- error |= info->data.efuse_min_value;
+ error |= (info->data.efuse_min_value == -1);
info->data.efuse_value = fdtdec_get_int(blob,
node, "samsung,efuse-value", -1);
- error |= info->data.efuse_value;
+ error |= (info->data.efuse_value == -1);
info->data.efuse_max_value = fdtdec_get_int(blob,
node, "samsung,efuse-max-value", -1);
- error |= info->data.efuse_max_value;
+ error |= (info->data.efuse_max_value == -1);
info->data.slope = fdtdec_get_int(blob,
node, "samsung,slope", -1);
- error |= info->data.slope;
+ error |= (info->data.slope == -1);
info->dc_value = fdtdec_get_int(blob,
node, "samsung,dc-value", -1);
- error |= info->dc_value;
+ error |= (info->dc_value == -1);
- if (error == -1) {
+ if (error) {
debug("fail to get tmu node properties\n");
return -1;
}
+#else
+ /* Non DT support may never be added. Just in case */
+ return -1;
#endif
return 0;
@@ -236,12 +264,12 @@
*/
static void tmu_setup_parameters(struct tmu_info *info)
{
- unsigned int te_code, con;
- unsigned int warning_code, trip_code, hwtrip_code;
- unsigned int cooling_temp;
- unsigned int rising_value;
+ unsigned te_code, con;
+ unsigned warning_code, trip_code, hwtrip_code;
+ unsigned cooling_temp;
+ unsigned rising_value;
struct tmu_data *data = &info->data;
- struct exynos5_tmu_reg *reg = (struct exynos5_tmu_reg *)info->tmu_base;
+ struct exynos5_tmu_reg *reg = info->tmu_base;
/* Must reload for reading efuse value from triminfo register */
writel(TRIMINFO_RELOAD, ®->triminfo_control);
@@ -288,7 +316,7 @@
/* TMU core enable */
con = readl(®->tmu_control);
- con |= THERM_TRIP_EN | CORE_EN;
+ con |= THERM_TRIP_EN | CORE_EN | (info->tmu_mux << 20);
writel(con, ®->tmu_control);
@@ -314,6 +342,5 @@
tmu_setup_parameters(&gbl_info);
gbl_info.tmu_state = TMU_STATUS_NORMAL;
ret:
-
return gbl_info.tmu_state;
}
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
index 09c832d..2d275a7 100644
--- a/drivers/power/palmas.c
+++ b/drivers/power/palmas.c
@@ -25,28 +25,137 @@
void palmas_init_settings(void)
{
- return;
+#ifdef CONFIG_PALMAS_SMPS7_FPWM
+ int err;
+ /*
+ * Set SMPS7 (1.8 V I/O supply on platforms with TWL6035/37) to
+ * forced PWM mode. This reduces noise (but affects efficiency).
+ */
+ u8 val = SMPS_MODE_SLP_FPWM | SMPS_MODE_ACT_FPWM;
+ err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS7_CTRL, val);
+ if (err)
+ printf("palmas: could not force PWM for SMPS7: err = %d\n",
+ err);
+#endif
}
int palmas_mmc1_poweron_ldo(void)
{
u8 val = 0;
- /* set LDO9 TWL6035 to 3V */
- val = 0x2b; /* (3 -.9)*28 +1 */
-
- if (palmas_i2c_write_u8(0x48, LDO9_VOLTAGE, val)) {
- printf("twl6035: could not set LDO9 voltage.\n");
+#if defined(CONFIG_DRA7XX)
+ /*
+ * Currently valid for the dra7xx_evm board:
+ * Set TPS659038 LDO1 to 3.0 V
+ */
+ val = LDO_VOLT_3V0;
+ if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, val)) {
+ printf("tps65903x: could not set LDO1 voltage.\n");
return 1;
}
-
- /* TURN ON LDO9 */
- val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
-
- if (palmas_i2c_write_u8(0x48, LDO9_CTRL, val)) {
- printf("twl6035: could not turn on LDO9.\n");
+ /* TURN ON LDO1 */
+ val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
+ if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val)) {
+ printf("tps65903x: could not turn on LDO1.\n");
return 1;
}
-
return 0;
+#else
+ /*
+ * We assume that this is a OMAP543X + TWL603X board:
+ * Set TWL6035/37 LDO9 to 3.0 V
+ */
+ val = LDO_VOLT_3V0;
+ return twl603x_mmc1_set_ldo9(val);
+#endif
+}
+
+/*
+ * On some OMAP5 + TWL603X hardware the SD card socket and LDO9_IN are
+ * powered by an external 3.3 V regulator, while the output of LDO9
+ * supplies VDDS_SDCARD for the OMAP5 interface only. This implies that
+ * LDO9 could be set to 'bypass' mode when required (e.g. for 3.3 V cards).
+ */
+int twl603x_mmc1_set_ldo9(u8 vsel)
+{
+ u8 cval = 0, vval = 0; /* Off by default */
+ int err;
+
+ if (vsel) {
+ /* Turn on */
+ if (vsel > LDO_VOLT_3V3) {
+ /* Put LDO9 in bypass */
+ cval = LDO9_BYP_EN | RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
+ vval = LDO_VOLT_3V3;
+ } else {
+ cval = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
+ vval = vsel & 0x3f;
+ }
+ }
+ err = palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_VOLTAGE, vval);
+ if (err) {
+ printf("twl603x: could not set LDO9 %s: err = %d\n",
+ vsel > LDO_VOLT_3V3 ? "bypass" : "voltage", err);
+ return err;
+ }
+ err = palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_CTRL, cval);
+ if (err)
+ printf("twl603x: could not turn %s LDO9: err = %d\n",
+ cval ? "on" : "off", err);
+ return err;
+}
+
+#ifdef CONFIG_PALMAS_AUDPWR
+/*
+ * Turn audio codec power and 32 kHz clock on/off. Use for
+ * testing OMAP543X + TWL603X + TWL604X boards only.
+ */
+int twl603x_audio_power(u8 on)
+{
+ u8 cval = 0, vval = 0, c32k = 0;
+ int err;
+
+ if (on) {
+ vval = SMPS_VOLT_2V1;
+ cval = SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO;
+ c32k = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
+ }
+ /* Set SMPS9 to 2.1 V (for TWL604x), or to 0 (off) */
+ err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS9_VOLTAGE, vval);
+ if (err) {
+ printf("twl603x: could not set SMPS9 voltage: err = %d\n",
+ err);
+ return err;
+ }
+ /* Turn on or off SMPS9 */
+ err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS9_CTRL, cval);
+ if (err) {
+ printf("twl603x: could not turn SMPS9 %s: err = %d\n",
+ cval ? "on" : "off", err);
+ return err;
+ }
+ /* Output 32 kHz clock on or off */
+ err = palmas_i2c_write_u8(TWL603X_CHIP_P1, CLK32KGAUDIO_CTRL, c32k);
+ if (err)
+ printf("twl603x: could not turn CLK32KGAUDIO %s: err = %d\n",
+ c32k ? "on" : "off", err);
+ return err;
+}
+#endif
+
+/*
+ * Enable/disable back-up battery (or super cap) charging on TWL6035/37.
+ * Please use defined BB_xxx values.
+ */
+int twl603x_enable_bb_charge(u8 bb_fields)
+{
+ u8 val = bb_fields & 0x0f;
+ int err;
+
+ val |= (VRTC_EN_SLP | VRTC_EN_OFF | VRTC_PWEN);
+ err = palmas_i2c_write_u8(TWL603X_CHIP_P1, BB_VRTC_CTRL, val);
+ if (err)
+ printf("twl603x: could not set BB_VRTC_CTRL to 0x%02x: err = %d\n",
+ val, err);
+ return err;
}
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 442b7ea..0f954a5 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -53,6 +53,7 @@
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
+COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 7f013ab..d77c25f 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -74,13 +74,8 @@
defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
defined(CONFIG_TI814X)
-#if defined(CONFIG_APTIX)
- /* /13 mode so Aptix 6MHz can hit 115200 */
- serial_out(3, &com_port->mdr1);
-#else
/* /16 is proper to hit 115200 with 48MHz */
serial_out(0, &com_port->mdr1);
-#endif
#endif /* CONFIG_OMAP */
}
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
new file mode 100644
index 0000000..51d5666
--- /dev/null
+++ b/drivers/serial/serial_lpuart.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#define US1_TDRE (1 << 7)
+#define US1_RDRF (1 << 5)
+#define UC2_TE (1 << 3)
+#define UC2_RE (1 << 2)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
+
+static void lpuart_serial_setbrg(void)
+{
+ u32 clk = mxc_get_clock(MXC_UART_CLK);
+ u16 sbr;
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ sbr = (u16)(clk / (16 * gd->baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ __raw_writeb(sbr >> 8, &base->ubdh);
+ __raw_writeb(sbr & 0xff, &base->ubdl);
+}
+
+static int lpuart_serial_getc(void)
+{
+ u8 status;
+
+ while (!(__raw_readb(&base->us1) & US1_RDRF))
+ WATCHDOG_RESET();
+
+ status = __raw_readb(&base->us1);
+ status |= US1_RDRF;
+ __raw_writeb(status, &base->us1);
+
+ return __raw_readb(&base->ud);
+}
+
+static void lpuart_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(__raw_readb(&base->us1) & US1_TDRE))
+ WATCHDOG_RESET();
+
+ __raw_writeb(c, &base->ud);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart_serial_tstc(void)
+{
+ if (__raw_readb(&base->urcfifo) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart_serial_init(void)
+{
+ u8 ctrl;
+
+ ctrl = __raw_readb(&base->uc2);
+ ctrl &= ~UC2_RE;
+ ctrl &= ~UC2_TE;
+ __raw_writeb(ctrl, &base->uc2);
+
+ __raw_writeb(0, &base->umodem);
+ __raw_writeb(0, &base->uc1);
+
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
+
+ return 0;
+}
+
+static struct serial_device lpuart_serial_drv = {
+ .name = "lpuart_serial",
+ .start = lpuart_serial_init,
+ .stop = NULL,
+ .setbrg = lpuart_serial_setbrg,
+ .putc = lpuart_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpuart_serial_getc,
+ .tstc = lpuart_serial_tstc,
+};
+
+void lpuart_serial_initialize(void)
+{
+ serial_register(&lpuart_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &lpuart_serial_drv;
+}
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index b92eef4..3c07da3 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -151,12 +151,7 @@
}
#endif
-#ifdef CONFIG_APTIX
-#define MODE_X_DIV 13
-#else
#define MODE_X_DIV 16
-#endif
-
/* Compute divisor value. Normally, we should simply return:
* CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
* but we need to round that value by adding 0.5.
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 3c41242..e65125c 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -30,6 +30,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#define RX_FIFO_COUNT_MASK 0xff
+#define RX_FIFO_FULL_MASK (1 << 8)
+#define TX_FIFO_FULL_MASK (1 << 24)
+
static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
{
u32 offset = dev_index * sizeof(struct s5p_uart);
@@ -87,8 +91,8 @@
{
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
- /* reset and enable FIFOs, set triggers to the maximum */
- writel(0, &uart->ufcon);
+ /* enable FIFOs */
+ writel(0x1, &uart->ufcon);
writel(0, &uart->umcon);
/* 8N1 */
writel(0x3, &uart->ulcon);
@@ -130,7 +134,8 @@
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
/* wait for character to arrive */
- while (!(readl(&uart->utrstat) & 0x1)) {
+ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
+ RX_FIFO_FULL_MASK))) {
if (serial_err_check(dev_index, 0))
return 0;
}
@@ -146,7 +151,7 @@
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
/* wait for room in the tx FIFO */
- while (!(readl(&uart->utrstat) & 0x2)) {
+ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
if (serial_err_check(dev_index, 1))
return;
}
diff --git a/drivers/spi/armada100_spi.c b/drivers/spi/armada100_spi.c
index afdbe05..b237c7c 100644
--- a/drivers/spi/armada100_spi.c
+++ b/drivers/spi/armada100_spi.c
@@ -182,15 +182,8 @@
goto done;
}
- if (dout)
- pss->tx = dout;
- else
- pss->tx = NULL;
-
- if (din)
- pss->rx = din;
- else
- pss->rx = NULL;
+ pss->tx = dout;
+ pss->rx = din;
if (flags & SPI_XFER_BEGIN) {
spi_cs_activate(slave);
diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c
index a37ac4e..06bcf91 100644
--- a/drivers/spi/cf_qspi.c
+++ b/drivers/spi/cf_qspi.c
@@ -171,7 +171,7 @@
volatile qspi_t *qspi = dev->regs;
u8 *txbuf = (u8 *)dout;
u8 *rxbuf = (u8 *)din;
- u32 count = ((bitlen / 8) + (bitlen % 8 ? 1 : 0));
+ u32 count = DIV_ROUND_UP(bitlen, 8);
u32 n, i = 0;
/* Sanitize arguments */
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 607e1cd..01378d0 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -51,6 +51,7 @@
unsigned int mode;
enum periph_id periph_id; /* Peripheral ID for this device */
unsigned int fifo_size;
+ int skip_preamble;
};
static struct spi_bus *spi_get_bus(unsigned dev_index)
@@ -105,6 +106,8 @@
else
spi_slave->fifo_size = 256;
+ spi_slave->skip_preamble = 0;
+
spi_slave->freq = bus->frequency;
if (max_hz)
spi_slave->freq = min(max_hz, spi_slave->freq);
@@ -217,17 +220,23 @@
writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
}
-static void spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
- void **dinp, void const **doutp)
+static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
+ void **dinp, void const **doutp, unsigned long flags)
{
struct exynos_spi *regs = spi_slave->regs;
uchar *rxp = *dinp;
const uchar *txp = *doutp;
int rx_lvl, tx_lvl;
uint out_bytes, in_bytes;
+ int toread;
+ unsigned start = get_timer(0);
+ int stopping;
out_bytes = in_bytes = todo;
+ stopping = spi_slave->skip_preamble && (flags & SPI_XFER_END) &&
+ !(spi_slave->mode & SPI_SLAVE);
+
/*
* If there's something to send, do a software reset and set a
* transaction size.
@@ -238,6 +247,8 @@
* Bytes are transmitted/received in pairs. Wait to receive all the
* data because then transmission will be done as well.
*/
+ toread = in_bytes;
+
while (in_bytes) {
int temp;
@@ -248,15 +259,43 @@
writel(temp, ®s->tx_data);
out_bytes--;
}
- if (rx_lvl > 0 && in_bytes) {
+ if (rx_lvl > 0) {
temp = readl(®s->rx_data);
- if (rxp)
- *rxp++ = temp;
- in_bytes--;
+ if (spi_slave->skip_preamble) {
+ if (temp == SPI_PREAMBLE_END_BYTE) {
+ spi_slave->skip_preamble = 0;
+ stopping = 0;
+ }
+ } else {
+ if (rxp || stopping)
+ *rxp++ = temp;
+ in_bytes--;
+ }
+ toread--;
+ } else if (!toread) {
+ /*
+ * We have run out of input data, but haven't read
+ * enough bytes after the preamble yet. Read some more,
+ * and make sure that we transmit dummy bytes too, to
+ * keep things going.
+ */
+ assert(!out_bytes);
+ out_bytes = in_bytes;
+ toread = in_bytes;
+ txp = NULL;
+ spi_request_bytes(regs, toread);
+ }
+ if (spi_slave->skip_preamble && get_timer(start) > 100) {
+ printf("SPI timeout: in_bytes=%d, out_bytes=%d, ",
+ in_bytes, out_bytes);
+ return -1;
}
}
+
*dinp = rxp;
*doutp = txp;
+
+ return 0;
}
/**
@@ -276,6 +315,7 @@
struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
int upto, todo;
int bytelen;
+ int ret = 0;
/* spi core configured to do 8 bit transfers */
if (bitlen % 8) {
@@ -289,16 +329,24 @@
/* Exynos SPI limits each transfer to 65535 bytes */
bytelen = bitlen / 8;
- for (upto = 0; upto < bytelen; upto += todo) {
+ for (upto = 0; !ret && upto < bytelen; upto += todo) {
todo = min(bytelen - upto, (1 << 16) - 1);
- spi_rx_tx(spi_slave, todo, &din, &dout);
+ ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags);
+ if (ret)
+ break;
}
/* Stop the transaction, if necessary. */
- if ((flags & SPI_XFER_END))
+ if ((flags & SPI_XFER_END) && !(spi_slave->mode & SPI_SLAVE)) {
spi_cs_deactivate(slave);
+ if (spi_slave->skip_preamble) {
+ assert(!spi_slave->skip_preamble);
+ debug("Failed to complete premable transaction\n");
+ ret = -1;
+ }
+ }
- return 0;
+ return ret;
}
/**
@@ -325,6 +373,7 @@
clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
debug("Activate CS, bus %d\n", spi_slave->slave.bus);
+ spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
}
/**
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 5bed858..2ea3228 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -224,7 +224,7 @@
const u8 *dout, u8 *din, unsigned long flags)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
- int nbytes = (bitlen + 7) / 8;
+ int nbytes = DIV_ROUND_UP(bitlen, 8);
u32 data, cnt, i;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
@@ -294,7 +294,7 @@
/* Transfer completed, clear any pending request */
reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
- nbytes = (bitlen + 7) / 8;
+ nbytes = DIV_ROUND_UP(bitlen, 8);
cnt = nbytes % 32;
@@ -330,7 +330,7 @@
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
- int n_bytes = (bitlen + 7) / 8;
+ int n_bytes = DIV_ROUND_UP(bitlen, 8);
int n_bits;
int ret;
u32 blk_size;
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index b11a0a1..4d2af48 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -152,13 +152,11 @@
return NULL;
}
- spi = malloc(sizeof(struct tegra_spi_slave));
+ spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
if (!spi) {
printf("SPI error: malloc of SPI structure failed\n");
return NULL;
}
- spi->slave.bus = bus;
- spi->slave.cs = cs;
spi->ctrl = &spi_ctrls[bus];
if (!spi->ctrl) {
printf("SPI error: could not find controller for bus %d\n",
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 9322ce7..7c3a3fc 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -132,8 +132,6 @@
printf("SPI error: malloc of SPI structure failed\n");
return NULL;
}
- spi->slave.bus = bus;
- spi->slave.cs = cs;
spi->ctrl = &spi_ctrls[bus];
if (!spi->ctrl) {
printf("SPI error: could not find controller for bus %d\n",
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index 75ec8f7..76624b9 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -407,6 +407,25 @@
rx_ctl = asix_read_rx_ctl(dev);
debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
+ dev->phy_id = asix_get_phy_addr(dev);
+ if (dev->phy_id < 0)
+ debug("Failed to read phy id\n");
+
+ asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
+ asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_CSMA);
+ mii_nway_restart(dev);
+
+ if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
+ return -1;
+
+ if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
+ AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
+ AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
+ debug("Write IPG,IPG1,IPG2 failed\n");
+ return -1;
+ }
+
return 0;
}
@@ -422,31 +441,6 @@
debug("** %s()\n", __func__);
- dev->phy_id = asix_get_phy_addr(dev);
- if (dev->phy_id < 0)
- debug("Failed to read phy id\n");
-
- if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0)
- goto out_err;
-
- if (asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL) < 0)
- goto out_err;
-
- asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
- asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
- ADVERTISE_ALL | ADVERTISE_CSMA);
- mii_nway_restart(dev);
-
- if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
- goto out_err;
-
- if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
- AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
- AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
- debug("Write IPG,IPG1,IPG2 failed\n");
- goto out_err;
- }
-
if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
goto out_err;
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index e545b6b..432cf17 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -35,6 +35,7 @@
# new USB gadget layer dependencies
ifdef CONFIG_USB_GADGET
COBJS-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
+COBJS-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
COBJS-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
COBJS-$(CONFIG_DFU_FUNCTION) += f_dfu.o
endif
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 2c5600e..f30778a 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -1098,4 +1098,5 @@
if (composite != driver)
return;
usb_gadget_unregister_driver(&composite_driver);
+ composite = NULL;
}
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index c28866f..45bc132 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -2261,7 +2261,8 @@
if (rc)
goto reset;
fsg->bulk_out_enabled = 1;
- common->bulk_out_maxpacket = le16_to_cpu(d->wMaxPacketSize);
+ common->bulk_out_maxpacket =
+ le16_to_cpu(get_unaligned(&d->wMaxPacketSize));
clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
/* Allocate the requests */
diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c
new file mode 100644
index 0000000..d003331
--- /dev/null
+++ b/drivers/usb/gadget/fotg210.c
@@ -0,0 +1,948 @@
+/*
+ * Faraday USB 2.0 OTG Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <net.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include <usb/fotg210.h>
+
+#define CFG_NUM_ENDPOINTS 4
+#define CFG_EP0_MAX_PACKET_SIZE 64
+#define CFG_EPX_MAX_PACKET_SIZE 512
+
+#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
+
+struct fotg210_chip;
+
+struct fotg210_ep {
+ struct usb_ep ep;
+
+ uint maxpacket;
+ uint id;
+ uint stopped;
+
+ struct list_head queue;
+ struct fotg210_chip *chip;
+ const struct usb_endpoint_descriptor *desc;
+};
+
+struct fotg210_request {
+ struct usb_request req;
+ struct list_head queue;
+ struct fotg210_ep *ep;
+};
+
+struct fotg210_chip {
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ struct fotg210_regs *regs;
+ uint8_t irq;
+ uint16_t addr;
+ int pullup;
+ enum usb_device_state state;
+ struct fotg210_ep ep[1 + CFG_NUM_ENDPOINTS];
+};
+
+static struct usb_endpoint_descriptor ep0_desc = {
+ .bLength = sizeof(struct usb_endpoint_descriptor),
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
+};
+
+static inline int fifo_to_ep(struct fotg210_chip *chip, int id, int in)
+{
+ return (id < 0) ? 0 : ((id & 0x03) + 1);
+}
+
+static inline int ep_to_fifo(struct fotg210_chip *chip, int id)
+{
+ return (id <= 0) ? -1 : ((id - 1) & 0x03);
+}
+
+static inline int ep_reset(struct fotg210_chip *chip, uint8_t ep_addr)
+{
+ int ep = ep_addr & USB_ENDPOINT_NUMBER_MASK;
+ struct fotg210_regs *regs = chip->regs;
+
+ if (ep_addr & USB_DIR_IN) {
+ /* reset endpoint */
+ setbits_le32(®s->iep[ep - 1], IEP_RESET);
+ mdelay(1);
+ clrbits_le32(®s->iep[ep - 1], IEP_RESET);
+ /* clear endpoint stall */
+ clrbits_le32(®s->iep[ep - 1], IEP_STALL);
+ } else {
+ /* reset endpoint */
+ setbits_le32(®s->oep[ep - 1], OEP_RESET);
+ mdelay(1);
+ clrbits_le32(®s->oep[ep - 1], OEP_RESET);
+ /* clear endpoint stall */
+ clrbits_le32(®s->oep[ep - 1], OEP_STALL);
+ }
+
+ return 0;
+}
+
+static int fotg210_reset(struct fotg210_chip *chip)
+{
+ struct fotg210_regs *regs = chip->regs;
+ uint32_t i;
+
+ chip->state = USB_STATE_POWERED;
+
+ /* chip enable */
+ writel(DEVCTRL_EN, ®s->dev_ctrl);
+
+ /* device address reset */
+ chip->addr = 0;
+ writel(0, ®s->dev_addr);
+
+ /* set idle counter to 7ms */
+ writel(7, ®s->idle);
+
+ /* disable all interrupts */
+ writel(IMR_MASK, ®s->imr);
+ writel(GIMR_MASK, ®s->gimr);
+ writel(GIMR0_MASK, ®s->gimr0);
+ writel(GIMR1_MASK, ®s->gimr1);
+ writel(GIMR2_MASK, ®s->gimr2);
+
+ /* clear interrupts */
+ writel(ISR_MASK, ®s->isr);
+ writel(0, ®s->gisr);
+ writel(0, ®s->gisr0);
+ writel(0, ®s->gisr1);
+ writel(0, ®s->gisr2);
+
+ /* chip reset */
+ setbits_le32(®s->dev_ctrl, DEVCTRL_RESET);
+ mdelay(10);
+ if (readl(®s->dev_ctrl) & DEVCTRL_RESET) {
+ printf("fotg210: chip reset failed\n");
+ return -1;
+ }
+
+ /* CX FIFO reset */
+ setbits_le32(®s->cxfifo, CXFIFO_CXFIFOCLR);
+ mdelay(10);
+ if (readl(®s->cxfifo) & CXFIFO_CXFIFOCLR) {
+ printf("fotg210: ep0 fifo reset failed\n");
+ return -1;
+ }
+
+ /* create static ep-fifo map (EP1 <-> FIFO0, EP2 <-> FIFO1 ...) */
+ writel(EPMAP14_DEFAULT, ®s->epmap14);
+ writel(EPMAP58_DEFAULT, ®s->epmap58);
+ writel(FIFOMAP_DEFAULT, ®s->fifomap);
+ writel(0, ®s->fifocfg);
+ for (i = 0; i < 8; ++i) {
+ writel(CFG_EPX_MAX_PACKET_SIZE, ®s->iep[i]);
+ writel(CFG_EPX_MAX_PACKET_SIZE, ®s->oep[i]);
+ }
+
+ /* FIFO reset */
+ for (i = 0; i < 4; ++i) {
+ writel(FIFOCSR_RESET, ®s->fifocsr[i]);
+ mdelay(10);
+ if (readl(®s->fifocsr[i]) & FIFOCSR_RESET) {
+ printf("fotg210: fifo%d reset failed\n", i);
+ return -1;
+ }
+ }
+
+ /* enable only device interrupt and triggered at level-high */
+ writel(IMR_IRQLH | IMR_HOST | IMR_OTG, ®s->imr);
+ writel(ISR_MASK, ®s->isr);
+ /* disable EP0 IN/OUT interrupt */
+ writel(GIMR0_CXOUT | GIMR0_CXIN, ®s->gimr0);
+ /* disable EPX IN+SPK+OUT interrupts */
+ writel(GIMR1_MASK, ®s->gimr1);
+ /* disable wakeup+idle+dma+zlp interrupts */
+ writel(GIMR2_WAKEUP | GIMR2_IDLE | GIMR2_DMAERR | GIMR2_DMAFIN
+ | GIMR2_ZLPRX | GIMR2_ZLPTX, ®s->gimr2);
+ /* enable all group interrupt */
+ writel(0, ®s->gimr);
+
+ /* suspend delay = 3 ms */
+ writel(3, ®s->idle);
+
+ /* turn-on device interrupts */
+ setbits_le32(®s->dev_ctrl, DEVCTRL_GIRQ_EN);
+
+ return 0;
+}
+
+static inline int fotg210_cxwait(struct fotg210_chip *chip, uint32_t mask)
+{
+ struct fotg210_regs *regs = chip->regs;
+ int ret = -1;
+ ulong ts;
+
+ for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+ if ((readl(®s->cxfifo) & mask) != mask)
+ continue;
+ ret = 0;
+ break;
+ }
+
+ if (ret)
+ printf("fotg210: cx/ep0 timeout\n");
+
+ return ret;
+}
+
+static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req)
+{
+ struct fotg210_chip *chip = ep->chip;
+ struct fotg210_regs *regs = chip->regs;
+ uint32_t tmp, ts;
+ uint8_t *buf = req->req.buf + req->req.actual;
+ uint32_t len = req->req.length - req->req.actual;
+ int fifo = ep_to_fifo(chip, ep->id);
+ int ret = -EBUSY;
+
+ /* 1. init dma buffer */
+ if (len > ep->maxpacket)
+ len = ep->maxpacket;
+
+ /* 2. wait for dma ready (hardware) */
+ for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+ if (!(readl(®s->dma_ctrl) & DMACTRL_START)) {
+ ret = 0;
+ break;
+ }
+ }
+ if (ret) {
+ printf("fotg210: dma busy\n");
+ req->req.status = ret;
+ return ret;
+ }
+
+ /* 3. DMA target setup */
+ if (ep->desc->bEndpointAddress & USB_DIR_IN)
+ flush_dcache_range((ulong)buf, (ulong)buf + len);
+ else
+ invalidate_dcache_range((ulong)buf, (ulong)buf + len);
+
+ writel(virt_to_phys(buf), ®s->dma_addr);
+
+ if (ep->desc->bEndpointAddress & USB_DIR_IN) {
+ if (ep->id == 0) {
+ /* Wait until cx/ep0 fifo empty */
+ fotg210_cxwait(chip, CXFIFO_CXFIFOE);
+ writel(DMAFIFO_CX, ®s->dma_fifo);
+ } else {
+ /* Wait until epx fifo empty */
+ fotg210_cxwait(chip, CXFIFO_FIFOE(fifo));
+ writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo);
+ }
+ writel(DMACTRL_LEN(len) | DMACTRL_MEM2FIFO, ®s->dma_ctrl);
+ } else {
+ uint32_t blen;
+
+ if (ep->id == 0) {
+ writel(DMAFIFO_CX, ®s->dma_fifo);
+ do {
+ blen = CXFIFO_BYTES(readl(®s->cxfifo));
+ } while (blen < len);
+ } else {
+ writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo);
+ blen = FIFOCSR_BYTES(readl(®s->fifocsr[fifo]));
+ }
+ len = (len < blen) ? len : blen;
+ writel(DMACTRL_LEN(len) | DMACTRL_FIFO2MEM, ®s->dma_ctrl);
+ }
+
+ /* 4. DMA start */
+ setbits_le32(®s->dma_ctrl, DMACTRL_START);
+
+ /* 5. DMA wait */
+ ret = -EBUSY;
+ for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
+ tmp = readl(®s->gisr2);
+ /* DMA complete */
+ if (tmp & GISR2_DMAFIN) {
+ ret = 0;
+ break;
+ }
+ /* DMA error */
+ if (tmp & GISR2_DMAERR) {
+ printf("fotg210: dma error\n");
+ break;
+ }
+ /* resume, suspend, reset */
+ if (tmp & (GISR2_RESUME | GISR2_SUSPEND | GISR2_RESET)) {
+ printf("fotg210: dma reset by host\n");
+ break;
+ }
+ }
+
+ /* 7. DMA target reset */
+ if (ret)
+ writel(DMACTRL_ABORT | DMACTRL_CLRFF, ®s->dma_ctrl);
+
+ writel(0, ®s->gisr2);
+ writel(0, ®s->dma_fifo);
+
+ req->req.status = ret;
+ if (!ret)
+ req->req.actual += len;
+ else
+ printf("fotg210: ep%d dma error(code=%d)\n", ep->id, ret);
+
+ return len;
+}
+
+/*
+ * result of setup packet
+ */
+#define CX_IDLE 0
+#define CX_FINISH 1
+#define CX_STALL 2
+
+static void fotg210_setup(struct fotg210_chip *chip)
+{
+ int id, ret = CX_IDLE;
+ uint32_t tmp[2];
+ struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)tmp;
+ struct fotg210_regs *regs = chip->regs;
+
+ /*
+ * If this is the first Cx 8 byte command,
+ * we can now query USB mode (high/full speed; USB 2.0/USB 1.0)
+ */
+ if (chip->state == USB_STATE_POWERED) {
+ chip->state = USB_STATE_DEFAULT;
+ if (readl(®s->otgcsr) & OTGCSR_DEV_B) {
+ /* Mini-B */
+ if (readl(®s->dev_ctrl) & DEVCTRL_HS) {
+ puts("fotg210: HS\n");
+ chip->gadget.speed = USB_SPEED_HIGH;
+ /* SOF mask timer = 1100 ticks */
+ writel(SOFMTR_TMR(1100), ®s->sof_mtr);
+ } else {
+ puts("fotg210: FS\n");
+ chip->gadget.speed = USB_SPEED_FULL;
+ /* SOF mask timer = 10000 ticks */
+ writel(SOFMTR_TMR(10000), ®s->sof_mtr);
+ }
+ } else {
+ printf("fotg210: mini-A?\n");
+ }
+ }
+
+ /* switch data port to ep0 */
+ writel(DMAFIFO_CX, ®s->dma_fifo);
+ /* fetch 8 bytes setup packet */
+ tmp[0] = readl(®s->ep0_data);
+ tmp[1] = readl(®s->ep0_data);
+ /* release data port */
+ writel(0, ®s->dma_fifo);
+
+ if (req->bRequestType & USB_DIR_IN)
+ ep0_desc.bEndpointAddress = USB_DIR_IN;
+ else
+ ep0_desc.bEndpointAddress = USB_DIR_OUT;
+
+ ret = CX_IDLE;
+
+ if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
+ switch (req->bRequest) {
+ case USB_REQ_SET_CONFIGURATION:
+ debug("fotg210: set_cfg(%d)\n", req->wValue & 0x00FF);
+ if (!(req->wValue & 0x00FF)) {
+ chip->state = USB_STATE_ADDRESS;
+ writel(chip->addr, ®s->dev_addr);
+ } else {
+ chip->state = USB_STATE_CONFIGURED;
+ writel(chip->addr | DEVADDR_CONF,
+ ®s->dev_addr);
+ }
+ ret = CX_IDLE;
+ break;
+
+ case USB_REQ_SET_ADDRESS:
+ debug("fotg210: set_addr(0x%04X)\n", req->wValue);
+ chip->state = USB_STATE_ADDRESS;
+ chip->addr = req->wValue & DEVADDR_ADDR_MASK;
+ ret = CX_FINISH;
+ writel(chip->addr, ®s->dev_addr);
+ break;
+
+ case USB_REQ_CLEAR_FEATURE:
+ debug("fotg210: clr_feature(%d, %d)\n",
+ req->bRequestType & 0x03, req->wValue);
+ switch (req->wValue) {
+ case 0: /* [Endpoint] halt */
+ ep_reset(chip, req->wIndex);
+ ret = CX_FINISH;
+ break;
+ case 1: /* [Device] remote wake-up */
+ case 2: /* [Device] test mode */
+ default:
+ ret = CX_STALL;
+ break;
+ }
+ break;
+
+ case USB_REQ_SET_FEATURE:
+ debug("fotg210: set_feature(%d, %d)\n",
+ req->wValue, req->wIndex & 0xf);
+ switch (req->wValue) {
+ case 0: /* Endpoint Halt */
+ id = req->wIndex & 0xf;
+ setbits_le32(®s->iep[id - 1], IEP_STALL);
+ setbits_le32(®s->oep[id - 1], OEP_STALL);
+ ret = CX_FINISH;
+ break;
+ case 1: /* Remote Wakeup */
+ case 2: /* Test Mode */
+ default:
+ ret = CX_STALL;
+ break;
+ }
+ break;
+
+ case USB_REQ_GET_STATUS:
+ debug("fotg210: get_status\n");
+ ret = CX_STALL;
+ break;
+
+ case USB_REQ_SET_DESCRIPTOR:
+ debug("fotg210: set_descriptor\n");
+ ret = CX_STALL;
+ break;
+
+ case USB_REQ_SYNCH_FRAME:
+ debug("fotg210: sync frame\n");
+ ret = CX_STALL;
+ break;
+ }
+ } /* if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) */
+
+ if (ret == CX_IDLE && chip->driver->setup) {
+ if (chip->driver->setup(&chip->gadget, req) < 0)
+ ret = CX_STALL;
+ else
+ ret = CX_FINISH;
+ }
+
+ switch (ret) {
+ case CX_FINISH:
+ setbits_le32(®s->cxfifo, CXFIFO_CXFIN);
+ break;
+
+ case CX_STALL:
+ setbits_le32(®s->cxfifo, CXFIFO_CXSTALL | CXFIFO_CXFIN);
+ printf("fotg210: cx_stall!\n");
+ break;
+
+ case CX_IDLE:
+ debug("fotg210: cx_idle?\n");
+ default:
+ break;
+ }
+}
+
+/*
+ * fifo - FIFO id
+ * zlp - zero length packet
+ */
+static void fotg210_recv(struct fotg210_chip *chip, int ep_id)
+{
+ struct fotg210_regs *regs = chip->regs;
+ struct fotg210_ep *ep = chip->ep + ep_id;
+ struct fotg210_request *req;
+ int len;
+
+ if (ep->stopped || (ep->desc->bEndpointAddress & USB_DIR_IN)) {
+ printf("fotg210: ep%d recv, invalid!\n", ep->id);
+ return;
+ }
+
+ if (list_empty(&ep->queue)) {
+ printf("fotg210: ep%d recv, drop!\n", ep->id);
+ return;
+ }
+
+ req = list_first_entry(&ep->queue, struct fotg210_request, queue);
+ len = fotg210_dma(ep, req);
+ if (len < ep->ep.maxpacket || req->req.length <= req->req.actual) {
+ list_del_init(&req->queue);
+ if (req->req.complete)
+ req->req.complete(&ep->ep, &req->req);
+ }
+
+ if (ep->id > 0 && list_empty(&ep->queue)) {
+ setbits_le32(®s->gimr1,
+ GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id)));
+ }
+}
+
+/*
+ * USB Gadget Layer
+ */
+static int fotg210_ep_enable(
+ struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
+{
+ struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
+ struct fotg210_chip *chip = ep->chip;
+ struct fotg210_regs *regs = chip->regs;
+ int id = ep_to_fifo(chip, ep->id);
+ int in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0;
+
+ if (!_ep || !desc
+ || desc->bDescriptorType != USB_DT_ENDPOINT
+ || le16_to_cpu(desc->wMaxPacketSize) == 0) {
+ printf("fotg210: bad ep or descriptor\n");
+ return -EINVAL;
+ }
+
+ ep->desc = desc;
+ ep->stopped = 0;
+
+ if (in)
+ setbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_IN));
+
+ switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+ case USB_ENDPOINT_XFER_CONTROL:
+ return -EINVAL;
+
+ case USB_ENDPOINT_XFER_ISOC:
+ setbits_le32(®s->fifocfg,
+ FIFOCFG(id, FIFOCFG_EN | FIFOCFG_ISOC));
+ break;
+
+ case USB_ENDPOINT_XFER_BULK:
+ setbits_le32(®s->fifocfg,
+ FIFOCFG(id, FIFOCFG_EN | FIFOCFG_BULK));
+ break;
+
+ case USB_ENDPOINT_XFER_INT:
+ setbits_le32(®s->fifocfg,
+ FIFOCFG(id, FIFOCFG_EN | FIFOCFG_INTR));
+ break;
+ }
+
+ return 0;
+}
+
+static int fotg210_ep_disable(struct usb_ep *_ep)
+{
+ struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
+ struct fotg210_chip *chip = ep->chip;
+ struct fotg210_regs *regs = chip->regs;
+ int id = ep_to_fifo(chip, ep->id);
+
+ ep->desc = NULL;
+ ep->stopped = 1;
+
+ clrbits_le32(®s->fifocfg, FIFOCFG(id, FIFOCFG_CFG_MASK));
+ clrbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_DIR_MASK));
+
+ return 0;
+}
+
+static struct usb_request *fotg210_ep_alloc_request(
+ struct usb_ep *_ep, gfp_t gfp_flags)
+{
+ struct fotg210_request *req = malloc(sizeof(*req));
+
+ if (req) {
+ memset(req, 0, sizeof(*req));
+ INIT_LIST_HEAD(&req->queue);
+ }
+ return &req->req;
+}
+
+static void fotg210_ep_free_request(
+ struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct fotg210_request *req;
+
+ req = container_of(_req, struct fotg210_request, req);
+ free(req);
+}
+
+static int fotg210_ep_queue(
+ struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
+{
+ struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
+ struct fotg210_chip *chip = ep->chip;
+ struct fotg210_regs *regs = chip->regs;
+ struct fotg210_request *req;
+
+ req = container_of(_req, struct fotg210_request, req);
+ if (!_req || !_req->complete || !_req->buf
+ || !list_empty(&req->queue)) {
+ printf("fotg210: invalid request to ep%d\n", ep->id);
+ return -EINVAL;
+ }
+
+ if (!chip || chip->state == USB_STATE_SUSPENDED) {
+ printf("fotg210: request while chip suspended\n");
+ return -EINVAL;
+ }
+
+ req->req.actual = 0;
+ req->req.status = -EINPROGRESS;
+
+ if (req->req.length == 0) {
+ req->req.status = 0;
+ if (req->req.complete)
+ req->req.complete(&ep->ep, &req->req);
+ return 0;
+ }
+
+ if (ep->id == 0) {
+ do {
+ int len = fotg210_dma(ep, req);
+ if (len < ep->ep.maxpacket)
+ break;
+ if (ep->desc->bEndpointAddress & USB_DIR_IN)
+ udelay(100);
+ } while (req->req.length > req->req.actual);
+ } else {
+ if (ep->desc->bEndpointAddress & USB_DIR_IN) {
+ do {
+ int len = fotg210_dma(ep, req);
+ if (len < ep->ep.maxpacket)
+ break;
+ } while (req->req.length > req->req.actual);
+ } else {
+ list_add_tail(&req->queue, &ep->queue);
+ clrbits_le32(®s->gimr1,
+ GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id)));
+ }
+ }
+
+ if (ep->id == 0 || (ep->desc->bEndpointAddress & USB_DIR_IN)) {
+ if (req->req.complete)
+ req->req.complete(&ep->ep, &req->req);
+ }
+
+ return 0;
+}
+
+static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
+ struct fotg210_request *req;
+
+ /* make sure it's actually queued on this endpoint */
+ list_for_each_entry(req, &ep->queue, queue) {
+ if (&req->req == _req)
+ break;
+ }
+ if (&req->req != _req)
+ return -EINVAL;
+
+ /* remove the request */
+ list_del_init(&req->queue);
+
+ /* update status & invoke complete callback */
+ if (req->req.status == -EINPROGRESS) {
+ req->req.status = -ECONNRESET;
+ if (req->req.complete)
+ req->req.complete(_ep, &req->req);
+ }
+
+ return 0;
+}
+
+static int fotg210_ep_halt(struct usb_ep *_ep, int halt)
+{
+ struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep);
+ struct fotg210_chip *chip = ep->chip;
+ struct fotg210_regs *regs = chip->regs;
+ int ret = -1;
+
+ debug("fotg210: ep%d halt=%d\n", ep->id, halt);
+
+ /* Endpoint STALL */
+ if (ep->id > 0 && ep->id <= CFG_NUM_ENDPOINTS) {
+ if (halt) {
+ /* wait until all ep fifo empty */
+ fotg210_cxwait(chip, 0xf00);
+ /* stall */
+ if (ep->desc->bEndpointAddress & USB_DIR_IN) {
+ setbits_le32(®s->iep[ep->id - 1],
+ IEP_STALL);
+ } else {
+ setbits_le32(®s->oep[ep->id - 1],
+ OEP_STALL);
+ }
+ } else {
+ if (ep->desc->bEndpointAddress & USB_DIR_IN) {
+ clrbits_le32(®s->iep[ep->id - 1],
+ IEP_STALL);
+ } else {
+ clrbits_le32(®s->oep[ep->id - 1],
+ OEP_STALL);
+ }
+ }
+ ret = 0;
+ }
+
+ return ret;
+}
+
+/*
+ * activate/deactivate link with host.
+ */
+static void pullup(struct fotg210_chip *chip, int is_on)
+{
+ struct fotg210_regs *regs = chip->regs;
+
+ if (is_on) {
+ if (!chip->pullup) {
+ chip->state = USB_STATE_POWERED;
+ chip->pullup = 1;
+ /* enable the chip */
+ setbits_le32(®s->dev_ctrl, DEVCTRL_EN);
+ /* clear unplug bit (BIT0) */
+ clrbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG);
+ }
+ } else {
+ chip->state = USB_STATE_NOTATTACHED;
+ chip->pullup = 0;
+ chip->addr = 0;
+ writel(chip->addr, ®s->dev_addr);
+ /* set unplug bit (BIT0) */
+ setbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG);
+ /* disable the chip */
+ clrbits_le32(®s->dev_ctrl, DEVCTRL_EN);
+ }
+}
+
+static int fotg210_pullup(struct usb_gadget *_gadget, int is_on)
+{
+ struct fotg210_chip *chip;
+
+ chip = container_of(_gadget, struct fotg210_chip, gadget);
+
+ debug("fotg210: pullup=%d\n", is_on);
+
+ pullup(chip, is_on);
+
+ return 0;
+}
+
+static int fotg210_get_frame(struct usb_gadget *_gadget)
+{
+ struct fotg210_chip *chip;
+ struct fotg210_regs *regs;
+
+ chip = container_of(_gadget, struct fotg210_chip, gadget);
+ regs = chip->regs;
+
+ return SOFFNR_FNR(readl(®s->sof_fnr));
+}
+
+static struct usb_gadget_ops fotg210_gadget_ops = {
+ .get_frame = fotg210_get_frame,
+ .pullup = fotg210_pullup,
+};
+
+static struct usb_ep_ops fotg210_ep_ops = {
+ .enable = fotg210_ep_enable,
+ .disable = fotg210_ep_disable,
+ .queue = fotg210_ep_queue,
+ .dequeue = fotg210_ep_dequeue,
+ .set_halt = fotg210_ep_halt,
+ .alloc_request = fotg210_ep_alloc_request,
+ .free_request = fotg210_ep_free_request,
+};
+
+static struct fotg210_chip controller = {
+ .regs = (void __iomem *)CONFIG_FOTG210_BASE,
+ .gadget = {
+ .name = "fotg210_udc",
+ .ops = &fotg210_gadget_ops,
+ .ep0 = &controller.ep[0].ep,
+ .speed = USB_SPEED_UNKNOWN,
+ .is_dualspeed = 1,
+ .is_otg = 0,
+ .is_a_peripheral = 0,
+ .b_hnp_enable = 0,
+ .a_hnp_support = 0,
+ .a_alt_hnp_support = 0,
+ },
+ .ep[0] = {
+ .id = 0,
+ .ep = {
+ .name = "ep0",
+ .ops = &fotg210_ep_ops,
+ },
+ .desc = &ep0_desc,
+ .chip = &controller,
+ .maxpacket = CFG_EP0_MAX_PACKET_SIZE,
+ },
+ .ep[1] = {
+ .id = 1,
+ .ep = {
+ .name = "ep1",
+ .ops = &fotg210_ep_ops,
+ },
+ .chip = &controller,
+ .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
+ },
+ .ep[2] = {
+ .id = 2,
+ .ep = {
+ .name = "ep2",
+ .ops = &fotg210_ep_ops,
+ },
+ .chip = &controller,
+ .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
+ },
+ .ep[3] = {
+ .id = 3,
+ .ep = {
+ .name = "ep3",
+ .ops = &fotg210_ep_ops,
+ },
+ .chip = &controller,
+ .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
+ },
+ .ep[4] = {
+ .id = 4,
+ .ep = {
+ .name = "ep4",
+ .ops = &fotg210_ep_ops,
+ },
+ .chip = &controller,
+ .maxpacket = CFG_EPX_MAX_PACKET_SIZE,
+ },
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+ struct fotg210_chip *chip = &controller;
+ struct fotg210_regs *regs = chip->regs;
+ uint32_t id, st, isr, gisr;
+
+ isr = readl(®s->isr) & (~readl(®s->imr));
+ gisr = readl(®s->gisr) & (~readl(®s->gimr));
+ if (!(isr & ISR_DEV) || !gisr)
+ return 0;
+
+ writel(ISR_DEV, ®s->isr);
+
+ /* CX interrupts */
+ if (gisr & GISR_GRP0) {
+ st = readl(®s->gisr0);
+ writel(0, ®s->gisr0);
+
+ if (st & GISR0_CXERR)
+ printf("fotg210: cmd error\n");
+
+ if (st & GISR0_CXABORT)
+ printf("fotg210: cmd abort\n");
+
+ if (st & GISR0_CXSETUP) /* setup */
+ fotg210_setup(chip);
+ else if (st & GISR0_CXEND) /* command finish */
+ setbits_le32(®s->cxfifo, CXFIFO_CXFIN);
+ }
+
+ /* FIFO interrupts */
+ if (gisr & GISR_GRP1) {
+ st = readl(®s->gisr1);
+ for (id = 0; id < 4; ++id) {
+ if (st & GISR1_RX_FIFO(id))
+ fotg210_recv(chip, fifo_to_ep(chip, id, 0));
+ }
+ }
+
+ /* Device Status Interrupts */
+ if (gisr & GISR_GRP2) {
+ st = readl(®s->gisr2);
+ writel(0, ®s->gisr2);
+
+ if (st & GISR2_RESET)
+ printf("fotg210: reset by host\n");
+ else if (st & GISR2_SUSPEND)
+ printf("fotg210: suspend/removed\n");
+ else if (st & GISR2_RESUME)
+ printf("fotg210: resume\n");
+
+ /* Errors */
+ if (st & GISR2_ISOCERR)
+ printf("fotg210: iso error\n");
+ if (st & GISR2_ISOCABT)
+ printf("fotg210: iso abort\n");
+ if (st & GISR2_DMAERR)
+ printf("fotg210: dma error\n");
+ }
+
+ return 0;
+}
+
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+ int i, ret = 0;
+ struct fotg210_chip *chip = &controller;
+
+ if (!driver || !driver->bind || !driver->setup) {
+ puts("fotg210: bad parameter.\n");
+ return -EINVAL;
+ }
+
+ INIT_LIST_HEAD(&chip->gadget.ep_list);
+ for (i = 0; i < CFG_NUM_ENDPOINTS + 1; ++i) {
+ struct fotg210_ep *ep = chip->ep + i;
+
+ ep->ep.maxpacket = ep->maxpacket;
+ INIT_LIST_HEAD(&ep->queue);
+
+ if (ep->id == 0) {
+ ep->stopped = 0;
+ } else {
+ ep->stopped = 1;
+ list_add_tail(&ep->ep.ep_list, &chip->gadget.ep_list);
+ }
+ }
+
+ if (fotg210_reset(chip)) {
+ puts("fotg210: reset failed.\n");
+ return -EINVAL;
+ }
+
+ ret = driver->bind(&chip->gadget);
+ if (ret) {
+ debug("fotg210: driver->bind() returned %d\n", ret);
+ return ret;
+ }
+ chip->driver = driver;
+
+ return ret;
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct fotg210_chip *chip = &controller;
+
+ driver->unbind(&chip->gadget);
+ chip->driver = NULL;
+
+ pullup(chip, 0);
+
+ return 0;
+}
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index e570142..f038747 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -150,6 +150,12 @@
#define gadget_is_mv(g) 0
#endif
+#ifdef CONFIG_USB_GADGET_FOTG210
+#define gadget_is_fotg210(g) (!strcmp("fotg210_udc", (g)->name))
+#else
+#define gadget_is_fotg210(g) 0
+#endif
+
/*
* CONFIG_USB_GADGET_SX2
* CONFIG_USB_GADGET_AU1X00
@@ -215,5 +221,7 @@
return 0x20;
else if (gadget_is_mv(gadget))
return 0x21;
+ else if (gadget_is_fotg210(gadget))
+ return 0x22;
return -ENOENT;
}
diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c
index 9ce98f0..085503d 100644
--- a/drivers/usb/gadget/pxa25x_udc.c
+++ b/drivers/usb/gadget/pxa25x_udc.c
@@ -314,7 +314,8 @@
if (!_ep || !desc || ep->desc || _ep->name == ep0name
|| desc->bDescriptorType != USB_DT_ENDPOINT
|| ep->bEndpointAddress != desc->bEndpointAddress
- || ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) {
+ || ep->fifo_size <
+ le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
printf("%s, bad ep or descriptor\n", __func__);
return -EINVAL;
}
@@ -329,9 +330,9 @@
/* hardware _could_ do smaller, but driver doesn't */
if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
- && le16_to_cpu(desc->wMaxPacketSize)
+ && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))
!= BULK_FIFO_SIZE)
- || !desc->wMaxPacketSize) {
+ || !get_unaligned(&desc->wMaxPacketSize)) {
printf("%s, bad %s maxpacket\n", __func__, _ep->name);
return -ERANGE;
}
@@ -345,7 +346,7 @@
ep->desc = desc;
ep->stopped = 0;
ep->pio_irqs = 0;
- ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
+ ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
/* flush fifo (mostly for OUT buffers) */
pxa25x_ep_fifo_flush(_ep);
@@ -485,7 +486,7 @@
{
unsigned max;
- max = le16_to_cpu(ep->desc->wMaxPacketSize);
+ max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize));
do {
unsigned count;
int is_last, is_short;
@@ -766,7 +767,7 @@
*/
if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
&& req->req.length >
- le16_to_cpu(ep->desc->wMaxPacketSize)))
+ le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize))))
return -EMSGSIZE;
debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 87a5970..98f2a10 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -43,6 +43,7 @@
else
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
endif
+COBJS-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
diff --git a/drivers/usb/host/ehci-faraday.c b/drivers/usb/host/ehci-faraday.c
new file mode 100644
index 0000000..86add36
--- /dev/null
+++ b/drivers/usb/host/ehci-faraday.c
@@ -0,0 +1,148 @@
+/*
+ * Faraday USB 2.0 EHCI Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <usb.h>
+#include <usb/fusbh200.h>
+#include <usb/fotg210.h>
+
+#include "ehci.h"
+
+#ifndef CONFIG_USB_EHCI_BASE_LIST
+#define CONFIG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE }
+#endif
+
+union ehci_faraday_regs {
+ struct fusbh200_regs usb;
+ struct fotg210_regs otg;
+};
+
+static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs)
+{
+ return !readl(®s->usb.easstr);
+}
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,
+ struct ehci_hcor **ret_hcor)
+{
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ union ehci_faraday_regs *regs;
+ uint32_t base_list[] = CONFIG_USB_EHCI_BASE_LIST;
+
+ if (index < 0 || index >= ARRAY_SIZE(base_list))
+ return -1;
+ regs = (void __iomem *)base_list[index];
+ hccr = (struct ehci_hccr *)®s->usb.hccr;
+ hcor = (struct ehci_hcor *)®s->usb.hcor;
+
+ if (ehci_is_fotg2xx(regs)) {
+ /* A-device bus reset */
+ /* ... Power off A-device */
+ setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP);
+ /* ... Drop vbus and bus traffic */
+ clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ);
+ mdelay(1);
+ /* ... Power on A-device */
+ clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP);
+ /* ... Drive vbus and bus traffic */
+ setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ);
+ mdelay(1);
+ /* Disable OTG & DEV interrupts, triggered at level-high */
+ writel(IMR_IRQLH | IMR_OTG | IMR_DEV, ®s->otg.imr);
+ /* Clear all interrupt status */
+ writel(ISR_HOST | ISR_OTG | ISR_DEV, ®s->otg.isr);
+ } else {
+ /* Interrupt=level-high */
+ setbits_le32(®s->usb.bmcsr, BMCSR_IRQLH);
+ /* VBUS on */
+ clrbits_le32(®s->usb.bmcsr, BMCSR_VBUS_OFF);
+ /* Disable all interrupts */
+ writel(0x00, ®s->usb.bmier);
+ writel(0x1f, ®s->usb.bmisr);
+ }
+
+ *ret_hccr = hccr;
+ *ret_hcor = hcor;
+
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(int index)
+{
+ return 0;
+}
+
+/*
+ * This ehci_set_usbmode() overrides the weak function
+ * in "ehci-hcd.c".
+ */
+void ehci_set_usbmode(int index)
+{
+ /* nothing needs to be done */
+}
+
+/*
+ * This ehci_get_port_speed() overrides the weak function
+ * in "ehci-hcd.c".
+ */
+int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
+{
+ int spd, ret = PORTSC_PSPD_HS;
+ union ehci_faraday_regs *regs = (void __iomem *)((ulong)hcor - 0x10);
+
+ if (ehci_is_fotg2xx(regs))
+ spd = OTGCSR_SPD(readl(®s->otg.otgcsr));
+ else
+ spd = BMCSR_SPD(readl(®s->usb.bmcsr));
+
+ switch (spd) {
+ case 0: /* full speed */
+ ret = PORTSC_PSPD_FS;
+ break;
+ case 1: /* low speed */
+ ret = PORTSC_PSPD_LS;
+ break;
+ case 2: /* high speed */
+ ret = PORTSC_PSPD_HS;
+ break;
+ default:
+ printf("ehci-faraday: invalid device speed\n");
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * This ehci_get_portsc_register() overrides the weak function
+ * in "ehci-hcd.c".
+ */
+uint32_t *ehci_get_portsc_register(struct ehci_hcor *hcor, int port)
+{
+ /* Faraday EHCI has one and only one portsc register */
+ if (port) {
+ /* Printing the message would cause a scan failure! */
+ debug("The request port(%d) is not configured\n", port);
+ return NULL;
+ }
+
+ /* Faraday EHCI PORTSC register offset is 0x20 from hcor */
+ return (uint32_t *)((uint8_t *)hcor + 0x20);
+}
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index e0f3e4b..706cf0c 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -589,10 +589,12 @@
dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
} else {
dev->act_len = 0;
+#ifndef CONFIG_USB_EHCI_FARADAY
debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
ehci_readl(&ctrl->hcor->or_portsc[0]),
ehci_readl(&ctrl->hcor->or_portsc[1]));
+#endif
}
free(qtd);
@@ -603,6 +605,17 @@
return -1;
}
+__weak uint32_t *ehci_get_portsc_register(struct ehci_hcor *hcor, int port)
+{
+ if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
+ /* Printing the message would cause a scan failure! */
+ debug("The request port(%u) is not configured\n", port);
+ return NULL;
+ }
+
+ return (uint32_t *)&hcor->or_portsc[port];
+}
+
int
ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, struct devrequest *req)
@@ -616,11 +629,6 @@
int port = le16_to_cpu(req->index) & 0xff;
struct ehci_ctrl *ctrl = dev->controller;
- if (port > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
- printf("The request port(%d) is not configured\n", port - 1);
- return -1;
- }
- status_reg = (uint32_t *)&ctrl->hcor->or_portsc[port - 1];
srclen = 0;
debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
@@ -631,6 +639,19 @@
typeReq = req->request | req->requesttype << 8;
switch (typeReq) {
+ case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
+ case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
+ case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
+ status_reg = ehci_get_portsc_register(ctrl->hcor, port - 1);
+ if (!status_reg)
+ return -1;
+ break;
+ default:
+ status_reg = NULL;
+ break;
+ }
+
+ switch (typeReq) {
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
switch (le16_to_cpu(req->value) >> 8) {
case USB_DT_DEVICE:
@@ -809,21 +830,23 @@
break;
case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
reg = ehci_readl(status_reg);
+ reg &= ~EHCI_PS_CLEAR;
switch (le16_to_cpu(req->value)) {
case USB_PORT_FEAT_ENABLE:
reg &= ~EHCI_PS_PE;
break;
case USB_PORT_FEAT_C_ENABLE:
- reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
+ reg |= EHCI_PS_PE;
break;
case USB_PORT_FEAT_POWER:
if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
- reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
+ reg &= ~EHCI_PS_PP;
+ break;
case USB_PORT_FEAT_C_CONNECTION:
- reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
+ reg |= EHCI_PS_CSC;
break;
case USB_PORT_FEAT_OVER_CURRENT:
- reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
+ reg |= EHCI_PS_OCC;
break;
case USB_PORT_FEAT_C_RESET:
ctrl->portreset &= ~(1 << port);
@@ -903,6 +926,9 @@
qh_list->qh_overlay.qt_token =
cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
+ flush_dcache_range((uint32_t)qh_list,
+ ALIGN_END_ADDR(struct QH, qh_list, 1));
+
/* Set async. queue head pointer. */
ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (uint32_t)qh_list);
@@ -916,6 +942,9 @@
periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+ flush_dcache_range((uint32_t)periodic,
+ ALIGN_END_ADDR(struct QH, periodic, 1));
+
/*
* Step 2: Setup frame-list: Every microframe, USB tries the same list.
* In particular, device specifications on polling frequency
@@ -933,6 +962,10 @@
| QH_LINK_TYPE_QH;
}
+ flush_dcache_range((uint32_t)ehcic[index].periodic_list,
+ ALIGN_END_ADDR(uint32_t, ehcic[index].periodic_list,
+ 1024));
+
/* Set periodic list base address */
ehci_writel(&ehcic[index].hcor->or_periodiclistbase,
(uint32_t)ehcic[index].periodic_list);
@@ -959,10 +992,13 @@
cmd |= CMD_RUN;
ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
+#ifndef CONFIG_USB_EHCI_FARADAY
/* take control over the ports */
cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
cmd |= FLAG_CF;
ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
+#endif
+
/* unblock posted write */
cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
mdelay(5);
@@ -1144,6 +1180,16 @@
*buf = buffer + i * elementsize;
}
+ flush_dcache_range((uint32_t)buffer,
+ ALIGN_END_ADDR(char, buffer,
+ queuesize * elementsize));
+ flush_dcache_range((uint32_t)result->first,
+ ALIGN_END_ADDR(struct QH, result->first,
+ queuesize));
+ flush_dcache_range((uint32_t)result->tds,
+ ALIGN_END_ADDR(struct qTD, result->tds,
+ queuesize));
+
if (disable_periodic(ctrl) < 0) {
debug("FATAL: periodic should never fail, but did");
goto fail3;
@@ -1154,6 +1200,11 @@
result->last->qh_link = list->qh_link;
list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH;
+ flush_dcache_range((uint32_t)result->last,
+ ALIGN_END_ADDR(struct QH, result->last, 1));
+ flush_dcache_range((uint32_t)list,
+ ALIGN_END_ADDR(struct QH, list, 1));
+
if (enable_periodic(ctrl) < 0) {
debug("FATAL: periodic should never fail, but did");
goto fail3;
@@ -1184,6 +1235,8 @@
return NULL;
}
/* still active */
+ invalidate_dcache_range((uint32_t)cur,
+ ALIGN_END_ADDR(struct QH, cur, 1));
if (cur->qh_overlay.qt_token & 0x80) {
debug("Exit poll_int_queue with no completed intr transfer. "
"token is %x\n", cur->qh_overlay.qt_token);
@@ -1290,6 +1343,9 @@
return -EINVAL;
}
+ invalidate_dcache_range((uint32_t)buffer,
+ ALIGN_END_ADDR(char, buffer, length));
+
ret = destroy_int_queue(dev, queue);
if (ret < 0)
return ret;
diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c
index c7876ed..a395ebc 100644
--- a/drivers/usb/musb/omap3.c
+++ b/drivers/usb/musb/omap3.c
@@ -30,6 +30,7 @@
* MA 02111-1307 USA
*/
+#include <asm/omap_common.h>
#include <twl4030.h>
#include <twl6030.h>
#include "omap3.h"
@@ -135,7 +136,8 @@
#endif
#ifdef CONFIG_OMAP4430
- u32 *usbotghs_control = (u32 *)(CTRL_BASE + 0x33C);
+ u32 *usbotghs_control =
+ (u32 *)((*ctrl)->control_usbotghs_ctrl);
*usbotghs_control = 0x15;
#endif
platform_needs_initialization = 0;
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index ed0823b..c3606d5 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -319,10 +319,10 @@
#ifdef CONFIG_OF_CONTROL
if (exynos_fimd_parse_dt(gd->fdt_blob))
debug("Can't get proper panel info\n");
-#endif
+#else
/* initialize parameters which is specific to panel. */
init_panel_info(&panel_info);
-
+#endif
panel_width = panel_info.vl_width;
panel_height = panel_info.vl_height;
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 461ff6e..b189419 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -39,6 +39,11 @@
* setenv videomode
* video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
* le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
+ *
+ * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
+ * setenv videomode
+ * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
+ * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
*/
static void mxs_lcd_init(GraphicDevice *panel,
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index d57578d..b9bbbc6 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -27,7 +27,7 @@
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
-ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6))
+ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
COBJS-y += imx_watchdog.o
endif
COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
diff --git a/examples/standalone/mem_to_mem_idma2intr.c b/examples/standalone/mem_to_mem_idma2intr.c
index e466c90..215dc22 100644
--- a/examples/standalone/mem_to_mem_idma2intr.c
+++ b/examples/standalone/mem_to_mem_idma2intr.c
@@ -309,7 +309,8 @@
memaddr = dpalloc (sizeof (pram_idma_t), 64);
- *(volatile ushort *) &immap->im_dprambase[PROFF_IDMA2_BASE] = memaddr;
+ *(volatile u16 *)&immap->im_dprambase16
+ [PROFF_IDMA2_BASE / sizeof(u16)] = memaddr;
piptr = (volatile pram_idma_t *) ((uint) (immap) + memaddr);
piptr->pi_resv1 = 0; /* manual says: clear it */
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 4b39844..3e32eee 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -90,9 +90,6 @@
extern ulong _rel_dyn_start_ofs;
extern ulong _rel_dyn_end_ofs;
-/* Start/end of the relocation symbol table, as an offset from _start */
-extern ulong _dynsym_start_ofs;
-
/* End of the region to be relocated, as an offset form _start */
extern ulong _image_copy_end_ofs;
diff --git a/include/commproc.h b/include/commproc.h
index 7ca28c8..6959905 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -127,6 +127,7 @@
*/
#define PROFF_SCC1 ((uint)0x0000)
#define PROFF_IIC ((uint)0x0080)
+#define PROFF_REVNUM ((uint)0x00b0)
#define PROFF_SCC2 ((uint)0x0100)
#define PROFF_SPI ((uint)0x0180)
#define PROFF_SCC3 ((uint)0x0200)
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index c15bbd8..a823f9f 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -34,6 +34,15 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
@@ -63,6 +72,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#endif
#define CONFIG_FSL_LAW /* Use common FSL init code */
@@ -84,14 +94,15 @@
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_ENV_IS_NOWHERE
+#endif
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#endif
-#ifndef CONFIG_SYS_NO_FLASH
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -113,16 +124,18 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
@@ -223,7 +236,7 @@
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
- FTIM0_NOR_TEADC(0x01) | \
+ FTIM0_NOR_TEADC(0x04) | \
FTIM0_NOR_TEAHC(0x20))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1A) |\
@@ -600,6 +613,16 @@
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index fd076e0..b5911c6 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -40,10 +40,34 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
+#define CONFIG_SPL_RELOC_STACK 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
@@ -55,7 +79,11 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
+#if defined(CONFIG_SYS_CLK_100)
+#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
+#else
#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
+#endif
#define CONFIG_HWCONFIG
/*
@@ -125,16 +153,21 @@
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
/* CONFIG_SYS_IMMR */
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
/*
* Memory map
*
* 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
* 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
+ * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
* 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
* 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
* 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
* 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
+ * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
* 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
* 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
*
@@ -214,6 +247,9 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
@@ -295,7 +331,6 @@
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
@@ -305,15 +340,16 @@
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#endif
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x400
+#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
@@ -406,7 +442,9 @@
"fdtfile=bsc9131rdb.dtb\0" \
"bdev=sda1\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
- "othbootargs=ramdisk_size=600000 \0" \
+ "bootm_size=0x37000000\0" \
+ "othbootargs=ramdisk_size=600000 " \
+ "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
"usbext2boot=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs; " \
"usb start;" \
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 9d15d0e..3aa4443 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -49,6 +49,27 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
+#define CONFIG_SPL_RELOC_STACK 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x8ff80000
#endif
@@ -57,11 +78,12 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
@@ -222,6 +244,10 @@
* IFC Definitions
*/
/* NOR Flash on IFC */
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
#define CONFIG_SYS_FLASH_BASE 0x88000000
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
@@ -302,7 +328,9 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_FSL_QIXIS
+#endif
#ifdef CONFIG_FSL_QIXIS
#define CONFIG_SYS_FPGA_BASE 0xffb00000
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
@@ -338,6 +366,22 @@
#endif
/* Set up IFC registers for boot location NOR/NAND */
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
@@ -352,6 +396,7 @@
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
@@ -374,6 +419,9 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
@@ -503,7 +551,6 @@
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
@@ -517,11 +564,15 @@
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
-#else
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 5185597..7b28a27 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -31,10 +31,10 @@
#define CONFIG_PHYS_64BIT
#endif
-#ifdef CONFIG_P1010RDB
#define CONFIG_P1010
+#define CONFIG_E500 /* BOOKE e500 family */
+#include <asm/config_mpc85xx.h>
#define CONFIG_NAND_FSL_IFC
-#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
@@ -48,15 +48,25 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
-#ifdef CONFIG_NAND /* NAND Boot */
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
-#else
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#endif /* CONFIG_NAND_SPL */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE 8192
+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
+#define CONFIG_SPL_RELOC_STACK 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
@@ -74,8 +84,10 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* High Level Configuration Options */
@@ -242,7 +254,7 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* Don't relocate CCSRBAR while in NAND_SPL */
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
@@ -268,6 +280,10 @@
* IFC Definitions
*/
/* NOR Flash on IFC */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
#define CONFIG_SYS_FLASH_BASE 0xee000000
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
@@ -353,7 +369,7 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
@@ -385,15 +401,6 @@
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#endif
-/* NAND boot: 8K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x2000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffb00000
@@ -421,14 +428,20 @@
#define CONFIG_SYS_CS3_FTIM3 0x0
#endif /* CONFIG_SDCARD */
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
- defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
#undef CONFIG_SYS_RAMBOOT
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\
+ && !defined(CONFIG_SECURE_BOOT)
+#define CONFIG_A003399_NOR_WORKAROUND
+#endif
+#endif
+
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
@@ -450,7 +463,7 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
@@ -505,7 +518,7 @@
* SPI interface will not be available in case of NAND boot SPI CS0 will be
* used for SLIC
*/
-#if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT)
+#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
/* eSPI - Enhanced SPI */
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
@@ -600,7 +613,6 @@
/*
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
@@ -615,16 +627,15 @@
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
-#elif defined(CONFIG_NAND_U_BOOT)
+#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE
+#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#else
+#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
new file mode 100644
index 0000000..fee8040
--- /dev/null
+++ b/include/configs/P1023RDB.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors: Roy Zang <tie-fei.zang@freescale.com>
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE /* BOOKE */
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx
+#define CONFIG_P1023
+#define CONFIG_MP /* support multiple processors */
+
+#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x02000000
+
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/* Implement conversion of addresses in the LBC */
+#define CONFIG_SYS_LBC_LBCR 0x00000000
+#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
+ * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
+ * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
+ * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
+ * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
+ * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
+ * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+ | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
+ | OR_FCM_PGS \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+
+#define CONFIG_CMD_I2C
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME "Slot 3"
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME "Slot 2"
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#endif /* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR 0xfff80000
+#else
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE 115200
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
+#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
+#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
+#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
+#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
+
+/* For FM */
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/* Default address of microcode for the Linux Fman driver */
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xeff40000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
+
+#define CONFIG_SYS_TBIPA_VALUE 8
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 9cd3a7c..4ea8717 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -77,6 +77,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_FSL_LAW /* Use common FSL init code */
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index ce8f9b0..dd2b9c3 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -40,7 +40,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 53979dd..48acee4 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -36,7 +36,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index 778230d..d1e27c4 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -41,7 +41,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
-
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index e9af825..8f29229 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -426,6 +426,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_ENV_SUPPORT
/* Place patched DT blob (fdt) at this address */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 737e19e..9c3c2cd 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -60,7 +60,7 @@
"rdaddr=0x81000000\0" \
"bootdir=/boot\0" \
"bootfile=uImage\0" \
- "fdtfile=\0" \
+ "fdtfile=undefined\0" \
"console=ttyO0,115200n8\0" \
"optargs=\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
@@ -145,8 +145,9 @@
"if test $board_name = A33515BB; then " \
"setenv fdtfile am335x-evm.dtb; fi; " \
"if test $board_name = A335X_SK; then " \
- "setenv fdtfile am335x-evmsk.dtb; fi\0" \
-
+ "setenv fdtfile am335x-evmsk.dtb; fi " \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0"
#endif
#define CONFIG_BOOTCOMMAND \
@@ -355,6 +356,7 @@
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index 058da4f..d51f5f8 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -56,7 +56,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index 6a99175..f3916de 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -55,7 +55,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
new file mode 100644
index 0000000..1363858
--- /dev/null
+++ b/include/configs/cgtqmx6eval.h
@@ -0,0 +1,194 @@
+/*
+ *
+ * Congatec Conga-QEVAl board configuration file.
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Based on Freescale i.MX6Q Sabre Lite board configuration file.
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Leo Sartre, <lsartre@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_CGTQMX6EVAL_H
+#define __CONFIG_CGTQMX6EVAL_H
+
+#define CONFIG_MX6
+
+#include "mx6_common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE 4122
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART2_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "boot_dir=/boot\0" \
+ "console=ttymxc1\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_addr=0x11000000\0" \
+ "boot_fdt=try\0" \
+ "mmcdev=1\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+ "${boot_dir}/${uimage}\0" \
+ "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
+ "${boot_dir}/${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else "\
+ "echo ERR: Fail to boot from mmc; " \
+ "fi; " \
+ "fi; " \
+ "else echo ERR: Fail to boot from mmc; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "CGT-QMX6-Quad U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __CONFIG_CGTQMX6EVAL_H */
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index 198892b..00e92a6 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -36,6 +36,7 @@
#define CONFIG_MACH_DAVINCI_DA830_EVM
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SOC_DA830 /* TI DA830 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
@@ -226,6 +227,28 @@
#define CONFIG_CMD_SAVEENV
#endif
+/* SD/MMC configuration */
+#ifndef CONFIG_USE_NAND
+#define CONFIG_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#endif
+
+/*
+ * Enable MMC commands only when
+ * MMC support is present
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_DA8XX)
+#define CONFIG_DOS_PARTITION /* include support for FAT/storage */
+#define CONFIG_CMD_FAT /* include support for FAT cmd */
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#endif
+
#if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH)
@@ -244,8 +267,6 @@
#define CONFIG_USB_STORAGE /* MSC class support */
#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
-#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
-#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
#ifdef CONFIG_USB_KEYBOARD /* HID class support */
#define CONFIG_SYS_USB_EVENT_POLL
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index 7b68f7c..6d7a187 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -60,7 +60,7 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
-#define CONFIG_ENV_OFFSET ((4096 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 28a306b..c11f005 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -28,11 +28,20 @@
#ifndef __CONFIG_DRA7XX_EVM_H
#define __CONFIG_DRA7XX_EVM_H
+/* High Level Configuration Options */
+#define CONFIG_DRA7XX /* in a TI DRA7XX core */
#define CONFIG_ENV_IS_NOWHERE /* For now. */
#include <configs/omap5_common.h>
-#define CONFIG_DRA7XX /* in a TI DRA7XX core */
#define CONFIG_SYS_PROMPT "DRA752 EVM # "
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 UART1_BASE
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+
+#define CONSOLEDEV "ttyO0"
+
#endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 41d6cf9..1632435 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -93,13 +93,15 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
EXYNOS_DEVICE_SETTINGS
-#define TZPC_BASE_OFFSET 0x10000
-
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_SDHCI
#define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+
#define CONFIG_BOARD_EARLY_INIT_F
@@ -232,6 +234,10 @@
#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
#define CONFIG_IRAM_STACK 0x02050000
@@ -262,6 +268,7 @@
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 09b5798..e2b3b21 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -120,10 +120,14 @@
#endif
/*
+ * Enable platform initialisation via misc_init_r() function
+ */
+#define CONFIG_MISC_INIT_R
+
+/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_NETCONSOLE
#endif
@@ -153,6 +157,9 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
+#if defined(CONFIG_NET2BIG_V2)
+#define CONFIG_SYS_I2C_G762_ADDR 0x3e
+#endif
#endif /* CONFIG_CMD_I2C */
/*
diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h
new file mode 100644
index 0000000..026f321
--- /dev/null
+++ b/include/configs/lp8x4x.h
@@ -0,0 +1,262 @@
+/*
+ * ICP DAS LP-8x4x configuration file
+ *
+ * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */
+#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */
+#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOOTCOMMAND \
+ "bootm 80000;"
+
+#define CONFIG_BOOTARGS \
+ "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
+ "init=/sbin/init rootfstype=ext3"
+
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_LZMA /* LZMA compression support */
+#undef CONFIG_OF_LIBFDT
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART 1
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_USB
+#undef CONFIG_LCD
+#undef CONFIG_CMD_IDE
+
+/*
+ * Networking Configuration
+ * chip on the ICPDAS LINPAC board
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x0C000000
+#define DM9000_IO 0x0C000000
+#define DM9000_DATA 0x0C004000
+#define DM9000_IO_2 0x0D000000
+#define DM9000_DATA_2 0x0D004000
+#define CONFIG_NET_RETRY_COUNT 10
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+
+#undef CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ "
+#else
+#define CONFIG_SYS_PROMPT "=> "
+#endif
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Clock Configuration
+ */
+#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0xa0008000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+/* Use first 64kb bank of the internal SRAM */
+#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
+
+/*
+ * NOR FLASH
+ */
+#define CONFIG_SYS_MONITOR_BASE 0x0
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+#define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x40000
+#define CONFIG_ENV_SECT_SIZE 0x40000
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+
+#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_PROTECTION 1
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPSR0_VAL 0x0808c014
+#define CONFIG_SYS_GPSR1_VAL 0x00cf0002
+#define CONFIG_SYS_GPSR2_VAL 0x0221c000
+#define CONFIG_SYS_GPSR3_VAL 0x00020000
+
+#define CONFIG_SYS_GPCR0_VAL 0x00000000
+#define CONFIG_SYS_GPCR1_VAL 0x0000ab80
+#define CONFIG_SYS_GPCR2_VAL 0x00100000
+#define CONFIG_SYS_GPCR3_VAL 0x0
+
+#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4
+#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
+#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff
+#define CONFIG_SYS_GPDR3_VAL 0x00021b81
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018
+#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a
+#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402
+#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
+#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
+
+#define CONFIG_SYS_PSSR_VAL 0x32
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x005002c0
+#define CONFIG_SYS_CCCR 0x02000290
+#define CONFIG_SYS_CLKCFG 0x0000000b
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2
+#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc
+#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9
+#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
+#define CONFIG_SYS_MDREFR_VAL 0x2093e018
+#define CONFIG_SYS_MDCNFG_VAL 0x890009d1
+#define CONFIG_SYS_MDMRS_VAL 0x00220022
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000001
+#define CONFIG_SYS_MCMEM0_VAL 0x0000c497
+#define CONFIG_SYS_MCMEM1_VAL 0x0000c497
+#define CONFIG_SYS_MCATT0_VAL 0x0000c497
+#define CONFIG_SYS_MCATT1_VAL 0x0000c497
+#define CONFIG_SYS_MCIO0_VAL 0x00008407
+#define CONFIG_SYS_MCIO1_VAL 0x00008407
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_VOIPAC_LCD
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x"
+#define CONFIG_USB_STORAGE
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index e5a15a4..3a58afe 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -60,6 +60,7 @@
#define CONFIG_CMD_MMC
#define CONFIG_CMD_USB
#define CONFIG_CMD_BOOTZ
+#define CONFIG_VIDEO
/* Memory configurations */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
@@ -133,6 +134,22 @@
#define CONFIG_USB_STORAGE
#endif
+/* Framebuffer support */
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
+#endif
+
/* Boot Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 54d01f9..de69182 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -64,6 +64,7 @@
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_VIDEO
/* Memory configurations */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
@@ -235,6 +236,22 @@
#endif
#endif
+/* Framebuffer support */
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
+#endif
+
/* Boot Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 41974b1..b0a965f 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -118,7 +118,7 @@
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
+ "mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
"update_sd_firmware_filename=u-boot.imx\0" \
"update_sd_firmware=" \
@@ -240,7 +240,6 @@
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_OF_LIBFDT
diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
index 7298a76..bfaa420 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -97,7 +97,7 @@
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 1583c11..76f7812 100644
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -35,7 +35,12 @@
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */
#endif
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
#endif /* __MX6QSABREAUTO_CONFIG_H */
diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h
index 3b8d752..44f07cb 100644
--- a/include/configs/mx6qsabresd.h
+++ b/include/configs/mx6qsabresd.h
@@ -29,7 +29,6 @@
#define CONFIG_SYS_FSL_USDHC_NUM 3
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
-#define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */
#endif
#endif /* __MX6QSABRESD_CONFIG_H */
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 8a94efd..19dcdd6 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -59,7 +59,7 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_LOADADDR 0x80800000
+#define CONFIG_LOADADDR 0x82000000
#define CONFIG_SYS_TEXT_BASE 0x87800000
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
deleted file mode 100644
index 04e8d3a..0000000
--- a/include/configs/omap2420h4.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Kshitij Gupta <kshitij@ti.com>
- *
- * Configuration settings for the 242x TI H4 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP2420 1 /* which is in a 2420 */
-#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
-/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
-/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
-
-#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
-
-/* Clock config to target*/
-#define PRCM_CONFIG_II 1
-/* #define PRCM_CONFIG_III 1 */
-
-#include <asm/arch/omap2420.h> /* get chip and board defs */
-
-/* On H4, NOR and NAND flash are mutual exclusive.
- Define this if you want to use NAND
- */
-/*#define CONFIG_SYS_NAND_BOOT */
-
-#ifdef CONFIG_APTIX
-#define V_SCLK 1500000
-#else
-#define V_SCLK 12000000
-#endif
-
-/* input clock of PLL */
-/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
-#define CONFIG_SYS_CLK_FREQ V_SCLK
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-#define CONFIG_OF_LIBFDT
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
-
-/*
- * Hardware drivers
- */
-
-/*
- * SMC91c96 Etherent
- */
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#ifdef CONFIG_APTIX
-#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
-#else
-#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
-#endif
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
-#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1 /* UART1 on H4 */
-
- /*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP24XX_I2C
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#ifdef CONFIG_SYS_NAND_BOOT
- #define CONFIG_CMD_DHCP
- #define CONFIG_CMD_I2C
- #define CONFIG_CMD_NAND
- #define CONFIG_CMD_JFFS2
-#else
- #define CONFIG_CMD_DHCP
- #define CONFIG_CMD_I2C
- #define CONFIG_CMD_JFFS2
-
- #undef CONFIG_CMD_SOURCE
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-#define CONFIG_BOOTDELAY 3
-
-#ifdef NFS_BOOT_DEFAULTS
-#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
-#else
-#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
-#endif
-
-#define CONFIG_NETMASK 255.255.254.0
-#define CONFIG_IPADDR 128.247.77.90
-#define CONFIG_SERVERIP 128.247.77.158
-#define CONFIG_BOOTFILE "uImage"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#ifdef CONFIG_APTIX
-# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # "
-#else
-# define CONFIG_SYS_PROMPT "OMAP242x H4 # "
-#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
-
-/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
- */
-#ifdef CONFIG_APTIX
-#define V_PTV 3
-#else
-#define V_PTV 7 /* use with 12MHz/128 */
-#endif
-
-#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
-#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
-#define CONFIG_SYS_HZ 1000
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
-#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
-
-#define PHYS_FLASH_SECT_SIZE SZ_128K
-#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE_1 SZ_32M
-#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
-#define PHYS_FLASH_SIZE_2 SZ_32M
-
-#define PHYS_SRAM 0x4020F800
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
-
-#ifdef CONFIG_SYS_NAND_BOOT
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_256K)
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
-#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
-#endif
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_SYS_JFFS2_MEM_NAND
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor1"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor1=omap2420-1"
-#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
-*/
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index d6448b0..2fa4382 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -45,10 +45,6 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
-/* Clock Defines */
-#define V_OSCK 38400000 /* Clock output from T2 */
-#define V_SCLK V_OSCK
-
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
@@ -154,6 +150,7 @@
"console=ttyO2,115200n8\0" \
"fdt_high=0xffffffff\0" \
"fdtaddr=0x80f80000\0" \
+ "fdtfile=undefined\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
@@ -181,8 +178,12 @@
"setenv fdtfile omap4-sdp.dtb; fi; " \
"if test $board_name = panda; then " \
"setenv fdtfile omap4-panda.dtb; fi;" \
+ "if test $board_name = panda-a4; then " \
+ "setenv fdtfile omap4-panda-a4.dtb; fi;" \
"if test $board_name = panda-es; then " \
- "setenv fdtfile omap4-panda-es.dtb; fi; \0" \
+ "setenv fdtfile omap4-panda-es.dtb; fi;" \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
#define CONFIG_BOOTCOMMAND \
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index deb5e9f..b87ee42 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -45,10 +45,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-/* Clock Defines */
-#define V_OSCK 19200000 /* Clock output from T2 */
-#define V_SCLK V_OSCK
-
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT
@@ -81,10 +77,6 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
-
-#define CONFIG_BAUDRATE 115200
/* CPU */
#define CONFIG_ARCH_CPU_INIT
@@ -144,9 +136,10 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
+ "console=" CONSOLEDEV ",115200n8\0" \
"fdt_high=0xffffffff\0" \
"fdtaddr=0x80f80000\0" \
+ "fdtfile=undefined\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
@@ -174,7 +167,11 @@
"bootz ${loadaddr} - ${fdtaddr}\0" \
"findfdt="\
"if test $board_name = omap5_uevm; then " \
- "setenv fdtfile omap5-uevm.dtb; fi;\0 " \
+ "setenv fdtfile omap5-uevm.dtb; fi; " \
+ "if test $board_name = dra7xx; then " \
+ "setenv fdtfile dra7-evm.dtb; fi;" \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
#define CONFIG_BOOTCOMMAND \
@@ -246,6 +243,10 @@
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#endif
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PALMAS_POWER
+#endif
+
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 9e0339b..46dacc2 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -35,10 +35,9 @@
#include <configs/omap5_common.h>
-/* TWL6035 */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PALMAS_POWER
-#endif
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+#define CONFIG_BAUDRATE 115200
/* MMC ENV related defines */
#define CONFIG_ENV_IS_IN_MMC
@@ -54,7 +53,9 @@
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
-#define CONFIG_SYS_PROMPT "OMAP5430 EVM # "
+#define CONFIG_SYS_PROMPT "OMAP5432 uEVM # "
+
+#define CONSOLEDEV "ttyO2"
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
#endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/origen.h b/include/configs/origen.h
index ff2b24d..e179911 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -96,6 +96,8 @@
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR 0x02020030
+#define CONFIG_SPL_TEXT_BASE 0x02021410
+
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
/* Miscellaneous configurable options */
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index eac1ef9..9e2686a 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -46,7 +46,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 2ecd105..9b16c47 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -231,6 +231,7 @@
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL"
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index 233d87d..3f9fdd4 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -234,7 +234,7 @@
#define CONFIG_SYS_FLASH_ERASE_TOUT 250000
#define CONFIG_SYS_FLASH_WRITE_TOUT 5000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 19
+#define CONFIG_SYS_MAX_FLASH_SECT 128
/*
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index f66173e..f0da1fc 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -72,7 +72,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index b796b46..5e43066 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -95,6 +95,8 @@
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR 0x00002488
+#define CONFIG_SPL_TEXT_BASE 0x02021410
+
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
/* Miscellaneous configurable options */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index aa90249..92b2179 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -33,6 +33,15 @@
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
@@ -65,20 +74,22 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_ENV_IS_NOWHERE
+#endif
#else
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#endif
-#ifndef CONFIG_SYS_NO_FLASH
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -100,18 +111,18 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR 0xffe20000
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
-
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
@@ -633,6 +644,16 @@
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
diff --git a/include/configs/trats.h b/include/configs/trats.h
index fd58558..c70838b 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -146,7 +146,8 @@
#define CONFIG_DFU_ALT \
"u-boot mmc 80 400;" \
- "uImage ext4 0 2\0" \
+ "uImage ext4 0 2;" \
+ "exynos4210-trats.dtb ext4 0 2\0"
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
@@ -154,7 +155,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootk=" \
- "run loaduimage; bootm 0x40007FC0\0" \
+ "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
"updatemmc=" \
"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
"mmc boot 0 1 1 0\0" \
@@ -177,7 +178,7 @@
"mmcboot=" \
"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
- "run loaduimage; bootm 0x40007FC0\0" \
+ "run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
@@ -188,6 +189,8 @@
"nfsroot=/nfsroot/arm\0" \
"bootblock=" CONFIG_BOOTBLOCK "\0" \
"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+ "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr}" \
+ "${fdtfile}\0" \
"mmcdev=0\0" \
"mmcbootpart=2\0" \
"mmcrootpart=5\0" \
@@ -212,7 +215,10 @@
" /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
"setenv spl_imgsize;" \
"setenv spl_imgaddr;" \
- "setenv spl_addr_tmp;\0"
+ "setenv spl_addr_tmp;\0" \
+ "fdtaddr=40800000\0" \
+ "fdtfile=exynos4210-trats.dtb\0"
+
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
@@ -322,4 +328,7 @@
#define CONFIG_USB_GADGET_MASS_STORAGE
#endif
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+
#endif /* __CONFIG_H */
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 5755f11..41a7176 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -52,7 +52,7 @@
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
new file mode 100644
index 0000000..77fe893
--- /dev/null
+++ b/include/configs/vf610twr.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale Vybrid vf610twr board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_VF610
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE 4146
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+#define LPUART_BASE UART1_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT (1)
+#define CONFIG_BAUDRATE 115200
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_SYS_TEXT_BASE 0x3f008000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80010000
+#define CONFIG_SYS_MEMTEST_END 0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR 0x80010000
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM (0x80000000)
+#define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#endif
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 9d7ec3f..5593f1c 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -29,7 +29,7 @@
#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
@@ -86,6 +86,21 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+
#if defined(CONFIG_MX6DL)
#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
#elif defined(CONFIG_MX6S)
@@ -103,7 +118,7 @@
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
+ "mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
"update_sd_firmware_filename=u-boot.imx\0" \
"update_sd_firmware=" \
@@ -217,7 +232,6 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index 9542c7e..994edec 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -61,12 +61,12 @@
/*
* Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
- * the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If
+ * the user plugged the standard 8GB MoviNAND card into J29/HSMMC/POP. If
* they didn't, the boot sector layout may be different. However, use of that
* particular card is standard practice as far as I know.
*/
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
diff --git a/include/dwmmc.h b/include/dwmmc.h
index c8b1d40..e142f3e 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -123,6 +123,8 @@
#define MSIZE(x) ((x) << 28)
#define RX_WMARK(x) ((x) << 16)
#define TX_WMARK(x) (x)
+#define RX_WMARK_SHIFT 16
+#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
#define DWMCI_IDMAC_OWN (1 << 31)
#define DWMCI_IDMAC_CH (1 << 4)
@@ -144,6 +146,7 @@
unsigned int bus_hz;
int dev_index;
int buswidth;
+ u32 clksel_val;
u32 fifoth_val;
struct mmc *mmc;
diff --git a/include/environment.h b/include/environment.h
index 4c6a37b..460ccb4 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -75,6 +75,12 @@
# endif
#endif /* CONFIG_ENV_IS_IN_FLASH */
+#if defined(CONFIG_ENV_IS_IN_MMC)
+# ifdef CONFIG_ENV_OFFSET_REDUND
+# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+#endif
+
#if defined(CONFIG_ENV_IS_IN_NAND)
# if defined(CONFIG_ENV_OFFSET_OOB)
# ifdef CONFIG_ENV_OFFSET_REDUND
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 1ece612..8845e29 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -89,6 +89,7 @@
COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */
COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
+ COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */
diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
index d1d732c..bd48704 100644
--- a/include/linux/usb/ch9.h
+++ b/include/linux/usb/ch9.h
@@ -35,6 +35,7 @@
#include <linux/types.h> /* __u8 etc */
#include <asm/byteorder.h> /* le16_to_cpu */
+#include <asm/unaligned.h> /* get_unaligned() */
/*-------------------------------------------------------------------------*/
@@ -596,7 +597,7 @@
*/
static inline int usb_endpoint_maxp(const struct usb_endpoint_descriptor *epd)
{
- return __le16_to_cpu(epd->wMaxPacketSize);
+ return __le16_to_cpu(get_unaligned(&epd->wMaxPacketSize));
}
static inline int usb_endpoint_interrupt_type(
diff --git a/include/mmc.h b/include/mmc.h
index 566db59..583c30e 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -93,6 +93,11 @@
#define MMC_CMD_APP_CMD 55
#define MMC_CMD_SPI_READ_OCR 58
#define MMC_CMD_SPI_CRC_ON_OFF 59
+#define MMC_CMD_RES_MAN 62
+
+#define MMC_CMD62_ARG1 0xefac62ec
+#define MMC_CMD62_ARG2 0xcbaea7
+
#define SD_CMD_SEND_RELATIVE_ADDR 3
#define SD_CMD_SWITCH_FUNC 6
@@ -158,14 +163,18 @@
/*
* EXT_CSD fields
*/
+#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
+#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
+#define EXT_CSD_BOOT_BUS_WIDTH 177
#define EXT_CSD_PART_CONF 179 /* R/W */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
+#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
@@ -184,6 +193,16 @@
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
+#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
+#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
+#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
+#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
+
+#define EXT_CSD_BOOT_ACK(x) (x << 6)
+#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
+#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
+
+
#define R1_ILLEGAL_COMMAND (1 << 22)
#define R1_APP_CMD (1 << 5)
@@ -211,6 +230,11 @@
/* Maximum block size for MMC */
#define MMC_MAX_BLOCK_LEN 512
+/* The number of MMC physical partitions. These consist of:
+ * boot partitions (2), general purpose partitions (4) in MMC v4.4.
+ */
+#define MMC_NUM_BOOT_PARTITION 2
+
struct mmc_cid {
unsigned long psn;
unsigned short oid;
@@ -263,6 +287,10 @@
uint write_bl_len;
uint erase_grp_size;
u64 capacity;
+ u64 capacity_user;
+ u64 capacity_boot;
+ u64 capacity_rpmb;
+ u64 capacity_gp[4];
block_dev_desc_t block_dev;
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
@@ -291,6 +319,11 @@
int mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
void spl_mmc_load(void) __noreturn;
+/* Function to change the size of boot partition and rpmb partitions */
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+ unsigned long rpmbsize);
+/* Function to send commands to open/close the specified boot partition */
+int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
/**
* Start device initialization and return immediately; it does not block on
diff --git a/include/palmas.h b/include/palmas.h
index 3b18589..aff48b5 100644
--- a/include/palmas.h
+++ b/include/palmas.h
@@ -26,17 +26,90 @@
#include <common.h>
#include <i2c.h>
-/* I2C chip addresses */
-#define PALMAS_CHIP_ADDR 0x48
+/* I2C chip addresses, TW6035/37 */
+#define TWL603X_CHIP_P1 0x48 /* Page 1 */
+#define TWL603X_CHIP_P2 0x49 /* Page 2 */
+#define TWL603X_CHIP_P3 0x4a /* Page 3 */
-/* 0x1XY translates to page 1, register address 0xXY */
+/* TPS659038/39 */
+#define TPS65903X_CHIP_P1 0x58 /* Page 1 */
+
+/* Page 1 registers (0x1XY translates to page 1, reg addr 0xXY): */
+
+/* LDO1 control/voltage */
+#define LDO1_CTRL 0x50
+#define LDO1_VOLTAGE 0x51
+
+/* LDO9 control/voltage */
#define LDO9_CTRL 0x60
#define LDO9_VOLTAGE 0x61
-/* Bit field definitions for LDOx_CTRL */
-#define LDO_ON (1 << 4)
-#define LDO_MODE_SLEEP (1 << 2)
-#define LDO_MODE_ACTIVE (1 << 0)
+/* LDOUSB control/voltage */
+#define LDOUSB_CTRL 0x64
+#define LDOUSB_VOLTAGE 0x65
+
+/* Control of 32 kHz audio clock */
+#define CLK32KGAUDIO_CTRL 0xd5
+
+/* SYSEN2_CTRL for VCC_3v3_AUX supply on the sEVM */
+#define SYSEN2_CTRL 0xd9
+
+/*
+ * Bit field definitions for LDOx_CTRL, SYSENx_CTRL
+ * and some other xxx_CTRL resources:
+ */
+#define LDO9_BYP_EN (1 << 6) /* LDO9 only! */
+#define RSC_STAT_ON (1 << 4) /* RO status bit! */
+#define RSC_MODE_SLEEP (1 << 2)
+#define RSC_MODE_ACTIVE (1 << 0)
+
+/* Some LDO voltage values */
+#define LDO_VOLT_OFF 0
+#define LDO_VOLT_1V8 0x13
+#define LDO_VOLT_3V0 0x2b
+#define LDO_VOLT_3V3 0x31
+/* Request bypass, LDO9 only */
+#define LDO9_BYPASS 0x3f
+
+/* SMPS7_CTRL */
+#define SMPS7_CTRL 0x30
+
+/* SMPS9_CTRL */
+#define SMPS9_CTRL 0x38
+#define SMPS9_VOLTAGE 0x3b
+
+/* Bit field definitions for SMPSx_CTRL */
+#define SMPS_MODE_ACT_AUTO 1
+#define SMPS_MODE_ACT_ECO 2
+#define SMPS_MODE_ACT_FPWM 3
+#define SMPS_MODE_SLP_AUTO (1 << 2)
+#define SMPS_MODE_SLP_ECO (2 << 2)
+#define SMPS_MODE_SLP_FPWM (3 << 2)
+
+/*
+ * Some popular SMPS voltages, all with RANGE=1; note
+ * that RANGE cannot be changed on the fly
+ */
+#define SMPS_VOLT_OFF 0
+#define SMPS_VOLT_1V2 0x90
+#define SMPS_VOLT_1V8 0xae
+#define SMPS_VOLT_2V1 0xbd
+#define SMPS_VOLT_3V0 0xea
+#define SMPS_VOLT_3V3 0xf9
+
+/* Backup Battery & VRTC Control */
+#define BB_VRTC_CTRL 0xa8
+/* Bit definitions for BB_VRTC_CTRL */
+#define VRTC_EN_SLP (1 << 6)
+#define VRTC_EN_OFF (1 << 5)
+#define VRTC_PWEN (1 << 4)
+#define BB_LOW_ICHRG (1 << 3)
+#define BB_HIGH_ICHRG (0 << 3)
+#define BB_VSEL_3V0 (0 << 1)
+#define BB_VSEL_2V5 (1 << 1)
+#define BB_VSEL_3V15 (2 << 1)
+#define BB_VSEL_VBAT (3 << 1)
+#define BB_CHRG_EN (1 << 0)
/*
* Functions to read and write from TPS659038/TWL6035/TWL6037
@@ -54,5 +127,8 @@
void palmas_init_settings(void);
int palmas_mmc1_poweron_ldo(void);
+int twl603x_mmc1_set_ldo9(u8 vsel);
+int twl603x_audio_power(u8 on);
+int twl603x_enable_bb_charge(u8 bb_fields);
#endif /* PALMAS_H */
diff --git a/include/spi.h b/include/spi.h
index 3fe2e1e..1638b50 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -37,11 +37,16 @@
#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
#define SPI_3WIRE 0x10 /* SI/SO signals shared */
#define SPI_LOOP 0x20 /* loopback mode */
+#define SPI_SLAVE 0x40 /* slave mode */
+#define SPI_PREAMBLE 0x80 /* Skip preamble bytes */
/* SPI transfer flags */
#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
+/* Header byte that marks the start of the message */
+#define SPI_PREAMBLE_END_BYTE 0xec
+
/*-----------------------------------------------------------------------
* Representation of a SPI slave, i.e. what we're communicating with.
*
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 3b6a44e..e80785f 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -38,6 +38,16 @@
u32 page_size;
/* Erase (sector) size */
u32 sector_size;
+#ifdef CONFIG_SPI_FLASH_BAR
+ /* Bank read cmd */
+ u8 bank_read_cmd;
+ /* Bank write cmd */
+ u8 bank_write_cmd;
+ /* Current flash bank */
+ u8 bank_curr;
+#endif
+ /* Poll cmd - for flash erase/program */
+ u8 poll_cmd;
void *memory_map; /* Address of read-only SPI flash access */
int (*read)(struct spi_flash *flash, u32 offset,
diff --git a/include/usb/fotg210.h b/include/usb/fotg210.h
new file mode 100644
index 0000000..2d2d243
--- /dev/null
+++ b/include/usb/fotg210.h
@@ -0,0 +1,364 @@
+/*
+ * Faraday USB 2.0 OTG Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef _FOTG210_H
+#define _FOTG210_H
+
+struct fotg210_regs {
+ /* USB Host Controller */
+ struct {
+ uint32_t data[4];
+ } hccr; /* 0x00 - 0x0f: hccr */
+ struct {
+ uint32_t data[9];
+ } hcor; /* 0x10 - 0x33: hcor */
+ uint32_t rsvd1[3];
+ uint32_t miscr; /* 0x40: Miscellaneous Register */
+ uint32_t rsvd2[15];
+ /* USB OTG Controller */
+ uint32_t otgcsr;/* 0x80: OTG Control Status Register */
+ uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */
+ uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */
+ uint32_t rsvd3[13];
+ uint32_t isr; /* 0xC0: Global Interrupt Status Register */
+ uint32_t imr; /* 0xC4: Global Interrupt Mask Register */
+ uint32_t rsvd4[14];
+ /* USB Device Controller */
+ uint32_t dev_ctrl;/* 0x100: Device Control Register */
+ uint32_t dev_addr;/* 0x104: Device Address Register */
+ uint32_t dev_test;/* 0x108: Device Test Register */
+ uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */
+ uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */
+ uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */
+ uint32_t rsvd5[2];
+ uint32_t cxfifo;/* 0x120: CX FIFO Register */
+ uint32_t idle; /* 0x124: IDLE Counter Register */
+ uint32_t rsvd6[2];
+ uint32_t gimr; /* 0x130: Group Interrupt Mask Register */
+ uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */
+ uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */
+ uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */
+ uint32_t gisr; /* 0x140: Group Interrupt Status Register */
+ uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */
+ uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */
+ uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */
+ uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */
+ uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */
+ uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */
+ uint32_t rsvd7[1];
+ uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */
+ uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */
+ uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */
+ uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */
+ uint32_t fifomap;/* 0x1a8: FIFO Map Register */
+ uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */
+ uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */
+ uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */
+ uint32_t rsvd8[1];
+ uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */
+ uint32_t dma_addr; /* 0x1cc: DMA Address Register */
+ uint32_t ep0_data; /* 0x1d0: EP0 Setup Packet PIO Register */
+};
+
+/* Miscellaneous Register */
+#define MISCR_SUSPEND (1 << 6) /* Put transceiver in suspend mode */
+#define MISCR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */
+#define MISCR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */
+#define MISCR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
+
+/* OTG Control Status Register */
+#define OTGCSR_SPD_HIGH (2 << 22) /* Speed of the attached device (host) */
+#define OTGCSR_SPD_LOW (1 << 22)
+#define OTGCSR_SPD_FULL (0 << 22)
+#define OTGCSR_SPD_MASK (3 << 22)
+#define OTGCSR_SPD_SHIFT 22
+#define OTGCSR_SPD(x) (((x) >> 22) & 0x03)
+#define OTGCSR_DEV_A (0 << 21) /* Acts as A-device */
+#define OTGCSR_DEV_B (1 << 21) /* Acts as B-device */
+#define OTGCSR_ROLE_H (0 << 20) /* Acts as Host */
+#define OTGCSR_ROLE_D (1 << 20) /* Acts as Device */
+#define OTGCSR_A_VBUS_VLD (1 << 19) /* A-device VBUS Valid */
+#define OTGCSR_A_SESS_VLD (1 << 18) /* A-device Session Valid */
+#define OTGCSR_B_SESS_VLD (1 << 17) /* B-device Session Valid */
+#define OTGCSR_B_SESS_END (1 << 16) /* B-device Session End */
+#define OTGCSR_HFT_LONG (1 << 11) /* HDISCON noise filter = 270 us*/
+#define OTGCSR_HFT (0 << 11) /* HDISCON noise filter = 135 us*/
+#define OTGCSR_VFT_LONG (1 << 10) /* VBUS noise filter = 472 us*/
+#define OTGCSR_VFT (0 << 10) /* VBUS noise filter = 135 us*/
+#define OTGCSR_IDFT_LONG (1 << 9) /* ID noise filter = 4 ms*/
+#define OTGCSR_IDFT (0 << 9) /* ID noise filter = 3 ms*/
+#define OTGCSR_A_SRPR_VBUS (0 << 8) /* A-device: SRP responds to VBUS */
+#define OTGCSR_A_SRPR_DATA (1 << 8) /* A-device: SRP responds to DATA-LINE */
+#define OTGCSR_A_SRP_EN (1 << 7) /* A-device SRP detection enabled */
+#define OTGCSR_A_HNP (1 << 6) /* Set role=A-device with HNP enabled */
+#define OTGCSR_A_BUSDROP (1 << 5) /* A-device drop bus (power-down) */
+#define OTGCSR_A_BUSREQ (1 << 4) /* A-device request bus */
+#define OTGCSR_B_VBUS_DISC (1 << 2) /* B-device discharges VBUS */
+#define OTGCSR_B_HNP (1 << 1) /* B-device enable HNP */
+#define OTGCSR_B_BUSREQ (1 << 0) /* B-device request bus */
+
+/* OTG Interrupt Status Register */
+#define OTGISR_APRM (1 << 12) /* Mini-A plug removed */
+#define OTGISR_BPRM (1 << 11) /* Mini-B plug removed */
+#define OTGISR_OVD (1 << 10) /* over-current detected */
+#define OTGISR_IDCHG (1 << 9) /* ID(A/B) changed */
+#define OTGISR_RLCHG (1 << 8) /* Role(Host/Device) changed */
+#define OTGISR_BSESSEND (1 << 6) /* B-device Session End */
+#define OTGISR_AVBUSERR (1 << 5) /* A-device VBUS Error */
+#define OTGISR_ASRP (1 << 4) /* A-device SRP detected */
+#define OTGISR_BSRP (1 << 0) /* B-device SRP complete */
+
+/* OTG Interrupt Enable Register */
+#define OTGIER_APRM (1 << 12) /* Mini-A plug removed */
+#define OTGIER_BPRM (1 << 11) /* Mini-B plug removed */
+#define OTGIER_OVD (1 << 10) /* over-current detected */
+#define OTGIER_IDCHG (1 << 9) /* ID(A/B) changed */
+#define OTGIER_RLCHG (1 << 8) /* Role(Host/Device) changed */
+#define OTGIER_BSESSEND (1 << 6) /* B-device Session End */
+#define OTGIER_AVBUSERR (1 << 5) /* A-device VBUS Error */
+#define OTGIER_ASRP (1 << 4) /* A-device SRP detected */
+#define OTGIER_BSRP (1 << 0) /* B-device SRP complete */
+
+/* Global Interrupt Status Register (W1C) */
+#define ISR_HOST (1 << 2) /* USB Host interrupt */
+#define ISR_OTG (1 << 1) /* USB OTG interrupt */
+#define ISR_DEV (1 << 0) /* USB Device interrupt */
+#define ISR_MASK 0x07
+
+/* Global Interrupt Mask Register */
+#define IMR_IRQLH (1 << 3) /* Interrupt triggered at level-high */
+#define IMR_IRQLL (0 << 3) /* Interrupt triggered at level-low */
+#define IMR_HOST (1 << 2) /* USB Host interrupt */
+#define IMR_OTG (1 << 1) /* USB OTG interrupt */
+#define IMR_DEV (1 << 0) /* USB Device interrupt */
+#define IMR_MASK 0x0f
+
+/* Device Control Register */
+#define DEVCTRL_FS_FORCED (1 << 9) /* Forced to be Full-Speed Mode */
+#define DEVCTRL_HS (1 << 6) /* High Speed Mode */
+#define DEVCTRL_FS (0 << 6) /* Full Speed Mode */
+#define DEVCTRL_EN (1 << 5) /* Chip Enable */
+#define DEVCTRL_RESET (1 << 4) /* Chip Software Reset */
+#define DEVCTRL_SUSPEND (1 << 3) /* Enter Suspend Mode */
+#define DEVCTRL_GIRQ_EN (1 << 2) /* Global Interrupt Enabled */
+#define DEVCTRL_HALFSPD (1 << 1) /* Half speed mode for FPGA test */
+#define DEVCTRL_RWAKEUP (1 << 0) /* Enable remote wake-up */
+
+/* Device Address Register */
+#define DEVADDR_CONF (1 << 7) /* SET_CONFIGURATION has been executed */
+#define DEVADDR_ADDR(x) ((x) & 0x7f)
+#define DEVADDR_ADDR_MASK 0x7f
+
+/* Device Test Register */
+#define DEVTEST_NOSOF (1 << 6) /* Do not generate SOF */
+#define DEVTEST_TST_MODE (1 << 5) /* Enter Test Mode */
+#define DEVTEST_TST_NOTS (1 << 4) /* Do not toggle sequence */
+#define DEVTEST_TST_NOCRC (1 << 3) /* Do not append CRC */
+#define DEVTEST_TST_CLREA (1 << 2) /* Clear External Side Address */
+#define DEVTEST_TST_CXLP (1 << 1) /* EP0 loopback test */
+#define DEVTEST_TST_CLRFF (1 << 0) /* Clear FIFO */
+
+/* SOF Frame Number Register */
+#define SOFFNR_UFN(x) (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */
+#define SOFFNR_FNR(x) ((x) & 0x7ff) /* SOF Frame Number */
+
+/* SOF Mask Timer Register */
+#define SOFMTR_TMR(x) ((x) & 0xffff)
+
+/* PHY Test Mode Selector Register */
+#define PHYTMSR_TST_PKT (1 << 4) /* Packet send test */
+#define PHYTMSR_TST_SE0NAK (1 << 3) /* High-Speed quiescent state */
+#define PHYTMSR_TST_KSTA (1 << 2) /* High-Speed K state */
+#define PHYTMSR_TST_JSTA (1 << 1) /* High-Speed J state */
+#define PHYTMSR_UNPLUG (1 << 0) /* Enable soft-detachment */
+
+/* CX FIFO Register */
+#define CXFIFO_BYTES(x) (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */
+#define CXFIFO_FIFOE(x) (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */
+#define CXFIFO_FIFOE_FIFO0 (1 << 8)
+#define CXFIFO_FIFOE_FIFO1 (1 << 9)
+#define CXFIFO_FIFOE_FIFO2 (1 << 10)
+#define CXFIFO_FIFOE_FIFO3 (1 << 11)
+#define CXFIFO_FIFOE_MASK (0x0f << 8)
+#define CXFIFO_CXFIFOE (1 << 5) /* CX FIFO empty */
+#define CXFIFO_CXFIFOF (1 << 4) /* CX FIFO full */
+#define CXFIFO_CXFIFOCLR (1 << 3) /* CX FIFO clear */
+#define CXFIFO_CXSTALL (1 << 2) /* CX Stall */
+#define CXFIFO_TSTPKTFIN (1 << 1) /* Test packet data transfer finished */
+#define CXFIFO_CXFIN (1 << 0) /* CX data transfer finished */
+
+/* IDLE Counter Register */
+#define IDLE_MS(x) ((x) & 0x07) /* PHY suspend delay = x ms */
+
+/* Group Interrupt Mask(Disable) Register */
+#define GIMR_GRP2 (1 << 2) /* Disable interrupt group 2 */
+#define GIMR_GRP1 (1 << 1) /* Disable interrupt group 1 */
+#define GIMR_GRP0 (1 << 0) /* Disable interrupt group 0 */
+#define GIMR_MASK 0x07
+
+/* Group Interrupt Mask(Disable) Register 0 (CX) */
+#define GIMR0_CXABORT (1 << 5) /* CX command abort interrupt */
+#define GIMR0_CXERR (1 << 4) /* CX command error interrupt */
+#define GIMR0_CXEND (1 << 3) /* CX command end interrupt */
+#define GIMR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */
+#define GIMR0_CXIN (1 << 1) /* EP0-IN packet interrupt */
+#define GIMR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */
+#define GIMR0_MASK 0x3f
+
+/* Group Interrupt Mask(Disable) Register 1 (FIFO) */
+#define GIMR1_FIFO_IN(x) (1 << (((x) & 3) + 16)) /* FIFOx IN */
+#define GIMR1_FIFO_TX(x) GIMR1_FIFO_IN(x)
+#define GIMR1_FIFO_OUT(x) (1 << (((x) & 3) * 2)) /* FIFOx OUT */
+#define GIMR1_FIFO_SPK(x) (1 << (((x) & 3) * 2 + 1)) /* FIFOx SHORT PACKET */
+#define GIMR1_FIFO_RX(x) (GIMR1_FIFO_OUT(x) | GIMR1_FIFO_SPK(x))
+#define GIMR1_MASK 0xf00ff
+
+/* Group Interrupt Mask(Disable) Register 2 (Device) */
+#define GIMR2_WAKEUP (1 << 10) /* Device waked up */
+#define GIMR2_IDLE (1 << 9) /* Device idle */
+#define GIMR2_DMAERR (1 << 8) /* DMA error */
+#define GIMR2_DMAFIN (1 << 7) /* DMA finished */
+#define GIMR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */
+#define GIMR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */
+#define GIMR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */
+#define GIMR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */
+#define GIMR2_RESUME (1 << 2) /* Resume state change Interrupt */
+#define GIMR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */
+#define GIMR2_RESET (1 << 0) /* Reset Interrupt */
+#define GIMR2_MASK 0x7ff
+
+/* Group Interrupt Status Register */
+#define GISR_GRP2 (1 << 2) /* Interrupt group 2 */
+#define GISR_GRP1 (1 << 1) /* Interrupt group 1 */
+#define GISR_GRP0 (1 << 0) /* Interrupt group 0 */
+
+/* Group Interrupt Status Register 0 (CX) */
+#define GISR0_CXABORT (1 << 5) /* CX command abort interrupt */
+#define GISR0_CXERR (1 << 4) /* CX command error interrupt */
+#define GISR0_CXEND (1 << 3) /* CX command end interrupt */
+#define GISR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */
+#define GISR0_CXIN (1 << 1) /* EP0-IN packet interrupt */
+#define GISR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */
+
+/* Group Interrupt Status Register 1 (FIFO) */
+#define GISR1_IN_FIFO(x) (1 << (((x) & 0x03) + 16)) /* FIFOx IN */
+#define GISR1_OUT_FIFO(x) (1 << (((x) & 0x03) * 2)) /* FIFOx OUT */
+#define GISR1_SPK_FIFO(x) (1 << (((x) & 0x03) * 2 + 1)) /* FIFOx SPK */
+#define GISR1_RX_FIFO(x) (3 << (((x) & 0x03) * 2)) /* FIFOx OUT/SPK */
+
+/* Group Interrupt Status Register 2 (Device) */
+#define GISR2_WAKEUP (1 << 10) /* Device waked up */
+#define GISR2_IDLE (1 << 9) /* Device idle */
+#define GISR2_DMAERR (1 << 8) /* DMA error */
+#define GISR2_DMAFIN (1 << 7) /* DMA finished */
+#define GISR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */
+#define GISR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */
+#define GISR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */
+#define GISR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */
+#define GISR2_RESUME (1 << 2) /* Resume state change Interrupt */
+#define GISR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */
+#define GISR2_RESET (1 << 0) /* Reset Interrupt */
+
+/* Receive Zero-Length-Packet Register */
+#define RXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP rx interrupt */
+
+/* Transfer Zero-Length-Packet Register */
+#define TXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP tx interrupt */
+
+/* ISOC Error/Abort Status Register */
+#define ISOEASR_EP(x) (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */
+
+/* IN Endpoint Register */
+#define IEP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */
+#define IEP_TNRHB(x) (((x) & 0x03) << 13) \
+ /* Transaction Number for High-Bandwidth EP(ISOC) */
+#define IEP_RESET (1 << 12) /* Reset Toggle Sequence */
+#define IEP_STALL (1 << 11) /* Stall */
+#define IEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */
+
+/* OUT Endpoint Register */
+#define OEP_RESET (1 << 12) /* Reset Toggle Sequence */
+#define OEP_STALL (1 << 11) /* Stall */
+#define OEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */
+
+/* Endpoint Map Register (EP1 ~ EP4) */
+#define EPMAP14_SET_IN(ep, fifo) \
+ ((fifo) & 3) << (((ep) - 1) << 3 + 0)
+#define EPMAP14_SET_OUT(ep, fifo) \
+ ((fifo) & 3) << (((ep) - 1) << 3 + 4)
+#define EPMAP14_SET(ep, in, out) \
+ do { \
+ EPMAP14_SET_IN(ep, in); \
+ EPMAP14_SET_OUT(ep, out); \
+ } while (0)
+
+#define EPMAP14_DEFAULT 0x33221100 /* EP1->FIFO0, EP2->FIFO1... */
+
+/* Endpoint Map Register (EP5 ~ EP8) */
+#define EPMAP58_SET_IN(ep, fifo) \
+ ((fifo) & 3) << (((ep) - 5) << 3 + 0)
+#define EPMAP58_SET_OUT(ep, fifo) \
+ ((fifo) & 3) << (((ep) - 5) << 3 + 4)
+#define EPMAP58_SET(ep, in, out) \
+ do { \
+ EPMAP58_SET_IN(ep, in); \
+ EPMAP58_SET_OUT(ep, out); \
+ } while (0)
+
+#define EPMAP58_DEFAULT 0x00000000 /* All EPx->FIFO0 */
+
+/* FIFO Map Register */
+#define FIFOMAP_BIDIR (2 << 4)
+#define FIFOMAP_IN (1 << 4)
+#define FIFOMAP_OUT (0 << 4)
+#define FIFOMAP_DIR_MASK 0x30
+#define FIFOMAP_EP(x) ((x) & 0x0f)
+#define FIFOMAP_EP_MASK 0x0f
+#define FIFOMAP_CFG_MASK 0x3f
+#define FIFOMAP_DEFAULT 0x04030201 /* FIFO0->EP1, FIFO1->EP2... */
+#define FIFOMAP(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3))
+
+/* FIFO Configuration Register */
+#define FIFOCFG_EN (1 << 5)
+#define FIFOCFG_BLKSZ_1024 (1 << 4)
+#define FIFOCFG_BLKSZ_512 (0 << 4)
+#define FIFOCFG_3BLK (2 << 2)
+#define FIFOCFG_2BLK (1 << 2)
+#define FIFOCFG_1BLK (0 << 2)
+#define FIFOCFG_NBLK_MASK 3
+#define FIFOCFG_NBLK_SHIFT 2
+#define FIFOCFG_INTR (3 << 0)
+#define FIFOCFG_BULK (2 << 0)
+#define FIFOCFG_ISOC (1 << 0)
+#define FIFOCFG_RSVD (0 << 0) /* Reserved */
+#define FIFOCFG_TYPE_MASK 3
+#define FIFOCFG_TYPE_SHIFT 0
+#define FIFOCFG_CFG_MASK 0x3f
+#define FIFOCFG(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3))
+
+/* FIFO Control Status Register */
+#define FIFOCSR_RESET (1 << 12) /* FIFO Reset */
+#define FIFOCSR_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */
+
+/* DMA Target FIFO Register */
+#define DMAFIFO_CX (1 << 4) /* DMA FIFO = CX FIFO */
+#define DMAFIFO_FIFO(x) (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */
+
+/* DMA Control Register */
+#define DMACTRL_LEN(x) (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */
+#define DMACTRL_LEN_SHIFT 8
+#define DMACTRL_CLRFF (1 << 4) /* Clear FIFO upon DMA abort */
+#define DMACTRL_ABORT (1 << 3) /* DMA abort */
+#define DMACTRL_IO2IO (1 << 2) /* IO to IO */
+#define DMACTRL_FIFO2MEM (0 << 1) /* FIFO to Memory */
+#define DMACTRL_MEM2FIFO (1 << 1) /* Memory to FIFO */
+#define DMACTRL_START (1 << 0) /* DMA start */
+
+#endif
diff --git a/include/usb/fusbh200.h b/include/usb/fusbh200.h
new file mode 100644
index 0000000..8a9c488
--- /dev/null
+++ b/include/usb/fusbh200.h
@@ -0,0 +1,61 @@
+/*
+ * Faraday USB 2.0 EHCI Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef _FUSBH200_H
+#define _FUSBH200_H
+
+struct fusbh200_regs {
+ struct {
+ uint32_t data[4];
+ } hccr; /* 0x00 - 0x0f: hccr */
+ struct {
+ uint32_t data[9];
+ } hcor; /* 0x10 - 0x33: hcor */
+ uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */
+ uint32_t rsvd[2];
+ uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */
+ uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */
+ uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */
+};
+
+/* EOF & Async. Schedule Sleep Timer Register */
+#define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */
+#define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */
+#define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */
+#define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */
+#define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
+
+/* Bus Monitor Control Status Register */
+#define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */
+#define BMCSR_SPD_LOW (1 << 9)
+#define BMCSR_SPD_FULL (0 << 9)
+#define BMCSR_SPD_MASK (3 << 9)
+#define BMCSR_SPD_SHIFT 9
+#define BMCSR_SPD(x) ((x >> 9) & 0x03)
+#define BMCSR_VBUS (1 << 8) /* VBUS Valid */
+#define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */
+#define BMCSR_VBUS_ON (0 << 4) /* VBUS On */
+#define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */
+#define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */
+#define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */
+#define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/
+#define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/
+#define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/
+#define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/
+
+/* Bus Monitor Interrupt Status Register */
+/* Bus Monitor Interrupt Enable Register */
+#define BMISR_DMAERR (1 << 4) /* DMA error */
+#define BMISR_DMA (1 << 3) /* DMA complete */
+#define BMISR_DEVRM (1 << 2) /* device removed */
+#define BMISR_OVD (1 << 1) /* over-current detected */
+#define BMISR_VBUSERR (1 << 0) /* VBUS error */
+
+#endif
diff --git a/lib/Makefile b/lib/Makefile
index 5d58609..a94830f 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -26,7 +26,6 @@
LIB = $(obj)libgeneric.o
ifndef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
COBJS-$(CONFIG_AES) += aes.o
COBJS-$(CONFIG_BZIP2) += bzlib.o
COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o
@@ -36,13 +35,10 @@
COBJS-$(CONFIG_USB_TTY) += circbuf.o
COBJS-y += crc7.o
COBJS-y += crc16.o
-COBJS-y += display_options.o
-COBJS-y += errno.o
COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o
COBJS-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
COBJS-$(CONFIG_GZIP) += gunzip.o
COBJS-$(CONFIG_GZIP_COMPRESSED) += gzip.o
-COBJS-y += hashtable.o
COBJS-y += initcall.o
COBJS-$(CONFIG_LMB) += lmb.o
COBJS-y += ldiv.o
@@ -60,14 +56,12 @@
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += crc32.o
-ifneq ($(CONFIG_SPL_SPI_FLASH_SUPPORT)$(CONFIG_SPL_NET_SUPPORT),)
-COBJS-y += display_options.o
-endif
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += errno.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
endif
+COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
+COBJS-y += hashtable.o
+COBJS-y += errno.o
+COBJS-y += display_options.o
COBJS-$(CONFIG_BCH) += bch.o
COBJS-y += crc32.o
COBJS-y += ctype.o
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 005ad3d..ad25a0c 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -62,6 +62,7 @@
COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
+ COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile
deleted file mode 100644
index f7bdf92..0000000
--- a/nand_spl/board/freescale/p1010rdb/Makefile
+++ /dev/null
@@ -1,142 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2011 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-NAND_SPL := y
-CONFIG_SYS_TEXT_BASE_SPL := 0xff800000
-PAD_TO := 0xff802000
-
-include $(TOPDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o ticks.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
-
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)cache.c:
- @rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
- @rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
- @rm -f $(obj)spl_minimal.c
- ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
- @rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
- @rm -f $(obj)law.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_ifc.c:
- @rm -f $(obj)nand_boot_fsl_ifc.c
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \
- $(obj)nand_boot_fsl_ifc.c
-
-$(obj)ns16550.c:
- @rm -f $(obj)ns16550.c
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
-
-$(obj)fixed_ivor.S:
- @rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
-
-$(obj)start.S: $(obj)fixed_ivor.S
- @rm -f $(obj)start.S
- ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
-
-$(obj)ticks.S:
- @rm -f $(obj)ticks.S
- ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
-
-$(obj)tlb.c:
- @rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
-
-$(obj)tlb_table.c:
- @rm -f $(obj)tlb_table.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/net/net.c b/net/net.c
index df94789..7663b9c 100644
--- a/net/net.c
+++ b/net/net.c
@@ -271,7 +271,8 @@
#endif
env_changed_id = env_id;
}
- memcpy(NetOurEther, eth_get_dev()->enetaddr, 6);
+ if (eth_get_dev())
+ memcpy(NetOurEther, eth_get_dev()->enetaddr, 6);
return;
}
diff --git a/spl/Makefile b/spl/Makefile
index 8b655c4..01873de 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -88,7 +88,7 @@
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+ifneq (,$(CONFIG_MX23)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
@@ -102,6 +102,10 @@
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
+ifeq ($(SOC),exynos)
+LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
+endif
+
# Add GCC lib
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
diff --git a/tools/Makefile b/tools/Makefile
index 26eb500..4630f03 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -130,27 +130,20 @@
LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H)
LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_DATA_H)
+# Generic logo
ifeq ($(LOGO_BMP),)
LOGO_BMP= logos/denx.bmp
+
+# Use board logo and fallback to vendor
+ifneq ($(wildcard logos/$(BOARD).bmp),)
+LOGO_BMP= logos/$(BOARD).bmp
+else
+ifneq ($(wildcard logos/$(VENDOR).bmp),)
+LOGO_BMP= logos/$(VENDOR).bmp
endif
-ifeq ($(VENDOR),atmel)
-LOGO_BMP= logos/atmel.bmp
endif
-ifeq ($(VENDOR),esd)
-LOGO_BMP= logos/esd.bmp
-endif
-ifeq ($(VENDOR),freescale)
-LOGO_BMP= logos/freescale.bmp
-endif
-ifeq ($(VENDOR),ronetix)
-LOGO_BMP= logos/ronetix.bmp
-endif
-ifeq ($(VENDOR),syteco)
-LOGO_BMP= logos/syteco.bmp
-endif
-ifeq ($(VENDOR),intercontrol)
-LOGO_BMP= logos/intercontrol.bmp
-endif
+
+endif # !LOGO_BMP
# now $(obj) is defined
HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
diff --git a/tools/logos/wandboard.bmp b/tools/logos/wandboard.bmp
new file mode 100644
index 0000000..7f288a8
--- /dev/null
+++ b/tools/logos/wandboard.bmp
Binary files differ
diff --git a/tools/pblimage.c b/tools/pblimage.c
index 508a747..5f39dc5 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -26,18 +26,14 @@
#include "pblimage.h"
/*
- * The PBL can load up to 64 bytes at a time, so we split the U-Boot
- * image into 64 byte chunks. PBL needs a command for each piece, of
- * the form "81xxxxxx", where "xxxxxx" is the offset. SYS_TEXT_BASE
- * is 0xFFF80000 for PBL boot, and PBL only cares about low 24-bit,
- * so it starts from 0x81F80000.
+ * Initialize to an invalid value.
*/
-static uint32_t next_pbl_cmd = 0x81F80000;
+static uint32_t next_pbl_cmd = 0x82000000;
/*
* need to store all bytes in memory for calculating crc32, then write the
* bytes to image file for PBL boot.
*/
-static unsigned char mem_buf[600000];
+static unsigned char mem_buf[1000000];
static unsigned char *pmem_buf = mem_buf;
static int pbl_size;
static char *fname = "Unknown";
@@ -52,6 +48,27 @@
#define ENDIANNESS ((char)endian_test.l)
+/*
+ * The PBL can load up to 64 bytes at a time, so we split the U-Boot
+ * image into 64 byte chunks. PBL needs a command for each piece, of
+ * the form "81xxxxxx", where "xxxxxx" is the offset. Calculate the
+ * start offset by subtracting the size of the u-boot image from the
+ * top of the allowable 24-bit range.
+ */
+static void init_next_pbl_cmd(FILE *fp_uboot)
+{
+ struct stat st;
+ int fd = fileno(fp_uboot);
+
+ if (fstat(fd, &st) == -1) {
+ printf("Error: Could not determine u-boot image size. %s\n",
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ next_pbl_cmd = 0x82000000 - st.st_size;
+}
+
static void generate_pbl_cmd(void)
{
uint32_t val = next_pbl_cmd;
@@ -80,6 +97,7 @@
/* load split u-boot with PBI command 81xxxxxx. */
static void load_uboot(FILE *fp_uboot)
{
+ init_next_pbl_cmd(fp_uboot);
while (next_pbl_cmd < 0x82000000) {
generate_pbl_cmd();
pbl_fget(64, fp_uboot);
