ipq40xx: Added emmc clk reset during mmc deinit

1. Added emmc clk reset during mmc deinitialization to 
avoid the mmc init failure in kernal bootup. 
2. Clock has been configured to 192 Mhz for SDHCI mode
3. Proper register is used for disabling emmc clock

Change-Id: Id21e294380ee904027e5d6d2b2929acbd7bac672
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
2 files changed