diff --git a/board/qca/arm/ipq40xx/ipq40xx.c b/board/qca/arm/ipq40xx/ipq40xx.c
index 1fb020d..07c679c 100644
--- a/board/qca/arm/ipq40xx/ipq40xx.c
+++ b/board/qca/arm/ipq40xx/ipq40xx.c
@@ -248,7 +248,7 @@
 void emmc_clock_reset(void)
 {
 	writel(0x1, GCC_SDCC1_BCR);
-	udelay(10);
+	udelay(100);
 	writel(0x0, GCC_SDCC1_BCR);
 }
 
@@ -315,6 +315,8 @@
 
 void board_mmc_deinit(void)
 {
+	emmc_clock_reset();
+	udelay(10);
 	emmc_clock_disable();
 }
 #endif
diff --git a/drivers/clk/ipq40xx_clk.c b/drivers/clk/ipq40xx_clk.c
index cc4439c..01620be 100644
--- a/drivers/clk/ipq40xx_clk.c
+++ b/drivers/clk/ipq40xx_clk.c
@@ -50,11 +50,21 @@
 		writel(0x1, GCC_SDCC1_APPS_CBCR);
 		udelay(10);
 	}
+	if (mode == MMC_DATA_TRANSFER_SDHCI_MODE) {
+		/* Set root clock generator to bypass mode */
+		writel(0x0, GCC_SDCC1_APPS_CBCR);
+		udelay(10);
+		/* Choose divider for 192MHz */
+		writel(0x0, GCC_SDCC1_MISC);
+		/* Enable root clock generator */
+		writel(0x1, GCC_SDCC1_APPS_CBCR);
+		udelay(10);
+	}
 }
 void emmc_clock_disable(void)
 {
-	/* Clear divider */
-	writel(0x0, GCC_SDCC1_MISC);
+	writel(0x0, GCC_SDCC1_APPS_CBCR);
+	udelay(10);
 
 }