qca: Adding device tree support for qpic-nand
Sets qpic-nand base address by reading from device tree using the
compatible string
Change-Id: I6e23ea579d9472fc9c977f9b549c312d61e9402b
Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
diff --git a/board/qca/ipq40xx/ipq40xx.c b/board/qca/ipq40xx/ipq40xx.c
index db3f78e..059a9ac 100644
--- a/board/qca/ipq40xx/ipq40xx.c
+++ b/board/qca/ipq40xx/ipq40xx.c
@@ -25,6 +25,7 @@
#include <asm/arch-qcom-common/scm.h>
#include <asm/arch-qcom-common/qpic_nand.h>
#include <jffs2/load_kernel.h>
+#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -343,11 +344,27 @@
{
struct qpic_nand_init_config config;
gpio_func_data_t *gpio;
+ int node;
+ fdt_addr_t nand_base;
#ifdef CONFIG_IPQ40XX_SPI
ipq_spi_init(CONFIG_IPQ_SPI_NOR_INFO_IDX);
#endif
+ node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_QCOM_QPIC_NAND_V1_4_20);
+
+ if (node < 0) {
+ printf("Could not find nand-flash in device tree\n");
+ return;
+ }
+
+ nand_base = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+
+ if (nand_base == FDT_ADDR_T_NONE) {
+ printf("No valid NAND base address found in device tree\n");
+ return;
+ }
config.pipes.read_pipe = DATA_PRODUCER_PIPE;
config.pipes.write_pipe = DATA_CONSUMER_PIPE;
config.pipes.cmd_pipe = CMD_PIPE;
@@ -357,7 +374,7 @@
config.pipes.cmd_pipe_grp = CMD_PIPE_GRP;
config.bam_base = QPIC_BAM_CTRL_BASE;
- config.nand_base = IPQ40xx_EBI2ND_BASE;
+ config.nand_base = nand_base;
config.ee = QPIC_NAND_EE;
config.max_desc_len = QPIC_NAND_MAX_DESC_LEN;
diff --git a/board/qca/ipq807x/ipq807x.c b/board/qca/ipq807x/ipq807x.c
index 30bf223..a476abd 100644
--- a/board/qca/ipq807x/ipq807x.c
+++ b/board/qca/ipq807x/ipq807x.c
@@ -112,14 +112,22 @@
{
int node;
+ fdt_addr_t nand_base;
node = fdtdec_next_compatible(gd->fdt_blob, 0,
- COMPAT_QCOM_QPIC_NAND);
+ COMPAT_QCOM_QPIC_NAND_V1_5_20);
if (node < 0) {
printf("Could not find nand-flash in device tree\n");
return;
}
+ nand_base = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+
+ if (nand_base == FDT_ADDR_T_NONE) {
+ printf("No valid NAND base address found in device tree\n");
+ return;
+ }
+
struct qpic_nand_init_config config;
config.pipes.read_pipe = DATA_PRODUCER_PIPE;
@@ -131,7 +139,7 @@
config.pipes.cmd_pipe_grp = CMD_PIPE_GRP;
config.bam_base = QPIC_BAM_CTRL_BASE;
- config.nand_base = fdtdec_get_addr(gd->fdt_blob, node, "reg");;
+ config.nand_base = nand_base;
config.ee = QPIC_NAND_EE;
config.max_desc_len = QPIC_NAND_MAX_DESC_LEN;
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 51811b4..c55bf7f 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -170,7 +170,8 @@
COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
- COMPAT_QCOM_QPIC_NAND, /* Qualcomm QPIC NAND controller */
+ COMPAT_QCOM_QPIC_NAND_V1_5_20, /* Qualcomm QPIC NAND controller */
+ COMPAT_QCOM_QPIC_NAND_V1_4_20, /* Qualcomm QPIC NAND controller */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index e906ab3..3ed8b9c 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -75,7 +75,8 @@
COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
- COMPAT(QCOM_QPIC_NAND, "qcom,qpic-nand.1.5.20"),
+ COMPAT(COMPAT_QCOM_QPIC_NAND_V1_5_20, "qcom,qpic-nand.1.5.20"),
+ COMPAT(COMPAT_QCOM_QPIC_NAND_V1_4_20, "qcom,qpic-nand.1.4.20"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)