tree 5483a1fbc3b8e885b3a16cf60149c888609e6ce8
parent 0118033b6700fc96a84a8c0593af3cbe2f10a6dc
author York Sun <yorksun@freescale.com> 1351269614 +0000
committer Andy Fleming <afleming@freescale.com> 1354062486 -0600

powerpc/corenet_ds: Update DDR timing for single-rank DIMMs

Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>