diff --git a/MAINTAINERS b/MAINTAINERS
index 59d3aec..a5d5835 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -862,6 +862,7 @@
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
+	nios2-generic	Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index 95ac60f..34bc4a1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -831,6 +831,7 @@
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
+	nios2-generic	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 0f1601e..25e3b8c 100644
--- a/Makefile
+++ b/Makefile
@@ -3537,6 +3537,12 @@
 PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
+# nios2 generic boards
+NIOS2_GENERIC = nios2-generic
+
+$(NIOS2_GENERIC:%=%_config) : unconfig
+	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
+
 #========================================================================
 ## Microblaze
 #========================================================================
diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk
index f455982..8e5d6ef 100644
--- a/arch/nios2/config.mk
+++ b/arch/nios2/config.mk
@@ -29,4 +29,4 @@
 PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__
 PLATFORM_CPPFLAGS += -ffixed-r15 -G0
 
-LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S
index 31cd5b0..d1016ea 100644
--- a/arch/nios2/cpu/start.S
+++ b/arch/nios2/cpu/start.S
@@ -34,6 +34,7 @@
 	.global _start
 
 _start:
+	wrctl	status, r0		/* Disable interrupts */
 	/* ICACHE INIT -- only the icache line at the reset address
 	 * is invalidated at reset. So the init must stay within
 	 * the cache line size (8 words). If GERMS is used, we'll
@@ -43,10 +44,9 @@
 	ori	r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
 	movhi	r5, %hi(CONFIG_SYS_ICACHE_SIZE)
 	ori	r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
-	mov	r6, r0
-0:	initi	r6
-	add	r6, r6, r4
-	bltu	r6, r5, 0b
+0:	initi	r5
+	sub	r5, r5, r4
+	bgt	r5, r0, 0b
 	br	_except_end	/* Skip the tramp */
 
 	/* EXCEPTION TRAMPOLINE -- the following gets copied
@@ -62,7 +62,6 @@
 	/* INTERRUPTS -- for now, all interrupts masked and globally
 	 * disabled.
 	 */
-	wrctl	status, r0		/* Disable interrupts */
 	wrctl	ienable, r0		/* All disabled	*/
 
 	/* DCACHE INIT -- if dcache not implemented, initd behaves as
diff --git a/arch/nios2/include/asm/byteorder.h b/arch/nios2/include/asm/byteorder.h
index 495c823..d5c152e 100644
--- a/arch/nios2/include/asm/byteorder.h
+++ b/arch/nios2/include/asm/byteorder.h
@@ -25,6 +25,12 @@
 #define __ASM_NIOS2_BYTEORDER_H_
 
 #include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
 #include <linux/byteorder/little_endian.h>
 
 #endif /* __ASM_NIOS2_BYTEORDER_H_ */
diff --git a/arch/nios2/include/asm/dma-mapping.h b/arch/nios2/include/asm/dma-mapping.h
new file mode 100644
index 0000000..1350e3b
--- /dev/null
+++ b/arch/nios2/include/asm/dma-mapping.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_NIOS2_DMA_MAPPING_H
+#define __ASM_NIOS2_DMA_MAPPING_H
+
+/* dma_alloc_coherent() return cache-line aligned allocation which is mapped
+ * to uncached io region.
+ *
+ * IO_REGION_BASE should be defined in board config header file
+ *   0x80000000 for nommu, 0xe0000000 for mmu
+ */
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE);
+	if (!addr)
+		return 0;
+	flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE);
+	*handle = ((unsigned long)addr +
+		   (CONFIG_SYS_DCACHELINE_SIZE - 1)) &
+		~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE);
+	return (void *)(*handle | IO_REGION_BASE);
+}
+
+#endif /* __ASM_NIOS2_DMA_MAPPING_H */
diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c
index 8ec66a3..f83e691 100644
--- a/arch/nios2/lib/board.c
+++ b/arch/nios2/lib/board.c
@@ -28,6 +28,7 @@
 #include <stdio_dev.h>
 #include <watchdog.h>
 #include <malloc.h>
+#include <mmc.h>
 #include <net.h>
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
@@ -35,6 +36,9 @@
 #if defined(CONFIG_SYS_NIOS_EPCSBASE)
 #include <nios2-epcs.h>
 #endif
+#ifdef CONFIG_CMD_NAND
+#include <nand.h>	/* cannot even include nand.h if it isnt configured */
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -100,7 +104,9 @@
 	bd = gd->bd;
 	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
 	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_SYS_NO_FLASH
 	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
 #if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
 	bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
 	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
@@ -119,8 +125,20 @@
 	/* The Malloc area is immediately below the monitor copy in RAM */
 	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
 
+#ifndef CONFIG_SYS_NO_FLASH
 	WATCHDOG_RESET ();
 	bd->bi_flashsize = flash_init();
+#endif
+
+#ifdef CONFIG_CMD_NAND
+	puts("NAND:  ");
+	nand_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(bd);
+#endif
 
 	WATCHDOG_RESET ();
 	env_relocate();
diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c
index 64033fe..fecfc80 100644
--- a/arch/powerpc/cpu/mpc83xx/serdes.c
+++ b/arch/powerpc/cpu/mpc83xx/serdes.c
@@ -15,7 +15,7 @@
 #include <config.h>
 #include <common.h>
 #include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
 
 /* SerDes registers */
 #define FSL_SRDSCR0_OFFS		0x0
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 0cc6e03..fddeb2f 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
  * (C) Copyright 2002, 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
@@ -44,21 +44,19 @@
 	uint major, minor;
 	struct cpu_type *cpu;
 	char buf1[32], buf2[32];
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif /* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
+	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+#else
 #ifdef CONFIG_FSL_CORENET
 	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
 		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
 #else
-	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
-		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#endif
-#else
-#ifdef CONFIG_FSL_CORENET
-	u32 ddr_sync = 0;
-#else
 	u32 ddr_ratio = 0;
-#endif
+#endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
 	int i;
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e0126d3..e578b29 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -180,54 +180,54 @@
 	 * has been determined
 	 */
 #if defined(CONFIG_SYS_OR0_REMAP)
-	memctl->or0 = CONFIG_SYS_OR0_REMAP;
+	out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
 #endif
 #if defined(CONFIG_SYS_OR1_REMAP)
-	memctl->or1 = CONFIG_SYS_OR1_REMAP;
+	out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
 #endif
 
 	/* now restrict to preliminary range */
 	/* if cs1 is already set via debugger, leave cs0/cs1 alone */
 	if (! memctl->br1 & 1) {
 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
-		memctl->br0 = CONFIG_SYS_BR0_PRELIM;
-		memctl->or0 = CONFIG_SYS_OR0_PRELIM;
+		out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
+		out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
-		memctl->or1 = CONFIG_SYS_OR1_PRELIM;
-		memctl->br1 = CONFIG_SYS_BR1_PRELIM;
+		out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
+		out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
 #endif
 	}
 
 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
-	memctl->or2 = CONFIG_SYS_OR2_PRELIM;
-	memctl->br2 = CONFIG_SYS_BR2_PRELIM;
+	out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
+	out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
-	memctl->or3 = CONFIG_SYS_OR3_PRELIM;
-	memctl->br3 = CONFIG_SYS_BR3_PRELIM;
+	out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
+	out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
-	memctl->or4 = CONFIG_SYS_OR4_PRELIM;
-	memctl->br4 = CONFIG_SYS_BR4_PRELIM;
+	out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
+	out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
-	memctl->or5 = CONFIG_SYS_OR5_PRELIM;
-	memctl->br5 = CONFIG_SYS_BR5_PRELIM;
+	out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
+	out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
-	memctl->or6 = CONFIG_SYS_OR6_PRELIM;
-	memctl->br6 = CONFIG_SYS_BR6_PRELIM;
+	out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
+	out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
-	memctl->or7 = CONFIG_SYS_OR7_PRELIM;
-	memctl->br7 = CONFIG_SYS_BR7_PRELIM;
+	out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
+	out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
 #endif
 
 #if defined(CONFIG_CPM2)
@@ -260,6 +260,10 @@
 
 int cpu_init_r(void)
 {
+#ifdef CONFIG_SYS_LBC_LCRR
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+#endif
+
 	puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)
@@ -383,6 +387,17 @@
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif
+
+#ifdef CONFIG_SYS_LBC_LCRR
+	/*
+	 * Modify the CLKDIV field of LCRR register to improve the writing
+	 * speed for NOR flash.
+	 */
+	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
+	__raw_readl(&lbc->lcrr);
+	isync();
+#endif
+
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 268edbc..8132115 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
@@ -71,22 +71,30 @@
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
 	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
+	uint ratio[4];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	uint mem_pll_rat;
 
 	sysInfo->freqSystemBus = sysclk;
 	sysInfo->freqDDRBus = sysclk;
-	freqCC_PLL[0] = sysclk;
-	freqCC_PLL[1] = sysclk;
-	freqCC_PLL[2] = sysclk;
-	freqCC_PLL[3] = sysclk;
 
 	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
-	freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
-	freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
-	freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
-	freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+	if (mem_pll_rat > 2)
+		sysInfo->freqDDRBus *= mem_pll_rat;
+	else
+		sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
 
+	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
+	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
+	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
+	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+	for (i = 0; i < 4; i++) {
+		if (ratio[i] > 4)
+			freqCC_PLL[i] = sysclk * ratio[i];
+		else
+			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
+	}
 	rcw_tmp = in_be32(&gur->rcwsr[3]);
 	for (i = 0; i < cpu_numcores(); i++) {
 		u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 03f9c43..4a282bc 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -198,6 +198,8 @@
 	pre_pd_exit_mclk = act_pd_exit_mclk;
 	taxpd_mclk = 8;
 	tmrd_mclk = 4;
+	/* set the turnaround time */
+	trwt_mclk = 1;
 #else /* CONFIG_FSL_DDR2 */
 	/*
 	 * (tXARD and tXARDS). Empirical?
diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
index 9b7181d..85995ca 100644
--- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
+++ b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
@@ -176,15 +176,14 @@
 			 (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
 	},
 	[LAW_TRGT_IF_PCIE_2] = {
-		.cfg =   (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
-			 (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
-			 (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
-			 (1 << 0x18) | (1 << 0x1c),
+		.cfg =   (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
+			 (1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
+			 (1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
 	},
 	[LAW_TRGT_IF_PCIE_3] = {
-		.cfg =   (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
-			 (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
-			 (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
+		.cfg =   (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
+			 (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) |
+			 (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c),
 	},
 };
 #elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 3216a50..02920db 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -24,6 +24,12 @@
 #define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
 #define DDR_BL8		8	/* burst length 8 */
 
+#define DDR3_RTT_60_OHM		1 /* RTT_Nom = RZQ/4 */
+#define DDR3_RTT_120_OHM	2 /* RTT_Nom = RZQ/2 */
+#define DDR3_RTT_40_OHM		3 /* RTT_Nom = RZQ/6 */
+#define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
+#define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */
+
 #if defined(CONFIG_FSL_DDR1)
 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 5723de6..dfe8f79 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -125,8 +125,12 @@
 #define OR_GPCM_SETA_SHIFT		3
 #define OR_GPCM_TRLX			0x00000004
 #define OR_GPCM_TRLX_SHIFT		2
+#define OR_GPCM_TRLX_CLEAR		0x00000000
+#define OR_GPCM_TRLX_SET		0x00000004
 #define OR_GPCM_EHTR			0x00000002
 #define OR_GPCM_EHTR_SHIFT		1
+#define OR_GPCM_EHTR_CLEAR		0x00000000
+#define OR_GPCM_EHTR_SET		0x00000002
 #define OR_GPCM_EAD			0x00000001
 #define OR_GPCM_EAD_SHIFT		0
 
diff --git a/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h
new file mode 100644
index 0000000..2d813f4
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_MPC83XX_SERDES_H
+#define __FSL_MPC83XX_SERDES_H
+
+#include <config.h>
+
+#define FSL_SERDES_CLK_100		(0 << 28)
+#define FSL_SERDES_CLK_125		(1 << 28)
+#define FSL_SERDES_CLK_150		(3 << 28)
+#define FSL_SERDES_PROTO_SATA		0
+#define FSL_SERDES_PROTO_PEX		1
+#define FSL_SERDES_PROTO_PEX_X2		2
+#define FSL_SERDES_PROTO_SGMII		3
+#define FSL_SERDES_VDD_1V		1
+
+extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
+
+#endif /* __FSL_MPC83XX_SERDES_H */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 957ad76..e7954e6 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1,7 +1,7 @@
 /*
  * MPC85xx Internal Memory Map
  *
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
  *
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
@@ -1647,7 +1647,7 @@
 	u8	res4[12];
 	u32	gpindr;		/* General-purpose input data */
 	u8	res5[12];
-	u32	pmuxcr;		/* Alt function signal multiplex control */
+	u32	alt_pmuxcr;	/* Alt function signal multiplex control */
 	u8	res6[12];
 	u32	devdisr;	/* Device disable control */
 #define FSL_CORENET_DEVDISR_PCIE1	0x80000000
@@ -1672,7 +1672,23 @@
 #define FSL_CORENET_DEVDISR_I2C2	0x00000010
 #define FSL_CORENET_DEVDISR_DUART1	0x00000002
 #define FSL_CORENET_DEVDISR_DUART2	0x00000001
-	u8	res7[12];
+	u32	devdisr2;	/* Device disable control 2 */
+#define FSL_CORENET_DEVDISR2_PME	0x80000000
+#define FSL_CORENET_DEVDISR2_SEC	0x40000000
+#define FSL_CORENET_DEVDISR2_QMBM	0x08000000
+#define FSL_CORENET_DEVDISR2_FM1	0x02000000
+#define FSL_CORENET_DEVDISR2_10GEC1	0x01000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_1	0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2	0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3	0x00200000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4	0x00100000
+#define FSL_CORENET_DEVDISR2_FM2	0x00020000
+#define FSL_CORENET_DEVDISR2_10GEC2	0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00002000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00001000
+	u8	res7[8];
 	u32	powmgtcsr;	/* Power management status & control */
 	u8	res8[12];
 	u32	coredisru;	/* uppper portion for support of 64 cores */
@@ -1697,8 +1713,9 @@
 	u8	res17[24];
 	u32	rcwsr[16];	/* Reset control word status */
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
-#define FSL_CORENET_RCWSR5_DDR_SYNC		0x00008000
-#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		15
+#define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
+#define FSL_CORENET_RCWSR5_SRDS_EN		0x00002000
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000
@@ -1750,7 +1767,17 @@
 	u32	cgencrl;	/* Core general control */
 	u8	res31[184];
 	u32	sriopstecr;	/* SRIO prescaler timer enable control */
-	u8	res32[2300];
+	u8	res32[1788];
+	u32	pmuxcr;		/* Pin multiplexing control */
+	u8	res33[60];
+	u32	iovselsr;	/* I/O voltage selection status */
+	u8	res34[28];
+	u32	ddrclkdr;	/* DDR clock disable */
+	u8	res35;
+	u32	elbcclkdr;	/* eLBC clock disable */
+	u8	res36[20];
+	u32	sdhcpcr;	/* eSDHC polarity configuration */
+	u8	res37[380];
 } ccsr_gur_t;
 
 typedef struct ccsr_clk {
@@ -1846,8 +1873,13 @@
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL	0x38000000
 #define MPC85xx_PORDEVSR_PCI1		0x00800000
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PORDEVSR_IO_SEL		0x007c0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	18
+#else
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19
+#endif
 #define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
 #define MPC85xx_PORDEVSR_PCI1_PCI32	0x00010000
@@ -1942,7 +1974,15 @@
 #define SRDS_RSTCTL_RST		0x80000000
 #define SRDS_RSTCTL_RSTDONE	0x40000000
 #define SRDS_RSTCTL_RSTERR	0x20000000
+#define SRDS_RSTCTL_SDPD	0x00000020
 		u32	pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x00030000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_6_25	0x00010000
 		u32	pllcr1; /* PLL Control Register 1 */
 #define SRDS_PLLCR1_PLL_BWSEL	0x08000000
 		u32	res[5];
@@ -2018,6 +2058,7 @@
 #define CONFIG_SYS_MPC85xx_USB_OFFSET		0x210000
 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET	0x318000
 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET	0x31a000
+#define CONFIG_SYS_TSEC1_OFFSET			0x4e0000 /* FM1@DTSEC0 */
 #else
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x2000
diff --git a/board/altera/common/cfide.c b/board/altera/common/cfide.c
new file mode 100644
index 0000000..40d6a12
--- /dev/null
+++ b/board/altera/common/cfide.c
@@ -0,0 +1,33 @@
+/*
+ * Altera CF drvier
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_IDE_RESET) && defined(CONFIG_SYS_CF_CTL_BASE)
+/* ide_set_reset for Altera CF interface */
+#define ALTERA_CF_CTL_STATUS			0
+#define ALTERA_CF_IDE_CTL			4
+#define ALTERA_CF_CTL_STATUS_PRESENT_MSK	(0x1)
+#define ALTERA_CF_CTL_STATUS_POWER_MSK		(0x2)
+#define ALTERA_CF_CTL_STATUS_RESET_MSK		(0x4)
+#define ALTERA_CF_CTL_STATUS_IRQ_EN_MSK	(0x8)
+#define ALTERA_CF_IDE_CTL_IRQ_EN_MSK		(0x1)
+
+void ide_set_reset(int idereset)
+{
+	int i;
+	writel(idereset ? ALTERA_CF_CTL_STATUS_RESET_MSK :
+	       ALTERA_CF_CTL_STATUS_POWER_MSK,
+	       CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS);
+	/* wait 500 ms for power to stabilize */
+	for (i = 0; i < 500; i++)
+		udelay(1000);
+}
+#endif
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
new file mode 100644
index 0000000..6780872
--- /dev/null
+++ b/board/altera/nios2-generic/Makefile
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
+COBJS-$(CONFIG_EPLED) += ../common/epled.o
+COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
+
+SOBJS-y	:= text_base.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
new file mode 100644
index 0000000..d500133
--- /dev/null
+++ b/board/altera/nios2-generic/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# we get text_base from board config header, so do not use this
+#TEXT_BASE = do-not-use-me
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
new file mode 100644
index 0000000..761f605
--- /dev/null
+++ b/board/altera/nios2-generic/custom_fpga.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is generated by sopc-create-config-files.
+ */
+#ifndef _CUSTOM_FPGA_H_
+#define _CUSTOM_FPGA_H_
+
+/* generated from std_1c20.sopc */
+
+/* cpu.data_master is a altera_nios2 */
+#define CONFIG_SYS_CLK_FREQ 50000000
+#define CONFIG_SYS_RESET_ADDR 0x00000000
+#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
+#define CONFIG_SYS_ICACHE_SIZE 4096
+#define CONFIG_SYS_ICACHELINE_SIZE 32
+#define CONFIG_SYS_DCACHE_SIZE 2048
+#define CONFIG_SYS_DCACHELINE_SIZE 4
+
+/* sdram.s1 is a altera_avalon_new_sdram_controller */
+#define CONFIG_SYS_SDRAM_BASE 0x01000000
+#define CONFIG_SYS_SDRAM_SIZE 0x01000000
+
+/* uart1.s1 is a altera_avalon_uart */
+#define CONFIG_SYS_UART_BASE 0x82120840
+#define CONFIG_SYS_UART_FREQ 50000000
+#define CONFIG_SYS_UART_BAUD 115200
+
+/* lan91c111.s1 is a altera_avalon_lan91c111 */
+#define CONFIG_SMC91111_BASE 0x82110300
+#define CONFIG_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+
+/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
+#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
+
+/* led_pio.s1 is a altera_avalon_pio */
+#define LED_PIO_BASE 0x82120870
+
+/* high_res_timer.s1 is a altera_avalon_timer */
+#define CONFIG_SYS_TIMER_BASE 0x82120820
+#define CONFIG_SYS_TIMER_IRQ 3
+#define CONFIG_SYS_TIMER_FREQ 50000000
+
+/* ext_flash.s1 is a altera_avalon_cfi_flash */
+#define CONFIG_SYS_FLASH_BASE 0x80000000
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+
+/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
+#define CONFIG_SYS_SRAM_BASE 0x02000000
+#define CONFIG_SYS_SRAM_SIZE 0x00100000
+
+/* sysid.control_slave is a altera_avalon_sysid */
+#define CONFIG_SYS_SYSID_BASE 0x821208b8
+
+#endif /* _CUSTOM_FPGA_H_ */
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
new file mode 100644
index 0000000..89848cf
--- /dev/null
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+void text_base_hook(void); /* nop hook for text_base.S */
+
+int board_early_init_f(void)
+{
+	text_base_hook();
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("BOARD : %s\n", CONFIG_BOARD_NAME);
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	rc += dm9000_initialize(bis);
+#endif
+#ifdef CONFIG_ALTERA_TSE
+	rc += altera_tse_initialize(0,
+				    CONFIG_SYS_ALTERA_TSE_MAC_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE);
+#endif
+#ifdef CONFIG_ETHOC
+	rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/board/altera/nios2-generic/text_base.S b/board/altera/nios2-generic/text_base.S
new file mode 100644
index 0000000..f236db1
--- /dev/null
+++ b/board/altera/nios2-generic/text_base.S
@@ -0,0 +1,21 @@
+/*
+ * text_base
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <config.h>
+
+#ifdef CONFIG_SYS_MONITOR_BASE
+	.text
+	/* text base used in link script u-boot.lds */
+	.global text_base
+	.equ text_base,CONFIG_SYS_MONITOR_BASE
+	/* dummy func to let linker include this file */
+	.global text_base_hook
+text_base_hook:
+	ret
+#endif
diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds
new file mode 100644
index 0000000..d4be077
--- /dev/null
+++ b/board/altera/nios2-generic/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = text_base;
+	.text :
+	{
+	  arch/nios2/cpu/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss (NOLOAD) :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss (NOLOAD) :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 9d8b18d..32a87ad 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -14,7 +14,7 @@
 #include <hwconfig.h>
 #include <i2c.h>
 #include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
 #include <spd_sdram.h>
 #include <tsec.h>
 #include <libfdt.h>
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
index 6b7b8b2..82f34f8 100644
--- a/board/freescale/mpc837xemds/pci.c
+++ b/board/freescale/mpc837xemds/pci.c
@@ -18,7 +18,7 @@
 #include <i2c.h>
 #include <fdt_support.h>
 #include <asm/fsl_i2c.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
 
 static struct pci_region pci_regions[] = {
 	{
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index c5c2e40..d636796 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -16,7 +16,7 @@
 #include <hwconfig.h>
 #include <i2c.h>
 #include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
 #include <fdt_support.h>
 #include <spd_sdram.h>
 #include <vsc7385.h>
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 3af660e..31cdf9a 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -198,6 +198,8 @@
 #endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_pci_board_setup(void *blob);
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
@@ -208,6 +210,8 @@
 	base = getenv_bootm_low();
 	size = getenv_bootm_size();
 
+	ft_pci_board_setup(blob);
+
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 }
 #endif
diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c
index abcda6f..8878560 100644
--- a/drivers/block/fsl_sata.c
+++ b/drivers/block/fsl_sata.c
@@ -21,6 +21,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/io.h>
+#include <asm/processor.h>
 #include <malloc.h>
 #include <libata.h>
 #include <fis.h>
@@ -191,6 +192,27 @@
 	/* Wait the controller offline */
 	ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
 
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+	/*
+	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
+	 * controller is configured in legacy mode instead of the
+	 * expected enterprise mode. software needs to clear bit[28]
+	 * of HControl register to change to enterprise mode from
+	 * legacy mode.
+	 */
+	{
+		u32 svr = get_svr();
+		if (IS_SVR_REV(svr, 1, 0) &&
+		    ((SVR_SOC_VER(svr) == SVR_P1022) ||
+		     (SVR_SOC_VER(svr) == SVR_P1022_E) ||
+		     (SVR_SOC_VER(svr) == SVR_P1013) ||
+		     (SVR_SOC_VER(svr) == SVR_P1013_E))) {
+			out_le32(&reg->hstatus, 0x20000000);
+			out_le32(&reg->hcontrol, 0x00000100);
+		}
+	}
+#endif
+
 	/* Set the command header base address to CHBA register to tell DMA */
 	out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
 
diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h
index 18e88fa..576efaf 100644
--- a/drivers/block/fsl_sata.h
+++ b/drivers/block/fsl_sata.h
@@ -243,8 +243,12 @@
 
 /* ext_c_ddc
 */
-#define PRD_ENTRY_EXT		0x80000000 /* extension flag or called indirect descriptor flag */
-#define PRD_ENTRY_DATA_SNOOP	0x00400000 /* Snoop enable for all data associated with the PRD entry */
+#define PRD_ENTRY_EXT		0x80000000 /* extension flag */
+#ifdef CONFIG_FSL_SATA_V2
+#define PRD_ENTRY_DATA_SNOOP	0x10000000 /* Data snoop enable */
+#else
+#define PRD_ENTRY_DATA_SNOOP	0x00400000 /* Data snoop enable */
+#endif
 #define PRD_ENTRY_LEN_MASK	0x003fffff /* Data word count */
 
 #define PRD_ENTRY_MAX_XFER_SZ	(PRD_ENTRY_LEN_MASK + 1)
diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c
index fb28aa9..2980e4d 100644
--- a/drivers/serial/altera_jtag_uart.c
+++ b/drivers/serial/altera_jtag_uart.c
@@ -38,8 +38,16 @@
 
 void serial_putc (char c)
 {
-	while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
-		WATCHDOG_RESET ();
+	while (1) {
+		unsigned st = readl(&jtag->control);
+		if (NIOS_JTAG_WSPACE(st))
+			break;
+#ifdef CONFIG_ALTERA_JTAG_UART_BYPASS
+		if (!(st & NIOS_JTAG_AC)) /* no connection */
+			return;
+#endif
+		WATCHDOG_RESET();
+	}
 	writel ((unsigned char)c, &jtag->data);
 }
 
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
new file mode 100644
index 0000000..e83e1e3
--- /dev/null
+++ b/include/configs/nios2-generic.h
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */
+#define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_SYS_NIOS_SYSID_BASE	CONFIG_SYS_SYSID_BASE
+
+/*
+ * SERIAL
+ */
+#define CONFIG_ALTERA_UART
+#if defined(CONFIG_ALTERA_JTAG_UART)
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_JTAG_UART_BASE
+#else
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_UART_BASE
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE		CONFIG_SYS_UART_BAUD
+#define CONFIG_SYS_BAUDRATE_TABLE	{CONFIG_BAUDRATE}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_TIMER_BASE
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_TIMER_IRQ
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_EPLED			/* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR		LED_PIO_BASE
+
+#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD	(500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE		0x10000	/* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 CONFIG_SYS_FLASH_BASE)
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN		0x40000	/* Reserve 256k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 9641041..89f7cc4 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -174,7 +174,7 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384KiB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */
 
 /* FPGA and NAND */
@@ -342,19 +342,19 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_BMP
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
+#undef CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_BMP
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI