diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
index b1bd022..c4af252 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -5,7 +5,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y	+= aemif.o
 obj-y	+= init.o
 obj-y	+= psc.o
 obj-y	+= clock.o
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 7ac2662..50ce649 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -9,13 +9,6 @@
 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
 #define __ASM_ARCH_HARDWARE_K2HK_H
 
-#define K2HK_ASYNC_EMIF_CNTRL_BASE      0x21000a00
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE   K2HK_ASYNC_EMIF_CNTRL_BASE
-#define K2HK_ASYNC_EMIF_DATA_CE0_BASE   0x30000000
-#define K2HK_ASYNC_EMIF_DATA_CE1_BASE   0x34000000
-#define K2HK_ASYNC_EMIF_DATA_CE2_BASE   0x38000000
-#define K2HK_ASYNC_EMIF_DATA_CE3_BASE   0x3c000000
-
 #define K2HK_PLL_CNTRL_BASE             0x02310000
 #define CLOCK_BASE                      K2HK_PLL_CNTRL_BASE
 #define KS2_RSTCTRL                     (K2HK_PLL_CNTRL_BASE + 0xe8)
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 6c532ca..ffdecbf 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -22,32 +22,6 @@
 typedef volatile unsigned int   dv_reg;
 typedef volatile unsigned int   *dv_reg_p;
 
-#define ASYNC_EMIF_NUM_CS               4
-#define ASYNC_EMIF_MODE_NOR             0
-#define ASYNC_EMIF_MODE_NAND            1
-#define ASYNC_EMIF_MODE_ONENAND         2
-#define ASYNC_EMIF_PRESERVE             -1
-
-struct async_emif_config {
-	unsigned mode;
-	unsigned select_strobe;
-	unsigned extend_wait;
-	unsigned wr_setup;
-	unsigned wr_strobe;
-	unsigned wr_hold;
-	unsigned rd_setup;
-	unsigned rd_strobe;
-	unsigned rd_hold;
-	unsigned turn_around;
-	enum {
-		ASYNC_EMIF_8	= 0,
-		ASYNC_EMIF_16	= 1,
-		ASYNC_EMIF_32	= 2,
-	} width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
 struct ddr3_phy_config {
 	unsigned int pllcr;
 	unsigned int pgcr1_mask;
@@ -145,6 +119,10 @@
 #define KS2_UART0_BASE                	0x02530c00
 #define KS2_UART1_BASE                	0x02531000
 
+/* AEMIF */
+#define KS2_AEMIF_CNTRL_BASE       	0x21000a00
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif
diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h
new file mode 100644
index 0000000..4a311d4
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/ti-aemif.h
@@ -0,0 +1,39 @@
+/*
+ * AEMIF definitions
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _AEMIF_H_
+#define _AEMIF_H_
+
+#define AEMIF_NUM_CS               4
+#define AEMIF_MODE_NOR             0
+#define AEMIF_MODE_NAND            1
+#define AEMIF_MODE_ONENAND         2
+#define AEMIF_PRESERVE             -1
+
+struct aemif_config {
+	unsigned mode;
+	unsigned select_strobe;
+	unsigned extend_wait;
+	unsigned wr_setup;
+	unsigned wr_strobe;
+	unsigned wr_hold;
+	unsigned rd_setup;
+	unsigned rd_strobe;
+	unsigned rd_hold;
+	unsigned turn_around;
+	enum {
+		AEMIF_WIDTH_8	= 0,
+		AEMIF_WIDTH_16	= 1,
+		AEMIF_WIDTH_32	= 2,
+	} width;
+};
+
+void aemif_init(int num_cs, struct aemif_config *config);
+
+#endif
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c
index 53f26b2..ef90f9d 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/k2hk_evm/board.c
@@ -18,6 +18,7 @@
 #include <asm/mach-types.h>
 #include <asm/arch/emac_defs.h>
 #include <asm/arch/psc_defs.h>
+#include <asm/ti-common/ti-aemif.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,9 +40,9 @@
 						what is that */
 };
 
-static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
+static struct aemif_config aemif_configs[] = {
 	{			/* CS0 */
-		.mode		= ASYNC_EMIF_MODE_NAND,
+		.mode		= AEMIF_MODE_NAND,
 		.wr_setup	= 0xf,
 		.wr_strobe	= 0x3f,
 		.wr_hold	= 7,
@@ -49,7 +50,7 @@
 		.rd_strobe	= 0x3f,
 		.rd_hold	= 7,
 		.turn_around	= 3,
-		.width		= ASYNC_EMIF_8,
+		.width		= AEMIF_WIDTH_8,
 	},
 
 };
@@ -66,7 +67,7 @@
 
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
-	init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
+	aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
 	return 0;
 }
 
diff --git a/drivers/Makefile b/drivers/Makefile
index 5d03f37..b23076f 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -14,3 +14,4 @@
 obj-y += video/
 obj-y += watchdog/
 obj-$(CONFIG_QE) += qe/
+obj-y += memory/
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
new file mode 100644
index 0000000..9bfb9c7
--- /dev/null
+++ b/drivers/memory/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
diff --git a/arch/arm/cpu/armv7/keystone/aemif.c b/drivers/memory/ti-aemif.c
similarity index 63%
rename from arch/arm/cpu/armv7/keystone/aemif.c
rename to drivers/memory/ti-aemif.c
index bcbb95a..f821dae 100644
--- a/arch/arm/cpu/armv7/keystone/aemif.c
+++ b/drivers/memory/ti-aemif.c
@@ -8,9 +8,13 @@
  */
 
 #include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/ti-common/davinci_nand.h>
+#include <asm/ti-common/ti-aemif.h>
+
+#define AEMIF_WAITCYCLE_CONFIG		(CONFIG_AEMIF_CNTRL_BASE + 0x4)
+#define AEMIF_NAND_CONTROL		(CONFIG_AEMIF_CNTRL_BASE + 0x60)
+#define AEMIF_ONENAND_CONTROL		(CONFIG_AEMIF_CNTRL_BASE + 0x5c)
+#define AEMIF_CONFIG(cs)		(CONFIG_AEMIF_CNTRL_BASE + 0x10 \
+					 + (cs * 4))
 
 #define AEMIF_CFG_SELECT_STROBE(v)	((v) ? 1 << 31 : 0)
 #define AEMIF_CFG_EXTEND_WAIT(v)	((v) ? 1 << 30 : 0)
@@ -31,22 +35,22 @@
 		}						\
 	} while (0)
 
-void configure_async_emif(int cs, struct async_emif_config *cfg)
+static void aemif_configure(int cs, struct aemif_config *cfg)
 {
 	unsigned long tmp;
 
-	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
-		tmp = __raw_readl(&davinci_emif_regs->nandfcr);
+	if (cfg->mode == AEMIF_MODE_NAND) {
+		tmp = __raw_readl(AEMIF_NAND_CONTROL);
 		tmp |= (1 << cs);
-		__raw_writel(tmp, &davinci_emif_regs->nandfcr);
+		__raw_writel(tmp, AEMIF_NAND_CONTROL);
 
-	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
-		tmp = __raw_readl(&davinci_emif_regs->one_nand_cr);
+	} else if (cfg->mode == AEMIF_MODE_ONENAND) {
+		tmp = __raw_readl(AEMIF_ONENAND_CONTROL);
 		tmp |= (1 << cs);
-		__raw_writel(tmp, &davinci_emif_regs->one_nand_cr);
+		__raw_writel(tmp, AEMIF_ONENAND_CONTROL);
 	}
 
-	tmp = __raw_readl(&davinci_emif_regs->abncr[cs]);
+	tmp = __raw_readl(AEMIF_CONFIG(cs));
 
 	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
 	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
@@ -59,13 +63,18 @@
 	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
 	set_config_field(tmp, WIDTH,		cfg->width);
 
-	__raw_writel(tmp, &davinci_emif_regs->abncr[cs]);
+	__raw_writel(tmp, AEMIF_CONFIG(cs));
 }
 
-void init_async_emif(int num_cs, struct async_emif_config *config)
+void aemif_init(int num_cs, struct aemif_config *config)
 {
 	int cs;
 
+	if (num_cs > AEMIF_NUM_CS) {
+		num_cs = AEMIF_NUM_CS;
+		printf("AEMIF: csnum has to be <= 5");
+	}
+
 	for (cs = 0; cs < num_cs; cs++)
-		configure_async_emif(cs, config + cs);
+		aemif_configure(cs, config + cs);
 }
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index fcfbca9..858329f 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -129,6 +129,10 @@
 #define CONFIG_SYS_SGMII_LINERATE_MHZ          1250
 #define CONFIG_SYS_SGMII_RATESCALE             2
 
+/* AEMIF */
+#define CONFIG_TI_AEMIF
+#define CONFIG_AEMIF_CNTRL_BASE		       KS2_AEMIF_CNTRL_BASE
+
 /* NAND Configuration */
 #define CONFIG_NAND_DAVINCI
 #define CONFIG_CMD_NAND_ECCLAYOUT