tree 94edfc80e63eb36793f6feed2c46339e0cfb9cce
parent 85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4b
author Andy Fleming <afleming@freescale.com> 1172301405 -0600
committer Andrew Fleming-AFLEMING <afleming@freescale.com> 1177376308 -0500

Tweak DDR ECC error counter

Enable single-bit error counter when memory was cleared by ddr controller.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>