tree 6f8361c6771812663f2654467219bd7acd9dd513
parent 1cc619be8b73abbee2fd6faf2cd4ade27b516531
author Liu Ying <Ying.Liu@freescale.com> 1349496964 +0000
committer Anatolij Gustschin <agust@denx.de> 1352237051 +0100

ipu common: reset ipuv3 correctly

This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>