tree 0cf5592aeb45af97ff734a8653589dde5a16e1b7
parent 1f3402e7291afa3ba0a5f4da72640edaf2f65405
author York Sun <yorksun@freescale.com> 1420579127 -0800
committer York Sun <yorksun@freescale.com> 1424812146 -0800

driver/ddr/fsl: Add workaround for A008336

Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.

Signed-off-by: York Sun <yorksun@freescale.com>