| commit | a1d558a20f1eaeae9927abc4e0978725d33bae53 | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Mon Oct 08 07:44:26 2012 +0000 |
| committer | Andy Fleming <afleming@freescale.com> | Mon Oct 22 14:31:29 2012 -0500 |
| tree | 3af577ebb7be24efd3c23d7a8559512d2f9bfa70 | |
| parent | eb5394120643922626f18e5fe7b0b3dc0ed43b9a [diff] |
powerpc/mpc85xx: Add workaround for DDR erratum A004934 After DDR controller is enabled, it performs a calibration for the transmit data vs DQS paths. During this calibration, the DDR controller may make an inaccurate calculation, resulting in a non-optimal tap point. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>