tree 2353fac130d22844bf03a50b7304899f48963d17
parent 6904e377465db6c731adf4fb0eb67e55454606d7
author Benoît Thébaudeau <benoit.thebaudeau@advansee.com> 1359544754 +0000
committer Stefano Babic <sbabic@denx.de> 1360673550 +0100

imx: mx6q DDR3 init: Fix tXPR

MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR.

For all DDR3 speed bins:
  tXPR(min) = max(5 nCK, tRFC(min) + 10 ns)
  tRFC(2 Gb) = 160 ns

All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron
MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD).

Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns
and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>