qcom: serial: common serial driver
Porting serial driver from IPQ806x u-boot for IPQ807x
Change-Id: I860af26485231d5634f33422ca5cb7a0219e6125
Signed-off-by: Manoharan Vijaya Raghavan <mraghava@codeaurora.org>
diff --git a/arch/arm/include/asm/arch-qcom-common/gsbi.h b/arch/arm/include/asm/arch-qcom-common/gsbi.h
new file mode 100644
index 0000000..333a4bf
--- /dev/null
+++ b/arch/arm/include/asm/arch-qcom-common/gsbi.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2012-2013, 2015-2016, The Linux Foundation.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __GSBI_H_
+#define __GSBI_H_
+
+#include <asm/io.h>
+
+/* GSBI Registers */
+#define GSBI_CTRL_REG(base) ((base) + 0x0)
+
+#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4
+#define GSBI_PROTOCOL_CODE_I2C 0x2
+#define GSBI_PROTOCOL_CODE_SPI 0x3
+#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4
+#define GSBI_PROTOCOL_CODE_I2C_UART 0x6
+
+#define GSBI_HCLK_CTL_S 4
+#define GSBI_HCLK_CTL_CLK_ENA 0x1
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-qcom-common/uart.h b/arch/arm/include/asm/arch-qcom-common/uart.h
new file mode 100644
index 0000000..54e38ae
--- /dev/null
+++ b/arch/arm/include/asm/arch-qcom-common/uart.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2012-2013, 2015-2016, The Linux Foundation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * * Neither the name of [Owner Organization] nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __UART_DM_H__
+#define __UART_DM_H__
+
+#include <asm/io.h>
+#include "common.h"
+#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
+ ((value << (32 - end_pos))\
+ >> (32 - (end_pos - start_pos)))
+
+
+extern void dsb(void);
+#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \
+ word = 0; \
+ int j; \
+ for(j=0; j < (int)cnt; j++) { \
+ word |= (a[j] & 0xff)<< (j * 8);\
+ } \
+ }
+
+extern void __udelay(unsigned long usec);
+
+
+enum MSM_BOOT_UART_DM_PARITY_MODE {
+ MSM_BOOT_UART_DM_NO_PARITY,
+ MSM_BOOT_UART_DM_ODD_PARITY,
+ MSM_BOOT_UART_DM_EVEN_PARITY,
+ MSM_BOOT_UART_DM_SPACE_PARITY
+};
+
+/* UART Stop Bit Length */
+enum MSM_BOOT_UART_DM_STOP_BIT_LEN {
+ MSM_BOOT_UART_DM_SBL_9_16,
+ MSM_BOOT_UART_DM_SBL_1,
+ MSM_BOOT_UART_DM_SBL_1_9_16,
+ MSM_BOOT_UART_DM_SBL_2
+};
+
+/* UART Bits per Char */
+enum MSM_BOOT_UART_DM_BITS_PER_CHAR {
+ MSM_BOOT_UART_DM_5_BPS,
+ MSM_BOOT_UART_DM_6_BPS,
+ MSM_BOOT_UART_DM_7_BPS,
+ MSM_BOOT_UART_DM_8_BPS
+};
+
+/* UART clock @ 7.3728 MHz */
+#ifdef CONFIG_IPQ806X
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#elif defined CONFIG_IPQ40XX
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xff
+#endif
+
+/* 8-N-1 Configuration */
+#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
+ (MSM_BOOT_UART_DM_SBL_1 << 2) | \
+ (MSM_BOOT_UART_DM_8_BPS << 4))
+
+#define GCC_BLSP1_UART1_APPS_CBCR 0x0180203c
+/* UART_DM Registers */
+
+/* UART Operational Mode Register */
+#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00)
+#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04)
+#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
+#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
+
+/* UART Clock Selection Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0)
+#else
+#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08)
+#endif
+
+/* UART DM TX FIFO Registers - 4 */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x)))
+#else
+#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x)))
+#endif
+
+/* UART Command Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8)
+#else
+#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10)
+#endif
+#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
+#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
+#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
+#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
+
+/* UART Channel Command */
+#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
+#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 )
+#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\
+ | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
+#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
+#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
+#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
+#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
+#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
+#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
+#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
+#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
+#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
+#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
+#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
+#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
+#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
+#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
+#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
+#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
+
+/*UART General Command */
+#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
+
+#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
+#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
+#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
+#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
+#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
+
+/* UART Interrupt Mask Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0)
+#else
+#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14)
+#endif
+
+#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
+#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
+#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
+#define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
+#define MSM_BOOT_UART_DM_RXLEV (1 << 4)
+#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
+#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
+#define MSM_BOOT_UART_DM_TX_READY (1 << 7)
+#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
+#define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
+#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
+#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
+#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
+
+#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
+ MSM_BOOT_UART_DM_TXLEV | \
+ MSM_BOOT_UART_DM_RXSTALE)
+
+/* UART Interrupt Programming Register */
+#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18)
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
+
+/* UART Transmit/Receive FIFO Watermark Register */
+#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C)
+/* Interrupt is generated when FIFO level is less than or equal to this value */
+#define MSM_BOOT_UART_DM_TFW_VALUE 0
+
+#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20)
+/*Interrupt generated when no of words in RX FIFO is greater than this value */
+#define MSM_BOOT_UART_DM_RFW_VALUE 0
+
+/* UART Hunt Character Register */
+#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24)
+
+/* Used for RX transfer initialization */
+#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34)
+
+/* Default DMRX value - any value bigger than FIFO size would be fine */
+#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
+
+/* Register to enable IRDA function */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8)
+#else
+#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38)
+#endif
+
+/* UART Data Mover Enable Register */
+#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C)
+
+/* Number of characters for Transmission */
+#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040)
+
+/* UART RX FIFO Base Address */
+#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44)
+
+/* UART Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4)
+#else
+#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008)
+#endif
+#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
+#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
+#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
+#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
+#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
+#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
+#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
+#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
+#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
+
+/* UART Receive FIFO Registers - 4 in numbers */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x)))
+#else
+#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x)))
+#endif
+
+/* UART Masked Interrupt Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC)
+#else
+#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10)
+#endif
+
+/* UART Interrupt Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4)
+#else
+#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14)
+#endif
+
+/* Number of characters received since the end of last RX transfer */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC)
+#else
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38)
+#endif
+
+/* UART TX FIFO Status Register */
+#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C)
+#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
+#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
+#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
+#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
+
+/* UART RX FIFO Status Register */
+#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50)
+#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
+#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
+#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
+#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
+
+/* Macros for Common Errors */
+#define MSM_BOOT_UART_DM_E_SUCCESS 0
+#define MSM_BOOT_UART_DM_E_FAILURE 1
+#define MSM_BOOT_UART_DM_E_TIMEOUT 2
+#define MSM_BOOT_UART_DM_E_INVAL 3
+#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
+#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
+
+#endif /* __UART_DM_H__ */
+
diff --git a/drivers/serial/qcom_uart.c b/drivers/serial/qcom_uart.c
new file mode 100644
index 0000000..4e4dd96
--- /dev/null
+++ b/drivers/serial/qcom_uart.c
@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * * Neither the name of [Owner Organization] nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/arch-qcom-common/uart.h>
+#include <asm/arch-qcom-common/gsbi.h>
+
+#define FIFO_DATA_SIZE 4
+
+#if defined CONFIG_IPQ806X
+extern board_ipq806x_params_t *gboard_param;
+#elif defined CONFIG_IPQ40XX
+extern board_ipq40xx_params_t *gboard_param;
+#endif
+
+static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base);
+
+/* Received data is valid or not */
+static int valid_data = 0;
+
+/* Received data */
+static unsigned int word = 0;
+
+/**
+ * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
+ * @uart_dm_base: UART controller base address
+ */
+static unsigned int msm_boot_uart_dm_init_rx_transfer(unsigned int uart_dm_base)
+{
+ /* Reset receiver */
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX,
+ MSM_BOOT_UART_DM_CR(uart_dm_base));
+
+ /* Enable receiver */
+ writel(MSM_BOOT_UART_DM_CR_RX_ENABLE,
+ MSM_BOOT_UART_DM_CR(uart_dm_base));
+ writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE,
+ MSM_BOOT_UART_DM_DMRX(uart_dm_base));
+
+ /* Clear stale event */
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT,
+ MSM_BOOT_UART_DM_CR(uart_dm_base));
+
+ /* Enable stale event */
+ writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT,
+ MSM_BOOT_UART_DM_CR(uart_dm_base));
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/**
+ * msm_boot_uart_dm_read - reads a word from the RX FIFO.
+ * @data: location where the read data is stored
+ * @count: no of valid data in the FIFO
+ * @wait: indicates blocking call or not blocking call
+ *
+ * Reads a word from the RX FIFO. If no data is available blocks if
+ * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY.
+ */
+static unsigned int
+msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
+{
+ static int total_rx_data = 0;
+ static int rx_data_read = 0;
+ unsigned int base = 0;
+ uint32_t status_reg;
+
+ base = gboard_param->uart_dm_base;
+
+ if (data == NULL)
+ return MSM_BOOT_UART_DM_E_INVAL;
+
+ status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
+
+ /* Check for DM_RXSTALE for RX transfer to finish */
+ while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) {
+ status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
+ if (!wait)
+ return MSM_BOOT_UART_DM_E_RX_NOT_READY;
+ }
+
+ /* Check for Overrun error. We'll just reset Error Status */
+ if (readl(MSM_BOOT_UART_DM_SR(base)) &
+ MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
+ MSM_BOOT_UART_DM_CR(base));
+ total_rx_data = rx_data_read = 0;
+ msm_boot_uart_dm_init(base);
+ return MSM_BOOT_UART_DM_E_RX_NOT_READY;
+ }
+
+ /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
+ if (total_rx_data == 0)
+ total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
+
+ /* Data available in FIFO; read a word. */
+ *data = readl(MSM_BOOT_UART_DM_RF(base, 0));
+
+ /* WAR for http://prism/CR/548280 */
+ if (*data == 0) {
+ return MSM_BOOT_UART_DM_E_RX_NOT_READY;
+ }
+
+ /* increment the total count of chars we've read so far */
+ rx_data_read += FIFO_DATA_SIZE;
+
+ /* actual count of valid data in word */
+ *count = ((total_rx_data < rx_data_read) ?
+ (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) :
+ FIFO_DATA_SIZE);
+
+ /* If there are still data left in FIFO we'll read them before
+ * initializing RX Transfer again
+ */
+ if (rx_data_read < total_rx_data)
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+
+ msm_boot_uart_dm_init_rx_transfer(base);
+ total_rx_data = rx_data_read = 0;
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/**
+ * msm_boot_uart_replace_lr_with_cr - replaces "\n" with "\r\n"
+ * @data_in: characters to be converted
+ * @num_of_chars: no. of characters
+ * @data_out: location where converted chars are stored
+ *
+ * Replace linefeed char "\n" with carriage return + linefeed
+ * "\r\n". Currently keeping it simple than efficient.
+ */
+static unsigned int
+msm_boot_uart_replace_lr_with_cr(char *data_in,
+ int num_of_chars,
+ char *data_out, int *num_of_chars_out)
+{
+ int i = 0, j = 0;
+
+ if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0))
+ return MSM_BOOT_UART_DM_E_INVAL;
+
+ for (i = 0, j = 0; i < num_of_chars; i++, j++) {
+ if (data_in[i] == '\n')
+ data_out[j++] = '\r';
+
+ data_out[j] = data_in[i];
+ }
+
+ *num_of_chars_out = j;
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/**
+ * msm_boot_uart_dm_write - transmit data
+ * @data: data to transmit
+ * @num_of_chars: no. of bytes to transmit
+ *
+ * Writes the data to the TX FIFO. If no space is available blocks
+ * till space becomes available.
+ */
+static unsigned int
+msm_boot_uart_dm_write(char *data, unsigned int num_of_chars)
+{
+ unsigned int tx_word_count = 0;
+ unsigned int tx_char_left = 0, tx_char = 0;
+ unsigned int tx_word = 0;
+ int i = 0;
+ char *tx_data = NULL;
+ char new_data[1024];
+ unsigned int base = gboard_param->uart_dm_base;
+
+ if ((data == NULL) || (num_of_chars <= 0))
+ return MSM_BOOT_UART_DM_E_INVAL;
+
+ /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */
+ msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i);
+
+ tx_data = new_data;
+ num_of_chars = i;
+
+ /* Write to NO_CHARS_FOR_TX register number of characters
+ * to be transmitted. However, before writing TX_FIFO must
+ * be empty as indicated by TX_READY interrupt in IMR register
+ */
+ /* Check if transmit FIFO is empty.
+ * If not we'll wait for TX_READY interrupt. */
+
+ if (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) {
+ while (!(readl(MSM_BOOT_UART_DM_ISR(base)) & MSM_BOOT_UART_DM_TX_READY))
+ __udelay(1);
+ }
+
+ /* We are here. FIFO is ready to be written. */
+ /* Write number of characters to be written */
+ writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
+
+ /* Clear TX_READY interrupt */
+ writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR(base));
+
+ /* We use four-character word FIFO. So we need to divide data into
+ * four characters and write in UART_DM_TF register */
+ tx_word_count = (num_of_chars % 4) ? ((num_of_chars / 4) + 1) :
+ (num_of_chars / 4);
+ tx_char_left = num_of_chars;
+
+ for (i = 0; i < (int)tx_word_count; i++) {
+ tx_char = (tx_char_left < 4) ? tx_char_left : 4;
+ PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word);
+
+ /* Wait till TX FIFO has space */
+ while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXRDY))
+ __udelay(1);
+
+ /* TX FIFO has space. Write the chars */
+ writel(tx_word, MSM_BOOT_UART_DM_TF(base, 0));
+ tx_char_left = num_of_chars - (i + 1) * 4;
+ tx_data = tx_data + 4;
+ }
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * msm_boot_uart_dm_reset - resets UART controller
+ * @base: UART controller base address
+ */
+static unsigned int msm_boot_uart_dm_reset(unsigned int base)
+{
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR(base));
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR(base));
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * msm_boot_uart_dm_init - initilaizes UART controller
+ * @uart_dm_base: UART controller base address
+ */
+static unsigned int msm_boot_uart_dm_init(unsigned int uart_dm_base)
+{
+ /* Configure UART mode registers MR1 and MR2 */
+ /* Hardware flow control isn't supported */
+ writel(0x0, MSM_BOOT_UART_DM_MR1(uart_dm_base));
+
+ /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
+ writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2(uart_dm_base));
+
+ /* Configure Interrupt Mask register IMR */
+ writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR(uart_dm_base));
+
+ /*
+ * Configure Tx and Rx watermarks configuration registers
+ * TX watermark value is set to 0 - interrupt is generated when
+ * FIFO level is less than or equal to 0
+ */
+ writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR(uart_dm_base));
+
+ /* RX watermark value */
+ writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR(uart_dm_base));
+
+ /* Configure Interrupt Programming Register */
+ /* Set initial Stale timeout value */
+ writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB,
+ MSM_BOOT_UART_DM_IPR(uart_dm_base));
+
+ /* Configure IRDA if required */
+ /* Disabling IRDA mode */
+ writel(0x0, MSM_BOOT_UART_DM_IRDA(uart_dm_base));
+
+ /* Configure hunt character value in HCR register */
+ /* Keep it in reset state */
+ writel(0x0, MSM_BOOT_UART_DM_HCR(uart_dm_base));
+
+ /*
+ * Configure Rx FIFO base address
+ * Both TX/RX shares same SRAM and default is half-n-half.
+ * Sticking with default value now.
+ * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
+ * We have found RAM_ADDR_WIDTH = 0x7f
+ */
+
+ /* Issue soft reset command */
+ msm_boot_uart_dm_reset(uart_dm_base);
+
+ /* Enable/Disable Rx/Tx DM interfaces */
+ /* Data Mover not currently utilized. */
+ writel(0x0, MSM_BOOT_UART_DM_DMEN(uart_dm_base));
+
+ /* Enable transmitter */
+ writel(MSM_BOOT_UART_DM_CR_TX_ENABLE,
+ MSM_BOOT_UART_DM_CR(uart_dm_base));
+
+ /* Initialize Receive Path */
+ msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
+
+ return 0;
+}
+
+/**
+ * uart_dm_init - initializes UART
+ *
+ * Initializes clocks, GPIO and UART controller.
+ */
+static void uart_dm_init(void)
+{
+ unsigned int dm_base;
+#ifdef CONFIG_IPQ806X
+ unsigned int gsbi_base;
+#endif
+
+ dm_base = gboard_param->uart_dm_base;
+
+#ifdef CONFIG_IPQ806X
+ gsbi_base = gboard_param->uart_gsbi_base;
+ ipq_configure_gpio(gboard_param->dbg_uart_gpio, NO_OF_DBG_UART_GPIOS);
+
+ /* Configure the uart clock */
+ uart_clock_config(gboard_param->uart_gsbi,
+ gboard_param->uart_mnd_value.m_value,
+ gboard_param->uart_mnd_value.n_value,
+ gboard_param->uart_mnd_value.d_value,
+ gboard_param->clk_dummy);
+
+ writel(GSBI_PROTOCOL_CODE_I2C_UART <<
+ GSBI_CTRL_REG_PROTOCOL_CODE_S,
+ GSBI_CTRL_REG(gsbi_base));
+#elif defined CONFIG_IPQ40XX
+ qca_configure_gpio(gboard_param->dbg_uart_gpio, NO_OF_DBG_UART_GPIOS);
+ writel(1, GCC_BLSP1_UART1_APPS_CBCR);
+#endif
+ writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(dm_base));
+
+ /* Intialize UART_DM */
+ msm_boot_uart_dm_init(dm_base);
+}
+
+/**
+ * serial_putc - transmits a character
+ * @c: character to transmit
+ */
+void serial_putc(char c)
+{
+ msm_boot_uart_dm_write(&c, 1);
+}
+
+/**
+ * serial_puts - transmits a string of data
+ * @s: string to transmit
+ */
+void serial_puts(const char *s)
+{
+ while (*s != '\0')
+ serial_putc(*s++);
+}
+
+/**
+ * serial_tstc - checks if data available for reading
+ *
+ * Returns 1 if data available, 0 otherwise
+ */
+int serial_tstc(void)
+{
+ /* Return if data is already read */
+ if (valid_data)
+ return 1;
+
+ /* Read data from the FIFO */
+ if (msm_boot_uart_dm_read(&word, &valid_data, 0) != MSM_BOOT_UART_DM_E_SUCCESS)
+ return 0;
+
+ return 1;
+}
+
+/**
+ * serial_getc - reads a character
+ *
+ * Returns the character read from serial port.
+ */
+int serial_getc(void)
+{
+ int byte;
+
+ while (!serial_tstc()) {
+ WATCHDOG_RESET();
+ /* wait for incoming data */
+ }
+
+ byte = (int)word & 0xff;
+ word = word >> 8;
+ valid_data--;
+
+ return byte;
+}
+
+/*
+ * serial_setbrg - sets serial baudarate
+ */
+void serial_setbrg(void)
+{
+ return;
+}
+
+/**
+ * serial_init - initializes serial controller
+ */
+int serial_init(void)
+{
+ uart_dm_init();
+ return 0;
+}