tree 5141e4352c2db17593f8c30b0f19cb6ab3ba354d
parent f07217c9e2912af5b2f05d61829f62cc865b481f
author Wolfgang Denk <wd@pollux.denx.de> 1142207165 +0100
committer Wolfgang Denk <wd@pollux.denx.de> 1142207165 +0100

Fix bug in [id]cache_status commands for MPC85xx processors;
should look at LSB of L1CSRn registers to determine if L1 cache is
enabled, not the MSB.
Patch by Murray Jensen, 19 Jul 2005