tree 73824a5325ebcf7c0c7cfe28ac5790655f7ca2ca
parent d3daba10f159cca7e9d24c6f154926a9b92c75e3
author Lokesh Vutla <lokeshvutla@ti.com> 1386667943 +0530
committer Tom Rini <trini@ti.com> 1387419285 -0500

ARM: AM43xx: GP_EVM: Add support for DDR3

GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>