| commit | b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 | [log] [tgz] |
|---|---|---|
| author | Haiying Wang <Haiying.Wang@freescale.com> | Tue Jan 13 16:29:28 2009 -0500 |
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | Tue Jan 13 16:58:46 2009 -0600 |
| tree | 86bc278f77095fe7d3279605e972eb45007e976c | |
| parent | 950264317eb9594b2b5ee2fb65206200a1c6007a [diff] |
Some changes of TLB entry setting for MPC8572DS - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>