Merge branch 'master' of git://git.denx.de/u-boot-x86
diff --git a/MAINTAINERS b/MAINTAINERS
index 5e3a3fa..e003226 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -117,7 +117,6 @@
c2mon MPC855
hermes MPC860
lwmon MPC823
- pcu_e MPC855
CU824 MPC8240
Sandpoint8240 MPC8240
@@ -208,8 +207,6 @@
ipek01 MPC5200
- CCM MPC855
-
PN62 MPC8240
IPHASE4539 MPC8260
SCM MPC8260
diff --git a/README b/README
index 171e0d6..f997a5d 100644
--- a/README
+++ b/README
@@ -1781,7 +1781,7 @@
ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
HERMES, IP860, RPXlite, LWMON, LANTEC,
- PCU_E, FLAGADM, TQM8260
+ FLAGADM, TQM8260
- Error Recovery:
CONFIG_PANIC_HANG
diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c
index c29f577..eba2435 100644
--- a/arch/m68k/lib/board.c
+++ b/arch/m68k/lib/board.c
@@ -73,10 +73,6 @@
static char *failed = "*** failed ***\n";
-#ifdef CONFIG_PCU_E
-extern flash_info_t flash_info[];
-#endif
-
#include <environment.h>
extern ulong __init_end;
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index a6cfaa5..df25048 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -81,10 +81,16 @@
#endif
struct liodn_id_table sec_liodn_tbl[] = {
- SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
- SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
- SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
- SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
+ /*
+ * We assume currently that all JR are in the same partition
+ * and as such they need to represent the same LIODN due to
+ * a 4080 rev.2 h/w requirement that DECOs sharing from themselves
+ * or from another DECO have the two Non-SEQ LIODN values equal
+ */
+ SET_SEC_JR_LIODN_ENTRY(0, 146, 154), /* (0, 146, 154), */
+ SET_SEC_JR_LIODN_ENTRY(1, 146, 154), /* (1, 147, 155), */
+ SET_SEC_JR_LIODN_ENTRY(2, 146, 154), /* (2, 178, 186), */
+ SET_SEC_JR_LIODN_ENTRY(3, 146, 154), /* (3, 179, 187), */
SET_SEC_RTIC_LIODN_ENTRY(a, 144),
SET_SEC_RTIC_LIODN_ENTRY(b, 145),
SET_SEC_RTIC_LIODN_ENTRY(c, 176),
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index e97ae68..49b354d 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -156,7 +156,6 @@
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_MHPC) || \
- defined(CONFIG_PCU_E) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
defined(CONFIG_RPXCLASSIC) || \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 3dd2b7f..30c64eb 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1589,7 +1589,9 @@
u32 cpcerreaddr; /* error extended address */
u32 cpcerraddr; /* error address */
u32 cpcerrctl; /* error control */
- u32 res9[105]; /* pad out to 4k */
+ u32 res9[41]; /* pad out to 4k */
+ u32 cpchdbcr0; /* hardware debug control register 0 */
+ u32 res10[63]; /* pad out to 4k */
} cpc_corenet_t;
#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
@@ -1616,6 +1618,7 @@
#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
#define CPC_SRCR0_SRAMEN 0x00000001
#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
+#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
#endif /* CONFIG_SYS_FSL_CPC */
/* Global Utilities Block */
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 8f6a7c9..bfdfa86 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -107,7 +107,7 @@
static char *failed = "*** failed ***\n";
-#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
+#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
extern flash_info_t flash_info[];
#endif
@@ -681,11 +681,10 @@
unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
#endif
-#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
- * Do PCI configuration on BAB7xx and CPC45 _before_ the flash
- * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus
- * bridge there.
+ * Do early PCI configuration _before_ the flash gets initialised,
+ * because PCU ressources are crucial for flash access on some boards.
*/
pci_init ();
#endif
@@ -735,7 +734,7 @@
#endif
-# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
+# if defined(CONFIG_OXC) || defined(CONFIG_RMU)
/* flash mapped at end of memory map */
bd->bi_flashoffset = TEXT_BASE + flash_size;
# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
@@ -856,7 +855,7 @@
WATCHDOG_RESET ();
-#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45)
+#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do pci configuration
*/
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 3929ad0..11dfd84 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -28,13 +28,21 @@
#include <i2c.h>
#include <linux/ctype.h>
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
#include "../common/eeprom.h"
-
-#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID)
-#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID"
+#define MAX_NUM_PORTS 8
#endif
-#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+#define MAX_NUM_PORTS 8
+#define NXID_VERSION 0
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define MAX_NUM_PORTS 23
+#define NXID_VERSION 1
+#endif
/**
* static eeprom: EEPROM layout for CCID or NXID formats
@@ -68,8 +76,8 @@
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
- u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
- u32 crc; /* 0x72 CRC32 checksum */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
+ u32 crc; /* x+1 CRC32 checksum */
#endif
} e;
@@ -204,7 +212,7 @@
*/
static int prog_eeprom(void)
{
- int ret = 0; /* shut up gcc */
+ int ret = 0;
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
@@ -225,6 +233,11 @@
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
+ /*
+ * The AT24C02 datasheet says that data can only be written in page
+ * mode, which means 8 bytes at a time, and it takes up to 5ms to
+ * complete a given write.
+ */
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((sizeof(e) - i), 8));
@@ -233,12 +246,23 @@
udelay(5000); /* 5ms write cycle timing */
}
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
if (ret) {
printf("Programming failed.\n");
+ has_been_read = 0;
return -1;
}
@@ -300,7 +324,7 @@
char *p = (char *) string;
unsigned int i;
- if (!string) {
+ if ((index >= MAX_NUM_PORTS) || !string) {
printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
return;
}
@@ -333,7 +357,7 @@
if (cmd == 'i') {
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
memcpy(e.id, "NXID", sizeof(e.id));
- e.version = 0;
+ e.version = NXID_VERSION;
#else
memcpy(e.id, "CCID", sizeof(e.id));
#endif
@@ -382,8 +406,8 @@
e.mac_count = simple_strtoul(argv[2], NULL, 16);
update_crc();
break;
- case '0' ... '7': /* "mac 0" through "mac 7" */
- set_mac_address(cmd - '0', argv[2]);
+ case '0' ... '9': /* "mac 0" through "mac 22" */
+ set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
break;
case 'h': /* help */
default:
diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c
index 2994e36..e1bca19 100644
--- a/board/freescale/corenet_ds/pci.c
+++ b/board/freescale/corenet_ds/pci.c
@@ -40,10 +40,14 @@
static struct pci_controller pcie3_hose;
#endif
+#ifdef CONFIG_PCIE4
+static struct pci_controller pcie4_hose;
+#endif
+
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info[3];
+ struct fsl_pci_info pci_info[4];
u32 devdisr;
int first_free_busno = 0;
int num = 0;
@@ -119,6 +123,28 @@
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
#endif
+
+#ifdef CONFIG_PCIE4
+ pcie_configured = is_serdes_configured(PCIE4);
+
+ if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
+ set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
+ LAW_TRGT_IF_PCIE_4);
+ set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
+ LAW_TRGT_IF_PCIE_4);
+ SET_STD_PCIE_INFO(pci_info[num], 4);
+ pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
+ printf(" PCIE4 connected to as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie4_hose, first_free_busno);
+ } else {
+ printf (" PCIE4: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
+#endif
}
void pci_of_setup(void *blob, bd_t *bd)
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index e938788..e3f5b4a 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -77,8 +77,18 @@
popts->write_data_delay = 2;
/*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
+ * Enable half drive strength
*/
- popts->half_strength_driver_enable = 0;
+ popts->half_strength_driver_enable = 1;
+
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xa;
+ popts->wrlvl_start = 0x4;
+
+ /* Rtt and Rtt_W override */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = DDR3_RTT_60_OHM;
+ popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
}
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 01b7dcb..795e565 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -27,6 +27,7 @@
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
+#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
@@ -211,6 +212,31 @@
return 0;
}
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+ const u8 flash_esel = 0;
+
+ /*
+ * Remap Boot flash to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, /* ts, esel */
+ BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
+
+ return 0;
+}
+
int checkboard (void)
{
printf ("Board: 8569 MDS\n");
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index 73dcc3e..f852fc3 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -46,15 +46,20 @@
/* TLB 1 Initializations */
/*
- * TLBe 0: 64M Non-cacheable, guarded
+ * TLBe 0: 64M write-through, guarded
* Out of reset this entry is only 4K.
- * 0xfc000000 256K NAND FLASH (CS3)
- * 0xfe000000 32M NOR FLASH (CS0)
+ * 0xfc000000 32MB NAND FLASH (CS3)
+ * 0xfe000000 32MB NOR FLASH (CS0)
*/
+#ifdef CONFIG_NAND_SPL
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
-
+#endif
/*
* TLBe 1: 256KB Non-cacheable, guarded
* 0xf8000000 32K BCSR
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 5cdee9f..ee93e8b 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -27,6 +27,7 @@
#include <asm/mp.h>
#include <netdev.h>
#include <i2c.h>
+#include <hwconfig.h>
#include "../common/ngpixis.h"
@@ -90,34 +91,58 @@
#define CONFIG_TFP410_I2C_ADDR 0x38
+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
+
+/* Route the I2C1 pins to the SSI port instead. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
+
+/* Choose the 12.288Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
+
+/* Choose the 11.2896Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
+
int misc_init_r(void)
{
u8 temp;
+ const char *audclk;
+ size_t arglen;
- /* Enable the TFP410 Encoder */
+ /* For DVI, enable the TFP410 Encoder. */
temp = 0xBF;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
-
- /* Verify if enabled */
- temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
-
debug("DVI Encoder Read: 0x%02x\n", temp);
temp = 0x10;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
-
- /* Verify if enabled */
- temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
-
debug("DVI Encoder Read: 0x%02x\n",temp);
+ /*
+ * Enable the reference clock for the WM8776 codec, and route the MUX
+ * pins for SSI. The default is the 12.288 MHz clock
+ */
+
+ temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+ CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+ temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ /* Check the first two chars only */
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+ else
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+ out_8(&pixis->brdcfg1, temp);
+
return 0;
}
@@ -310,6 +335,27 @@
}
#ifdef CONFIG_OF_BOARD_SETUP
+/**
+ * ft_codec_setup - fix up the clock-frequency property of the codec node
+ *
+ * Update the clock-frequency property based on the value of the 'audclk'
+ * hwconfig option. If audclk is not specified, then default to 12.288MHz.
+ */
+static void ft_codec_setup(void *blob, const char *compatible)
+{
+ const char *audclk;
+ size_t arglen;
+ u32 freq;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ freq = 11289600;
+ else
+ freq = 12288000;
+
+ do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+}
+
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
@@ -327,6 +373,9 @@
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
+
+ /* Update the WM8776 node's clock frequency property */
+ ft_codec_setup(blob, "wlf,wm8776");
}
#endif
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 624c708..d3300ed 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -430,12 +430,12 @@
int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong size,src,ld_addr;
+ ulong ld_addr;
int result;
#if !defined(CONFIG_PATI)
+ ulong size = IMAGE_SIZE;
+ ulong src = MULTI_PURPOSE_SOCKET_ADDR;
backup_t back;
- src = MULTI_PURPOSE_SOCKET_ADDR;
- size = IMAGE_SIZE;
#endif
if (strcmp(argv[1], "flash") == 0)
@@ -480,30 +480,6 @@
}
#endif /* #if !defined(CONFIG_PATI) */
}
- if (strcmp(argv[1], "mem") == 0)
- {
- result=0;
- if(argc==3)
- {
- result = (int)simple_strtol(argv[2], NULL, 16);
- }
- src=(unsigned long)&result;
- src-=CONFIG_SYS_MEMTEST_START;
- src-=(100*1024); /* - 100k */
- src&=0xfff00000;
- size=0;
- do {
- size++;
- printf("\n\nPass %ld\n",size);
- mem_test(CONFIG_SYS_MEMTEST_START,src,1);
- if(ctrlc())
- break;
- if(result>0)
- result--;
-
- }while(result);
- return 0;
- }
#if !defined(CONFIG_PATI)
if (strcmp(argv[1], "clearenvvalues") == 0)
{
diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c
deleted file mode 100644
index 9c08065..0000000
--- a/board/mpl/common/memtst.c
+++ /dev/null
@@ -1,565 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/* NOT Used yet...
- add following code to PIP405.c :
-int testdram (void)
-{
- unsigned char s[32];
- int i;
-
- i = getenv_f("testmem", s, 32);
- if (i != 0) {
- i = (int) simple_strtoul (s, NULL, 10);
- if ((i > 0) && (i < 0xf)) {
- printf ("testing ");
- i = mem_test (0, ramsize, i);
- if (i > 0)
- printf ("ERROR ");
- else
- printf ("Ok ");
- }
- }
- return (1);
-}
-*/
-
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FALSE 0
-#define TRUE 1
-
-#define TEST_QUIET 8
-#define TEST_SHOW_PROG 4
-#define TEST_SHOW_ERR 2
-#define TEST_SHOW_ALL 1
-
-#define TESTPAT1 0xAA55AA55
-#define TESTPAT2 0x55AA55AA
-#define TEST_PASSED 0
-#define TEST_FAILED 1
-#define MEGABYTE (1024*1024)
-
-
-typedef struct {
- volatile unsigned long pat1;
- volatile unsigned long pat2;
-} RAM_MEMTEST_PATTERN2;
-
-typedef struct {
- volatile unsigned long addr;
-} RAM_MEMTEST_ADDRLINE;
-
-static __inline unsigned long Swap_32 (unsigned long val)
-{
- return (((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF));
-}
-
-void testm_puts (int quiet, char *buf)
-{
- if ((quiet & TEST_SHOW_ALL) == TEST_SHOW_ALL)
- puts (buf);
-}
-
-
-void Write_Error (int mode, unsigned long addr, unsigned long expected,
- unsigned long actual)
-{
-
- char dispbuf[64];
-
- sprintf (dispbuf, "\n ERROR @ 0x%08lX: (exp: 0x%08lX act: 0x%08lX) ",
- addr, expected, actual);
- testm_puts (((mode & TEST_SHOW_ERR) ==
- TEST_SHOW_ERR) ? TEST_SHOW_ALL : mode, dispbuf);
-}
-
-
-/*
- * fills the memblock of <size> bytes from <startaddr> with pat1 and pat2
- */
-
-
-void RAM_MemTest_WritePattern2 (unsigned long startaddr,
- unsigned long size, unsigned long pat1,
- unsigned long pat2)
-{
- RAM_MEMTEST_PATTERN2 *p, *pe;
-
- p = (RAM_MEMTEST_PATTERN2 *) startaddr;
- pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size);
-
- while (p < pe) {
- p->pat1 = pat1;
- p->pat2 = pat2;
- p++;
- } /* endwhile */
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr> with pat1 and pat2
- * returns the address of the first error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckPattern2 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long pat1,
- unsigned long pat2)
-{
- RAM_MEMTEST_PATTERN2 *p, *pe;
- unsigned long actual1, actual2;
-
- p = (RAM_MEMTEST_PATTERN2 *) startaddr;
- pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size);
-
- while (p < pe) {
- actual1 = p->pat1;
- actual2 = p->pat2;
-
- if (actual1 != pat1) {
- Write_Error (mode, (unsigned long) &(p->pat1), pat1, actual1);
- return ((void *) &(p->pat1));
- }
- /* endif */
- if (actual2 != pat2) {
- Write_Error (mode, (unsigned long) &(p->pat2), pat2, actual2);
- return ((void *) &(p->pat2));
- }
- /* endif */
- p++;
- } /* endwhile */
-
- return (NULL);
-}
-
-/*
- * fills the memblock of <size> bytes from <startaddr> with the address
- */
-
-void RAM_MemTest_WriteAddrLine (unsigned long startaddr,
- unsigned long size, int swapped)
-{
- RAM_MEMTEST_ADDRLINE *p, *pe;
-
- p = (RAM_MEMTEST_ADDRLINE *) startaddr;
- pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size);
-
- if (!swapped) {
- while (p < pe) {
- p->addr = (unsigned long) p;
- p++;
- } /* endwhile */
- } else {
- while (p < pe) {
- p->addr = Swap_32 ((unsigned long) p);
- p++;
- } /* endwhile */
- } /* endif */
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr>
- * returns the address of the error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckAddrLine (int mode, unsigned long startaddr,
- unsigned long size, int swapped)
-{
- RAM_MEMTEST_ADDRLINE *p, *pe;
- unsigned long actual, expected;
-
- p = (RAM_MEMTEST_ADDRLINE *) startaddr;
- pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size);
-
- if (!swapped) {
- while (p < pe) {
- actual = p->addr;
- expected = (unsigned long) p;
- if (actual != expected) {
- Write_Error (mode, (unsigned long) &(p->addr), expected,
- actual);
- return ((void *) &(p->addr));
- } /* endif */
- p++;
- } /* endwhile */
- } else {
- while (p < pe) {
- actual = p->addr;
- expected = Swap_32 ((unsigned long) p);
- if (actual != expected) {
- Write_Error (mode, (unsigned long) &(p->addr), expected,
- actual);
- return ((void *) &(p->addr));
- } /* endif */
- p++;
- } /* endwhile */
- } /* endif */
-
- return (NULL);
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr+size>
- * returns the address of the error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckAddrLineReverse (int mode, unsigned long startaddr,
- unsigned long size, int swapped)
-{
- RAM_MEMTEST_ADDRLINE *p, *pe;
- unsigned long actual, expected;
-
- p = (RAM_MEMTEST_ADDRLINE *) (startaddr + size - sizeof (p->addr));
- pe = (RAM_MEMTEST_ADDRLINE *) startaddr;
-
- if (!swapped) {
- while (p > pe) {
- actual = p->addr;
- expected = (unsigned long) p;
- if (actual != expected) {
- Write_Error (mode, (unsigned long) &(p->addr), expected,
- actual);
- return ((void *) &(p->addr));
- } /* endif */
- p--;
- } /* endwhile */
- } else {
- while (p > pe) {
- actual = p->addr;
- expected = Swap_32 ((unsigned long) p);
- if (actual != expected) {
- Write_Error (mode, (unsigned long) &(p->addr), expected,
- actual);
- return ((void *) &(p->addr));
- } /* endif */
- p--;
- } /* endwhile */
- } /* endif */
-
- return (NULL);
-}
-
-/*
- * fills the memblock of <size> bytes from <startaddr> with walking bit pattern
- */
-
-void RAM_MemTest_WriteWalkBit (unsigned long startaddr, unsigned long size)
-{
- volatile unsigned long *p, *pe;
- unsigned long i;
-
- p = (unsigned long *) startaddr;
- pe = (unsigned long *) (startaddr + size);
- i = 0;
-
- while (p < pe) {
- *p = 1UL << i;
- i = (i + 1 + (((unsigned long) p) >> 7)) % 32;
- p++;
- } /* endwhile */
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr>
- * returns the address of the error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckWalkBit (int mode, unsigned long startaddr,
- unsigned long size)
-{
- volatile unsigned long *p, *pe;
- unsigned long actual, expected;
- unsigned long i;
-
- p = (unsigned long *) startaddr;
- pe = (unsigned long *) (startaddr + size);
- i = 0;
-
- while (p < pe) {
- actual = *p;
- expected = (1UL << i);
- if (actual != expected) {
- Write_Error (mode, (unsigned long) p, expected, actual);
- return ((void *) p);
- } /* endif */
- i = (i + 1 + (((unsigned long) p) >> 7)) % 32;
- p++;
- } /* endwhile */
-
- return (NULL);
-}
-
-/*
- * fills the memblock of <size> bytes from <startaddr> with "random" pattern
- */
-
-void RAM_MemTest_WriteRandomPattern (unsigned long startaddr,
- unsigned long size,
- unsigned long *pat)
-{
- unsigned long i, p;
-
- p = *pat;
-
- for (i = 0; i < (size / 4); i++) {
- *(unsigned long *) (startaddr + i * 4) = p;
- if ((p % 2) > 0) {
- p ^= i;
- p >>= 1;
- p |= 0x80000000;
- } else {
- p ^= ~i;
- p >>= 1;
- } /* endif */
- } /* endfor */
- *pat = p;
-}
-
-/*
- * checks the memblock of <size> bytes from <startaddr>
- * returns the address of the error or NULL if all is well
- */
-
-void *RAM_MemTest_CheckRandomPattern (int mode, unsigned long startaddr,
- unsigned long size,
- unsigned long *pat)
-{
- void *perr = NULL;
- unsigned long i, p, p1;
-
- p = *pat;
-
- for (i = 0; i < (size / 4); i++) {
- p1 = *(unsigned long *) (startaddr + i * 4);
- if (p1 != p) {
- if (perr == NULL) {
- Write_Error (mode, startaddr + i * 4, p, p1);
- perr = (void *) (startaddr + i * 4);
- } /* endif */
- }
- /* endif */
- if ((p % 2) > 0) {
- p ^= i;
- p >>= 1;
- p |= 0x80000000;
- } else {
- p ^= ~i;
- p >>= 1;
- } /* endif */
- } /* endfor */
-
- *pat = p;
- return (perr);
-}
-
-
-void RAM_MemTest_WriteData1 (unsigned long startaddr, unsigned long size,
- unsigned long *pat)
-{
- RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT1, TESTPAT2);
-}
-
-void *RAM_MemTest_CheckData1 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckPattern2
- (mode, startaddr, size, TESTPAT1, TESTPAT2));
-}
-
-void RAM_MemTest_WriteData2 (unsigned long startaddr, unsigned long size,
- unsigned long *pat)
-{
- RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT2, TESTPAT1);
-}
-
-void *RAM_MemTest_CheckData2 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckPattern2
- (mode, startaddr, size, TESTPAT2, TESTPAT1));
-}
-
-void RAM_MemTest_WriteAddr1 (unsigned long startaddr, unsigned long size,
- unsigned long *pat)
-{
- RAM_MemTest_WriteAddrLine (startaddr, size, FALSE);
-}
-
-void *RAM_MemTest_Check1Addr1 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, FALSE));
-}
-
-void *RAM_MemTest_Check2Addr1 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckAddrLineReverse
- (mode, startaddr, size, FALSE));
-}
-
-void RAM_MemTest_WriteAddr2 (unsigned long startaddr, unsigned long size,
- unsigned long *pat)
-{
- RAM_MemTest_WriteAddrLine (startaddr, size, TRUE);
-}
-
-void *RAM_MemTest_Check1Addr2 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, TRUE));
-}
-
-void *RAM_MemTest_Check2Addr2 (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat)
-{
- return (RAM_MemTest_CheckAddrLineReverse
- (mode, startaddr, size, TRUE));
-}
-
-
-typedef struct {
- void (*test_write) (unsigned long startaddr, unsigned long size,
- unsigned long *pat);
- char *test_write_desc;
- void *(*test_check1) (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat);
- void *(*test_check2) (int mode, unsigned long startaddr,
- unsigned long size, unsigned long *pat);
-} RAM_MEMTEST_FUNC;
-
-
-#define TEST_STAGES 5
-static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = {
- {RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1,
- NULL},
- {RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2,
- NULL},
- {RAM_MemTest_WriteAddr1, "address line test...\n",
- RAM_MemTest_Check1Addr1, RAM_MemTest_Check2Addr1},
- {RAM_MemTest_WriteAddr2, "address line test (swapped)...\n",
- RAM_MemTest_Check1Addr2, RAM_MemTest_Check2Addr2},
- {RAM_MemTest_WriteRandomPattern, "random data test...\n",
- RAM_MemTest_CheckRandomPattern, NULL}
-};
-
-
-int mem_test (unsigned long start, unsigned long ramsize, int quiet)
-{
- unsigned long errors, stage;
- unsigned long startaddr, size, i;
- const unsigned long blocksize = 0x80000; /* check in 512KB blocks */
- unsigned long *perr;
- unsigned long rdatapat;
- char dispbuf[80];
- int status = TEST_PASSED;
- int prog = 0;
-
- errors = 0;
- startaddr = start;
- size = ramsize;
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- prog++;
- printf (".");
- }
- sprintf (dispbuf, "\nMemory Test: addr = 0x%lx size = 0x%lx\n",
- startaddr, size);
- testm_puts (quiet, dispbuf);
- for (stage = 0; stage < TEST_STAGES; stage++) {
- sprintf (dispbuf, test_stage[stage].test_write_desc);
- testm_puts (quiet, dispbuf);
- /* fill SDRAM */
- rdatapat = 0x12345678;
- sprintf (dispbuf, "writing block: ");
- testm_puts (quiet, dispbuf);
- for (i = 0; i < size; i += blocksize) {
- sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
- testm_puts (quiet, dispbuf);
- test_stage[stage].test_write (startaddr + i, blocksize,
- &rdatapat);
- } /* endfor */
- sprintf (dispbuf, "\n");
- testm_puts (quiet, dispbuf);
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- prog++;
- printf (".");
- }
- /* check SDRAM */
- rdatapat = 0x12345678;
- sprintf (dispbuf, "checking block: ");
- testm_puts (quiet, dispbuf);
- for (i = 0; i < size; i += blocksize) {
- sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
- testm_puts (quiet, dispbuf);
- if ((perr =
- test_stage[stage].test_check1 (quiet, startaddr + i,
- blocksize,
- &rdatapat)) != NULL) {
- status = TEST_FAILED;
- } /* endif */
- } /* endfor */
- sprintf (dispbuf, "\n");
- testm_puts (quiet, dispbuf);
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- prog++;
- printf (".");
- }
- if (test_stage[stage].test_check2 != NULL) {
- /* check2 SDRAM */
- sprintf (dispbuf, "2nd checking block: ");
- rdatapat = 0x12345678;
- testm_puts (quiet, dispbuf);
- for (i = 0; i < size; i += blocksize) {
- sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
- testm_puts (quiet, dispbuf);
- if ((perr =
- test_stage[stage].test_check2 (quiet, startaddr + i,
- blocksize,
- &rdatapat)) != NULL) {
- status = TEST_FAILED;
- } /* endif */
- } /* endfor */
- sprintf (dispbuf, "\n");
- testm_puts (quiet, dispbuf);
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- prog++;
- printf (".");
- }
- }
-
- } /* next stage */
- if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
- while (prog-- > 0)
- printf ("\b \b");
- }
-
- if (status == TEST_FAILED)
- errors++;
-
- return (errors);
-}
diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile
index 18a8d86..21e3cda 100644
--- a/board/mpl/mip405/Makefile
+++ b/board/mpl/mip405/Makefile
@@ -29,7 +29,7 @@
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \
- ../common/usb_uhci.o ../common/memtst.o ../common/common_util.o
+ ../common/usb_uhci.o ../common/common_util.o
SOBJS = init.o
diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c
index 8ddb54d..f7cc37b 100644
--- a/board/mpl/mip405/cmd_mip405.c
+++ b/board/mpl/mip405/cmd_mip405.c
@@ -59,8 +59,7 @@
"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
"mip405 flash mps - updates U-Boot with image from MPS\n"
"mip405 info - displays board information\n"
- "mip405 led <on> - switches LED on (on=1) or off (on=0)\n"
- "mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever"
+ "mip405 led <on> - switches LED on (on=1) or off (on=0)"
);
/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile
index adeba69..9f38d70 100644
--- a/board/mpl/pati/Makefile
+++ b/board/mpl/pati/Makefile
@@ -28,7 +28,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o
+COBJS := pati.o ../common/flash.o cmd_pati.o ../common/common_util.o
#### cmd_pati.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile
index 774b59f..fb39ec3 100644
--- a/board/mpl/pip405/Makefile
+++ b/board/mpl/pip405/Makefile
@@ -32,7 +32,7 @@
../common/flash.o cmd_pip405.o ../common/pci.o \
../common/isa.o ../common/kbd.o \
../common/usb_uhci.o \
- ../common/memtst.o ../common/common_util.o
+ ../common/common_util.o
SOBJS = init.o
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
index 10bcb3b..3f629fc 100644
--- a/board/mpl/vcma9/Makefile
+++ b/board/mpl/vcma9/Makefile
@@ -29,7 +29,7 @@
LIB = $(obj)lib$(BOARD).a
COBJS := vcma9.o flash.o cmd_vcma9.o
-COBJS += ../common/common_util.o ../common/memtst.o
+COBJS += ../common/common_util.o
SOBJS := lowlevel_init.o
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index e41c84c..4dc0237 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -96,7 +96,6 @@
static void pm9263_macb_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
/*
* PB27 enables the 50MHz oscillator for Ethernet PHY
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 3b4d9a3..f3d48f2 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -96,7 +96,6 @@
static void pm9g45_macb_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
- at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
/*
* PD2 enables the 50MHz oscillator for Ethernet PHY
diff --git a/board/siemens/CCM/Makefile b/board/siemens/CCM/Makefile
deleted file mode 100644
index c5695f9..0000000
--- a/board/siemens/CCM/Makefile
+++ /dev/null
@@ -1,56 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-$(shell mkdir -p $(obj)../../tqc/tqm8xx)
-endif
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \
- ../../tqc/tqm8xx/load_sernum_ethaddr.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c
deleted file mode 100644
index e91ceb0..0000000
--- a/board/siemens/CCM/ccm.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-#include <command.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-void can_driver_enable (void);
-void can_driver_disable (void);
-
-int fpga_init(void);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
- 0x1FF5FC47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Always return 1 (no second DRAM bank since based on TQM8xxL module)
- */
-
-int checkboard (void)
-{
- unsigned char *s;
- unsigned char buf[64];
-
- s = (getenv_f("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL;
-
- puts ("Board: Siemens CCM");
-
- if (s) {
- puts (" (");
-
- for (; *s; ++s) {
- if (*s == ' ')
- break;
- putc (*s);
- }
- putc (')');
- }
-
- putc ('\n');
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * If Power-On-Reset switch off the Red and Green LED: At reset, the
- * data direction registers are cleared and must therefore be restored.
- */
-#define RSR_CSRS 0x08000000
-
-int power_on_reset(void)
-{
- /* Test Reset Status Register */
- return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
-}
-
-#define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */
-#define PB_LED_RED 0x20000 /* red LED is on PB.14 */
-#define PB_LEDS (PB_LED_GREEN | PB_LED_RED);
-
-static void init_leds (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-
- immap->im_cpm.cp_pbpar &= ~PB_LEDS;
- immap->im_cpm.cp_pbodr &= ~PB_LEDS;
- immap->im_cpm.cp_pbdir |= PB_LEDS;
- /* Check stop reset status */
- if (power_on_reset()) {
- immap->im_cpm.cp_pbdat &= ~PB_LEDS;
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size8, size9;
- long int size = 0;
- unsigned long reg;
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay(200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
- udelay(1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size = size9;
-/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay(500);
-/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if (size < 0x02000000) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay(1000);
- }
-
- /*
- * Final mapping
- */
-
- memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
-
- can_driver_enable ();
- init_leds ();
-
- udelay(10000);
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Warning - both the PUMA load mode and the CAN driver use UPM B,
- * so make sure only one of both is active.
- */
-void can_driver_enable (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* Initialize MBMR */
- memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
-
- /* Initialize UPMB for CAN: single read */
- memctl->memc_mdr = 0xFFFFC004;
- memctl->memc_mcr = 0x0100 | UPMB;
-
- memctl->memc_mdr = 0x0FFFD004;
- memctl->memc_mcr = 0x0101 | UPMB;
-
- memctl->memc_mdr = 0x0FFFC000;
- memctl->memc_mcr = 0x0102 | UPMB;
-
- memctl->memc_mdr = 0x3FFFC004;
- memctl->memc_mcr = 0x0103 | UPMB;
-
- memctl->memc_mdr = 0xFFFFDC05;
- memctl->memc_mcr = 0x0104 | UPMB;
-
- /* Initialize UPMB for CAN: single write */
- memctl->memc_mdr = 0xFFFCC004;
- memctl->memc_mcr = 0x0118 | UPMB;
-
- memctl->memc_mdr = 0xCFFCD004;
- memctl->memc_mcr = 0x0119 | UPMB;
-
- memctl->memc_mdr = 0x0FFCC000;
- memctl->memc_mcr = 0x011A | UPMB;
-
- memctl->memc_mdr = 0x7FFCC004;
- memctl->memc_mcr = 0x011B | UPMB;
-
- memctl->memc_mdr = 0xFFFDCC05;
- memctl->memc_mcr = 0x011C | UPMB;
-
- /* Initialize OR3 / BR3 for CAN Bus Controller */
- memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
- memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
-}
-
-void can_driver_disable (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* Reset OR3 / BR3 to disable CAN Bus Controller */
- memctl->memc_br3 = 0;
- memctl->memc_or3 = 0;
-
- memctl->memc_mbmr = 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
-
-#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN)
-
-void reset_phy(void)
-{
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- ulong value;
-
- /* Configure all needed port pins for GPIO */
-#ifdef CONFIG_SYS_ETH_MDDIS_VALUE
- immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
-#else
- immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* Set low */
-#endif
- immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* GPIO */
- immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* active output */
- immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET; /* output */
-
- immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
-
- value = immr->im_cpm.cp_pbdat;
-
- /* Assert Powerdown and Reset signals */
- value |= CONFIG_SYS_PB_ETH_POWERDOWN;
-
- /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
-#ifdef CONFIG_SYS_ETH_CFG1_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG1;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG1);
-#endif
-#ifdef CONFIG_SYS_ETH_CFG2_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG2;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG2);
-#endif
-#ifdef CONFIG_SYS_ETH_CFG3_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG3;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG3);
-#endif
-
- /* Drive output signals to initial state */
- immr->im_cpm.cp_pbdat = value;
- immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
- udelay (10000);
-
- /* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
- udelay (10000);
-
- /* de-assert RESET signal of PHY */
- immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET;
- udelay (1000);
-}
-
-
-int misc_init_r (void)
-{
- fpga_init();
- return (0);
-}
-/* ------------------------------------------------------------------------- */
diff --git a/board/siemens/CCM/config.mk b/board/siemens/CCM/config.mk
deleted file mode 100644
index 9c72c79..0000000
--- a/board/siemens/CCM/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# TQM8xxL boards
-#
-
-TEXT_BASE = 0x40000000
diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c
deleted file mode 100644
index ad1ed79..0000000
--- a/board/siemens/CCM/flash.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
- memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
- &flash_info[1]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[1]);
-#endif
- } else {
- memctl->memc_br1 = 0; /* invalidate bank */
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-
- value = addr[0];
-
- switch (value) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c
deleted file mode 100644
index 50b08ab..0000000
--- a/board/siemens/CCM/fpga_ccm.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-#include <common.h>
-
-#include "../common/fpga.h"
-
-fpga_t fpga_list[] = {
- { "PUMA" , PUMA_CONF_BASE ,
- CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE }
-};
-int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
-
-void can_driver_enable (void);
-void can_driver_disable (void);
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*
- * PUMA access using UPM B
- */
-const uint puma_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_,
- /*
- * Precharge and MRS
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-
-ulong fpga_control (fpga_t* fpga, int cmd)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- switch (cmd) {
- case FPGA_INIT_IS_HIGH:
- immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */
- return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0;
-
- case FPGA_INIT_SET_LOW:
- immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
- immr->im_ioport.iop_pcdat &= ~fpga->init_mask;
- break;
-
- case FPGA_INIT_SET_HIGH:
- immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
- immr->im_ioport.iop_pcdat |= fpga->init_mask;
- break;
-
- case FPGA_PROG_SET_LOW:
- immr->im_ioport.iop_pcdat &= ~fpga->prog_mask;
- break;
-
- case FPGA_PROG_SET_HIGH:
- immr->im_ioport.iop_pcdat |= fpga->prog_mask;
- break;
-
- case FPGA_DONE_IS_HIGH:
- return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0;
-
- case FPGA_READ_MODE:
- /* disable FPGA in memory controller */
- memctl->memc_br4 = 0;
- memctl->memc_or4 = PUMA_CONF_OR_READ;
- memctl->memc_br4 = PUMA_CONF_BR_READ;
-
- /* (re-) enable CAN drivers */
- can_driver_enable ();
-
- break;
-
- case FPGA_LOAD_MODE:
- /* disable FPGA in memory controller */
- memctl->memc_br4 = 0;
- /*
- * We must disable the CAN drivers first because
- * they use UPM B, too.
- */
- can_driver_disable ();
- /*
- * Configure UPMB for FPGA
- */
- upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
- memctl->memc_or4 = PUMA_CONF_OR_LOAD;
- memctl->memc_br4 = PUMA_CONF_BR_LOAD;
- break;
-
- case FPGA_GET_ID:
- return *(volatile ulong *)fpga->conf_base;
-
- case FPGA_INIT_PORTS:
- immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */
- immr->im_ioport.iop_pcso &= ~fpga->init_mask;
- immr->im_ioport.iop_pcdir &= ~fpga->init_mask;
-
- immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */
- immr->im_ioport.iop_pcso &= ~fpga->prog_mask;
- immr->im_ioport.iop_pcdir |= fpga->prog_mask;
-
- immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */
- immr->im_ioport.iop_pcso &= ~fpga->done_mask;
- immr->im_ioport.iop_pcdir &= ~fpga->done_mask;
-
- break;
-
- }
- return 0;
-}
diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds
deleted file mode 100644
index 36dd55d..0000000
--- a/board/siemens/CCM/u-boot.lds
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- arch/powerpc/lib/ppcstring.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- lib/zlib.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug
deleted file mode 100644
index 7e066b1..0000000
--- a/board/siemens/CCM/u-boot.lds.debug
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-/*
- . = env_offset;
- common/env_embedded.o(.text)
-*/
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/siemens/pcu_e/Makefile b/board/siemens/pcu_e/Makefile
deleted file mode 100644
index dcb1907..0000000
--- a/board/siemens/pcu_e/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS = $(BOARD).o flash.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/siemens/pcu_e/config.mk b/board/siemens/pcu_e/config.mk
deleted file mode 100644
index 10f3773..0000000
--- a/board/siemens/pcu_e/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Siemens PCU E Boards
-#
-
-TEXT_BASE = 0xFFF00000
diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c
deleted file mode 100644
index 3ce7bb3..0000000
--- a/board/siemens/pcu_e/flash.c
+++ /dev/null
@@ -1,700 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- *
- * The PCU E uses an address map where flash banks are aligned top
- * down, so that the "first" flash bank ends at top of memory, and
- * the monitor entry point is at address (0xFFF00100). The second
- * flash bank is mapped immediately below bank 0.
- *
- * This is NOT in conformance to the "official" memory map!
- *
- */
-
-#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \
- - (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) )
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long base, size_b0, size_b1;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- /*
- * Warning:
- *
- * Since the PCU E memory map assigns flash banks top down,
- * we swap the numbering later if both banks are equipped,
- * so they look like a contiguous area of memory.
- */
- DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE6_PRELIM);
- size_b1 = flash_get_size((vu_long *)FLASH_BASE6_PRELIM, &flash_info[1]);
-
- DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n", size_b0, size_b1);
-
- if (size_b1 > size_b0) {
- printf ("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1<<20,
- size_b0, size_b0<<20
- );
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
- return (0);
- }
-
- DEBUGF ("## Before remap: "
- "BR0: 0x%08x OR0: 0x%08x "
- "BR6: 0x%08x OR6: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0,
- memctl->memc_br6, memctl->memc_or6);
-
- /* Remap FLASH according to real size */
- base = 0 - size_b0;
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
-
- DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0);
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)base, &flash_info[0]);
- base = 0 - size_b0;
-
- flash_info[0].size = size_b0;
-
- flash_get_offsets (base, &flash_info[0]);
-
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- PCU_MONITOR_BASE,
- PCU_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- flash_info_t tmp_info;
-
- memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
- memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) |
- BR_PS_16 | BR_MS_GPCM | BR_V;
-
- DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n",
- memctl->memc_br6, memctl->memc_or6);
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(base - size_b1),
- &flash_info[1]);
- base -= size_b1;
-
- flash_get_offsets (base, &flash_info[1]);
-
- flash_info[1].size = size_b1;
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[1]);
-#endif
- /*
- * Swap bank numbers so that addresses are in ascending order
- */
- tmp_info = flash_info[0];
- flash_info[0] = flash_info[1];
- flash_info[1] = tmp_info;
- } else {
- memctl->memc_br1 = 0; /* invalidate bank */
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
-
- DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
- return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
- short n;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) {
- return;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDL322T:
- case FLASH_AMDL323T:
- case FLASH_AMDL324T:
- /* set sector offsets for top boot block type */
-
- base += info->size;
- i = info->sector_count;
- for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- return;
- case FLASH_AMDL322B:
- case FLASH_AMDL323B:
- case FLASH_AMDL324B:
- /* set sector offsets for bottom boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- while (base < info->size) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- return;
- case FLASH_AMDL640:
- /* set sector offsets for dual boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- n = info->sector_count - 8;
- while (i < n) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- while (i < info->sector_count) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- ++i;
- }
- return;
- default:
- return;
- }
- /* NOTREACHED */
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n");
- break;
- default: printf ("Unknown Chip Type 0x%lX\n",
- info->flash_id);
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ushort value;
- vu_short *saddr = (vu_short *)addr;
-
- /* Write auto select command: read Manufacturer ID */
- saddr[0x0555] = 0x00AA;
- saddr[0x02AA] = 0x0055;
- saddr[0x0555] = 0x0090;
-
- value = saddr[0];
-
- DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value);
-
- switch (value) {
- case (AMD_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFFFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- DEBUGF("Unknown Manufacturer ID\n");
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = saddr[1]; /* device ID */
-
- DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value);
-
- switch (value) {
-
- case (AMD_ID_DL322T & 0xFFFF):
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL322B & 0xFFFF):
- info->flash_id += FLASH_AMDL322B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL323T & 0xFFFF):
- info->flash_id += FLASH_AMDL323T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL323B & 0xFFFF):
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL324T & 0xFFFF):
- info->flash_id += FLASH_AMDL324T;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL324B & 0xFFFF):
- info->flash_id += FLASH_AMDL324B;
- info->sector_count = 71;
- info->size = 0x00400000;
- break; /* => 8 MB */
- case (AMD_ID_DL640 & 0xFFFF):
- info->flash_id += FLASH_AMDL640;
- info->sector_count = 142;
- info->size = 0x00800000;
- break;
- default:
- DEBUGF("Unknown Device ID\n");
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- flash_get_offsets ((ulong)addr, info);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
-#if 0
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- saddr = (vu_short *)(info->start[i]);
- info->protect[i] = saddr[2] & 1;
-#else
- info->protect[i] =0;
-#endif
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- saddr = (vu_short *)info->start[0];
- *saddr = 0x00F0; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_short *addr = (vu_short*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x0080;
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_short*)(info->start[sect]);
- addr[0] = 0x0030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_short*)(info->start[l_sect]);
- while ((addr[0] & 0x0080) != 0x0080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_short *)info->start[0];
- addr[0] = 0x00F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-#define FLASH_WIDTH 2 /* flash bus width in bytes */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<FLASH_WIDTH && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- }
-
- /*
- * handle FLASH_WIDTH aligned part
- */
- while (cnt >= FLASH_WIDTH) {
- data = 0;
- for (i=0; i<FLASH_WIDTH; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data(info, wp, data)) != 0) {
- return (rc);
- }
- wp += FLASH_WIDTH;
- cnt -= FLASH_WIDTH;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<FLASH_WIDTH; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_data(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, ulong data)
-{
- vu_short *addr = (vu_short*)(info->start[0]);
- vu_short *sdest = (vu_short *)dest;
- ushort sdata = (ushort)data;
- ushort sval;
- ulong start, passed;
- int flag, rc;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*sdest & sdata) != sdata) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x00A0;
-
-#ifdef WORKAROUND_FOR_BROKEN_HARDWARE
- /* work around the timeout bugs */
- udelay(20);
-#endif
-
- *sdest = sdata;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- rc = 0;
- /* data polling for D7 */
- start = get_timer (0);
-
- for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) {
-
- sval = *sdest;
-
- if ((sval & 0x0080) == (sdata & 0x0080))
- break;
-
- if ((sval & 0x0020) == 0) /* DQ5: Timeout? */
- continue;
-
- sval = *sdest;
-
- if ((sval & 0x0080) != (sdata & 0x0080))
- rc = 1;
-
- break;
- }
-
- if (rc) {
- DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n",
- dest, sval, sdata);
- }
-
- if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) {
- DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n",
- dest, sval, sdata);
- rc = 1;
- }
-
- /* reset to read mode */
- addr = (vu_short *)info->start[0];
- addr[0] = 0x00F0; /* reset bank */
-
- return (rc);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c
deleted file mode 100644
index 9795284..0000000
--- a/board/siemens/pcu_e/pcu_e.c
+++ /dev/null
@@ -1,562 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-#include <i2c.h>
-#include <command.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-static void puma_status (void);
-static void puma_set_mode (int mode);
-static int puma_init_done (void);
-static void puma_load (ulong addr, ulong len);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*
- * 50 MHz SDRAM access using UPM A
- */
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
- 0x1ffddc47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPM RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
- 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * PUMA access using UPM B
- */
-const uint puma_table[] = {
- /*
- * Single Read. (Offset 0 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_,
- /*
- * Precharge and MRS
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Read. (Offset 8 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPM RAM)
- */
- 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPM RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPM RAM)
- */
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- */
-
-int checkboard (void)
-{
- puts ("Board: Siemens PCU E\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- long int size_b0, reg;
- int i;
-
- /*
- * Configure UPMA for SDRAM
- */
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* burst length=4, burst type=sequential, CAS latency=2 */
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 2 to the SDRAM bank at preliminary address.
- */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
- memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
-#else /* XXX */
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-#endif /* XXX */
-
- /* initialize memory address register */
- memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */
-
- /* mode initialization (offset 5) */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay (200); /* 0x8000A105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
-#else /* XXX */
- udelay (200); /* 0x80004105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
-#endif /* XXX */
-
- /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay (1); /* 0x8000A830 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
-#else /* XXX */
- udelay (1); /* 0x80004830 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
-#endif /* XXX */
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay (1); /* 0x8000A106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
-#else /* XXX */
- udelay (1); /* 0x80004106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
-#endif /* XXX */
-
- reg = memctl->memc_mamr;
- reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
- reg |= MAMR_TLFA_4X; /* ... to 4x */
- reg |= MAMR_PTAE; /* enable refresh */
- memctl->memc_mamr = reg;
-
- udelay (200);
-
- /* Need at least 10 DRAM accesses to stabilize */
- for (i = 0; i < 10; ++i) {
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- volatile unsigned long *addr =
- (volatile unsigned long *) SDRAM_BASE5_PRELIM;
-#else /* XXX */
- volatile unsigned long *addr =
- (volatile unsigned long *) SDRAM_BASE2_PRELIM;
-#endif /* XXX */
- unsigned long val;
-
- val = *(addr + i);
- *(addr + i) = val;
- }
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
-#else /* XXX */
- size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-#endif /* XXX */
-
- memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE;
-
- /*
- * Final mapping:
- */
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-#else /* XXX */
- memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-#endif /* XXX */
- udelay (1000);
-
- /*
- * Configure UPMB for PUMA
- */
- upmconfig (UPMB, (uint *) puma_table,
- sizeof (puma_table) / sizeof (uint));
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
-#else /* XXX */
-#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \
- CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
-#endif /* XXX */
-
-#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET)
-
-void reset_phy (void)
-{
- immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- ulong value;
-
- /* Configure all needed port pins for GPIO */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
- immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
-# else
- immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */
-# endif
- immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */
- immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */
- immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */
-#endif /* XXX */
- immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
-
- value = immr->im_cpm.cp_pbdat;
-
- /* Assert Powerdown and Reset signals */
- value |= CONFIG_SYS_PB_ETH_POWERDOWN;
- value &= ~(CONFIG_SYS_PB_ETH_RESET);
-
- /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
-#if !PCU_E_WITH_SWAPPED_CS
-# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
- value |= CONFIG_SYS_PB_ETH_MDDIS;
-# else
- value &= ~(CONFIG_SYS_PB_ETH_MDDIS);
-# endif
-#endif
-#ifdef CONFIG_SYS_ETH_CFG1_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG1;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG1);
-#endif
-#ifdef CONFIG_SYS_ETH_CFG2_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG2;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG2);
-#endif
-#ifdef CONFIG_SYS_ETH_CFG3_VALUE
- value |= CONFIG_SYS_PB_ETH_CFG3;
-#else
- value &= ~(CONFIG_SYS_PB_ETH_CFG3);
-#endif
-
- /* Drive output signals to initial state */
- immr->im_cpm.cp_pbdat = value;
- immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
- udelay (10000);
-
- /* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
- udelay (10000);
-
- /* de-assert RESET signal of PHY */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET;
- udelay (1000);
-}
-
-/*-----------------------------------------------------------------------
- * Board Special Commands: access functions for "PUMA" FPGA
- */
-#if defined(CONFIG_CMD_BSP)
-
-#define PUMA_READ_MODE 0
-#define PUMA_LOAD_MODE 1
-
-int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr, len;
-
- switch (argc) {
- case 2: /* PUMA reset */
- if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
- puma_status ();
- return 0;
- }
- break;
- case 4: /* PUMA load addr len */
- if (strcmp (argv[1], "load") != 0)
- break;
-
- addr = simple_strtoul (argv[2], NULL, 16);
- len = simple_strtoul (argv[3], NULL, 16);
-
- printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
- addr, len, len);
- puma_load (addr, len);
-
- return 0;
- default:
- break;
- }
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD (puma, 4, 1, do_puma,
- "access PUMA FPGA",
- "status - print PUMA status\n"
- "puma load addr len - load PUMA configuration data"
-);
-#endif
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static void puma_set_mode (int mode)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- /* disable PUMA in memory controller */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_br3 = 0;
-#else /* XXX */
- memctl->memc_br4 = 0;
-#endif /* XXX */
-
- switch (mode) {
- case PUMA_READ_MODE:
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or3 = PUMA_CONF_OR_READ;
- memctl->memc_br3 = PUMA_CONF_BR_READ;
-#else /* XXX */
- memctl->memc_or4 = PUMA_CONF_OR_READ;
- memctl->memc_br4 = PUMA_CONF_BR_READ;
-#endif /* XXX */
- break;
- case PUMA_LOAD_MODE:
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or3 = PUMA_CONF_OR_LOAD;
- memctl->memc_br3 = PUMA_CONF_BR_LOAD;
-#else /* XXX */
- memctl->memc_or4 = PUMA_CONF_OR_READ;
- memctl->memc_br4 = PUMA_CONF_BR_READ;
-#endif /* XXX */
- break;
- }
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
-
-static void puma_load (ulong addr, ulong len)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
- uchar *data = (uchar *) addr;
- int i;
-
- /* align length */
- if (len & 1)
- ++len;
-
- /* Reset FPGA */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */
- immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT);
- immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT);
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */
-#else
- immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */
- immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */
- immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */
- immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */
-#endif /* XXX */
- udelay (100);
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */
-#else
- immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */
-#endif /* XXX */
-
- /* wait until INIT indicates completion of reset */
- for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
- udelay (1000);
- if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT)
- break;
- }
- if (i == PUMA_INIT_TIMEOUT) {
- printf ("*** PUMA init timeout ***\n");
- return;
- }
-
- puma_set_mode (PUMA_LOAD_MODE);
-
- while (len--)
- *fpga_addr = *data++;
-
- puma_set_mode (PUMA_READ_MODE);
-
- puma_status ();
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static void puma_status (void)
-{
- /* Check state */
- printf ("PUMA initialization is %scomplete\n",
- puma_init_done ()? "" : "NOT ");
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static int puma_init_done (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
- /* make sure pin is GPIO input */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE);
- immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE);
- immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE);
-
- return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r (void)
-{
- ulong addr = 0;
- ulong len = 0;
- char *s;
-
- printf ("PUMA: ");
- if (puma_init_done ()) {
- printf ("initialized\n");
- return 0;
- }
-
- if ((s = getenv ("puma_addr")) != NULL)
- addr = simple_strtoul (s, NULL, 16);
-
- if ((s = getenv ("puma_len")) != NULL)
- len = simple_strtoul (s, NULL, 16);
-
- if ((!addr) || (!len)) {
- printf ("net list undefined\n");
- return 0;
- }
-
- printf ("loading... ");
-
- puma_load (addr, len);
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds
deleted file mode 100644
index b871958..0000000
--- a/board/siemens/pcu_e/u-boot.lds
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/env_embedded.o(.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug
deleted file mode 100644
index 131ad23..0000000
--- a/board/siemens/pcu_e/u-boot.lds.debug
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/boards.cfg b/boards.cfg
index 9909685..202de1a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -161,9 +161,7 @@
KUP4K powerpc mpc8xx kup4k kup
KUP4X powerpc mpc8xx kup4x kup
ELPT860 powerpc mpc8xx elpt860 LEOX
-CCM powerpc mpc8xx - siemens
IAD210 powerpc mpc8xx - siemens
-pcu_e powerpc mpc8xx - siemens
QS823 powerpc mpc8xx qs850 snmc
QS850 powerpc mpc8xx qs850 snmc
QS860T powerpc mpc8xx qs860t snmc
diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index 104d6e6..bf32612 100644
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -25,7 +25,8 @@
#endif
int valid_elf_image (unsigned long addr);
-unsigned long load_elf_image (unsigned long addr);
+static unsigned long load_elf_image_phdr(unsigned long addr);
+static unsigned long load_elf_image_shdr(unsigned long addr);
/* Allow ports to override the default behavior */
__attribute__((weak))
@@ -61,19 +62,34 @@
{
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
+ char *sload, *saddr;
/* -------------------------------------------------- */
int rcode = 0;
- if (argc < 2)
- addr = load_addr;
+ sload = saddr = NULL;
+ if (argc == 3) {
+ sload = argv[1];
+ saddr = argv[2];
+ } else if (argc == 2) {
+ if (argv[1][0] == '-')
+ sload = argv[1];
+ else
+ saddr = argv[1];
+ }
+
+ if (saddr)
+ addr = simple_strtoul(saddr, NULL, 16);
else
- addr = simple_strtoul (argv[1], NULL, 16);
+ addr = load_addr;
if (!valid_elf_image (addr))
return 1;
- addr = load_elf_image (addr);
+ if (sload && sload[1] == 'p')
+ addr = load_elf_image_phdr(addr);
+ else
+ addr = load_elf_image_shdr(addr);
printf ("## Starting application at 0x%08lx ...\n", addr);
@@ -204,7 +220,7 @@
*/
if (valid_elf_image (addr)) {
- addr = load_elf_image (addr);
+ addr = load_elf_image_shdr (addr);
} else {
puts ("## Not an ELF image, assuming binary\n");
/* leave addr as load_addr */
@@ -258,7 +274,33 @@
* A very simple elf loader, assumes the image is valid, returns the
* entry point address.
* ====================================================================== */
-unsigned long load_elf_image (unsigned long addr)
+static unsigned long load_elf_image_phdr(unsigned long addr)
+{
+ Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+ Elf32_Phdr *phdr; /* Program header structure pointer */
+ int i;
+
+ ehdr = (Elf32_Ehdr *) addr;
+ phdr = (Elf32_Phdr *) (addr + ehdr->e_phoff);
+
+ /* Load each program header */
+ for (i = 0; i < ehdr->e_phnum; ++i) {
+ void *dst = (void *) phdr->p_paddr;
+ void *src = (void *) addr + phdr->p_offset;
+ debug("Loading phdr %i to 0x%p (%i bytes)\n",
+ i, dst, phdr->p_filesz);
+ if (phdr->p_filesz)
+ memcpy(dst, src, phdr->p_filesz);
+ if (phdr->p_filesz != phdr->p_memsz)
+ memset(dst + phdr->p_filesz, 0x00, phdr->p_memsz - phdr->p_filesz);
+ flush_cache((unsigned long)dst, phdr->p_filesz);
+ ++phdr;
+ }
+
+ return ehdr->e_entry;
+}
+
+static unsigned long load_elf_image_shdr(unsigned long addr)
{
Elf32_Ehdr *ehdr; /* Elf header structure pointer */
Elf32_Shdr *shdr; /* Section header structure pointer */
@@ -312,9 +354,11 @@
/* ====================================================================== */
U_BOOT_CMD(
- bootelf, 2, 0, do_bootelf,
+ bootelf, 3, 0, do_bootelf,
"Boot from an ELF image in memory",
- " [address] - load address of ELF image."
+ "[-p|-s] [address]\n"
+ "\t- load ELF image at [address] via program headers (-p)\n"
+ "\t or via section headers (-s)"
);
U_BOOT_CMD(
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index c3d63b8..3d30c32 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -837,6 +837,13 @@
U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""),
};
+#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+void env_reloc(void)
+{
+ fixup_cmdtable(cmd_env_sub, ARRAY_SIZE(cmd_env_sub));
+}
+#endif
+
static int do_env (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *cp;
diff --git a/common/cmd_spi.c b/common/cmd_spi.c
index bafa217..8c623c9 100644
--- a/common/cmd_spi.c
+++ b/common/cmd_spi.c
@@ -47,7 +47,9 @@
/*
* Values from last command.
*/
-static unsigned int device;
+static unsigned int bus;
+static unsigned int cs;
+static unsigned int mode;
static int bitlen;
static uchar dout[MAX_SPI_BYTES];
static uchar din[MAX_SPI_BYTES];
@@ -78,8 +80,18 @@
if ((flag & CMD_FLAG_REPEAT) == 0)
{
- if (argc >= 2)
- device = simple_strtoul(argv[1], NULL, 10);
+ if (argc >= 2) {
+ mode = CONFIG_DEFAULT_SPI_MODE;
+ bus = simple_strtoul(argv[1], &cp, 10);
+ if (*cp == ':') {
+ cs = simple_strtoul(cp+1, &cp, 10);
+ } else {
+ cs = bus;
+ bus = CONFIG_DEFAULT_SPI_BUS;
+ }
+ if (*cp == '.');
+ mode = simple_strtoul(cp+1, NULL, 10);
+ }
if (argc >= 3)
bitlen = simple_strtoul(argv[2], NULL, 10);
if (argc >= 4) {
@@ -91,7 +103,7 @@
if(tmp > 15)
tmp -= ('a' - 'A');
if(tmp > 15) {
- printf("Hex conversion error on %c, giving up.\n", *cp);
+ printf("Hex conversion error on %c\n", *cp);
return 1;
}
if((j % 2) == 0)
@@ -103,24 +115,20 @@
}
if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) {
- printf("Invalid bitlen %d, giving up.\n", bitlen);
+ printf("Invalid bitlen %d\n", bitlen);
return 1;
}
- /* FIXME: Make these parameters run-time configurable */
- slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, device, 1000000,
- CONFIG_DEFAULT_SPI_MODE);
+ slave = spi_setup_slave(bus, cs, 1000000, mode);
if (!slave) {
- printf("Invalid device %d, giving up.\n", device);
+ printf("Invalid device %d:%d\n", bus, cs);
return 1;
}
- debug ("spi chipsel = %08X\n", device);
-
spi_claim_bus(slave);
if(spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
- printf("Error with the SPI transaction.\n");
+ printf("Error during SPI transaction\n");
rcode = 1;
} else {
for(j = 0; j < ((bitlen + 7) / 8); j++) {
@@ -138,9 +146,11 @@
U_BOOT_CMD(
sspi, 5, 1, do_spi,
- "SPI utility commands",
- "<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n"
- "<device> - Identifies the chip select of the device\n"
+ "SPI utility command",
+ "[<bus>:]<cs>[.<mode>] <bit_len> <dout> - Send and receive bits\n"
+ "<bus> - Identifies the SPI bus\n"
+ "<cs> - Identifies the chip select\n"
+ "<mode> - Identifies the SPI mode to use\n"
"<bit_len> - Number of bits to send (base 10)\n"
"<dout> - Hexadecimal string that gets sent"
);
diff --git a/common/env_common.c b/common/env_common.c
index a415ef8..88f068c 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -227,6 +227,11 @@
void env_relocate (void)
{
+#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+ extern void env_reloc(void);
+
+ env_reloc();
+#endif
if (gd->env_valid == 0) {
#if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */
set_default_env(NULL);
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 14203b6..cc288d4 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -147,7 +147,6 @@
#if !defined(ENV_IS_EMBEDDED)
static void use_default()
{
- puts ("*** Warning - bad CRC or MMC, using default environment\n\n");
- set_default_env();
+ set_default_env(NULL);
}
#endif
diff --git a/common/main.c b/common/main.c
index 8d548db..d97ccd7 100644
--- a/common/main.c
+++ b/common/main.c
@@ -518,9 +518,6 @@
} while (0)
#define CTL_CH(c) ((c) - 'a' + 1)
-
-#define MAX_CMDBUF_SIZE CONFIG_SYS_CBSIZE
-
#define CTL_BACKSPACE ('\b')
#define DEL ((char)255)
#define DEL7 ((char)127)
@@ -531,7 +528,7 @@
#define getcmd_cbeep() getcmd_putch('\a')
#define HIST_MAX 20
-#define HIST_SIZE MAX_CMDBUF_SIZE
+#define HIST_SIZE CONFIG_SYS_CBSIZE
static int hist_max = 0;
static int hist_add_idx = 0;
@@ -947,7 +944,7 @@
{
char *p = buffer;
#ifdef CONFIG_CMDLINE_EDITING
- unsigned int len=MAX_CMDBUF_SIZE;
+ unsigned int len = CONFIG_SYS_CBSIZE;
int rc;
static int initted = 0;
diff --git a/common/serial.c b/common/serial.c
index 25b235a..7bebc12 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -54,6 +54,7 @@
#else
#error "Bad CONFIG_CONS_INDEX."
#endif
+#else
return &serial0_device;
#endif
#elif defined(CONFIG_MPC512X)
diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig
new file mode 100644
index 0000000..03fea74
--- /dev/null
+++ b/doc/README.fsl-hwconfig
@@ -0,0 +1,21 @@
+Freescale-specific 'hwconfig' options.
+
+This file documents Freescale-specific key:value pairs for the 'hwconfig'
+option. See README.hwconfig for general information about 'hwconfig'.
+
+audclk
+ Specific to the P1022DS reference board.
+
+ This option specifies which of the two oscillator frequencies should be
+ routed to the Wolfson WM8776 codec. The ngPIXIS can be programmed to
+ route either a 11.2896MHz or a 12.288MHz clock. The default is
+ 12.288MHz. This option has two effects. First, the MUX on the board
+ will be programmed accordingly. Second, the clock-frequency property
+ in the codec node in the device tree will be updated to the correct
+ value.
+
+ 'audclk:11'
+ Select the 11.2896MHz clock
+
+ 'audclk:12'
+ Select the 12.288MHz clock
diff --git a/drivers/hwmon/ds1621.c b/drivers/hwmon/ds1621.c
index d15a082..5a2ea62 100644
--- a/drivers/hwmon/ds1621.c
+++ b/drivers/hwmon/ds1621.c
@@ -22,7 +22,7 @@
*/
/*
- * Dallas Semiconductor's DS1621 Digital Thermometer and Thermostat.
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
*/
#include <common.h>
@@ -32,7 +32,7 @@
/*
* Device code
*/
-#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
+#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
#define DTT_READ_TEMP 0xAA
#define DTT_READ_COUNTER 0xA8
#define DTT_READ_SLOPE 0xA9
@@ -42,148 +42,147 @@
#define DTT_TEMP_LOW 0xA2
#define DTT_CONFIG 0xAC
+/*
+ * Config register bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_POLARITY 0x02
+#define DTT_CONFIG_R0 0x04 /* ds1631 only */
+#define DTT_CONFIG_R1 0x08 /* ds1631 only */
+#define DTT_CONFIG_NVB 0x10
+#define DTT_CONFIG_TLF 0x20
+#define DTT_CONFIG_THF 0x40
+#define DTT_CONFIG_DONE 0x80
+
+
int dtt_read(int sensor, int reg)
{
- int dlen;
- uchar data[2];
+ int dlen;
+ uchar data[2];
- /*
- * Calculate sensor address and command.
- *
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/
+ /* Calculate sensor address and command */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/
- /*
- * Prepare to handle 2 byte result.
- */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW))
- dlen = 2;
- else
- dlen = 1;
+ /* Prepare to handle 2 byte result */
+ switch(reg) {
+ case DTT_READ_TEMP:
+ case DTT_TEMP_HIGH:
+ case DTT_TEMP_LOW:
+ dlen = 2;
+ break;
+ default:
+ dlen = 1;
+ }
- /*
- * Now try to read the register.
- */
- if (i2c_read(sensor, reg, 1, data, dlen) != 0)
- return 1;
+ /* Now try to read the register */
+ if (i2c_read(sensor, reg, 1, data, dlen) != 0)
+ return 1;
- /*
- * Handle 2 byte result.
- */
- if (dlen == 2)
- return ((int)((short)data[1] + (((short)data[0]) << 8)));
+ /* Handle 2 byte result */
+ if (dlen == 2)
+ return (short)((data[0] << 8) | data[1]);
- return (int)data[0];
-} /* dtt_read() */
+ return (int)data[0];
+}
int dtt_write(int sensor, int reg, int val)
{
- int dlen;
- uchar data[2];
+ int dlen;
+ uchar data[2];
- /*
- * Calculate sensor address and register.
- *
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
+ /* Calculate sensor address and register */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
- /*
- * Handle various data sizes.
- */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) {
- dlen = 2;
- data[0] = (char)((val >> 8) & 0xff); /* MSB first */
- data[1] = (char)(val & 0xff);
- }
- else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) {
- dlen = 0;
- data[0] = (char)0;
- data[1] = (char)0;
- }
- else {
- dlen = 1;
- data[0] = (char)(val & 0xff);
- }
+ /* Handle various data sizes. */
+ switch(reg) {
+ case DTT_READ_TEMP:
+ case DTT_TEMP_HIGH:
+ case DTT_TEMP_LOW:
+ dlen = 2;
+ data[0] = (char)((val >> 8) & 0xff); /* MSB first */
+ data[1] = (char)(val & 0xff);
+ break;
+ case DTT_WRITE_START_CONV:
+ case DTT_WRITE_STOP_CONV:
+ dlen = 0;
+ data[0] = (char)0;
+ data[1] = (char)0;
+ break;
+ default:
+ dlen = 1;
+ data[0] = (char)(val & 0xff);
+ }
- /*
- * Write value to device.
- */
- if (i2c_write(sensor, reg, 1, data, dlen) != 0)
- return 1;
+ /* Write value to device */
+ if (i2c_write(sensor, reg, 1, data, dlen) != 0)
+ return 1;
- return 0;
-} /* dtt_write() */
+ /* Poll NV memory busy bit in case write was to register stored in EEPROM */
+ while(i2c_reg_read(sensor, DTT_CONFIG) & DTT_CONFIG_NVB)
+ ;
+
+ return 0;
+}
static int _dtt_init(int sensor)
{
- int val;
+ int val;
- /*
- * Setup High Temp.
- */
- val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
+ /* Setup High Temp */
+ val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0)
+ return 1;
- /*
- * Setup Low Temp - hysteresis.
- */
- val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
+ /* Setup Low Temp - hysteresis */
+ val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0)
+ return 1;
- /*
- * Setup configuraton register
- *
- * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES
- *
- * We run in polled mode, since there isn't any way to know if this
- * lousy device is ready to provide temperature readings on power up.
- */
- val = 0x9;
- if (dtt_write(sensor, DTT_CONFIG, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
+ /*
+ * Setup configuraton register
+ *
+ * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES
+ *
+ * We run in polled mode, since there isn't any way to know if this
+ * lousy device is ready to provide temperature readings on power up.
+ */
+ val = 0x9;
+ if (dtt_write(sensor, DTT_CONFIG, val) != 0)
+ return 1;
- return 0;
-} /* _dtt_init() */
+ return 0;
+}
int dtt_init (void)
{
- int i;
- unsigned char sensors[] = CONFIG_DTT_SENSORS;
+ int i;
+ unsigned char sensors[] = CONFIG_DTT_SENSORS;
- for (i = 0; i < sizeof(sensors); i++) {
- if (_dtt_init(sensors[i]) != 0)
- printf("DTT%d: FAILED\n", i+1);
- else
- printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i]));
- }
+ for (i = 0; i < sizeof(sensors); i++) {
+ if (_dtt_init(sensors[i]) != 0)
+ printf("DTT%d: FAILED\n", i + 1);
+ else
+ printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i]));
+ }
- return (0);
-} /* dtt_init() */
+ return (0);
+}
int dtt_get_temp(int sensor)
{
- int i;
+ int i;
- /*
- * Start a conversion, may take up to 1 second.
- */
- dtt_write(sensor, DTT_WRITE_START_CONV, 0);
- for (i = 0; i <= 10; i++) {
- udelay(100000);
- if (dtt_read(sensor, DTT_CONFIG) & 0x80)
- break;
- }
+ /* Start a conversion, may take up to 1 second. */
+ dtt_write(sensor, DTT_WRITE_START_CONV, 0);
+ for (i = 0; i <= 10; i++) {
+ udelay(100000);
+ if (dtt_read(sensor, DTT_CONFIG) & DTT_CONFIG_DONE)
+ break;
+ }
- return (dtt_read(sensor, DTT_READ_TEMP) / 256);
-} /* dtt_get_temp() */
+ return (dtt_read(sensor, DTT_READ_TEMP) / 256);
+}
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index d6c1a5f..c0900f9 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -52,6 +52,7 @@
#define SPSN_ID_S25FL128P 0x2018
#define SPSN_EXT_ID_S25FL128P_256KB 0x0300
#define SPSN_EXT_ID_S25FL128P_64KB 0x0301
+#define SPSN_EXT_ID_S25FL032P 0x4d00
#define SPANSION_SR_WIP (1 << 0) /* Write-in-Progress */
@@ -124,6 +125,14 @@
.nr_sectors = 64,
.name = "S25FL128P_256K",
},
+ {
+ .idcode1 = SPSN_ID_S25FL032A,
+ .idcode2 = SPSN_EXT_ID_S25FL032P,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 64,
+ .name = "S25FL032P",
+ },
};
static int spansion_wait_ready(struct spi_flash *flash, unsigned long timeout)
@@ -262,7 +271,6 @@
return -1;
}
- len /= sector_size;
cmd[0] = CMD_S25FLXX_SE;
cmd[2] = 0x00;
cmd[3] = 0x00;
@@ -274,8 +282,8 @@
}
ret = 0;
- for (actual = 0; actual < len; actual++) {
- cmd[1] = (offset / sector_size) + actual;
+ for (actual = 0; actual < len; actual += sector_size) {
+ cmd[1] = (offset + actual) >> 16;
ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0);
if (ret < 0) {
@@ -298,7 +306,7 @@
}
debug("SF: SPANSION: Successfully erased %u bytes @ 0x%x\n",
- len * sector_size, offset);
+ len, offset);
spi_release_bus(flash->spi);
return ret;
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index ff1df25..de3aeb8 100644
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -27,6 +27,7 @@
#define WINBOND_ID_W25X16 0x3015
#define WINBOND_ID_W25X32 0x3016
#define WINBOND_ID_W25X64 0x3017
+#define WINBOND_ID_W25Q64 0x4017
#define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */
@@ -77,6 +78,14 @@
.nr_blocks = 128,
.name = "W25X64",
},
+ {
+ .id = WINBOND_ID_W25Q64,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 128,
+ .name = "W25Q64",
+ },
};
static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout)
diff --git a/include/commproc.h b/include/commproc.h
index 762238e..a69a809 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -579,34 +579,6 @@
/*********************************************************************/
-
-/*** CCM and PCU E ***********************************************/
-
-/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */
-
-#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
-
-#define FEC_ENET /* use FEC for EThernet */
-#undef SCC_ENET
-
-#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
-#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
-#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
-#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
-#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
-#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
-#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
-#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
-#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
-#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
-#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
-#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
-#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
-
-#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
-
-#endif /* CONFIG_PCU_E, CONFIG_CCM */
-
/*** ELPT860 *********************************************************/
#ifdef CONFIG_ELPT860
diff --git a/include/compiler.h b/include/compiler.h
index 23f4b83..91dbe56 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -47,7 +47,6 @@
#elif defined(__MACH__)
# include <machine/endian.h>
typedef unsigned long ulong;
-typedef unsigned int uint;
#endif
typedef uint8_t __u8;
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
index 4d83786..555145e 100644
--- a/include/configs/BAB7xx.h
+++ b/include/configs/BAB7xx.h
@@ -269,6 +269,7 @@
* PCI stuff
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP /* pci plug-and-play */
#define CONFIG_PCI_HOST PCI_HOST_AUTO
#undef CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/CCM.h b/include/configs/CCM.h
deleted file mode 100644
index 3f4a2c1..0000000
--- a/include/configs/CCM.h
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * configuration options, board specific, for Siemens Card Controller Module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#undef CCM_80MHz /* define for 80 MHz CPU only */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */
-#define CONFIG_CCM 1 /* on a Card Controller Module */
-#define CONFIG_MISC_INIT_R /* Call misc_init_r() */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-/* ENVIRONMENT */
-
-#define CONFIG_BAUDRATE 19200 /* console baudrate in bps */
-#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
-
-#define CONFIG_IPADDR 192.168.0.42
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 0.0.0.0
-#define CONFIG_SERVERIP 192.168.0.254
-
-#define CONFIG_HOSTNAME CCM
-
-#define CONFIG_LOADADDR 40180000
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_BOOTCOMMAND "setenv bootargs " \
- "mem=${mem} " \
- "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
- "wt_8xx=timeout:3600; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_WATCHDOG 1 /* watchdog enabled */
-
-#undef CONFIG_STATUS_LED /* Status LED disabled */
-
-#define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define CONFIG_SPI /* enable SPI driver */
-#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
-
-/* ----------------------------------------------------------------
- * Offset to initial SPI buffers in DPRAM (used if the environment
- * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
- * use at an early stage. It is used between the two initialization
- * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
- * far enough from the start of the data area (as well as from the
- * stack pointer).
- * ---------------------------------------------------------------- */
-#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */
-
-
-#define CONFIG_MAC_PARTITION /* nod used yet */
-#define CONFIG_DOS_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/* Ethernet hardware configuration done using port pins */
-#define CONFIG_SYS_PA_ETH_RESET 0x0200 /* PA 6 */
-#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
-#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */
-#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */
-#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */
-
-/* Ethernet settings:
- * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex
- */
-#define CONFIG_SYS_ETH_MDDIS_VALUE 0
-#define CONFIG_SYS_ETH_CFG1_VALUE 1
-#define CONFIG_SYS_ETH_CFG2_VALUE 1
-#define CONFIG_SYS_ETH_CFG3_VALUE 1
-
-/* PUMA configuration */
-#define CONFIG_SYS_PC_PUMA_PROG 0x0200 /* PC 6 */
-#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */
-#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Address accessed to reset the board - must not be mapped/assigned
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#if 1
-/* Start port with environment in flash; switch to SPI EEPROM later */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#else
-/* Final version: environment in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 2048
-#define CONFIG_ENV_SIZE 2048
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * we must activate GPL5 in the SIUMCR for CAN
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_PLPRCR \
- ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif /* CCM_80MHz */
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#else /* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR (SCCR_TBS | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#endif /* CCM_80MHz */
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
- OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2 and OR2 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR3 and OR3 (CAN Controller)
- */
-#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
-#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V )
-
-/*
- * BR4/OR4: PUMA Config
- *
- * Memory controller will be used in 2 modes:
- *
- * - "read" mode:
- * BR4: 0x10100801 OR4: 0xffff8520
- * - "load" mode (chip select on UPM B):
- * BR4: 0x101004c1 OR4: 0xffff8600
- *
- * Default initialization is in "read" mode
- */
-#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
-#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
-#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_2_CLK)
-#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK)
-
-#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
- BR_PS_8 | BR_MS_UPMB | BR_V)
-#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
-
-#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
-
-#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ
-#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ
-
-/*
- * BR5/OR5: PUMA: SMA Bus 8 Bit
- * BR5: 0x10200401 OR5: 0xffe0010a
- */
-#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
-#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
-
-/*
- * BR6/OR6: PUMA: SMA Bus 16 Bit
- * BR6: 0x10600801 OR6: 0xffe0010a
- */
-#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
-#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
-
-/*
- * BR7/OR7: PUMA: external Flash
- * BR7: 0x10a00801 OR7: 0xfe00010a
- */
-#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
-#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
-#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
-
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index 668cfa2..6451263 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -467,6 +467,7 @@
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
+#define CONFIG_SYS_EARLY_PCI_INIT
#undef CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 8ffd458..95c0a9f 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -74,6 +74,7 @@
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R 1
#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
@@ -505,8 +506,8 @@
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 2306e7f..da826fc 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -134,6 +134,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
#define CONFIG_FSL_NGPIXIS
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index d223a4d..9184eeb 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -399,6 +399,14 @@
#endif
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
/* Qman/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
@@ -607,14 +615,17 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
+ "bank_intlv=cs0_cs1\0" \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "ubootaddr=" MK_STR(TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=p4080ds/ramdisk.uboot\0" \
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
deleted file mode 100644
index 3aee206..0000000
--- a/include/configs/pcu_e.h
+++ /dev/null
@@ -1,550 +0,0 @@
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Workaround for layout bug on prototype board
- */
-#define PCU_E_WITH_SWAPPED_CS 1
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
-#define CONFIG_MPC860T 1
-#define CONFIG_PCU_E 1 /* ...on a PCU E board */
-
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-
-#define CONFIG_BAUDRATE 9600
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define CONFIG_SPI /* enable SPI driver */
-#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
-
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-
-/* ----------------------------------------------------------------
- * Offset to initial SPI buffers in DPRAM (used if the environment
- * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
- * use at an early stage. It is used between the two initialization
- * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
- * far enough from the start of the data area (as well as from the
- * stack pointer).
- * ---------------------------------------------------------------- */
-#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-
-/* Ethernet hardware configuration done using port pins */
-#define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
-#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */
-#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */
-#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */
-#else /* XXX */
-#define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */
-#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
-#define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */
-#define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */
-#define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */
-#endif /* XXX */
-
-/* Ethernet settings:
- * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
- */
-#define CONFIG_SYS_ETH_MDDIS_VALUE 0
-#define CONFIG_SYS_ETH_CFG1_VALUE 1
-#define CONFIG_SYS_ETH_CFG2_VALUE 1
-#define CONFIG_SYS_ETH_CFG3_VALUE 1
-
-/* PUMA configuration */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */
-#else /* XXX */
-#define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */
-#endif /* XXX */
-#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */
-#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFE000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Address accessed to reset the board - must not be mapped/assigned
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* this is an ugly hack needed because of the silly non-constant address map */
-#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size)
-
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#if 0
-/* Start port with environment in flash; switch to SPI EEPROM later */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
-#define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
-#else
-/* Final version: environment in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_ENV_OFFSET 1024
-#define CONFIG_ENV_SIZE 1024
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
- * running in RAM.
- */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * External Arbitration max. priority (7),
- * Debug pins configuration '11',
- * Asynchronous external master enable.
- */
-/* => 0x70600200 */
-#define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* 0x00004080 */
-#define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */
-#define CONFIG_SYS_PLPRCR \
- ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
- /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
- PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
- )
-
-#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
- */
-#define SCCR_MASK SCCR_EBDF11
-/* 0x01800000 */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
- SCCR_RTDIV | SCCR_RTSEL | \
- /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
- SCCR_EBDF00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | \
- SCCR_DFNH000 | SCCR_DFLCD100 | \
- SCCR_DFALCD01)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- *
- * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
- *
- * Don't expect the "date" command to work without a 32kHz clock input!
- */
-/* 0x00C3 => 0x0003 */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register 19-4
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0x0000
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- *
- * Interrupt Levels
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
- */
-
-#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */
-#else /* XXX */
-#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
-#endif /* XXX */
-
-/*
- * used to re-map FLASH: restrict access enough but not too much to
- * meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
-
-/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
- CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#else /* XXX */
-#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
-#endif /* XXX */
-
-/*
- * BR2/OR2: SDRAM
- *
- * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */
-#else /* XXX */
-#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
-#endif /* XXX */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */
-#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else /* XXX */
-#define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#endif /* XXX */
-
-/*
- * BR3/OR3: CAN Controller
- * BR3: 0x10000401 OR3: 0xffff818a
- */
-#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */
-#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */
-#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
-#else /* XXX */
-#define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
-#endif /* XXX */
-
-/*
- * BR4/OR4: PUMA Config
- *
- * Memory controller will be used in 2 modes:
- *
- * - "read" mode:
- * BR4: 0x10100801 OR4: 0xffff8530
- * - "load" mode (chip select on UPM B):
- * BR4: 0x101008c1 OR4: 0xffff8630
- *
- * Default initialization is in "read" mode
- */
-#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
-#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
-#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
-#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
-
-#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
- BR_PS_16 | BR_MS_UPMB | BR_V)
-#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
-
-#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ
-#define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ
-#else /* XXX */
-#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ
-#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ
-#endif /* XXX */
-
-/*
- * BR5/OR5: PUMA: SMA Bus 8 Bit
- * BR5: 0x10200401 OR5: 0xffe0010a
- */
-#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
-#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
-#else /* XXX */
-#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
-#endif /* XXX */
-
-/*
- * BR6/OR6: PUMA: SMA Bus 16 Bit
- * BR6: 0x10600801 OR6: 0xffe0010a
- */
-#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
-#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
-#define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
-#else /* XXX */
-#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
-#endif /* XXX */
-
-/*
- * BR7/OR7: PUMA: external Flash
- * BR7: 0x10a00801 OR7: 0xfe00010a
- */
-#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
-#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
-#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
-
-#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MPTPR 0x0200
-
-/*
- * MAMR settings for SDRAM
- * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
- * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
- * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
- */
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */
-
-#define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \
- MAMR_AMA_TYPE_1 | \
- MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | \
- MAMR_WLFA_1X | \
- MAMR_TLFA_8X )
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
-#endif /* __CONFIG_H */
diff --git a/include/status_led.h b/include/status_led.h
index b39ca64..360195c 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -190,22 +190,6 @@
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** PCU E and CCM ************************************************/
-#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM))
-
-# define STATUS_LED_PAR im_cpm.cp_pbpar
-# define STATUS_LED_DIR im_cpm.cp_pbdir
-# define STATUS_LED_ODR im_cpm.cp_pbodr
-# define STATUS_LED_DAT im_cpm.cp_pbdat
-
-# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
/***** ICU862 ********************************************************/
#elif defined(CONFIG_ICU862)
@@ -270,7 +254,7 @@
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** KUP4K, KUP4X ****************************************************/
-#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM)
+#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
diff --git a/lib/hashtable.c b/lib/hashtable.c
index b747f1f..57802cf 100644
--- a/lib/hashtable.c
+++ b/lib/hashtable.c
@@ -45,6 +45,9 @@
# include <linux/string.h>
#endif
+#ifndef CONFIG_ENV_MIN_ENTRIES /* minimum number of entries */
+#define CONFIG_ENV_MIN_ENTRIES 64
+#endif
#ifndef CONFIG_ENV_MAX_ENTRIES /* maximum number of entries */
#define CONFIG_ENV_MAX_ENTRIES 512
#endif
@@ -647,13 +650,14 @@
* (CONFIG_ENV_SIZE). This heuristics will result in
* unreasonably large numbers (and thus memory footprint) for
* big flash environments (>8,000 entries for 64 KB
- * envrionment size), so we clip it to a reasonable value
- * (which can be overwritten in the board config file if
- * needed).
+ * envrionment size), so we clip it to a reasonable value.
+ * On the other hand we need to add some more entries for free
+ * space when importing very small buffers. Both boundaries can
+ * be overwritten in the board config file if needed.
*/
if (!htab->table) {
- int nent = size / 8;
+ int nent = CONFIG_ENV_MIN_ENTRIES + size / 8;
if (nent > CONFIG_ENV_MAX_ENTRIES)
nent = CONFIG_ENV_MAX_ENTRIES;
diff --git a/rules.mk b/rules.mk
index c1670ac..c2860e5 100644
--- a/rules.mk
+++ b/rules.mk
@@ -27,6 +27,7 @@
$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS) $(HOSTSRCS)
@rm -f $@
+ @touch $@
@for f in $(SRCS); do \
g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
$(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \