Merge branch 'master' of /home/wd/git/u-boot/master/
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 2268bc0..e46efef 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -29,6 +29,7 @@
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -387,6 +388,16 @@
}
#endif
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices.
+ */
+void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
+}
+#endif
+
/*************************************************************************
* pci_pre_init
*
@@ -438,6 +449,9 @@
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
+#ifdef CONFIG_PCI_PNP
+ hose->fixup_irq = sequoia_pci_fixup_irq;
+#endif
return 1;
}
#endif /* defined(CONFIG_PCI) */
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index d588d8c..350af48 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -280,10 +280,10 @@
if (argc > 1) {
if (!strcmp(argv[1], "400")) {
- /* PLB=133MHz, PLB/PCI=4 */
+ /* PLB=133MHz, PLB/PCI=3 */
printf("Bootstrapping for 400MHz\n");
sdsdp[0]=0x8678624e;
- sdsdp[1]=0x0947a030;
+ sdsdp[1]=0x095fa030;
sdsdp[2]=0x40082350;
sdsdp[3]=0x0d050000;
} else if (!strcmp(argv[1], "533")) {
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
index 6798e80..5aade72 100644
--- a/board/lwmon5/init.S
+++ b/board/lwmon5/init.S
@@ -57,7 +57,7 @@
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#endif
/* TLB-entry for PCI Memory */
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index bfe0864..44659ff 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -90,7 +90,7 @@
#include <405_mal.h>
#include <miiphy.h>
#include <malloc.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
/*
* Only compile for platform with AMCC EMAC ethernet controller and
@@ -1036,7 +1036,7 @@
hw_p->bis = bis;
hw_p->first_init = 1;
- return (1);
+ return 0;
}
@@ -1755,7 +1755,8 @@
#endif
#endif
} /* end for each supported device */
- return (1);
+
+ return 0;
}
#if !defined(CONFIG_NET_MULTI)
diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
index ac2b12b..3d1124e 100644
--- a/cpu/ppc4xx/4xx_uart.c
+++ b/cpu/ppc4xx/4xx_uart.c
@@ -46,7 +46,7 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <watchdog.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
#ifdef CONFIG_SERIAL_MULTI
#include <serial.h>
diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c
index 68aab5b..22156dd 100644
--- a/cpu/ppc4xx/commproc.c
+++ b/cpu/ppc4xx/commproc.c
@@ -26,10 +26,21 @@
#include <common.h>
#include <commproc.h>
-
+#include <asm/io.h>
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+#if defined(CFG_POST_ALT_WORD_ADDR)
+void post_word_store (ulong a)
+{
+ out_be32((void *)CFG_POST_ALT_WORD_ADDR, a);
+}
+
+ulong post_word_load (void)
+{
+ return in_be32((void *)CFG_POST_ALT_WORD_ADDR);
+}
+#else /* CFG_POST_ALT_WORD_ADDR */
void post_word_store (ulong a)
{
volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
@@ -41,6 +52,7 @@
volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
return *(volatile ulong *) save_addr;
}
+#endif /* CFG_POST_ALT_WORD_ADDR */
#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 2026cc9..2f3dc32 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -34,7 +34,7 @@
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/cpu/ppc4xx/iop480_uart.c b/cpu/ppc4xx/iop480_uart.c
index 8dd2267..3af0767 100644
--- a/cpu/ppc4xx/iop480_uart.c
+++ b/cpu/ppc4xx/iop480_uart.c
@@ -26,7 +26,7 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <watchdog.h>
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
#ifdef CONFIG_SERIAL_MULTI
#include <serial.h>
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 52601ed..a730604 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -636,6 +636,33 @@
dcbz r0,r3
addi r3,r3,32
bdnz ..d_ag
+
+ /*
+ * Lock the init-ram/stack in d-cache, so that other regions
+ * may use d-cache as well
+ * Note, that this current implementation locks exactly 4k
+ * of d-cache, so please make sure that you don't define a
+ * bigger init-ram area. Take a look at the lwmon5 440EPx
+ * implementation as a reference.
+ */
+ msync
+ isync
+ /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
+ lis r1,0x0201
+ ori r1,r1,0xf808
+ mtspr dvlim,r1
+ lis r1,0x0808
+ ori r1,r1,0x0808
+ mtspr dnv0,r1
+ mtspr dnv1,r1
+ mtspr dnv2,r1
+ mtspr dnv3,r1
+ mtspr dtv0,r1
+ mtspr dtv1,r1
+ mtspr dtv2,r1
+ mtspr dtv3,r1
+ msync
+ isync
#endif /* CFG_INIT_RAM_DCACHE */
/* 440EP & 440GR are only 440er PPC's without internal SRAM */
@@ -1345,6 +1372,31 @@
mr r4,r10
mr r5,r11
#endif
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /*
+ * Unlock the previously locked d-cache
+ */
+ msync
+ isync
+ /* set TFLOOR/NFLOOR to 0 again */
+ lis r6,0x0001
+ ori r6,r6,0xf800
+ mtspr dvlim,r6
+ lis r6,0x0000
+ ori r6,r6,0x0000
+ mtspr dnv0,r6
+ mtspr dnv1,r6
+ mtspr dnv2,r6
+ mtspr dnv3,r6
+ mtspr dtv0,r6
+ mtspr dtv1,r6
+ mtspr dtv2,r6
+ mtspr dtv3,r6
+ msync
+ isync
+#endif /* CFG_INIT_RAM_DCACHE */
+
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c
index 5924a6c..d71ba77 100644
--- a/cpu/ppc4xx/usbdev.c
+++ b/cpu/ppc4xx/usbdev.c
@@ -7,7 +7,7 @@
#include <usb.h>
#include "usbdev.h"
-#include "vecnum.h"
+#include <asm/ppc4xx-intvec.h>
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
diff --git a/cpu/ppc4xx/vecnum.h b/include/asm-ppc/ppc4xx-intvec.h
similarity index 94%
rename from cpu/ppc4xx/vecnum.h
rename to include/asm-ppc/ppc4xx-intvec.h
index 93e51b9..8d04b69 100644
--- a/cpu/ppc4xx/vecnum.h
+++ b/include/asm-ppc/ppc4xx-intvec.h
@@ -106,16 +106,16 @@
#define VECNUM_RXDE VECNUM_MRDE
/* UIC 2 */
-#define VECNUM_EIR5 (62 + 0) /* External interrupt 5 */
-#define VECNUM_EIR6 (62 + 1) /* External interrupt 6 */
-#define VECNUM_OPB (62 + 2) /* OPB to PLB bridge int stat */
-#define VECNUM_EIR2 (62 + 3) /* External interrupt 2 */
-#define VECNUM_EIR3 (62 + 4) /* External interrupt 3 */
-#define VECNUM_DDR2 (62 + 5) /* DDR2 sdram */
-#define VECNUM_MCTX0 (62 + 6) /* MAl intp coalescence TX0 */
-#define VECNUM_MCTX1 (62 + 7) /* MAl intp coalescence TX1 */
-#define VECNUM_MCTR0 (62 + 8) /* MAl intp coalescence TR0 */
-#define VECNUM_MCTR1 (62 + 9) /* MAl intp coalescence TR1 */
+#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */
+#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */
+#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */
+#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */
+#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */
+#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */
+#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */
+#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */
+#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */
+#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */
#elif defined(CONFIG_440SPE)
@@ -152,12 +152,12 @@
#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
/* UIC 2 */
-#define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */
-#define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */
-#define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */
-#define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */
-#define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */
-#define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */
+#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */
+#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */
+#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */
+#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */
+#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */
+#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */
#elif defined(CONFIG_440SP)
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 3d2ed1e..87fca3c 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -167,6 +167,7 @@
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
+#if defined (CONFIG_NAND_U_BOOT)
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
@@ -195,6 +196,7 @@
#define CFG_NAND_OOBSIZE 16
#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
+#endif
#ifdef CFG_ENV_IS_IN_NAND
/*
@@ -501,6 +503,7 @@
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+#define CFG_NAND_QUIET_TEST 1
/*
* Internal Definitions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 5210024..0bf536b 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -71,15 +71,20 @@
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
-#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
-
+/*
+ * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
+ * the POST_WORD from OCM to a 440EPx register that preserves it's
+ * content during reset (GPT0_COM6). This way we reserve the OCM (16k)
+ * for logbuffer only.
+ */
+#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
+#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
-#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
+ /* unused GPT0 COMP reg */
/*-----------------------------------------------------------------------
* Serial Port
diff --git a/include/ppc440.h b/include/ppc440.h
index bfd1e10..907744b 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1362,8 +1362,6 @@
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
@@ -1429,7 +1427,7 @@
#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
-#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#define GPT0_COMP6 0x00000098
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_USB2D0CR 0x0320
diff --git a/post/tests.c b/post/tests.c
index e1c3d28..0c49e32 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -194,7 +194,7 @@
"SPR test",
"spr",
"This test checks SPR contents.",
- POST_ROM | POST_ALWAYS | POST_PREREL,
+ POST_RAM | POST_ALWAYS,
&spr_post_test,
NULL,
NULL,