| commit | c4243ac9e2713897a63dcdc3a96bf088fdb49866 | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Wed Nov 04 10:03:22 2015 -0800 |
| committer | York Sun <yorksun@freescale.com> | Sun Dec 13 18:27:28 2015 -0800 |
| tree | ff5766eef6dc2f238791a238bccbc484941373cc | |
| parent | 6c6e006a2083f2da7b4f66c6bb82ce8b3fb713a3 [diff] |
armv8/ls2080aqds: Update DDR settings for four chip-select case When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>