Merge branch 'reloc'
diff --git a/board/altera/ep1c20/ep1c20.c b/board/altera/ep1c20/ep1c20.c
index c5bfb85..82900f7 100644
--- a/board/altera/ep1c20/ep1c20.c
+++ b/board/altera/ep1c20/ep1c20.c
@@ -22,6 +22,7 @@
*/
#include <common.h>
+#include <netdev.h>
int board_early_init_f (void)
{
@@ -38,3 +39,14 @@
{
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/altera/ep1s10/ep1s10.c b/board/altera/ep1s10/ep1s10.c
index de9bf42..cf886da 100644
--- a/board/altera/ep1s10/ep1s10.c
+++ b/board/altera/ep1s10/ep1s10.c
@@ -22,6 +22,7 @@
*/
#include <common.h>
+#include <netdev.h>
int board_early_init_f (void)
{
@@ -38,3 +39,14 @@
{
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/altera/ep1s40/ep1s40.c b/board/altera/ep1s40/ep1s40.c
index c0eca17..6395de7 100644
--- a/board/altera/ep1s40/ep1s40.c
+++ b/board/altera/ep1s40/ep1s40.c
@@ -22,6 +22,7 @@
*/
#include <common.h>
+#include <netdev.h>
int checkboard (void)
{
@@ -33,3 +34,14 @@
{
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 38186a5..2598f2c 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -542,22 +542,22 @@
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index f359d23..91fae19 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -28,6 +28,7 @@
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
#include <asm/gpio.h>
+#include <asm/errno.h>
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
@@ -338,27 +339,27 @@
/*
* Disable everything
*/
- out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
- out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
- out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
- out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+ out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+ out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+ out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+ out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*/
- out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out_le32((void *)PCIX0_PIM0LAH, 0);
- out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out_le32((void *)PCIX0_BAR0, 0);
+ out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+ out_le32((void *)PCIL0_PIM0LAH, 0);
+ out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+ out_le32((void *)PCIL0_BAR0, 0);
/*
* Program the board's subsystem id/vendor id
*/
- out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+ out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
- out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+ out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
@@ -414,6 +415,8 @@
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
+ if (ret == -ENODEV)
+ continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index e61b5de..0ca1acc 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -210,28 +210,28 @@
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
- out32r(PCIX0_PIM0SA, 0); /* disable */
- out32r(PCIX0_PIM1SA, 0); /* disable */
- out32r(PCIX0_PIM2SA, 0); /* disable */
- out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
+ out32r(PCIL0_PIM0SA, 0); /* disable */
+ out32r(PCIL0_PIM1SA, 0); /* disable */
+ out32r(PCIL0_PIM2SA, 0); /* disable */
+ out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out32r(PCIX0_PIM0LAH, 0);
- out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+ out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+ out32r(PCIL0_PIM0LAH, 0);
+ out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out32r(PCIX0_BAR0, 0);
+ out32r(PCIL0_BAR0, 0);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+ out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
- out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+ out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index bcef707..908f1a5 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -32,6 +32,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/4xx_pcie.h>
+#include <asm/errno.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -304,27 +305,27 @@
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+ out32r( PCIL0_PIM0SA, 0 ); /* disable */
+ out32r( PCIL0_PIM1SA, 0 ); /* disable */
+ out32r( PCIL0_PIM2SA, 0 ); /* disable */
+ out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*-------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIX0_BAR0, 0 );
+ out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+ out32r( PCIL0_PIM0LAH, 0 );
+ out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ out32r( PCIL0_BAR0, 0 );
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+ out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+ out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
@@ -391,6 +392,8 @@
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
+ if (ret == -ENODEV)
+ continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 5ebe692..5cd822a 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -28,6 +28,7 @@
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
@@ -317,6 +318,8 @@
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
+ if (ret == -ENODEV)
+ continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h
index 05362e0..569d78c 100644
--- a/board/amcc/luan/epld.h
+++ b/board/amcc/luan/epld.h
@@ -8,8 +8,8 @@
#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */
#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */
-#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */
-#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */
+#define EPLD1_PCIL0_CNTL1 0x40 /* S*0 of 9531 */
+#define EPLD1_PCIL0_CNTL2 0x20 /* S*1 of 9531 */
#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */
#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */
#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */
@@ -29,25 +29,25 @@
#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */
#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */
-#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */
-#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */
-#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */
-#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */
+#define EPLD4_PCIL0_VTH1 0x80 /* PCI-X 0 VTH1 status */
+#define EPLD4_PCIL0_VTH2 0x40 /* PCI-X 0 VTH2 status */
+#define EPLD4_PCIL0_VTH3 0x20 /* PCI-X 0 VTH3 status */
+#define EPLD4_PCIL0_VTH4 0x10 /* PCI-X 0 VTH4 status */
#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */
#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */
#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */
#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */
-#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
-#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
-#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
-#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
+#define EPLD5_PCIL0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
+#define EPLD5_PCIL0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
+#define EPLD5_PCIL0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
+#define EPLD5_PCIL0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */
#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */
#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */
#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */
-#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCIL0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */
#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 5f76672..a04f2af 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -173,28 +173,28 @@
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+ out32r( PCIL0_PIM0SA, 0 ); /* disable */
+ out32r( PCIL0_PIM1SA, 0 ); /* disable */
+ out32r( PCIL0_PIM2SA, 0 ); /* disable */
+ out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+ out32r( PCIL0_PIM0LAH, 0 );
+ out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIX0_BAR0, 0 );
+ out32r( PCIL0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+ out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+ out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index fb0e7b7..d4277dd 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -29,6 +29,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <fdt_support.h>
+#include <asm/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
@@ -273,6 +274,8 @@
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
+ if (ret == -ENODEV)
+ continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index d776eda..0aa317e 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -321,28 +321,28 @@
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+ out32r( PCIL0_PIM0SA, 0 ); /* disable */
+ out32r( PCIL0_PIM1SA, 0 ); /* disable */
+ out32r( PCIL0_PIM2SA, 0 ); /* disable */
+ out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+ out32r( PCIL0_PIM0LAH, 0 );
+ out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIX0_BAR0, 0 );
+ out32r( PCIL0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+ out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+ out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 17f831c..d42c802 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -428,26 +428,26 @@
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*
* Set up Configuration registers
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c
index e4e441b..a9a80e5 100644
--- a/board/amcc/taishan/showinfo.c
+++ b/board/amcc/taishan/showinfo.c
@@ -39,13 +39,13 @@
mfcpr(CPR0_PLLD,reg);
printf("cpr_plld = %#010lx\n",reg);
- mfcpr(CPR0_PRIMAD,reg);
+ mfcpr(CPR0_PRIMAD0,reg);
printf("cpr_primad = %#010lx\n",reg);
- mfcpr(CPR0_PRIMBD,reg);
+ mfcpr(CPR0_PRIMBD0,reg);
printf("cpr_primbd = %#010lx\n",reg);
- mfcpr(CPR0_OPBD,reg);
+ mfcpr(CPR0_OPBD0,reg);
printf("cpr_opbd = %#010lx\n",reg);
mfcpr(CPR0_PERD,reg);
@@ -106,59 +106,59 @@
printf("SDR0_XPLLD = %#010lx\n", reg);
printf("PCI-X Bridge Configure registers\n");
- printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
- printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID));
- printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD));
- printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS));
- printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID));
- printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS));
- printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM));
- printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
- printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
+ printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID));
+ printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID));
+ printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD));
+ printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS));
+ printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID));
+ printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS));
+ printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM));
+ printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE));
+ printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST));
- printf("PCIX0_BAR0 = %#010lx\n", in32r(PCIX0_BAR0));
- printf("PCIX0_BAR1 = %#010lx\n", in32r(PCIX0_BAR1));
- printf("PCIX0_BAR2 = %#010lx\n", in32r(PCIX0_BAR2));
- printf("PCIX0_BAR3 = %#010lx\n", in32r(PCIX0_BAR3));
- printf("PCIX0_BAR4 = %#010lx\n", in32r(PCIX0_BAR4));
- printf("PCIX0_BAR5 = %#010lx\n", in32r(PCIX0_BAR5));
+ printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0));
+ printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1));
+ printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2));
+ printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3));
+ printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4));
+ printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5));
- printf("PCIX0_CISPTR = %#010lx\n", in32r(PCIX0_CISPTR));
- printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
- printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
- printf("PCIX0_EROMBA = %#010lx\n", in32r(PCIX0_EROMBA));
- printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
- printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
- printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
- printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
- printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
+ printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR));
+ printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID));
+ printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID));
+ printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA));
+ printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP));
+ printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN));
+ printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN));
+ printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT));
+ printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY));
- printf("PCIX0_BRDGOPT1 = %#010lx\n", in32r(PCIX0_BRDGOPT1));
- printf("PCIX0_BRDGOPT2 = %#010lx\n", in32r(PCIX0_BRDGOPT2));
+ printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1));
+ printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2));
- printf("PCIX0_POM0LAL = %#010lx\n", in32r(PCIX0_POM0LAL));
- printf("PCIX0_POM0LAH = %#010lx\n", in32r(PCIX0_POM0LAH));
- printf("PCIX0_POM0SA = %#010lx\n", in32r(PCIX0_POM0SA));
- printf("PCIX0_POM0PCILAL = %#010lx\n", in32r(PCIX0_POM0PCIAL));
- printf("PCIX0_POM0PCILAH = %#010lx\n", in32r(PCIX0_POM0PCIAH));
- printf("PCIX0_POM1LAL = %#010lx\n", in32r(PCIX0_POM1LAL));
- printf("PCIX0_POM1LAH = %#010lx\n", in32r(PCIX0_POM1LAH));
- printf("PCIX0_POM1SA = %#010lx\n", in32r(PCIX0_POM1SA));
- printf("PCIX0_POM1PCILAL = %#010lx\n", in32r(PCIX0_POM1PCIAL));
- printf("PCIX0_POM1PCILAH = %#010lx\n", in32r(PCIX0_POM1PCIAH));
- printf("PCIX0_POM2SA = %#010lx\n", in32r(PCIX0_POM2SA));
+ printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL));
+ printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH));
+ printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA));
+ printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL));
+ printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH));
+ printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL));
+ printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH));
+ printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA));
+ printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL));
+ printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH));
+ printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA));
- printf("PCIX0_PIM0SA = %#010lx\n", in32r(PCIX0_PIM0SA));
- printf("PCIX0_PIM0LAL = %#010lx\n", in32r(PCIX0_PIM0LAL));
- printf("PCIX0_PIM0LAH = %#010lx\n", in32r(PCIX0_PIM0LAH));
- printf("PCIX0_PIM1SA = %#010lx\n", in32r(PCIX0_PIM1SA));
- printf("PCIX0_PIM1LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
- printf("PCIX0_PIM1LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
- printf("PCIX0_PIM2SA = %#010lx\n", in32r(PCIX0_PIM1SA));
- printf("PCIX0_PIM2LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
- printf("PCIX0_PIM2LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
+ printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA));
+ printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL));
+ printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH));
+ printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA));
+ printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
+ printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
+ printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA));
+ printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
+ printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
- printf("PCIX0_XSTS = %#010lx\n", in32r(PCIX0_STS));
+ printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS));
}
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index 4a0573e..0c20faf 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -254,28 +254,28 @@
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+ out32r( PCIL0_PIM0SA, 0 ); /* disable */
+ out32r( PCIL0_PIM1SA, 0 ); /* disable */
+ out32r( PCIL0_PIM2SA, 0 ); /* disable */
+ out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+ out32r( PCIL0_PIM0LAH, 0 );
+ out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIX0_BAR0, 0 );
+ out32r( PCIL0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+ out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+ out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 1ec13eb..7ceccfa 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -408,22 +408,22 @@
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 033bdd2..d8f4bcb 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -32,6 +32,7 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/4xx_pcie.h>
+#include <asm/errno.h>
#include "yucca.h"
@@ -632,27 +633,27 @@
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+ out32r( PCIL0_PIM0SA, 0 ); /* disable */
+ out32r( PCIL0_PIM1SA, 0 ); /* disable */
+ out32r( PCIL0_PIM2SA, 0 ); /* disable */
+ out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*-------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIX0_BAR0, 0 );
+ out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+ out32r( PCIL0_PIM0LAH, 0 );
+ out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ out32r( PCIL0_BAR0, 0 );
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+ out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+ out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
@@ -830,6 +831,8 @@
yucca_setup_pcie_fpga_rootpoint(i);
ret = ppc4xx_init_pcie_rootport(i);
}
+ if (ret == -ENODEV)
+ continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index a46deea..518944e 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -34,9 +34,7 @@
*/
#include <common.h>
-#ifdef CONFIG_PCI
#include <netdev.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -127,9 +125,16 @@
return 0;
}
-#ifdef CONFIG_PCI
+#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
- return pci_eth_init(bis);
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_PCI
+ rc += pci_eth_init(bis);
+#endif
+ return rc;
}
#endif
diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c
index 197bc89..6e836dd 100644
--- a/board/armltd/versatile/versatile.c
+++ b/board/armltd/versatile/versatile.c
@@ -34,6 +34,7 @@
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -89,3 +90,14 @@
{
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c
index d5f0b7c..8727dee 100644
--- a/board/bf533-ezkit/bf533-ezkit.c
+++ b/board/bf533-ezkit/bf533-ezkit.c
@@ -26,6 +26,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include "psd4256.h"
#include "flash-defines.h"
@@ -57,3 +58,10 @@
return 0;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 7108dda..a226910 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -26,6 +26,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include "bf533-stamp.h"
@@ -283,3 +284,10 @@
}
#endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c
index bbee989..15916fa 100644
--- a/board/bf538f-ezkit/bf538f-ezkit.c
+++ b/board/bf538f-ezkit/bf538f-ezkit.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <config.h>
#include <asm/blackfin.h>
@@ -25,3 +26,10 @@
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
index 5aede17..e5d7eb3 100644
--- a/board/bf561-ezkit/bf561-ezkit.c
+++ b/board/bf561-ezkit/bf561-ezkit.c
@@ -26,6 +26,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -43,3 +44,10 @@
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c
index b671899..f55ab97 100644
--- a/board/blackstamp/blackstamp.c
+++ b/board/blackstamp/blackstamp.c
@@ -12,6 +12,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,3 +45,10 @@
SSYNC();
}
#endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c
index 307894f..59346bc 100644
--- a/board/cerf250/cerf250.c
+++ b/board/cerf250/cerf250.c
@@ -26,6 +26,7 @@
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -71,3 +72,14 @@
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c
index 7eb761d..ab0bf3b 100644
--- a/board/cm-bf533/cm-bf533.c
+++ b/board/cm-bf533/cm-bf533.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -23,3 +24,10 @@
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c
index 5bce9eb..f21a015 100644
--- a/board/cm-bf561/cm-bf561.c
+++ b/board/cm-bf561/cm-bf561.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -23,3 +24,10 @@
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
index 6d8d555..21eb655 100644
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -27,6 +27,7 @@
#include <asm/arch/pxa-regs.h>
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -223,3 +224,14 @@
PHYS_SDRAM_3_SIZE +
PHYS_SDRAM_4_SIZE );
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/delta/delta.c b/board/delta/delta.c
index 84ff47e..a294213 100644
--- a/board/delta/delta.c
+++ b/board/delta/delta.c
@@ -22,6 +22,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <i2c.h>
#include <da9030.h>
#include <malloc.h>
@@ -363,3 +364,14 @@
i2c_reg_write(addr, SYS_CONTROL_A, val);
}
#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/dnp1110/dnp1110.c b/board/dnp1110/dnp1110.c
index ab8e7be..c215f5f 100644
--- a/board/dnp1110/dnp1110.c
+++ b/board/dnp1110/dnp1110.c
@@ -23,6 +23,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <SA-1100.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -53,3 +54,14 @@
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
index 47e946f..eecae0a 100644
--- a/board/esd/common/cmd_loadpci.c
+++ b/board/esd/common/cmd_loadpci.c
@@ -48,7 +48,7 @@
u32 la, ptm1la;
#if defined(CONFIG_440)
- ptm1la = in32r(PCIX0_PTM1LA);
+ ptm1la = in32r(PCIL0_PTM1LA);
#else
ptm1la = in32r(PTM1LA);
#endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 056f455..d0e52cb 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -435,26 +435,26 @@
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*
* Set up Configuration registers
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index 1af431b..476e940 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -497,15 +497,15 @@
/* map PCI address at 0xc0000000 in PLB space */
/* PMM1 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM1MA, 0x00000000);
+ out32r(PCIL0_PMM1MA, 0x00000000);
/* PMM1 Local Address */
- out32r(PCIX0_PMM1LA, 0xc0000000);
+ out32r(PCIL0_PMM1LA, 0xc0000000);
/* PMM1 PCI Low Address */
- out32r(PCIX0_PMM1PCILA, pciaddr);
+ out32r(PCIL0_PMM1PCILA, pciaddr);
/* PMM1 PCI High Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000);
+ out32r(PCIL0_PMM1PCIHA, 0x00000000);
/* 256MB + No prefetching, and enable region */
- out32r(PCIX0_PMM1MA, 0xf0000001);
+ out32r(PCIL0_PMM1MA, 0xf0000001);
} else {
printf("Usage:\npmm %s\n", cmdtp->help);
}
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
index 26a8282..6585fed 100644
--- a/board/esd/pmc440/init.S
+++ b/board/esd/pmc440/init.S
@@ -23,7 +23,7 @@
#include <asm-ppc/mmu.h>
#include <config.h>
-/**************************************************************************
+/*
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
@@ -32,7 +32,7 @@
*
* Pointer to the table is returned in r1
*
- *************************************************************************/
+ */
.section .bootpg,"ax"
.globl tlbtab
@@ -49,12 +49,7 @@
tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
#endif
- /* TLB-entry for DDR SDRAM (Up to 2GB) */
-#ifdef CONFIG_4xx_DCACHE
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
-#else
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-#endif
+ /* TLB entries for DDR2 SDRAM are generated dynamically */
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index f0f9bff..ec92552 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -208,7 +208,7 @@
if (getenv("pciearly") && (!is_monarch())) {
printf("PCI: early target init\n");
- pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+ pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
pci_target_init(&hose);
}
return 0;
@@ -568,42 +568,42 @@
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
/* and enable region */
if (!is_monarch()) {
ptmla_str = getenv("ptm1la");
ptmms_str = getenv("ptm1ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
- out32r(PCIX0_PTM1MS,
+ out32r(PCIL0_PTM1MS,
simple_strtoul(ptmms_str, NULL, 16));
- out32r(PCIX0_PTM1LA,
+ out32r(PCIL0_PTM1LA,
simple_strtoul(ptmla_str, NULL, 16));
} else {
/* BAR1: default top 64MB of RAM */
- out32r(PCIX0_PTM1MS, 0xfc000001);
- out32r(PCIX0_PTM1LA, 0x0c000000);
+ out32r(PCIL0_PTM1MS, 0xfc000001);
+ out32r(PCIL0_PTM1LA, 0x0c000000);
}
} else {
/* BAR1: default: complete 256MB RAM */
- out32r(PCIX0_PTM1MS, 0xf0000001);
- out32r(PCIX0_PTM1LA, 0x00000000);
+ out32r(PCIL0_PTM1MS, 0xf0000001);
+ out32r(PCIL0_PTM1LA, 0x00000000);
}
ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
if(NULL != ptmla_str && NULL != ptmms_str ) {
- out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
- out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+ out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+ out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
} else {
/* BAR2: default: 4MB FPGA */
- out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
}
if (is_monarch()) {
diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
index bb46ecc..c3528bc 100644
--- a/board/esd/pmc440/sdram.c
+++ b/board/esd/pmc440/sdram.c
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
+ *
* (C) Copyright 2006
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
@@ -31,33 +34,30 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/mmu.h>
#include <ppc440.h>
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
+struct sdram_conf_s {
+ ulong size;
+ int rows;
+ int banks;
+};
-#if defined(CONFIG_NAND_SPL)
-/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
- * for the 4k NAND boot image so define bus_frequency to 133MHz here
- * which is save for the refresh counter setup.
- */
-#define get_bus_freq(val) 133000000
-#endif
+struct sdram_conf_s sdram_conf[] = {
+ {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
+ {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
+ {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
+};
-/*************************************************************************
- *
+/*
* initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
+ */
+int initdram_by_rb(int rows, int banks)
{
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#if !defined(CONFIG_NAND_SPL)
ulong speed = get_bus_freq(0);
-#else
- ulong speed = 133333333; /* 133MHz is on the safe side */
-#endif
mtsdram(DDR0_02, 0x00000000);
@@ -89,21 +89,25 @@
mtsdram(DDR0_27, 0x0000682B);
mtsdram(DDR0_28, 0x00000000);
mtsdram(DDR0_31, 0x00000000);
- mtsdram(DDR0_42, 0x01000006);
- mtsdram(DDR0_43, 0x030A0200);
+
+ mtsdram(DDR0_42,
+ DDR0_42_ADDR_PINS_DECODE(14 - rows) |
+ 0x00000006);
+ mtsdram(DDR0_43,
+ DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
+ 0x030A0200);
+
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001);
denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
#ifdef CONFIG_DDR_DATA_EYE
- /* -----------------------------------------------------------+
+ /*
* Perform data eye search if requested.
- * ----------------------------------------------------------*/
+ */
denali_core_search_data_eye();
#endif
-
/*
* Clear possible errors resulting from data-eye-search.
* If not done, then we could get an interrupt later on when
@@ -111,5 +115,35 @@
*/
set_mcsr(get_mcsr());
- return (CONFIG_SYS_MBYTES_SDRAM << 20);
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t size;
+ int n;
+
+ /* go through supported memory configurations */
+ for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
+ size = sdram_conf[n].size;
+
+ /* program TLB entries */
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
+ TLB_WORD2_I_ENABLE);
+
+ /*
+ * setup denali core
+ */
+ initdram_by_rb(sdram_conf[n].rows,
+ sdram_conf[n].banks);
+
+ /* check for suitable configuration */
+ if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
+ return size;
+
+ /* delete TLB entries */
+ remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
+ }
+
+ return 0;
}
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S
index 7a9726f..721aaac 100644
--- a/board/exbitgen/init.S
+++ b/board/exbitgen/init.S
@@ -52,7 +52,7 @@
#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
@@ -537,7 +537,7 @@
WRITE_I2C(IICHSADR, 0x00) /* clear hi slave address */
WRITE_I2C(IICSTS, 0x08) /* update status register */
WRITE_I2C(IICEXTSTS, 0x8f)
- WRITE_I2C(IICCLKDIV, 0x05)
+ WRITE_I2C(IIC0_CLKDIV, 0x05)
WRITE_I2C(IICINTRMSK, 0x00) /* no interrupts */
WRITE_I2C(IICXFRCNT, 0x00) /* clear transfer count */
WRITE_I2C(IICXTCNTLSS, 0xf0) /* clear extended control & stat */
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 13bd73c..2fa3650 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -169,11 +169,11 @@
* Elpida MDDRC and initialization settings are an alternative
* to the Default Micron ones for all but the earliest Rev 4 boards
*/
- u32 elpida_mddrc_config[4] = {
- CONFIG_SYS_MDDRC_TIME_CFG0,
- CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
- CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
- CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+ ddr512x_config_t elpida_mddrc_config = {
+ .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+ .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
+ .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
+ .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
};
u32 elpida_init_sequence[] = {
@@ -229,7 +229,7 @@
if (is_micron()) {
msize = fixed_sdram(NULL, NULL, 0);
} else {
- msize = fixed_sdram(elpida_mddrc_config,
+ msize = fixed_sdram(&elpida_mddrc_config,
elpida_init_sequence,
sizeof(elpida_init_sequence)/sizeof(u32));
}
diff --git a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
index 105a747..7fe85b8 100644
--- a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
+++ b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
@@ -19,6 +19,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <config.h>
#include <asm/leon.h>
@@ -37,3 +38,14 @@
{
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/gaisler/gr_ep2s60/gr_ep2s60.c b/board/gaisler/gr_ep2s60/gr_ep2s60.c
index 2904d32..7241c6d 100644
--- a/board/gaisler/gr_ep2s60/gr_ep2s60.c
+++ b/board/gaisler/gr_ep2s60/gr_ep2s60.c
@@ -19,6 +19,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <config.h>
#include <asm/leon.h>
@@ -37,3 +38,14 @@
{
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
index 7cc1bf2..90dbe52 100644
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -239,22 +239,22 @@
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIX0_PMM0PCIHA, 0x00000000);
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* disabled b4 setting */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+ out32r(PCIL0_PMM0PCIHA, 0x00000000);
+ out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */
- out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIX0_PMM1PCIHA, 0x00000000);
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
+ out32r(PCIL0_PMM1MA, 0x00000000); /* disabled b4 setting */
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+ out32r(PCIL0_PMM1PCIHA, 0x00000000);
+ out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
- out32r(PCIX0_PTM1MS, 0x00000001);
- out32r(PCIX0_PTM1LA, 0);
- out32r(PCIX0_PTM2MS, 0);
- out32r(PCIX0_PTM2LA, 0);
+ out32r(PCIL0_PTM1MS, 0x00000001);
+ out32r(PCIL0_PTM1LA, 0);
+ out32r(PCIL0_PTM2MS, 0);
+ out32r(PCIL0_PTM2LA, 0);
/*
* Set up Configuration registers
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 2cd2e6d..b42e908 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -154,27 +154,27 @@
/*
* Disable everything
*/
- out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
- out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
- out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
- out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+ out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+ out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+ out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+ out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*/
- out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out_le32((void *)PCIX0_PIM0LAH, 0);
- out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out_le32((void *)PCIX0_BAR0, 0);
+ out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+ out_le32((void *)PCIL0_PIM0LAH, 0);
+ out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+ out_le32((void *)PCIL0_BAR0, 0);
/*
* Program the board's subsystem id/vendor id
*/
- out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+ out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
- out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+ out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
index c2b88ae..3412f10 100644
--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -24,6 +24,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>
@@ -182,3 +183,14 @@
return;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/korat/korat.c b/board/korat/korat.c
index 40a097c..8c674a2 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -679,29 +679,29 @@
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA,
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA,
CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
+ out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM1LA,
+ out32r(PCIL0_PMM1LA,
CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA,
+ out32r(PCIL0_PMM1PCILA,
CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*
* Set up Configuration registers
diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c
index c57210a..2562ecc 100644
--- a/board/logodl/logodl.c
+++ b/board/logodl/logodl.c
@@ -23,6 +23,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/arch/pxa-regs.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -120,3 +121,14 @@
return;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/lpd7a40x/lpd7a40x.c b/board/lpd7a40x/lpd7a40x.c
index 7edb65e..437dad0 100644
--- a/board/lpd7a40x/lpd7a40x.c
+++ b/board/lpd7a40x/lpd7a40x.c
@@ -26,6 +26,7 @@
*/
#include <common.h>
+#include <netdev.h>
#if defined(CONFIG_LH7A400)
#include <lh7a400.h>
#elif defined(CONFIG_LH7A404)
@@ -79,3 +80,14 @@
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index f4090f4..ef7f2e8 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -351,22 +351,22 @@
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c
index 32234d3..4e40b17 100644
--- a/board/ms7722se/ms7722se.c
+++ b/board/ms7722se/ms7722se.c
@@ -24,6 +24,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
@@ -57,3 +58,14 @@
{
writew(value & 0xFF, LED_BASE);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 4522612..946c3f3 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -398,27 +398,27 @@
* Make this region non-prefetchable.
*/
/* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM0MA, 0x00000000);
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0MA, 0x00000000);
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
/* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
/* 512M + No prefetching, and enable region */
- out32r(PCIX0_PMM0MA, 0xE0000001);
+ out32r(PCIL0_PMM0MA, 0xE0000001);
/* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM1MA, 0x00000000);
- out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_PMM1MA, 0x00000000);
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
/* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
/* 512M + No prefetching, and enable region */
- out32r(PCIX0_PMM1MA, 0xE0000001);
+ out32r(PCIL0_PMM1MA, 0xE0000001);
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*
* Set up Configuration registers
diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c
index 5806128..1366457 100644
--- a/board/netstar/eeprom.c
+++ b/board/netstar/eeprom.c
@@ -27,43 +27,42 @@
#include <common.h>
#include <exports.h>
#include <timestamp.h>
+#include <net.h>
#include "../drivers/net/smc91111.h"
-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-
-static u16 read_eeprom_reg(u16 reg)
+static u16 read_eeprom_reg(struct eth_device *dev, u16 reg)
{
int timeout;
- SMC_SELECT_BANK(2);
- SMC_outw(reg, PTR_REG);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outw(dev, reg, PTR_REG);
- SMC_SELECT_BANK(1);
- SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
+ SMC_SELECT_BANK(dev, 1);
+ SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
CTL_REG);
timeout = 100;
- while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+ while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay(100);
if (timeout == 0) {
printf("Timeout Reading EEPROM register %02x\n", reg);
return 0;
}
- return SMC_inw (GP_REG);
+ return SMC_inw (dev, GP_REG);
}
-static int write_eeprom_reg(u16 value, u16 reg)
+static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg)
{
int timeout;
- SMC_SELECT_BANK(2);
- SMC_outw(reg, PTR_REG);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outw(dev, reg, PTR_REG);
- SMC_SELECT_BANK(1);
- SMC_outw(value, GP_REG);
- SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+ SMC_SELECT_BANK(dev, 1);
+ SMC_outw(dev, value, GP_REG);
+ SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
timeout = 100;
- while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout)
+ while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
if (timeout == 0) {
printf("Timeout Writing EEPROM register %02x\n", reg);
@@ -73,17 +72,17 @@
return 1;
}
-static int write_data(u16 *buf, int len)
+static int write_data(struct eth_device *dev, u16 *buf, int len)
{
u16 reg = 0x23;
while (len--)
- write_eeprom_reg(*buf++, reg++);
+ write_eeprom_reg(dev, *buf++, reg++);
return 0;
}
-static int verify_macaddr(char *s)
+static int verify_macaddr(struct eth_device *dev, char *s)
{
u16 reg;
int i, err = 0;
@@ -91,7 +90,7 @@
printf("MAC Address: ");
err = i = 0;
for (i = 0; i < 3; i++) {
- reg = read_eeprom_reg(0x20 + i);
+ reg = read_eeprom_reg(dev, 0x20 + i);
printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
if (s)
err |= reg != ((u16 *)s)[i];
@@ -100,7 +99,7 @@
return err ? 0 : 1;
}
-static int set_mac(char *s)
+static int set_mac(struct eth_device *dev, char *s)
{
int i;
char *e, eaddr[6];
@@ -112,7 +111,7 @@
}
for (i = 0; i < 3; i++)
- write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+ write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i);
return 0;
}
@@ -150,6 +149,10 @@
int i, len, ret;
unsigned char buf[58], *p;
+ struct eth_device dev = {
+ .iobase = CONFIG_SMC91111_BASE
+ };
+
app_startup(argv);
if (get_version() != XF_VERSION) {
printf("Wrong XF_VERSION.\n");
@@ -160,14 +163,14 @@
return crcek();
- if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+ if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
printf("SMSC91111 not found.\n");
return 2;
}
/* Called without parameters - print MAC address */
if (argc < 2) {
- verify_macaddr(NULL);
+ verify_macaddr(&dev, NULL);
return 0;
}
@@ -201,8 +204,8 @@
}
/* First argument (MAC) is mandatory */
- set_mac(argv[1]);
- if (verify_macaddr(argv[1])) {
+ set_mac(&dev, argv[1]);
+ if (verify_macaddr(&dev, argv[1])) {
printf("*** MAC address does not match! ***\n");
return 4;
}
@@ -210,7 +213,7 @@
while (len--)
*p++ = 0;
- write_data((u16 *)buf, sizeof(buf) >> 1);
+ write_data(&dev, (u16 *)buf, sizeof(buf) >> 1);
return 0;
}
diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c
index ffd60bf..df1704b 100644
--- a/board/netstar/netstar.c
+++ b/board/netstar/netstar.c
@@ -21,6 +21,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <i2c.h>
#include <flash.h>
#include <nand.h>
@@ -115,3 +116,14 @@
return 0;
}
#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index ac059a9..b70827e 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -626,22 +626,22 @@
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
- out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
- out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+ out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index cdb91ac..51335c4 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -192,28 +192,28 @@
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+ out32r( PCIL0_PIM0SA, 0 ); /* disable */
+ out32r( PCIL0_PIM1SA, 0 ); /* disable */
+ out32r( PCIL0_PIM2SA, 0 ); /* disable */
+ out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+ out32r( PCIL0_PIM0LAH, 0 );
+ out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIX0_BAR0, 0 );
+ out32r( PCIL0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+ out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
@@ -270,21 +270,21 @@
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
- out32r( PCIX0_POM0SA, 0 ); /* disable */
- out32r( PCIX0_POM1SA, 0 ); /* disable */
- out32r( PCIX0_POM2SA, 0 ); /* disable */
+ out32r( PCIL0_POM0SA, 0 ); /* disable */
+ out32r( PCIL0_POM1SA, 0 ); /* disable */
+ out32r( PCIL0_POM2SA, 0 ); /* disable */
- out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */
- out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
+ out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_POM0LAH, 0x00000003); /* PMM0 Local Address */
+ out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
- out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */
- out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
+ out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_POM1LAH, 0x00000003); /* PMM0 Local Address */
+ out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIL0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 20fd4dc..9a07852 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -209,28 +209,28 @@
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
- out32r(PCIX0_PIM0SA, 0); /* disable */
- out32r(PCIX0_PIM1SA, 0); /* disable */
- out32r(PCIX0_PIM2SA, 0); /* disable */
- out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
+ out32r(PCIL0_PIM0SA, 0); /* disable */
+ out32r(PCIL0_PIM1SA, 0); /* disable */
+ out32r(PCIL0_PIM2SA, 0); /* disable */
+ out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out32r(PCIX0_PIM0LAH, 0);
- out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+ out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+ out32r(PCIL0_PIM0LAH, 0);
+ out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out32r(PCIX0_BAR0, 0);
+ out32r(PCIL0_BAR0, 0);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+ out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
- out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+ out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c
index 95b48bc..0a24866 100644
--- a/board/psyent/pk1c20/pk1c20.c
+++ b/board/psyent/pk1c20/pk1c20.c
@@ -22,6 +22,7 @@
*/
#include <common.h>
+#include <netdev.h>
int board_early_init_f (void)
{
@@ -38,3 +39,14 @@
{
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index e9e479c..05e30ec 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -31,6 +31,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -133,3 +134,14 @@
);
#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/renesas/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c
index 204ca78..c0f26ac 100644
--- a/board/renesas/MigoR/migo_r.c
+++ b/board/renesas/MigoR/migo_r.c
@@ -24,6 +24,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
@@ -51,3 +52,14 @@
void led_set_state (unsigned short value)
{
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h
index 328abd6..90f27ca 100644
--- a/board/sandburst/common/ppc440gx_i2c.h
+++ b/board/sandburst/common/ppc440gx_i2c.h
@@ -44,7 +44,7 @@
#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS)
#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR)
#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR)
-#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV)
+#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IIC0_CLKDIV)
#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK)
#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT)
#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS)
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
index e1c6146..a484874 100644
--- a/board/sandburst/common/sb_common.c
+++ b/board/sandburst/common/sb_common.c
@@ -346,28 +346,28 @@
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+ out32r( PCIL0_PIM0SA, 0 ); /* disable */
+ out32r( PCIL0_PIM1SA, 0 ); /* disable */
+ out32r( PCIL0_PIM2SA, 0 ); /* disable */
+ out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+ out32r( PCIL0_PIM0LAH, 0 );
+ out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIX0_BAR0, 0 );
+ out32r( PCIL0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+ out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+ out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
diff --git a/board/st/nhk8815/nhk8815.c b/board/st/nhk8815/nhk8815.c
index 1fa506a..faef810 100644
--- a/board/st/nhk8815/nhk8815.c
+++ b/board/st/nhk8815/nhk8815.c
@@ -26,6 +26,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
@@ -89,3 +90,14 @@
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
index faa2e02..5a091c4 100644
--- a/board/tqc/tqm5200/tqm5200.c
+++ b/board/tqc/tqm5200/tqm5200.c
@@ -358,11 +358,9 @@
gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
/*
- * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
- * CODEC or UART mode. Consumer IrDA should still be possible.
+ * Configure PSC6_0 through PSC6_3 as GPIO.
*/
- gpio->port_config &= ~(0x07000000);
- gpio->port_config |= 0x03000000;
+ gpio->port_config &= ~(0x00700000);
/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
gpio->simple_gpioe |= 0x20000000;
diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c
index f01597a..2ae46d1 100644
--- a/board/voiceblue/eeprom.c
+++ b/board/voiceblue/eeprom.c
@@ -27,43 +27,42 @@
#include <common.h>
#include <exports.h>
#include <timestamp.h>
+#include <net.h>
#include "../drivers/net/smc91111.h"
-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-
-static u16 read_eeprom_reg(u16 reg)
+static u16 read_eeprom_reg(struct eth_device *dev, u16 reg)
{
int timeout;
- SMC_SELECT_BANK(2);
- SMC_outw(reg, PTR_REG);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outw(dev, reg, PTR_REG);
- SMC_SELECT_BANK(1);
- SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
+ SMC_SELECT_BANK(dev, 1);
+ SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
CTL_REG);
timeout = 100;
- while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+ while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay(100);
if (timeout == 0) {
printf("Timeout Reading EEPROM register %02x\n", reg);
return 0;
}
- return SMC_inw (GP_REG);
+ return SMC_inw (dev, GP_REG);
}
-static int write_eeprom_reg(u16 value, u16 reg)
+static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg)
{
int timeout;
- SMC_SELECT_BANK(2);
- SMC_outw(reg, PTR_REG);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outw(dev, reg, PTR_REG);
- SMC_SELECT_BANK(1);
- SMC_outw(value, GP_REG);
- SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+ SMC_SELECT_BANK(dev, 1);
+ SMC_outw(dev, value, GP_REG);
+ SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
timeout = 100;
- while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout)
+ while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
if (timeout == 0) {
printf("Timeout Writing EEPROM register %02x\n", reg);
@@ -73,17 +72,17 @@
return 1;
}
-static int write_data(u16 *buf, int len)
+static int write_data(struct eth_device *dev, u16 *buf, int len)
{
u16 reg = 0x23;
while (len--)
- write_eeprom_reg(*buf++, reg++);
+ write_eeprom_reg(dev, *buf++, reg++);
return 0;
}
-static int verify_macaddr(char *s)
+static int verify_macaddr(struct eth_device *dev, char *s)
{
u16 reg;
int i, err = 0;
@@ -91,7 +90,7 @@
printf("MAC Address: ");
err = i = 0;
for (i = 0; i < 3; i++) {
- reg = read_eeprom_reg(0x20 + i);
+ reg = read_eeprom_reg(dev, 0x20 + i);
printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
if (s)
err |= reg != ((u16 *)s)[i];
@@ -100,7 +99,7 @@
return err ? 0 : 1;
}
-static int set_mac(char *s)
+static int set_mac(struct eth_device *dev, char *s)
{
int i;
char *e, eaddr[6];
@@ -112,7 +111,7 @@
}
for (i = 0; i < 3; i++)
- write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+ write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i);
return 0;
}
@@ -148,6 +147,10 @@
int i, len, ret;
unsigned char buf[58], *p;
+ struct eth_device dev = {
+ .iobase = CONFIG_SMC91111_BASE
+ };
+
app_startup(argv);
if (get_version() != XF_VERSION) {
printf("Wrong XF_VERSION.\n");
@@ -156,14 +159,14 @@
return 1;
}
- if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+ if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
printf("SMSC91111 not found.\n");
return 2;
}
/* Called without parameters - print MAC address */
if (argc < 2) {
- verify_macaddr(NULL);
+ verify_macaddr(&dev, NULL);
return 0;
}
@@ -197,8 +200,8 @@
}
/* First argument (MAC) is mandatory */
- set_mac(argv[1]);
- if (verify_macaddr(argv[1])) {
+ set_mac(&dev, argv[1]);
+ if (verify_macaddr(&dev, argv[1])) {
printf("*** MAC address does not match! ***\n");
return 4;
}
@@ -206,7 +209,7 @@
while (len--)
*p++ = 0;
- write_data((u16 *)buf, sizeof(buf) >> 1);
+ write_data(&dev, (u16 *)buf, sizeof(buf) >> 1);
return 0;
}
diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c
index 59b3310..5f8af2b 100644
--- a/board/voiceblue/voiceblue.c
+++ b/board/voiceblue/voiceblue.c
@@ -20,6 +20,7 @@
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -66,3 +67,14 @@
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
index 9baa457..4c19c4d 100644
--- a/board/xaeniax/xaeniax.c
+++ b/board/xaeniax/xaeniax.c
@@ -29,6 +29,7 @@
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -71,3 +72,14 @@
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c
index 011fb94..04949bb 100644
--- a/board/xes/xpedite1000/xpedite1000.c
+++ b/board/xes/xpedite1000/xpedite1000.c
@@ -156,7 +156,7 @@
return 0;
#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
- /* Setup System Device Register PCIX0_XCR */
+ /* Setup System Device Register PCIL0_XCR */
mfsdr(SDR0_XCR, strap);
strap &= 0x0f000000;
mtsdr(SDR0_XCR, strap);
@@ -175,26 +175,26 @@
void pci_target_init(struct pci_controller * hose)
{
/* Disable everything */
- out32r(PCIX0_PIM0SA, 0);
- out32r(PCIX0_PIM1SA, 0);
- out32r(PCIX0_PIM2SA, 0);
- out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
+ out32r(PCIL0_PIM0SA, 0);
+ out32r(PCIL0_PIM1SA, 0);
+ out32r(PCIL0_PIM2SA, 0);
+ out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*/
- out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out32r(PCIX0_PIM0LAH, 0);
- out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+ out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+ out32r(PCIL0_PIM0LAH, 0);
+ out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out32r(PCIX0_BAR0, 0);
+ out32r(PCIL0_BAR0, 0);
/* Program the board's subsystem id/vendor id */
- out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+ out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
- out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+ out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c
index 56b1cd4..246bdde 100644
--- a/board/xm250/xm250.c
+++ b/board/xm250/xm250.c
@@ -27,6 +27,7 @@
#include <asm/arch/pxa-regs.h>
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -80,3 +81,14 @@
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c
index 65923e9..4464fd4 100644
--- a/board/xsengine/xsengine.c
+++ b/board/xsengine/xsengine.c
@@ -26,6 +26,7 @@
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -61,3 +62,14 @@
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/zylonite/zylonite.c b/board/zylonite/zylonite.c
index 5829170..749a40f 100644
--- a/board/zylonite/zylonite.c
+++ b/board/zylonite/zylonite.c
@@ -26,6 +26,7 @@
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -68,3 +69,14 @@
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c
index d0ebd0f..89fd9ec 100644
--- a/common/cmd_reginfo.c
+++ b/common/cmd_reginfo.c
@@ -25,8 +25,8 @@
#include <command.h>
#if defined(CONFIG_8xx)
#include <mpc8xx.h>
-#elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
-#include <asm/processor.h>
+#elif defined (CONFIG_4xx)
+extern void ppc4xx_reginfo(void);
#elif defined (CONFIG_5xx)
#include <mpc5xx.h>
#elif defined (CONFIG_MPC5200)
@@ -90,158 +90,8 @@
* May be some CPM info here?
*/
-#elif defined (CONFIG_405GP)
- printf ("\n405GP registers; MSR=%08x\n",mfmsr());
- printf ("\nUniversal Interrupt Controller Regs\n"
- "UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR"
- "\n"
- "%08x %08x %08x %08x %08x %08x %08x %08x\n",
- mfdcr(UIC0SR),
- mfdcr(UIC0ER),
- mfdcr(UIC0CR),
- mfdcr(UIC0PR),
- mfdcr(UIC0TR),
- mfdcr(UIC0MSR),
- mfdcr(UIC0VR),
- mfdcr(UIC0VCR));
-
- puts ("\nMemory (SDRAM) Configuration\n"
- "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
-
- mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_BEAR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
-
- puts ("\n"
- "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
- mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_B2CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_B3CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCCFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCESR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
-
- printf ("\n\n"
- "DMA Channels\n"
- "DMASR DMASGC DMAADR\n"
- "%08x %08x %08x\n"
- "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n"
- "%08x %08x %08x %08x %08x\n"
- "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n"
- "%08x %08x %08x %08x %08x\n",
- mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR),
- mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0),
- mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1));
-
- printf (
- "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
- "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
- mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2),
- mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) );
-
- puts ("\n"
- "External Bus\n"
- "PBEAR PBESR0 PBESR1 EBC0_CFG\n");
- mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA));
-
- puts ("\n"
- "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n");
- mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
-
- puts ("\n"
- "PB4CR PB4AP PB5CR bp5ap PB6CR PB6AP PB7CR PB7AP\n");
- mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB5CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB5AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB6CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB6AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB7CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB7AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
-
- puts ("\n\n");
-
-#elif defined(CONFIG_405EP)
- printf ("\n405EP registers; MSR=%08x\n",mfmsr());
- printf ("\nUniversal Interrupt Controller Regs\n"
- "UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR"
- "\n"
- "%08x %08x %08x %08x %08x %08x %08x %08x\n",
- mfdcr(UIC0SR),
- mfdcr(UIC0ER),
- mfdcr(UIC0CR),
- mfdcr(UIC0PR),
- mfdcr(UIC0TR),
- mfdcr(UIC0MSR),
- mfdcr(UIC0VR),
- mfdcr(UIC0VCR));
-
- puts ("\nMemory (SDRAM) Configuration\n"
- "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
-
- mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
- mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA));
-
- printf ("\n\n"
- "DMA Channels\n"
- "DMASR DMASGC DMAADR\n" "%08x %08x %08x\n"
- "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
- "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
- mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR),
- mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0),
- mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1));
-
- printf (
- "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
- "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
- mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2),
- mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) );
-
- puts ("\n"
- "External Bus\n"
- "PBEAR PBESR0 PBESR1 EBC0_CFG\n");
- mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA));
-
- puts ("\n"
- "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n");
- mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
-
- puts ("\n"
- "PB4CR PB4AP\n");
- mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA));
- mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA));
-
- puts ("\n\n");
+#elif defined (CONFIG_4xx)
+ ppc4xx_reginfo();
#elif defined(CONFIG_5xx)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c
index 673d61e..442b5fc 100644
--- a/cpu/mpc512x/fixed_sdram.c
+++ b/cpu/mpc512x/fixed_sdram.c
@@ -26,13 +26,13 @@
#include <asm/mpc512x.h>
/*
- * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers
+ * MDDRC Config Runtime Settings
*/
-u32 default_mddrc_config[4] = {
- CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */
- CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */
- CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */
- CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */
+ddr512x_config_t default_mddrc_config = {
+ .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG,
+ .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
+ .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1,
+ .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2,
};
u32 default_init_seq[] = {
@@ -74,7 +74,8 @@
* The board doesn't use memory modules that have serial presence
* detect or similar mechanism for discovery of the DRAM settings
*/
-long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz)
+long int fixed_sdram(ddr512x_config_t *mddrc_config,
+ u32 *dram_init_seq, int seq_sz)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
@@ -83,7 +84,7 @@
/* take default settings and init sequence if necessary */
if (mddrc_config == NULL)
- mddrc_config = default_mddrc_config;
+ mddrc_config = &default_mddrc_config;
if (dram_init_seq == NULL) {
dram_init_seq = default_init_seq;
seq_sz = sizeof(default_init_seq)/sizeof(u32);
@@ -130,18 +131,22 @@
* put MDDRC in CMD mode and
* set the max time between refreshes to 0 during init process
*/
- out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK);
- out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK);
- out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]);
- out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]);
+ out_be32(&im->mddrc.ddr_sys_config,
+ mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK);
+ out_be32(&im->mddrc.ddr_time_config0,
+ mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK);
+ out_be32(&im->mddrc.ddr_time_config1,
+ mddrc_config->ddr_time_config1);
+ out_be32(&im->mddrc.ddr_time_config2,
+ mddrc_config->ddr_time_config2);
/* Initialize DDR with either default or supplied init sequence */
for (i = 0; i < seq_sz; i++)
out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
/* Start MDDRC */
- out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]);
- out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]);
+ out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
+ out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
return msize;
}
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 2ab2336..3975306 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -9,7 +9,7 @@
* Copyright (c) 2008 Nuovation System Designs, LLC
* Grant Erickson <gerickson@nuovations.com>
- * (C) Copyright 2007-2008
+ * (C) Copyright 2007-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* COPYRIGHT AMCC CORPORATION 2004
@@ -86,8 +86,133 @@
/* disable caching on SDRAM */
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
#endif /* CONFIG_4xx_DCACHE */
+
+void dcbz_area(u32 start_address, u32 num_bytes);
#endif /* CONFIG_440 */
+#define MAXRANKS 4
+#define MAXBXCF 4
+
+#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
+
+#if !defined(CONFIG_NAND_SPL)
+/*-----------------------------------------------------------------------------+
+ * sdram_memsize
+ *-----------------------------------------------------------------------------*/
+phys_size_t sdram_memsize(void)
+{
+ phys_size_t mem_size;
+ unsigned long mcopt2;
+ unsigned long mcstat;
+ unsigned long mb0cf;
+ unsigned long sdsz;
+ unsigned long i;
+
+ mem_size = 0;
+
+ mfsdram(SDRAM_MCOPT2, mcopt2);
+ mfsdram(SDRAM_MCSTAT, mcstat);
+
+ /* DDR controller must be enabled and not in self-refresh. */
+ /* Otherwise memsize is zero. */
+ if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
+ && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
+ && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
+ == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
+ for (i = 0; i < MAXBXCF; i++) {
+ mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
+ /* Banks enabled */
+ if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
+#if defined(CONFIG_440)
+ sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
+#else
+ sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
+#endif
+ switch(sdsz) {
+ case SDRAM_RXBAS_SDSZ_8:
+ mem_size+=8;
+ break;
+ case SDRAM_RXBAS_SDSZ_16:
+ mem_size+=16;
+ break;
+ case SDRAM_RXBAS_SDSZ_32:
+ mem_size+=32;
+ break;
+ case SDRAM_RXBAS_SDSZ_64:
+ mem_size+=64;
+ break;
+ case SDRAM_RXBAS_SDSZ_128:
+ mem_size+=128;
+ break;
+ case SDRAM_RXBAS_SDSZ_256:
+ mem_size+=256;
+ break;
+ case SDRAM_RXBAS_SDSZ_512:
+ mem_size+=512;
+ break;
+ case SDRAM_RXBAS_SDSZ_1024:
+ mem_size+=1024;
+ break;
+ case SDRAM_RXBAS_SDSZ_2048:
+ mem_size+=2048;
+ break;
+ case SDRAM_RXBAS_SDSZ_4096:
+ mem_size+=4096;
+ break;
+ default:
+ printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
+ , sdsz);
+ mem_size=0;
+ break;
+ }
+ }
+ }
+ }
+
+ return mem_size << 20;
+}
+
+/*-----------------------------------------------------------------------------+
+ * is_ecc_enabled
+ *-----------------------------------------------------------------------------*/
+static unsigned long is_ecc_enabled(void)
+{
+ unsigned long val;
+
+ mfsdram(SDRAM_MCOPT1, val);
+
+ return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
+}
+
+/*-----------------------------------------------------------------------------+
+ * board_add_ram_info
+ *-----------------------------------------------------------------------------*/
+void board_add_ram_info(int use_default)
+{
+ PPC4xx_SYS_INFO board_cfg;
+ u32 val;
+
+ if (is_ecc_enabled())
+ puts(" (ECC");
+ else
+ puts(" (ECC not");
+
+ get_sys_info(&board_cfg);
+
+#if defined(CONFIG_405EX)
+ val = board_cfg.freqPLB;
+#else
+ mfsdr(SDR0_DDR0, val);
+ val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
+#endif
+ printf(" enabled, %d MHz", (val * 2) / 1000000);
+
+ mfsdram(SDRAM_MMODE, val);
+ val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
+ printf(", CL%d)", val);
+}
+#endif /* !CONFIG_NAND_SPL */
+
#if defined(CONFIG_SPD_EEPROM)
/*-----------------------------------------------------------------------------+
@@ -105,14 +230,10 @@
#define SDRAM_NONE 0
#define MAXDIMMS 2
-#define MAXRANKS 4
-#define MAXBXCF 4
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
#define ONE_BILLION 1000000000
-#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
-
#define CMD_NOP (7 << 19)
#define CMD_PRECHARGE (2 << 19)
#define CMD_REFRESH (1 << 19)
@@ -213,7 +334,6 @@
/*-----------------------------------------------------------------------------+
* Prototypes
*-----------------------------------------------------------------------------*/
-static phys_size_t sdram_memsize(void);
static void get_spd_info(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks);
@@ -257,15 +377,11 @@
unsigned long num_dimm_banks,
ddr_cas_id_t selected_cas,
int write_recovery);
-static unsigned long is_ecc_enabled(void);
#ifdef CONFIG_DDR_ECC
static void program_ecc(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks,
unsigned long tlb_word2_i_value);
-static void program_ecc_addr(unsigned long start_address,
- unsigned long num_bytes,
- unsigned long tlb_word2_i_value);
#endif
#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
static void program_DQS_calibration(unsigned long *dimm_populated,
@@ -278,7 +394,6 @@
#endif
#endif
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
-void dcbz_area(u32 start_address, u32 num_bytes);
static unsigned char spd_read(uchar chip, uint addr)
{
@@ -292,79 +407,6 @@
}
/*-----------------------------------------------------------------------------+
- * sdram_memsize
- *-----------------------------------------------------------------------------*/
-static phys_size_t sdram_memsize(void)
-{
- phys_size_t mem_size;
- unsigned long mcopt2;
- unsigned long mcstat;
- unsigned long mb0cf;
- unsigned long sdsz;
- unsigned long i;
-
- mem_size = 0;
-
- mfsdram(SDRAM_MCOPT2, mcopt2);
- mfsdram(SDRAM_MCSTAT, mcstat);
-
- /* DDR controller must be enabled and not in self-refresh. */
- /* Otherwise memsize is zero. */
- if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
- && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
- && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
- == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
- for (i = 0; i < MAXBXCF; i++) {
- mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
- /* Banks enabled */
- if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
- sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
-
- switch(sdsz) {
- case SDRAM_RXBAS_SDSZ_8:
- mem_size+=8;
- break;
- case SDRAM_RXBAS_SDSZ_16:
- mem_size+=16;
- break;
- case SDRAM_RXBAS_SDSZ_32:
- mem_size+=32;
- break;
- case SDRAM_RXBAS_SDSZ_64:
- mem_size+=64;
- break;
- case SDRAM_RXBAS_SDSZ_128:
- mem_size+=128;
- break;
- case SDRAM_RXBAS_SDSZ_256:
- mem_size+=256;
- break;
- case SDRAM_RXBAS_SDSZ_512:
- mem_size+=512;
- break;
- case SDRAM_RXBAS_SDSZ_1024:
- mem_size+=1024;
- break;
- case SDRAM_RXBAS_SDSZ_2048:
- mem_size+=2048;
- break;
- case SDRAM_RXBAS_SDSZ_4096:
- mem_size+=4096;
- break;
- default:
- printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
- , sdsz);
- mem_size=0;
- break;
- }
- }
- }
- }
-
- return mem_size << 20;
-}
-
-/*-----------------------------------------------------------------------------+
* initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
* Note: This routine runs from flash with a stack set up in the chip's
* sram space. It is important that the routine does not require .sbss, .bss or
@@ -643,26 +685,6 @@
}
}
-void board_add_ram_info(int use_default)
-{
- PPC4xx_SYS_INFO board_cfg;
- u32 val;
-
- if (is_ecc_enabled())
- puts(" (ECC");
- else
- puts(" (ECC not");
-
- get_sys_info(&board_cfg);
-
- mfsdr(SDR0_DDR0, val);
- val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
- printf(" enabled, %d MHz", (val * 2) / 1000000);
-
- mfsdram(SDRAM_MMODE, val);
- val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
- printf(", CL%d)", val);
-}
/*------------------------------------------------------------------
* For the memory DIMMs installed, this routine verifies that they
@@ -2277,25 +2299,6 @@
#endif
}
-/*-----------------------------------------------------------------------------+
- * is_ecc_enabled.
- *-----------------------------------------------------------------------------*/
-static unsigned long is_ecc_enabled(void)
-{
- unsigned long dimm_num;
- unsigned long ecc;
- unsigned long val;
-
- ecc = 0;
- /* loop through all the DIMM slots on the board */
- for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
- mfsdram(SDRAM_MCOPT1, val);
- ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
- }
-
- return ecc;
-}
-
#ifdef CONFIG_DDR_ECC
/*-----------------------------------------------------------------------------+
* program_ecc.
@@ -2305,9 +2308,6 @@
unsigned long num_dimm_banks,
unsigned long tlb_word2_i_value)
{
- unsigned long mcopt1;
- unsigned long mcopt2;
- unsigned long mcstat;
unsigned long dimm_num;
unsigned long ecc;
@@ -2321,105 +2321,7 @@
if (ecc == 0)
return;
- if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
- printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
- return;
- }
-
- mfsdram(SDRAM_MCOPT1, mcopt1);
- mfsdram(SDRAM_MCOPT2, mcopt2);
-
- if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
- /* DDR controller must be enabled and not in self-refresh. */
- mfsdram(SDRAM_MCSTAT, mcstat);
- if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
- && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
- && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
- == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
-
- program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
- }
- }
-
- return;
-}
-
-static void wait_ddr_idle(void)
-{
- u32 val;
-
- do {
- mfsdram(SDRAM_MCSTAT, val);
- } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
-}
-
-/*-----------------------------------------------------------------------------+
- * program_ecc_addr.
- *-----------------------------------------------------------------------------*/
-static void program_ecc_addr(unsigned long start_address,
- unsigned long num_bytes,
- unsigned long tlb_word2_i_value)
-{
- unsigned long current_address;
- unsigned long end_address;
- unsigned long address_increment;
- unsigned long mcopt1;
- char str[] = "ECC generation -";
- char slash[] = "\\|/-\\|/-";
- int loop = 0;
- int loopi = 0;
-
- current_address = start_address;
- mfsdram(SDRAM_MCOPT1, mcopt1);
- if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
- mtsdram(SDRAM_MCOPT1,
- (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
- sync();
- eieio();
- wait_ddr_idle();
-
- puts(str);
- if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
- /* ECC bit set method for non-cached memory */
- if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
- address_increment = 4;
- else
- address_increment = 8;
- end_address = current_address + num_bytes;
-
- while (current_address < end_address) {
- *((unsigned long *)current_address) = 0x00000000;
- current_address += address_increment;
-
- if ((loop++ % (2 << 20)) == 0) {
- putc('\b');
- putc(slash[loopi++ % 8]);
- }
- }
-
- } else {
- /* ECC bit set method for cached memory */
- dcbz_area(start_address, num_bytes);
- /* Write modified dcache lines back to memory */
- clean_dcache_range(start_address, start_address + num_bytes);
- }
-
- blank_string(strlen(str));
-
- sync();
- eieio();
- wait_ddr_idle();
-
- /* clear ECC error repoting registers */
- mtsdram(SDRAM_ECCCR, 0xffffffff);
- mtdcr(0x4c, 0xffffffff);
-
- mtsdram(SDRAM_MCOPT1,
- (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
- sync();
- eieio();
- wait_ddr_idle();
- }
+ do_program_ecc(tlb_word2_i_value);
}
#endif
@@ -3106,7 +3008,7 @@
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
#if defined(CONFIG_DDR_ECC)
- ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
+ do_program_ecc(0);
#endif /* defined(CONFIG_DDR_ECC) */
#if defined(CONFIG_440)
@@ -3183,18 +3085,6 @@
}
}
#endif /* defined(CONFIG_440) */
-
-void blank_string(int size)
-{
- int i;
-
- for (i = 0; i < size; i++)
- putc('\b');
- for (i = 0; i < size; i++)
- putc(' ');
- for (i = 0; i < size; i++)
- putc('\b');
-}
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
inline void ppc4xx_ibm_ddr2_register_dump(void)
diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 91bf582..0283c91 100644
--- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -42,6 +42,8 @@
#include <asm/io.h>
#include <asm/processor.h>
+#include "ecc.h"
+
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
/*
@@ -177,7 +179,7 @@
static inline void ecc_clear_status_reg(void)
{
- mtsdram(SDRAM_ECCCR, 0xffffffff);
+ mtsdram(SDRAM_ECCES, 0xffffffff);
#if defined(SDRAM_R0BAS)
mtdcr(SDRAM_ERRSTATLL, 0xffffffff);
#endif
@@ -210,7 +212,7 @@
* ecc error, then don't count
* this as a passing value
*/
- mfsdram(SDRAM_ECCCR, ecc_status);
+ mfsdram(SDRAM_ECCES, ecc_status);
if (ecc_status != 0x00000000) {
/* clear on error */
ecc_clear_status_reg();
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index e97f32c..fa521f0 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -518,7 +518,7 @@
/* PCI I/O space */
pci_set_region(hose->regions + reg_num++,
0x00000000,
- PCIX0_IOBASE,
+ PCIL0_IOBASE,
0x10000,
PCI_REGION_IO);
@@ -545,7 +545,7 @@
hose->region_count = reg_num;
- pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+ pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
/* Let board change/modify hose & do initial checks */
if (pci_pre_init (hose) == 0) {
@@ -562,18 +562,18 @@
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
pci_target_init(hose); /* Let board setup pci target */
#else
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
- out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
+ out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
+ out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
- out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
- out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
-#elif defined(PCIX0_BRDGOPT1)
- out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
- out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
+ out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
+ out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
+#elif defined(PCIL0_BRDGOPT1)
+ out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
+ out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */
#endif
/*--------------------------------------------------------------------------+
@@ -583,23 +583,23 @@
#if defined(CONFIG_SYS_PCI_MASTER_INIT)
pci_master_init(hose); /* Let board setup pci master */
#else
- out32r( PCIX0_POM0SA, 0 ); /* disable */
- out32r( PCIX0_POM1SA, 0 ); /* disable */
- out32r( PCIX0_POM2SA, 0 ); /* disable */
+ out32r( PCIL0_POM0SA, 0 ); /* disable */
+ out32r( PCIL0_POM1SA, 0 ); /* disable */
+ out32r( PCIL0_POM2SA, 0 ); /* disable */
#if defined(CONFIG_440SPE)
- out32r( PCIX0_POM0LAL, 0x10000000 );
- out32r( PCIX0_POM0LAH, 0x0000000c );
+ out32r( PCIL0_POM0LAL, 0x10000000 );
+ out32r( PCIL0_POM0LAH, 0x0000000c );
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
- out32r( PCIX0_POM0LAL, 0x20000000 );
- out32r( PCIX0_POM0LAH, 0x0000000c );
+ out32r( PCIL0_POM0LAL, 0x20000000 );
+ out32r( PCIL0_POM0LAH, 0x0000000c );
#else
- out32r( PCIX0_POM0LAL, 0x00000000 );
- out32r( PCIX0_POM0LAH, 0x00000003 );
+ out32r( PCIL0_POM0LAL, 0x00000000 );
+ out32r( PCIL0_POM0LAH, 0x00000003 );
#endif
- out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
- out32r( PCIX0_POM0PCIAH, 0x00000000 );
- out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
- out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
+ out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
+ out32r( PCIL0_POM0PCIAH, 0x00000000 );
+ out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
+ out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
#endif
/*--------------------------------------------------------------------------+
@@ -614,7 +614,7 @@
#endif
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
- out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+ out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
#endif
hose->last_busno = pci_hose_scan(hose);
}
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index e880c28..19d2c7d 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -30,6 +30,7 @@
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm-ppc/io.h>
+#include <asm/errno.h>
#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
@@ -874,7 +875,7 @@
val = SDR_READ(SDRN_PESDR_LOOP(port));
if (!(val & 0x00001000)) {
printf("PCIE%d: link is not up.\n", port);
- return -1;
+ return -ENODEV;
}
/*
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 2050b17..365f966 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -33,6 +33,7 @@
SOBJS += kgdb.o
COBJS := 40x_spd_sdram.o
+
COBJS += 44x_spd_ddr.o
COBJS += 44x_spd_ddr2.o
ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION
@@ -54,6 +55,9 @@
COBJS += i2c.o
COBJS += interrupts.o
COBJS += iop480_uart.o
+ifdef CONFIG_CMD_REGINFO
+COBJS += reginfo.o
+endif
COBJS += sdram.o
COBJS += speed.o
COBJS += tlb.o
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 2287904..a9a0ac3 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -371,16 +371,6 @@
strcpy(addstr, "Security support");
break;
- case PVR_405EX2_RA:
- puts("EX Rev. A");
- strcpy(addstr, "No Security support");
- break;
-
- case PVR_405EXR1_RA:
- puts("EXr Rev. A");
- strcpy(addstr, "Security support");
- break;
-
case PVR_405EXR2_RA:
puts("EXr Rev. A");
strcpy(addstr, "No Security support");
@@ -406,6 +396,26 @@
strcpy(addstr, "No Security support");
break;
+ case PVR_405EX1_RD:
+ puts("EX Rev. D");
+ strcpy(addstr, "Security support");
+ break;
+
+ case PVR_405EX2_RD:
+ puts("EX Rev. D");
+ strcpy(addstr, "No Security support");
+ break;
+
+ case PVR_405EXR1_RD:
+ puts("EXr Rev. D");
+ strcpy(addstr, "Security support");
+ break;
+
+ case PVR_405EXR2_RD:
+ puts("EXr Rev. D");
+ strcpy(addstr, "No Security support");
+ break;
+
#if defined(CONFIG_440)
case PVR_440GP_RB:
puts("GP Rev. B");
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index bd06b9b..a00da40 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -58,13 +58,13 @@
target_perdv0 = 4;
target_spcid0 = 4;
- mfcpr(CPR0_PRIMBD, reg);
+ mfcpr(CPR0_PRIMBD0, reg);
temp = (reg & PRBDV_MASK) >> 24;
prbdv0 = temp ? temp : 8;
if (prbdv0 != target_prbdv0) {
reg &= ~PRBDV_MASK;
reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
- mtcpr(CPR0_PRIMBD, reg);
+ mtcpr(CPR0_PRIMBD0, reg);
reset_needed = 1;
}
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index 4705e21..5858cb3 100644
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -1159,7 +1159,7 @@
mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
- mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) |
+ mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) |
DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c
index 3f989e7..f105605 100644
--- a/cpu/ppc4xx/ecc.c
+++ b/cpu/ppc4xx/ecc.c
@@ -2,7 +2,7 @@
* Copyright (c) 2008 Nuovation System Designs, LLC
* Grant Erickson <gerickson@nuovations.com>
*
- * (C) Copyright 2005-2007
+ * (C) Copyright 2005-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2002
@@ -42,81 +42,144 @@
#include <ppc_defs.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
#include "ecc.h"
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
+
+#if defined(CONFIG_405EX)
/*
- * void ecc_init()
- *
- * Description:
- * This routine initializes a range of DRAM ECC memory with known
- * data and enables ECC checking.
- *
- * TO DO:
- * - Improve performance by utilizing cache.
- * - Further generalize to make usable by other 4xx variants (e.g.
- * 440EPx, et al).
- *
- * Input(s):
- * start - A pointer to the start of memory covered by ECC requiring
- * initialization.
- * size - The size, in bytes, of the memory covered by ECC requiring
- * initialization.
- *
- * Output(s):
- * start - A pointer to the start of memory covered by ECC with
- * CONFIG_SYS_ECC_PATTERN written to all locations and ECC data
- * primed.
- *
- * Returns:
- * N/A
+ * Currently only 405EX uses 16bit data bus width as an alternative
+ * option to 32bit data width (SDRAM0_MCOPT1_WDTH)
*/
+#define SDRAM_DATA_ALT_WIDTH 2
+#else
+#define SDRAM_DATA_ALT_WIDTH 8
+#endif
+
+static void wait_ddr_idle(void)
+{
+ u32 val;
+
+ do {
+ mfsdram(SDRAM_MCSTAT, val);
+ } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
+}
+
+static void program_ecc_addr(unsigned long start_address,
+ unsigned long num_bytes,
+ unsigned long tlb_word2_i_value)
+{
+ unsigned long current_address;
+ unsigned long end_address;
+ unsigned long address_increment;
+ unsigned long mcopt1;
+ char str[] = "ECC generation -";
+ char slash[] = "\\|/-\\|/-";
+ int loop = 0;
+ int loopi = 0;
+
+ current_address = start_address;
+ mfsdram(SDRAM_MCOPT1, mcopt1);
+ if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
+ mtsdram(SDRAM_MCOPT1,
+ (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
+ sync();
+ eieio();
+ wait_ddr_idle();
+
+ puts(str);
+
+#ifdef CONFIG_440
+ if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
+#endif
+ /* ECC bit set method for non-cached memory */
+ if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
+ address_increment = 4;
+ else
+ address_increment = SDRAM_DATA_ALT_WIDTH;
+ end_address = current_address + num_bytes;
+
+ while (current_address < end_address) {
+ *((unsigned long *)current_address) = 0;
+ current_address += address_increment;
+
+ if ((loop++ % (2 << 20)) == 0) {
+ putc('\b');
+ putc(slash[loopi++ % 8]);
+ }
+ }
+#ifdef CONFIG_440
+ } else {
+ /* ECC bit set method for cached memory */
+ dcbz_area(start_address, num_bytes);
+ /* Write modified dcache lines back to memory */
+ clean_dcache_range(start_address, start_address + num_bytes);
+ }
+#endif /* CONFIG_440 */
+
+ blank_string(strlen(str));
+
+ sync();
+ eieio();
+ wait_ddr_idle();
+
+ /* clear ECC error repoting registers */
+ mtsdram(SDRAM_ECCES, 0xffffffff);
+ mtdcr(0x4c, 0xffffffff);
+
+ mtsdram(SDRAM_MCOPT1,
+ (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
+ sync();
+ eieio();
+ wait_ddr_idle();
+ }
+}
+
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
void ecc_init(unsigned long * const start, unsigned long size)
{
- const unsigned long pattern = CONFIG_SYS_ECC_PATTERN;
- unsigned long * const end = (unsigned long * const)((long)start + size);
- unsigned long * current = start;
- unsigned long mcopt1;
- long increment;
-
- if (start >= end)
- return;
-
- mfsdram(SDRAM_ECC_CFG, mcopt1);
-
- /* Enable ECC generation without checking or reporting */
-
- mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
- SDRAM_ECC_CFG_MCHK_GEN));
-
- increment = sizeof(u32);
-
-#if defined(CONFIG_440)
/*
- * Look at the geometry of SDRAM (data width) to determine whether we
- * can skip words when writing.
+ * Init ECC with cache disabled (on PPC's with IBM DDR
+ * controller (non DDR2), not tested with cache enabled yet
*/
+ program_ecc_addr((u32)start, size, TLB_WORD2_I_ENABLE);
+}
+#endif
- if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32)
- increment = sizeof(u64);
-#endif /* defined(CONFIG_440) */
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+void do_program_ecc(unsigned long tlb_word2_i_value)
+{
+ unsigned long mcopt1;
+ unsigned long mcopt2;
+ unsigned long mcstat;
+ phys_size_t memsize = sdram_memsize();
- while (current < end) {
- *current = pattern;
- current = (unsigned long *)((long)current + increment);
+ if (memsize > CONFIG_MAX_MEM_MAPPED) {
+ printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
+ return;
}
- /* Wait until the writes are finished. */
+ mfsdram(SDRAM_MCOPT1, mcopt1);
+ mfsdram(SDRAM_MCOPT2, mcopt2);
- sync();
+ if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
+ /* DDR controller must be enabled and not in self-refresh. */
+ mfsdram(SDRAM_MCSTAT, mcstat);
+ if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
+ && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
+ && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
+ == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
- /* Enable ECC generation with checking and no reporting */
-
- mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
- SDRAM_ECC_CFG_MCHK_CHK));
+ program_ecc_addr(0, memsize, tlb_word2_i_value);
+ }
+ }
}
+#endif
+
#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h
index 67c3bff..b258891 100644
--- a/cpu/ppc4xx/ecc.h
+++ b/cpu/ppc4xx/ecc.h
@@ -2,7 +2,7 @@
* Copyright (c) 2008 Nuovation System Designs, LLC
* Grant Erickson <gerickson@nuovations.com>
*
- * Copyright (c) 2007 DENX Software Engineering, GmbH
+ * Copyright (c) 2007-2009 DENX Software Engineering, GmbH
* Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
@@ -25,18 +25,13 @@
*
* Description:
* This file implements ECC initialization for PowerPC processors
- * using the SDRAM DDR2 controller, including the 405EX(r),
- * 440SP(E), 460EX and 460GT.
+ * using the IBM SDRAM DDR1 & DDR2 controller.
*
*/
#ifndef _ECC_H_
#define _ECC_H_
-#if !defined(CONFIG_SYS_ECC_PATTERN)
-#define CONFIG_SYS_ECC_PATTERN 0x00000000
-#endif /* !defined(CONFIG_SYS_ECC_PATTERN) */
-
/*
* Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
* compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
@@ -46,24 +41,35 @@
/* For 440GP/GX/EP/GR */
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
-#define SDRAM_ECC_CFG SDRAM_CFG0
-#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK
-#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN
-#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK
-#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK
-#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32
+#define SDRAM_MCOPT1 SDRAM_CFG0
+#define SDRAM_MCOPT1_MCHK_MASK SDRAM_CFG0_MCHK_MASK
+#define SDRAM_MCOPT1_MCHK_NON SDRAM_CFG0_MCHK_NON
+#define SDRAM_MCOPT1_MCHK_GEN SDRAM_CFG0_MCHK_GEN
+#define SDRAM_MCOPT1_MCHK_CHK SDRAM_CFG0_MCHK_CHK
+#define SDRAM_MCOPT1_MCHK_CHK_REP SDRAM_CFG0_MCHK_CHK
+#define SDRAM_MCOPT1_DMWD_MASK SDRAM_CFG0_DMWD_MASK
+#define SDRAM_MCOPT1_DMWD_32 SDRAM_CFG0_DMWD_32
+
+#define SDRAM_MCSTAT SDRAM0_MCSTS
+#define SDRAM_MCSTAT_IDLE_MASK SDRAM_MCSTS_CIS
+#define SDRAM_MCSTAT_IDLE_NOT SDRAM_MCSTS_IDLE_NOT
+
+#define SDRAM_ECCES SDRAM0_ECCESR
#endif
-/* For 405EX/440SP/SPe/460EX/GT */
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-#define SDRAM_ECC_CFG SDRAM_MCOPT1
-#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK
-#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN
-#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK
-#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK
-#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32
-#endif
+void ecc_init(unsigned long * const start, unsigned long size);
+void do_program_ecc(unsigned long tlb_word2_i_value);
-extern void ecc_init(unsigned long * const start, unsigned long size);
+static void inline blank_string(int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++)
+ putc('\b');
+ for (i = 0; i < size; i++)
+ putc(' ');
+ for (i = 0; i < size; i++)
+ putc('\b');
+}
#endif /* _ECC_H_ */
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index fa3bfc8..22ed5c2 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -195,7 +195,7 @@
unsigned long eoffset;
/* Need to find out which mdi port we're using */
- zmii = in_be32((void *)ZMII_FER);
+ zmii = in_be32((void *)ZMII0_FER);
if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
/* using port 0 */
@@ -217,12 +217,12 @@
/* None of the mdi ports are enabled! */
/* enable port 0 */
zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
- out_be32((void *)ZMII_FER, zmii);
+ out_be32((void *)ZMII0_FER, zmii);
eoffset = 0;
/* need to soft reset port 0 */
- zmii = in_be32((void *)EMAC_M0);
- zmii |= EMAC_M0_SRST;
- out_be32((void *)EMAC_M0, zmii);
+ zmii = in_be32((void *)EMAC0_MR0);
+ zmii |= EMAC_MR0_SRST;
+ out_be32((void *)EMAC0_MR0, zmii);
}
return (eoffset);
@@ -243,19 +243,19 @@
switch (addr) {
#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
case CONFIG_GPCS_PHY1_ADDR:
- if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x100)))
+ if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100)))
eoffset = 0x100;
break;
#endif
#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
case CONFIG_GPCS_PHY2_ADDR:
- if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x300)))
+ if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300)))
eoffset = 0x300;
break;
#endif
#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
case CONFIG_GPCS_PHY3_ADDR:
- if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x400)))
+ if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400)))
eoffset = 0x400;
break;
#endif
@@ -278,9 +278,9 @@
/* wait for completion */
i = 0;
do {
- sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
+ sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
if (i++ > 5) {
- debug("%s [%d]: Timeout! EMAC_STACR=0x%0x\n", __func__,
+ debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__,
__LINE__, sta_reg);
return -1;
}
@@ -324,7 +324,7 @@
if (cmd == EMAC_STACR_WRITE)
memcpy(&sta_reg, &value, 2); /* put in data */
- out_be32((void *)EMAC_STACR + emac_reg, sta_reg);
+ out_be32((void *)EMAC0_STACR + emac_reg, sta_reg);
debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
/* wait for completion */
@@ -349,7 +349,7 @@
if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
return -1;
- sta_reg = in_be32((void *)EMAC_STACR + emac_reg);
+ sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
*value = sta_reg >> 16;
return 0;
diff --git a/cpu/ppc4xx/reginfo.c b/cpu/ppc4xx/reginfo.c
new file mode 100644
index 0000000..a975667
--- /dev/null
+++ b/cpu/ppc4xx/reginfo.c
@@ -0,0 +1,370 @@
+/*
+ *(C) Copyright 2005-2009 Netstal Maschinen AG
+ * Bruno Hars (Bruno.Hars@netstal.com)
+ * Niklaus Giger (Niklaus.Giger@netstal.com)
+ *
+ * This source code is free software; you can redistribute it
+ * and/or modify it in source code form under the terms of the GNU
+ * General Public License as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+/*
+ * reginfo.c - register dump of HW-configuratin register for PPC4xx based board
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-uic.h>
+#include <ppc4xx_enet.h>
+
+enum REGISTER_TYPE {
+ IDCR1, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */
+ IDCR2, /* Indirectly Accessed DCR via EBC0_CFGADDR/EBC0_CFGDATA */
+ IDCR3, /* Indirectly Accessed DCR via EBM0_CFGADDR/EBM0_CFGDATA */
+ IDCR4, /* Indirectly Accessed DCR via PPM0_CFGADDR/PPM0_CFGDATA */
+ IDCR5, /* Indirectly Accessed DCR via CPR0_CFGADDR/CPR0_CFGDATA */
+ IDCR6, /* Indirectly Accessed DCR via SDR0_CFGADDR/SDR0_CFGDATA */
+ MM /* Directly Accessed MMIO Register */
+};
+
+struct cpu_register {
+ char *name;
+ enum REGISTER_TYPE type;
+ u32 address;
+};
+
+/*
+ * PPC440EPx registers ordered for output
+ * name type addr size
+ * -------------------------------------------
+ */
+
+const struct cpu_register ppc4xx_reg[] = {
+ {"PB0CR", IDCR2, PB0CR},
+ {"PB0AP", IDCR2, PB0AP},
+ {"PB1CR", IDCR2, PB1CR},
+ {"PB1AP", IDCR2, PB1AP},
+ {"PB2CR", IDCR2, PB2CR},
+ {"PB2AP", IDCR2, PB2AP},
+ {"PB3CR", IDCR2, PB3CR},
+ {"PB3AP", IDCR2, PB3AP},
+
+ {"PB4CR", IDCR2, PB4CR},
+ {"PB4AP", IDCR2, PB4AP},
+#if !defined(CONFIG_405EP)
+ {"PB5CR", IDCR2, PB5CR},
+ {"PB5AP", IDCR2, PB5AP},
+ {"PB6CR", IDCR2, PB6CR},
+ {"PB6AP", IDCR2, PB6AP},
+ {"PB7CR", IDCR2, PB7CR},
+ {"PB7AP", IDCR2, PB7AP},
+#endif
+
+ {"PBEAR", IDCR2, PBEAR},
+#if defined(CONFIG_405EP) || defined (CONFIG_405GP)
+ {"PBESR0", IDCR2, PBESR0},
+ {"PBESR1", IDCR2, PBESR1},
+#endif
+ {"EBC0_CFG", IDCR2, EBC0_CFG},
+
+#ifdef CONFIG_405GP
+ {"SDRAM0_BESR0", IDCR1, SDRAM0_BESR0},
+ {"SDRAM0_BESRS0", IDCR1, SDRAM0_BESRS0},
+ {"SDRAM0_BESR1", IDCR1, SDRAM0_BESR1},
+ {"SDRAM0_BESRS1", IDCR1, SDRAM0_BESRS1},
+ {"SDRAM0_BEAR", IDCR1, SDRAM0_BEAR},
+ {"SDRAM0_CFG", IDCR1, SDRAM0_CFG},
+ {"SDRAM0_RTR", IDCR1, SDRAM0_RTR},
+ {"SDRAM0_PMIT", IDCR1, SDRAM0_PMIT},
+
+ {"SDRAM0_B0CR", IDCR1, SDRAM0_B0CR},
+ {"SDRAM0_B1CR", IDCR1, SDRAM0_B1CR},
+ {"SDRAM0_B2CR", IDCR1, SDRAM0_B2CR},
+ {"SDRAM0_B3CR", IDCR1, SDRAM0_B1CR},
+ {"SDRAM0_TR", IDCR1, SDRAM0_TR},
+ {"SDRAM0_ECCCFG", IDCR1, SDRAM0_B1CR},
+ {"SDRAM0_ECCESR", IDCR1, SDRAM0_ECCESR},
+
+
+#endif
+
+#ifdef CONFIG_440EPX
+ {"SDR0_SDSTP0", IDCR6, SDR0_SDSTP0},
+ {"SDR0_SDSTP1", IDCR6, SDR0_SDSTP1},
+ {"SDR0_SDSTP2", IDCR6, SDR0_SDSTP2},
+ {"SDR0_SDSTP3", IDCR6, SDR0_SDSTP3},
+ {"SDR0_CUST0", IDCR6, SDR0_CUST0},
+ {"SDR0_CUST1", IDCR6, SDR0_CUST1},
+ {"SDR0_EBC0", IDCR6, SDR0_EBC0},
+ {"SDR0_AMP0", IDCR6, SD0_AMP0},
+ {"SDR0_AMP1", IDCR6, SD0_AMP1},
+ {"SDR0_CP440", IDCR6, SDR0_CP440},
+ {"SDR0_CRYP0", IDCR6, SDR0_CRYP0},
+ {"SDR0_DDRCFG", IDCR6, SDR0_DDRCFG},
+ {"SDR0_EMAC0RXST", IDCR6, SDR0_EMAC0RXST},
+ {"SDR0_EMAC0TXST", IDCR6, SDR0_EMAC0TXST},
+ {"SDR0_MFR", IDCR6, SDR0_MFR},
+ {"SDR0_PCI0", IDCR6, SDR0_PCI0},
+ {"SDR0_PFC0", IDCR6, SDR0_PFC0},
+ {"SDR0_PFC1", IDCR6, SDR0_PFC1},
+ {"SDR0_PFC2", IDCR6, SDR0_PFC2},
+ {"SDR0_PFC4", IDCR6, SDR0_PFC4},
+ {"SDR0_UART0", IDCR6, SDR0_UART0},
+ {"SDR0_UART1", IDCR6, SDR0_UART1},
+ {"SDR0_UART2", IDCR6, SDR0_UART2},
+ {"SDR0_UART3", IDCR6, SDR0_UART3},
+ {"DDR0_02", IDCR1, DDR0_02},
+ {"DDR0_00", IDCR1, DDR0_00},
+ {"DDR0_01", IDCR1, DDR0_01},
+ {"DDR0_03", IDCR1, DDR0_03},
+ {"DDR0_04", IDCR1, DDR0_04},
+ {"DDR0_05", IDCR1, DDR0_05},
+ {"DDR0_06", IDCR1, DDR0_06},
+ {"DDR0_07", IDCR1, DDR0_07},
+ {"DDR0_08", IDCR1, DDR0_08},
+ {"DDR0_09", IDCR1, DDR0_09},
+ {"DDR0_10", IDCR1, DDR0_10},
+ {"DDR0_11", IDCR1, DDR0_11},
+ {"DDR0_12", IDCR1, DDR0_12},
+ {"DDR0_14", IDCR1, DDR0_14},
+ {"DDR0_17", IDCR1, DDR0_17},
+ {"DDR0_18", IDCR1, DDR0_18},
+ {"DDR0_19", IDCR1, DDR0_19},
+ {"DDR0_20", IDCR1, DDR0_20},
+ {"DDR0_21", IDCR1, DDR0_21},
+ {"DDR0_22", IDCR1, DDR0_22},
+ {"DDR0_23", IDCR1, DDR0_23},
+ {"DDR0_24", IDCR1, DDR0_24},
+ {"DDR0_25", IDCR1, DDR0_25},
+ {"DDR0_26", IDCR1, DDR0_26},
+ {"DDR0_27", IDCR1, DDR0_27},
+ {"DDR0_28", IDCR1, DDR0_28},
+ {"DDR0_31", IDCR1, DDR0_31},
+ {"DDR0_32", IDCR1, DDR0_32},
+ {"DDR0_33", IDCR1, DDR0_33},
+ {"DDR0_34", IDCR1, DDR0_34},
+ {"DDR0_35", IDCR1, DDR0_35},
+ {"DDR0_36", IDCR1, DDR0_36},
+ {"DDR0_37", IDCR1, DDR0_37},
+ {"DDR0_38", IDCR1, DDR0_38},
+ {"DDR0_39", IDCR1, DDR0_39},
+ {"DDR0_40", IDCR1, DDR0_40},
+ {"DDR0_41", IDCR1, DDR0_41},
+ {"DDR0_42", IDCR1, DDR0_42},
+ {"DDR0_43", IDCR1, DDR0_43},
+ {"DDR0_44", IDCR1, DDR0_44},
+ {"CPR0_ICFG", IDCR5, CPR0_ICFG},
+ {"CPR0_MALD", IDCR5, CPR0_MALD},
+ {"CPR0_OPBD00", IDCR5, CPR0_OPBD0},
+ {"CPR0_PERD0", IDCR5, CPR0_PERD},
+ {"CPR0_PLLC0", IDCR5, CPR0_PLLC},
+ {"CPR0_PLLD0", IDCR5, CPR0_PLLD},
+ {"CPR0_PRIMAD0", IDCR5, CPR0_PRIMAD0},
+ {"CPR0_PRIMBD0", IDCR5, CPR0_PRIMBD0},
+ {"CPR0_SPCID", IDCR5, CPR0_SPCID},
+ {"SPI0_MODE", MM, SPI0_MODE},
+ {"IIC0_CLKDIV", MM, PCIL0_PMM1MA},
+ {"PCIL0_PMM0MA", MM, PCIL0_PMM0MA},
+ {"PCIL0_PMM1MA", MM, PCIL0_PMM1MA},
+ {"PCIL0_PTM1LA", MM, PCIL0_PMM1MA},
+ {"PCIL0_PTM1MS", MM, PCIL0_PTM1MS},
+ {"PCIL0_PTM2LA", MM, PCIL0_PMM1MA},
+ {"PCIL0_PTM2MS", MM, PCIL0_PTM2MS},
+ {"ZMII0_FER", MM, ZMII0_FER},
+ {"ZMII0_SSR", MM, ZMII0_SSR},
+ {"EMAC0_IPGVR", MM, EMAC0_IPGVR},
+ {"EMAC0_MR1", MM, EMAC0_MR1},
+ {"EMAC0_PTR", MM, EMAC0_PTR},
+ {"EMAC0_RWMR", MM, EMAC0_RWMR},
+ {"EMAC0_STACR", MM, EMAC0_STACR},
+ {"EMAC0_TMR0", MM, EMAC0_TMR0},
+ {"EMAC0_TMR1", MM, EMAC0_TMR1},
+ {"EMAC0_TRTR", MM, EMAC0_TRTR},
+ {"EMAC1_MR1", MM, EMAC1_MR1},
+ {"GPIO0_OR", MM, GPIO0_OR},
+ {"GPIO1_OR", MM, GPIO1_OR},
+ {"GPIO0_TCR", MM, GPIO0_TCR},
+ {"GPIO1_TCR", MM, GPIO1_TCR},
+ {"GPIO0_ODR", MM, GPIO0_ODR},
+ {"GPIO1_ODR", MM, GPIO1_ODR},
+ {"GPIO0_OSRL", MM, GPIO0_OSRL},
+ {"GPIO0_OSRH", MM, GPIO0_OSRH},
+ {"GPIO1_OSRL", MM, GPIO1_OSRL},
+ {"GPIO1_OSRH", MM, GPIO1_OSRH},
+ {"GPIO0_TSRL", MM, GPIO0_TSRL},
+ {"GPIO0_TSRH", MM, GPIO0_TSRH},
+ {"GPIO1_TSRL", MM, GPIO1_TSRL},
+ {"GPIO1_TSRH", MM, GPIO1_TSRH},
+ {"GPIO0_IR", MM, GPIO0_IR},
+ {"GPIO1_IR", MM, GPIO1_IR},
+ {"GPIO0_ISR1L", MM, GPIO0_ISR1L},
+ {"GPIO0_ISR1H", MM, GPIO0_ISR1H},
+ {"GPIO1_ISR1L", MM, GPIO1_ISR1L},
+ {"GPIO1_ISR1H", MM, GPIO1_ISR1H},
+ {"GPIO0_ISR2L", MM, GPIO0_ISR2L},
+ {"GPIO0_ISR2H", MM, GPIO0_ISR2H},
+ {"GPIO1_ISR2L", MM, GPIO1_ISR2L},
+ {"GPIO1_ISR2H", MM, GPIO1_ISR2H},
+ {"GPIO0_ISR3L", MM, GPIO0_ISR3L},
+ {"GPIO0_ISR3H", MM, GPIO0_ISR3H},
+ {"GPIO1_ISR3L", MM, GPIO1_ISR3L},
+ {"GPIO1_ISR3H", MM, GPIO1_ISR3H},
+ {"SDR0_USB2PHY0CR", IDCR6, SDR0_USB2PHY0CR},
+ {"SDR0_USB2H0CR", IDCR6, SDR0_USB2H0CR},
+ {"SDR0_USB2D0CR", IDCR6, SDR0_USB2D0CR},
+#endif
+};
+
+/*
+ * CPU Register dump of PPC4xx HW configuration registers
+ * Output: first all DCR-registers, then in order of struct ppc4xx_reg
+ */
+#define PRINT_DCR(dcr) printf("0x%08x %-16s: 0x%08x\n", dcr,#dcr, mfdcr(dcr));
+
+void ppc4xx_reginfo(void)
+{
+ unsigned int i;
+ unsigned int n;
+ u32 value;
+ enum REGISTER_TYPE type;
+#if defined (CONFIG_405EP)
+ printf("Dump PPC405EP HW configuration registers\n\n");
+#elif CONFIG_405GP
+ printf ("Dump 405GP HW configuration registers\n\n");
+#elif CONFIG_440EPX
+ printf("Dump PPC440EPx HW configuration registers\n\n");
+#endif
+ printf("MSR: 0x%08x\n", mfmsr());
+
+ printf ("\nUniversal Interrupt Controller Regs\n");
+ PRINT_DCR(UIC0SR);
+ PRINT_DCR(UIC0ER);
+ PRINT_DCR(UIC0CR);
+ PRINT_DCR(UIC0PR);
+ PRINT_DCR(UIC0TR);
+ PRINT_DCR(UIC0MSR);
+ PRINT_DCR(UIC0VR);
+ PRINT_DCR(UIC0VCR);
+
+#if (UIC_MAX > 1)
+ PRINT_DCR(UIC2SR);
+ PRINT_DCR(UIC2ER);
+ PRINT_DCR(UIC2CR);
+ PRINT_DCR(UIC2PR);
+ PRINT_DCR(UIC2TR);
+ PRINT_DCR(UIC2MSR);
+ PRINT_DCR(UIC2VR);
+ PRINT_DCR(UIC2VCR);
+#endif
+
+#if (UIC_MAX > 2)
+ PRINT_DCR(UIC2SR);
+ PRINT_DCR(UIC2ER);
+ PRINT_DCR(UIC2CR);
+ PRINT_DCR(UIC2PR);
+ PRINT_DCR(UIC2TR);
+ PRINT_DCR(UIC2MSR);
+ PRINT_DCR(UIC2VR);
+ PRINT_DCR(UIC2VCR);
+#endif
+
+#if (UIC_MAX > 3)
+ PRINT_DCR(UIC3SR);
+ PRINT_DCR(UIC3ER);
+ PRINT_DCR(UIC3CR);
+ PRINT_DCR(UIC3PR);
+ PRINT_DCR(UIC3TR);
+ PRINT_DCR(UIC3MSR);
+ PRINT_DCR(UIC3VR);
+ PRINT_DCR(UIC3VCR);
+#endif
+
+#if defined (CONFIG_405EP) || defined (CONFIG_405GP)
+ printf ("\n\nDMA Channels\n");
+ PRINT_DCR(DMASR);
+ PRINT_DCR(DMASGC);
+ PRINT_DCR(DMAADR);
+
+ PRINT_DCR(DMACR0);
+ PRINT_DCR(DMACT0);
+ PRINT_DCR(DMADA0);
+ PRINT_DCR(DMASA0);
+ PRINT_DCR(DMASB0);
+
+ PRINT_DCR(DMACR1);
+ PRINT_DCR(DMACT1);
+ PRINT_DCR(DMADA1);
+ PRINT_DCR(DMASA1);
+ PRINT_DCR(DMASB1);
+
+ PRINT_DCR(DMACR2);
+ PRINT_DCR(DMACT2);
+ PRINT_DCR(DMADA2);
+ PRINT_DCR(DMASA2);
+ PRINT_DCR(DMASB2);
+
+ PRINT_DCR(DMACR3);
+ PRINT_DCR(DMACT3);
+ PRINT_DCR(DMADA3);
+ PRINT_DCR(DMASA3);
+ PRINT_DCR(DMASB3);
+#endif
+
+ printf ("\n\nVarious HW-Configuration registers\n");
+#if defined (CONFIG_440EPX)
+ PRINT_DCR(MAL0_CFG);
+ PRINT_DCR(CPM0_ER);
+ PRINT_DCR(CPM1_ER);
+ PRINT_DCR(PLB4A0_ACR);
+ PRINT_DCR(PLB4A1_ACR);
+ PRINT_DCR(PLB3A0_ACR);
+ PRINT_DCR(OPB2PLB40_BCTRL);
+ PRINT_DCR(P4P3BO0_CFG);
+#endif
+ n = sizeof(ppc4xx_reg) / sizeof(ppc4xx_reg[0]);
+ for (i = 0; i < n; i++) {
+ value = 0;
+ type = ppc4xx_reg[i].type;
+ switch (type) {
+ case IDCR1: /* Indirect via SDRAM0_CFGADDR/DDR0_CFGDATA */
+ mtdcr(SDRAM0_CFGADDR, ppc4xx_reg[i].address);
+ value = mfdcr(SDRAM0_CFGDATA);
+ break;
+ case IDCR2: /* Indirect via EBC0_CFGADDR/EBC0_CFGDATA */
+ mtdcr(EBC0_CFGADDR, ppc4xx_reg[i].address);
+ value = mfdcr(EBC0_CFGDATA);
+ break;
+ case IDCR5: /* Indirect via CPR0_CFGADDR/CPR0_CFGDATA */
+ mtdcr(CPR0_CFGADDR, ppc4xx_reg[i].address);
+ value = mfdcr(CPR0_CFGDATA);
+ break;
+ case IDCR6: /* Indirect via SDR0_CFGADDR/SDR0_CFGDATA */
+ mtdcr(SDR0_CFGADDR, ppc4xx_reg[i].address);
+ value = mfdcr(SDR0_CFGDATA);
+ break;
+ case MM: /* Directly Accessed MMIO Register */
+ value = in_be32((const volatile unsigned __iomem *)
+ ppc4xx_reg[i].address);
+ break;
+ default:
+ printf("\nERROR: struct entry %d: unknown register"
+ "type\n", i);
+ break;
+ }
+ printf("0x%08x %-16s: 0x%08x\n",ppc4xx_reg[i].address,
+ ppc4xx_reg[i].name, value);
+ }
+}
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 988ba97..906face 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -334,7 +334,7 @@
sysInfo->pllFbkDiv = temp ? temp : 32;
lfdiv = reg & PLLD_LFBDV_MASK;
- mfcpr(CPR0_OPBD, reg);
+ mfcpr(CPR0_OPBD0, reg);
temp = (reg & OPBDDV_MASK) >> 24;
sysInfo->pllOpbDiv = temp ? temp : 4;
@@ -342,7 +342,7 @@
temp = (reg & PERDV_MASK) >> 24;
sysInfo->pllExtBusDiv = temp ? temp : 8;
- mfcpr(CPR0_PRIMBD, reg);
+ mfcpr(CPR0_PRIMBD0, reg);
temp = (reg & PRBDV_MASK) >> 24;
prbdv0 = temp ? temp : 8;
@@ -1050,7 +1050,7 @@
/*
* Determine OPBDV0
*/
- mfcpr(CPR0_OPBD, tmp);
+ mfcpr(CPR0_OPBD0, tmp);
tmp = (tmp >> 24) & 0x03;
sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;
diff --git a/doc/README.drivers.eth b/doc/README.drivers.eth
new file mode 100644
index 0000000..e06d3ad
--- /dev/null
+++ b/doc/README.drivers.eth
@@ -0,0 +1,182 @@
+-----------------------
+ Ethernet Driver Guide
+-----------------------
+
+The networking stack in Das U-Boot is designed for multiple network devices
+to be easily added and controlled at runtime. This guide is meant for people
+who wish to review the net driver stack with an eye towards implementing your
+own ethernet device driver. Here we will describe a new pseudo 'APE' driver.
+
+------------------
+ Driver Functions
+------------------
+
+All functions you will be implementing in this document have the return value
+meaning of 0 for success and non-zero for failure.
+
+ ----------
+ Register
+ ----------
+
+When U-Boot initializes, it will call the common function eth_initialize().
+This will in turn call the board-specific board_eth_init() (or if that fails,
+the cpu-specific cpu_eth_init()). These board-specific functions can do random
+system handling, but ultimately they will call the driver-specific register
+function which in turn takes care of initializing that particular instance.
+
+Keep in mind that you should code the driver to avoid storing state in global
+data as someone might want to hook up two of the same devices to one board.
+Any such information that is specific to an interface should be stored in a
+private, driver-defined data structure and pointed to by eth->priv (see below).
+
+So the call graph at this stage would look something like:
+board_init()
+ eth_initialize()
+ board_eth_init() / cpu_eth_init()
+ driver_register()
+ initialize eth_device
+ eth_register()
+
+At this point in time, the only thing you need to worry about is the driver's
+register function. The pseudo code would look something like:
+int ape_register(bd_t *bis, int iobase)
+{
+ struct ape_priv *priv;
+ struct eth_device *dev;
+
+ priv = malloc(sizeof(*priv));
+ if (priv == NULL)
+ return 1;
+
+ dev = malloc(sizeof(*dev));
+ if (dev == NULL) {
+ free(priv);
+ return 1;
+ }
+
+ /* setup whatever private state you need */
+
+ memset(dev, 0, sizeof(*dev));
+ sprintf(dev->name, "APE");
+
+ /* if your device has dedicated hardware storage for the
+ * MAC, read it and initialize dev->enetaddr with it
+ */
+ ape_mac_read(dev->enetaddr);
+
+ dev->iobase = iobase;
+ dev->priv = priv;
+ dev->init = ape_init;
+ dev->halt = ape_halt;
+ dev->send = ape_send;
+ dev->recv = ape_recv;
+
+ eth_register(dev);
+
+#ifdef CONFIG_CMD_MII)
+ miiphy_register(dev->name, ape_mii_read, ape_mii_write);
+#endif
+
+ return 1;
+}
+
+The exact arguments needed to initialize your device are up to you. If you
+need to pass more/less arguments, that's fine. You should also add the
+prototype for your new register function to include/netdev.h.
+
+The return value for this function should be as follows:
+< 0 - failure (hardware failure, not probe failure)
+>=0 - number of interfaces detected
+
+You might notice that many drivers seem to use xxx_initialize() rather than
+xxx_register(). This is the old naming convention and should be avoided as it
+causes confusion with the driver-specific init function.
+
+Other than locating the MAC address in dedicated hardware storage, you should
+not touch the hardware in anyway. That step is handled in the driver-specific
+init function. Remember that we are only registering the device here, we are
+not checking its state or doing random probing.
+
+ -----------
+ Callbacks
+ -----------
+
+Now that we've registered with the ethernet layer, we can start getting some
+real work done. You will need four functions:
+ int ape_init(struct eth_device *dev, bd_t *bis);
+ int ape_send(struct eth_device *dev, volatile void *packet, int length);
+ int ape_recv(struct eth_device *dev);
+ int ape_halt(struct eth_device *dev);
+
+The init function checks the hardware (probing/identifying) and gets it ready
+for send/recv operations. You often do things here such as resetting the MAC
+and/or PHY, and waiting for the link to autonegotiate. You should also take
+the opportunity to program the device's MAC address with the dev->enetaddr
+member. This allows the rest of U-Boot to dynamically change the MAC address
+and have the new settings be respected.
+
+The send function does what you think -- transmit the specified packet whose
+size is specified by length (in bytes). You should not return until the
+transmission is complete, and you should leave the state such that the send
+function can be called multiple times in a row.
+
+The recv function should process packets as long as the hardware has them
+readily available before returning. i.e. you should drain the hardware fifo.
+The common code sets up packet buffers for you already (NetRxPackets), so there
+is no need to allocate your own. For each packet you receive, you should call
+the NetReceive() function on it with the packet length. So the pseudo code
+here would look something like:
+int ape_recv(struct eth_device *dev)
+{
+ int length, i = 0;
+ ...
+ while (packets_are_available()) {
+ ...
+ length = ape_get_packet(&NetRxPackets[i]);
+ ...
+ NetReceive(&NetRxPackets[i], length);
+ ...
+ if (++i >= PKTBUFSRX)
+ i = 0;
+ ...
+ }
+ ...
+ return 0;
+}
+
+The halt function should turn off / disable the hardware and place it back in
+its reset state.
+
+So the call graph at this stage would look something like:
+some net operation (ping / tftp / whatever...)
+ eth_init()
+ dev->init()
+ eth_send()
+ dev->send()
+ eth_rx()
+ dev->recv()
+ eth_halt()
+ dev->halt()
+
+-----------------------------
+ CONFIG_MII / CONFIG_CMD_MII
+-----------------------------
+
+If your device supports banging arbitrary values on the MII bus (pretty much
+every device does), you should add support for the mii command. Doing so is
+fairly trivial and makes debugging mii issues a lot easier at runtime.
+
+After you have called eth_register() in your driver's register function, add
+a call to miiphy_register() like so:
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+ miiphy_register(dev->name, mii_read, mii_write);
+#endif
+
+And then define the mii_read and mii_write functions if you haven't already.
+Their syntax is straightforward:
+ int mii_read(char *devname, uchar addr, uchar reg, ushort *val);
+ int mii_write(char *devname, uchar addr, uchar reg, ushort val);
+
+The read function should read the register 'reg' from the phy at address 'addr'
+and store the result in the pointer 'val'. The implementation for the write
+function should logically follow.
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index afd1084..2fac641 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -44,7 +44,7 @@
* RX descriptor address up to the next cache line boundary.
* 16-Jan-00 Added support for booting with IP of 0x0 MKW
* 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
- * EMAC_RXM register. JWB
+ * EMAC0_RXM register. JWB
* 12-Mar-01 anne-sophie.harnois@nextream.fr
* - Variables are compatible with those already defined in
* include/net.h
@@ -58,7 +58,7 @@
* 08-May-01 stefan.roese@esd-electronics.com
* - MAL error handling added (eth_init called again)
* 13-Nov-01 stefan.roese@esd-electronics.com
- * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
+ * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
* 04-Jan-02 stefan.roese@esd-electronics.com
* - Wait for PHY auto negotiation to complete added
* 06-Feb-02 stefan.roese@esd-electronics.com
@@ -359,7 +359,7 @@
EMAC_4XX_HW_PST hw_p = dev->priv;
u32 val = 10000;
- out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
+ out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
@@ -382,7 +382,7 @@
emac_loopback_enable(hw_p);
/* EMAC RESET */
- out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+ out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
/* remove clocks for EMAC internal loopback */
emac_loopback_disable(hw_p);
@@ -485,7 +485,7 @@
/* Ensure we setup mdio for this devnum and ONLY this devnum */
zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
- out_be32((void *)ZMII_FER, zmiifer);
+ out_be32((void *)ZMII0_FER, zmiifer);
out_be32((void *)RGMII_FER, rmiifer);
return ((int)pfc1);
@@ -504,21 +504,21 @@
switch (pfc1) {
case SDR0_PFC1_SELECT_CONFIG_2:
/* 1 x GMII port */
- out_be32((void *)ZMII_FER, 0x00);
+ out_be32((void *)ZMII0_FER, 0x00);
out_be32((void *)RGMII_FER, 0x00000037);
bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
case SDR0_PFC1_SELECT_CONFIG_4:
/* 2 x RGMII ports */
- out_be32((void *)ZMII_FER, 0x00);
+ out_be32((void *)ZMII0_FER, 0x00);
out_be32((void *)RGMII_FER, 0x00000055);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
case SDR0_PFC1_SELECT_CONFIG_6:
/* 2 x SMII ports */
- out_be32((void *)ZMII_FER,
+ out_be32((void *)ZMII0_FER,
((ZMII_FER_SMII) << ZMII_FER_V(0)) |
((ZMII_FER_SMII) << ZMII_FER_V(1)));
out_be32((void *)RGMII_FER, 0x00000000);
@@ -527,7 +527,7 @@
break;
case SDR0_PFC1_SELECT_CONFIG_1_2:
/* only 1 x MII supported */
- out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
+ out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
out_be32((void *)RGMII_FER, 0x00000000);
bis->bi_phymode[0] = BI_PHYMODE_MII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
@@ -537,9 +537,9 @@
}
/* Ensure we setup mdio for this devnum and ONLY this devnum */
- zmiifer = in_be32((void *)ZMII_FER);
+ zmiifer = in_be32((void *)ZMII0_FER);
zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
- out_be32((void *)ZMII_FER, zmiifer);
+ out_be32((void *)ZMII0_FER, zmiifer);
return ((int)0x0);
}
@@ -953,18 +953,18 @@
/* NOTE: Therefore, disable all other EMACS, since we handle */
/* NOTE: only one emac at a time */
reg = 0;
- out_be32((void *)ZMII_FER, 0);
+ out_be32((void *)ZMII0_FER, 0);
udelay (100);
#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
- out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
+ out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#elif defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
#endif
- out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
+ out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
#if defined(CONFIG_405EX)
ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
@@ -976,13 +976,13 @@
emac_loopback_enable(hw_p);
/* EMAC RESET */
- out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+ out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
/* remove clocks for EMAC internal loopback */
emac_loopback_disable(hw_p);
failsafe = 1000;
- while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
+ while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
udelay (1000);
failsafe--;
}
@@ -1000,15 +1000,15 @@
opbfreq = sysinfo.freqOPB / 1000000;
if (opbfreq <= 50);
else if (opbfreq <= 66)
- mode_reg |= EMAC_M1_OBCI_66;
+ mode_reg |= EMAC_MR1_OBCI_66;
else if (opbfreq <= 83)
- mode_reg |= EMAC_M1_OBCI_83;
+ mode_reg |= EMAC_MR1_OBCI_83;
else if (opbfreq <= 100)
- mode_reg |= EMAC_M1_OBCI_100;
+ mode_reg |= EMAC_MR1_OBCI_100;
else
- mode_reg |= EMAC_M1_OBCI_GT100;
+ mode_reg |= EMAC_MR1_OBCI_GT100;
- out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
+ out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
@@ -1041,9 +1041,9 @@
#endif
}
- mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
- mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg);
- out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
+ mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
+ mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
+ out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
/* Configure GPCS interface to recommended setting for SGMII */
miiphy_reset(dev->name, reg);
@@ -1250,11 +1250,11 @@
#endif
/* Set ZMII/RGMII speed according to the phy link speed */
- reg = in_be32((void *)ZMII_SSR);
+ reg = in_be32((void *)ZMII0_SSR);
if ( (speed == 100) || (speed == 1000) )
- out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
+ out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
else
- out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
+ out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
if ((devnum == 2) || (devnum == 3)) {
if (speed == 1000)
@@ -1381,7 +1381,7 @@
reg = reg << 8;
reg |= dev->enetaddr[1];
- out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
+ out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
reg = 0x00000000;
reg |= dev->enetaddr[2]; /* set low address */
@@ -1392,7 +1392,7 @@
reg = reg << 8;
reg |= dev->enetaddr[5];
- out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
+ out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
switch (devnum) {
case 1:
@@ -1480,9 +1480,9 @@
mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
/* set transmit enable & receive enable */
- out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+ out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
- mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
+ mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
/* set rx-/tx-fifo size */
mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
@@ -1497,47 +1497,47 @@
pfc1 |= SDR0_PFC1_EM_1000;
mtsdr (SDR0_PFC1, pfc1);
#endif
- mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
+ mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
} else if (speed == _100BASET)
- mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
+ mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
else
mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
if (duplex == FULL)
- mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
+ mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
- out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
+ out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
/* Enable broadcast and indvidual address */
/* TBS: enabling runts as some misbehaved nics will send runts */
- out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
+ out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
/* we probably need to set the tx mode1 reg? maybe at tx time */
/* set transmit request threshold register */
- out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
+ out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440s has a 64 byte burst length */
- out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
+ out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
#else
/* 405s have a 16 byte burst length */
- out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
+ out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
#endif /* defined(CONFIG_440) */
- out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
+ out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
- out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
+ out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
/* Frame gap set */
- out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
+ out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
/* Set EMAC IER */
hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
if (speed == _100BASET)
hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
- out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
- out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
+ out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
+ out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
if (hw_p->first_init == 0) {
/*
@@ -1596,8 +1596,8 @@
sync();
- out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
- in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
+ out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
+ in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
#ifdef INFO_4XX_ENET
hw_p->stats.pkts_tx++;
#endif
@@ -1607,9 +1607,9 @@
*-----------------------------------------------------------------------*/
time_start = get_timer (0);
while (1) {
- temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
+ temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
/* loop until either TINT turns on or 3 seconds elapse */
- if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
+ if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
/* transmit is done, so now check for errors
* If there is an error, an interrupt should
* happen when we return
@@ -1678,7 +1678,7 @@
/* look for EMAC errors */
if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
- emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
+ emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
emac_err(dev, emac_isr);
/* clear EMAC error interrupt status bits */
@@ -1717,6 +1717,15 @@
rc = 0;
}
}
+#if defined(CONFIG_405EZ)
+ /*
+ * On 405EZ the RX-/TX-interrupts are coalesced into
+ * one IRQ bit in the UIC. We need to acknowledge the
+ * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
+ */
+ mtsdr(SDR0_ICINTSTAT,
+ SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
+#endif /* defined(CONFIG_405EZ) */
} while (serviced);
return (rc);
@@ -1752,7 +1761,7 @@
EMAC_4XX_HW_PST hw_p = dev->priv;
printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
- out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
+ out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
}
/*-----------------------------------------------------------------------------+
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index be5c484..fc9887b 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -64,7 +64,7 @@
COBJS-$(CONFIG_RTL8169) += rtl8169.o
COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
-COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o
+COBJS-$(CONFIG_SMC91111) += smc91111.o
COBJS-$(CONFIG_SMC911X) += smc911x.o
COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c
index 479035d..07a86cd 100644
--- a/drivers/net/kirkwood_egiga.c
+++ b/drivers/net/kirkwood_egiga.c
@@ -400,8 +400,10 @@
{
struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
struct kwgbe_registers *regs = dkwgbe->regs;
+#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
+ && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
-
+#endif
/* setup RX rings */
kwgbe_init_rx_desc_ring(dkwgbe);
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 3754e8b..2d1de02 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -201,11 +201,11 @@
*/
static int mv88e61xx_busychk(char *name)
{
- u32 reg = 0;
+ u16 reg = 0;
u32 timeout = MV88E61XX_PHY_TIMEOUT;
do {
RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
- MV88E61XX_PHY_CMD, (u16 *) & reg);
+ MV88E61XX_PHY_CMD, ®);
if (timeout-- == 0) {
printf("SMI busy timeout\n");
return -1;
diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
index b41e4d2..54a1bfb 100644
--- a/drivers/net/smc91111.c
+++ b/drivers/net/smc91111.c
@@ -62,6 +62,7 @@
#include <common.h>
#include <command.h>
#include <config.h>
+#include <malloc.h>
#include "smc91111.h"
#include <net.h>
@@ -122,17 +123,15 @@
. what you are doing.
.
-------------------------------------------------------------------------*/
-#define CARDNAME "LAN91C111"
/* Memory sizing constant */
#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
#ifndef CONFIG_SMC91111_BASE
-#define CONFIG_SMC91111_BASE 0x20000300
+#error "SMC91111 Base address must be passed to initialization funciton"
+/* #define CONFIG_SMC91111_BASE 0x20000300 */
#endif
-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-
#define SMC_DEV_NAME "SMC91111"
#define SMC_PHY_ADDR 0x0000
#define SMC_ALLOC_MAX_TRY 5
@@ -147,73 +146,18 @@
#else
#undef USE_32_BIT
#endif
-/*-----------------------------------------------------------------
- .
- . The driver can be entered at any of the following entry points.
- .
- .------------------------------------------------------------------ */
-
-extern int eth_init(bd_t *bd);
-extern void eth_halt(void);
-extern int eth_rx(void);
-extern int eth_send(volatile void *packet, int length);
#ifdef SHARED_RESOURCES
- extern void swap_to(int device_id);
+extern void swap_to(int device_id);
+#else
+# define swap_to(x)
#endif
-/*
- . This is called by register_netdev(). It is responsible for
- . checking the portlist for the SMC9000 series chipset. If it finds
- . one, then it will initialize the device, find the hardware information,
- . and sets up the appropriate device parameters.
- . NOTE: Interrupts are *OFF* when this procedure is called.
- .
- . NB:This shouldn't be static since it is referred to externally.
-*/
-int smc_init(void);
-
-/*
- . This is called by unregister_netdev(). It is responsible for
- . cleaning up before the driver is finally unregistered and discarded.
-*/
-void smc_destructor(void);
-
-/*
- . The kernel calls this function when someone wants to use the device,
- . typically 'ifconfig ethX up'.
-*/
-static int smc_open(bd_t *bd);
-
-
-/*
- . This is called by the kernel in response to 'ifconfig ethX down'. It
- . is responsible for cleaning up everything that the open routine
- . does, and maybe putting the card into a powerdown state.
-*/
-static int smc_close(void);
-
-/*
- . Configures the PHY through the MII Management interface
-*/
#ifndef CONFIG_SMC91111_EXT_PHY
-static void smc_phy_configure(void);
+static void smc_phy_configure(struct eth_device *dev);
#endif /* !CONFIG_SMC91111_EXT_PHY */
/*
- . This is a separate procedure to handle the receipt of a packet, to
- . leave the interrupt code looking slightly cleaner
-*/
-static int smc_rcv(void);
-
-/* See if a MAC address is defined in the current environment. If so use it. If not
- . print a warning and set the environment and other globals with the default.
- . If an EEPROM is present it really should be consulted.
-*/
-int smc_get_ethaddr(bd_t *bd);
-int get_rom_mac(uchar *v_rom_mac);
-
-/*
------------------------------------------------------------
.
. Internal routines
@@ -233,125 +177,69 @@
* packets being corrupt (shifted) on the wire, etc. Switching to the
* inx,outx functions fixed this problem.
*/
-static inline word SMC_inw(dword offset);
-static inline void SMC_outw(word value, dword offset);
-static inline byte SMC_inb(dword offset);
-static inline void SMC_outb(byte value, dword offset);
-static inline void SMC_insw(dword offset, volatile uchar* buf, dword len);
-static inline void SMC_outsw(dword offset, uchar* buf, dword len);
#define barrier() __asm__ __volatile__("": : :"memory")
-static inline word SMC_inw(dword offset)
+static inline word SMC_inw(struct eth_device *dev, dword offset)
{
word v;
- v = *((volatile word*)(SMC_BASE_ADDRESS+offset));
+ v = *((volatile word*)(dev->iobase + offset));
barrier(); *(volatile u32*)(0xc0000000);
return v;
}
-static inline void SMC_outw(word value, dword offset)
+static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
{
- *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value;
+ *((volatile word*)(dev->iobase + offset)) = value;
barrier(); *(volatile u32*)(0xc0000000);
}
-static inline byte SMC_inb(dword offset)
+static inline byte SMC_inb(struct eth_device *dev, dword offset)
{
word _w;
- _w = SMC_inw(offset & ~((dword)1));
+ _w = SMC_inw(dev, offset & ~((dword)1));
return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
}
-static inline void SMC_outb(byte value, dword offset)
+static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
{
word _w;
- _w = SMC_inw(offset & ~((dword)1));
+ _w = SMC_inw(dev, offset & ~((dword)1));
if (offset & 1)
- *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff);
+ *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
+ (value<<8) | (_w & 0x00ff);
else
- *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00);
+ *((volatile word*)(dev->iobase + offset)) =
+ value | (_w & 0xff00);
}
-static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
+static inline void SMC_insw(struct eth_device *dev, dword offset,
+ volatile uchar* buf, dword len)
{
volatile word *p = (volatile word *)buf;
while (len-- > 0) {
- *p++ = SMC_inw(offset);
+ *p++ = SMC_inw(dev, offset);
barrier();
*((volatile u32*)(0xc0000000));
}
}
-static inline void SMC_outsw(dword offset, uchar* buf, dword len)
+static inline void SMC_outsw(struct eth_device *dev, dword offset,
+ uchar* buf, dword len)
{
volatile word *p = (volatile word *)buf;
while (len-- > 0) {
- SMC_outw(*p++, offset);
+ SMC_outw(dev, *p++, offset);
barrier();
*(volatile u32*)(0xc0000000);
}
}
#endif /* CONFIG_SMC_USE_IOFUNCS */
-static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
-
-/*
- * This function must be called before smc_open() if you want to override
- * the default mac address.
- */
-
-void smc_set_mac_addr(const unsigned char *addr) {
- int i;
-
- for (i=0; i < sizeof(smc_mac_addr); i++){
- smc_mac_addr[i] = addr[i];
- }
-}
-
-/*
- * smc_get_macaddr is no longer used. If you want to override the default
- * mac address, call smc_get_mac_addr as a part of the board initialization.
- */
-
-#if 0
-void smc_get_macaddr( byte *addr ) {
- /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
- unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
- int i;
-
-
- for (i=0; i<6; i++) {
- addr[0] = *(dnp1110_mac+0);
- addr[1] = *(dnp1110_mac+1);
- addr[2] = *(dnp1110_mac+2);
- addr[3] = *(dnp1110_mac+3);
- addr[4] = *(dnp1110_mac+4);
- addr[5] = *(dnp1110_mac+5);
- }
-}
-#endif /* 0 */
-
-/***********************************************
- * Show available memory *
- ***********************************************/
-void dump_memory_info(void)
-{
- word mem_info;
- word old_bank;
-
- old_bank = SMC_inw(BANK_SELECT)&0xF;
-
- SMC_SELECT_BANK(0);
- mem_info = SMC_inw( MIR_REG );
- PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
-
- SMC_SELECT_BANK(old_bank);
-}
/*
. A rather simple routine to print out a packet for debugging purposes.
*/
@@ -361,35 +249,15 @@
#define tx_done(dev) 1
-
-/* this does a soft reset on the device */
-static void smc_reset( void );
-
-/* Enable Interrupts, Receive, and Transmit */
-static void smc_enable( void );
-
-/* this puts the device in an inactive state */
-static void smc_shutdown( void );
-
-/* Routines to Read and Write the PHY Registers across the
- MII Management Interface
-*/
-
-#ifndef CONFIG_SMC91111_EXT_PHY
-static word smc_read_phy_register(byte phyreg);
-static void smc_write_phy_register(byte phyreg, word phydata);
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-
-static int poll4int (byte mask, int timeout)
+static int poll4int (struct eth_device *dev, byte mask, int timeout)
{
int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
int is_timeout = 0;
- word old_bank = SMC_inw (BSR_REG);
+ word old_bank = SMC_inw (dev, BSR_REG);
PRINTK2 ("Polling...\n");
- SMC_SELECT_BANK (2);
- while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
+ SMC_SELECT_BANK (dev, 2);
+ while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
if (get_timer (0) >= tmo) {
is_timeout = 1;
break;
@@ -397,7 +265,7 @@
}
/* restore old bank selection */
- SMC_SELECT_BANK (old_bank);
+ SMC_SELECT_BANK (dev, old_bank);
if (is_timeout)
return 1;
@@ -406,12 +274,12 @@
}
/* Only one release command at a time, please */
-static inline void smc_wait_mmu_release_complete (void)
+static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
{
int count = 0;
/* assume bank 2 selected */
- while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
+ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
udelay (1); /* Wait until not busy */
if (++count > 200)
break;
@@ -435,49 +303,50 @@
. 5. clear all interrupts
.
*/
-static void smc_reset (void)
+static void smc_reset (struct eth_device *dev)
{
PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
/* This resets the registers mostly to defaults, but doesn't
affect EEPROM. That seems unnecessary */
- SMC_SELECT_BANK (0);
- SMC_outw (RCR_SOFTRST, RCR_REG);
+ SMC_SELECT_BANK (dev, 0);
+ SMC_outw (dev, RCR_SOFTRST, RCR_REG);
/* Setup the Configuration Register */
/* This is necessary because the CONFIG_REG is not affected */
/* by a soft reset */
- SMC_SELECT_BANK (1);
+ SMC_SELECT_BANK (dev, 1);
#if defined(CONFIG_SMC91111_EXT_PHY)
- SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
+ SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
#else
- SMC_outw (CONFIG_DEFAULT, CONFIG_REG);
+ SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
#endif
/* Release from possible power-down state */
/* Configuration register is not affected by Soft Reset */
- SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG);
+ SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
+ CONFIG_REG);
- SMC_SELECT_BANK (0);
+ SMC_SELECT_BANK (dev, 0);
/* this should pause enough for the chip to be happy */
udelay (10);
/* Disable transmit and receive functionality */
- SMC_outw (RCR_CLEAR, RCR_REG);
- SMC_outw (TCR_CLEAR, TCR_REG);
+ SMC_outw (dev, RCR_CLEAR, RCR_REG);
+ SMC_outw (dev, TCR_CLEAR, TCR_REG);
/* set the control register */
- SMC_SELECT_BANK (1);
- SMC_outw (CTL_DEFAULT, CTL_REG);
+ SMC_SELECT_BANK (dev, 1);
+ SMC_outw (dev, CTL_DEFAULT, CTL_REG);
/* Reset the MMU */
- SMC_SELECT_BANK (2);
- smc_wait_mmu_release_complete ();
- SMC_outw (MC_RESET, MMU_CMD_REG);
- while (SMC_inw (MMU_CMD_REG) & MC_BUSY)
+ SMC_SELECT_BANK (dev, 2);
+ smc_wait_mmu_release_complete (dev);
+ SMC_outw (dev, MC_RESET, MMU_CMD_REG);
+ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
udelay (1); /* Wait until not busy */
/* Note: It doesn't seem that waiting for the MMU busy is needed here,
@@ -485,7 +354,7 @@
of issuing another MMU command right after this */
/* Disable all interrupts */
- SMC_outb (0, IM_REG);
+ SMC_outb (dev, 0, IM_REG);
}
/*
@@ -496,20 +365,20 @@
. 2. Enable the receiver
. 3. Enable interrupts
*/
-static void smc_enable()
+static void smc_enable(struct eth_device *dev)
{
PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
- SMC_SELECT_BANK( 0 );
+ SMC_SELECT_BANK( dev, 0 );
/* see the header file for options in TCR/RCR DEFAULT*/
- SMC_outw( TCR_DEFAULT, TCR_REG );
- SMC_outw( RCR_DEFAULT, RCR_REG );
+ SMC_outw( dev, TCR_DEFAULT, TCR_REG );
+ SMC_outw( dev, RCR_DEFAULT, RCR_REG );
/* clear MII_DIS */
/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
}
/*
- . Function: smc_shutdown
+ . Function: smc_halt
. Purpose: closes down the SMC91xxx chip.
. Method:
. 1. zero the interrupt mask
@@ -522,26 +391,25 @@
. the manual says that it will wake up in response to any I/O requests
. in the register space. Empirical results do not show this working.
*/
-static void smc_shutdown()
+static void smc_halt(struct eth_device *dev)
{
- PRINTK2(CARDNAME ": smc_shutdown\n");
+ PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
/* no more interrupts for me */
- SMC_SELECT_BANK( 2 );
- SMC_outb( 0, IM_REG );
+ SMC_SELECT_BANK( dev, 2 );
+ SMC_outb( dev, 0, IM_REG );
/* and tell the card to stay away from that nasty outside world */
- SMC_SELECT_BANK( 0 );
- SMC_outb( RCR_CLEAR, RCR_REG );
- SMC_outb( TCR_CLEAR, TCR_REG );
-#ifdef SHARED_RESOURCES
+ SMC_SELECT_BANK( dev, 0 );
+ SMC_outb( dev, RCR_CLEAR, RCR_REG );
+ SMC_outb( dev, TCR_CLEAR, TCR_REG );
+
swap_to(FLASH);
-#endif
}
/*
- . Function: smc_hardware_send_packet(struct net_device * )
+ . Function: smc_send(struct net_device * )
. Purpose:
. This sends the actual packet to the SMC9xxx chip.
.
@@ -558,10 +426,10 @@
. Enable the transmit interrupt, so I know if it failed
. Free the kernel data if I actually sent it.
*/
-static int smc_send_packet (volatile void *packet, int packet_length)
+static int smc_send(struct eth_device *dev, volatile void *packet,
+ int packet_length)
{
byte packet_no;
- unsigned long ioaddr;
byte *buf;
int length;
int numPages;
@@ -572,9 +440,9 @@
word saved_ptr;
/* save PTR and PNR registers before manipulation */
- SMC_SELECT_BANK (2);
- saved_pnr = SMC_inb( PN_REG );
- saved_ptr = SMC_inw( PTR_REG );
+ SMC_SELECT_BANK (dev, 2);
+ saved_pnr = SMC_inb( dev, PN_REG );
+ saved_ptr = SMC_inw( dev, PTR_REG );
PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
@@ -601,8 +469,8 @@
}
/* now, try to allocate the memory */
- SMC_SELECT_BANK (2);
- SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
+ SMC_SELECT_BANK (dev, 2);
+ SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
/* FIXME: the ALLOC_INT bit never gets set *
* so the following will always give a *
@@ -615,10 +483,10 @@
try++;
time_out = MEMORY_WAIT_TIME;
do {
- status = SMC_inb (SMC91111_INT_REG);
+ status = SMC_inb (dev, SMC91111_INT_REG);
if (status & IM_ALLOC_INT) {
/* acknowledge the interrupt */
- SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG);
+ SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
break;
}
} while (--time_out);
@@ -635,14 +503,10 @@
PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
SMC_DEV_NAME, try);
- /* I can send the packet now.. */
-
- ioaddr = SMC_BASE_ADDRESS;
-
buf = (byte *) packet;
/* If I get here, I _know_ there is a packet slot waiting for me */
- packet_no = SMC_inb (AR_REG);
+ packet_no = SMC_inb (dev, AR_REG);
if (packet_no & AR_FAILED) {
/* or isn't there? BAD CHIP! */
printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
@@ -651,20 +515,20 @@
/* we have a packet address, so tell the card to use it */
#ifndef CONFIG_XAENIAX
- SMC_outb (packet_no, PN_REG);
+ SMC_outb (dev, packet_no, PN_REG);
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
* the Allocate MMU command will end up written to the command register
* as well, which will lead to a problem.
*/
- SMC_outl (packet_no << 16, 0);
+ SMC_outl (dev, packet_no << 16, 0);
#endif
/* do not write new ptr value if Write data fifo not empty */
while ( saved_ptr & PTR_NOTEMPTY )
printf ("Write data fifo not empty!\n");
/* point to the beginning of the packet */
- SMC_outw (PTR_AUTOINC, PTR_REG);
+ SMC_outw (dev, PTR_AUTOINC, PTR_REG);
PRINTK3 ("%s: Trying to xmit packet of length %x\n",
SMC_DEV_NAME, length);
@@ -677,11 +541,11 @@
/* send the packet length ( +6 for status, length and ctl byte )
and the status word ( set to zeros ) */
#ifdef USE_32_BIT
- SMC_outl ((length + 6) << 16, SMC91111_DATA_REG);
+ SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
#else
- SMC_outw (0, SMC91111_DATA_REG);
+ SMC_outw (dev, 0, SMC91111_DATA_REG);
/* send the packet length ( +6 for status words, length, and ctl */
- SMC_outw ((length + 6), SMC91111_DATA_REG);
+ SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
#endif
/* send the actual data
@@ -692,10 +556,10 @@
. almost as much time as is saved?
*/
#ifdef USE_32_BIT
- SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
+ SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
#ifndef CONFIG_XAENIAX
if (length & 0x2)
- SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
+ SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
SMC91111_DATA_REG);
#else
/* On XANEIAX, we can only use 32-bit writes, so we need to handle
@@ -703,48 +567,48 @@
*/
if ((length & 3) == 3) {
u16 * ptr = (u16*) &buf[length-3];
- SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16),
+ SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
SMC91111_DATA_REG);
} else if ((length & 2) == 2) {
u16 * ptr = (u16*) &buf[length-2];
- SMC_outl(*ptr, SMC91111_DATA_REG);
+ SMC_outl(dev, *ptr, SMC91111_DATA_REG);
} else if (length & 1) {
- SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG);
+ SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
} else {
- SMC_outl(0, SMC91111_DATA_REG);
+ SMC_outl(dev, 0, SMC91111_DATA_REG);
}
#endif
#else
- SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
+ SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
#endif /* USE_32_BIT */
#ifndef CONFIG_XAENIAX
/* Send the last byte, if there is one. */
if ((length & 1) == 0) {
- SMC_outw (0, SMC91111_DATA_REG);
+ SMC_outw (dev, 0, SMC91111_DATA_REG);
} else {
- SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
+ SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
}
#endif
/* and let the chipset deal with it */
- SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
+ SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
/* poll for TX INT */
- /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */
+ /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
/* poll for TX_EMPTY INT - autorelease enabled */
- if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
+ if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
/* sending failed */
PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
/* release packet */
/* no need to release, MMU does that now */
#ifdef CONFIG_XAENIAX
- SMC_outw (MC_FREEPKT, MMU_CMD_REG);
+ SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
#endif
/* wait for MMU getting ready (low) */
- while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
+ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
udelay (10);
}
@@ -754,7 +618,7 @@
return 0;
} else {
/* ack. int */
- SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG);
+ SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
/* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
length);
@@ -762,11 +626,11 @@
/* release packet */
/* no need to release, MMU does that now */
#ifdef CONFIG_XAENIAX
- SMC_outw (MC_FREEPKT, MMU_CMD_REG);
+ SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
#endif
/* wait for MMU getting ready (low) */
- while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
+ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
udelay (10);
}
@@ -777,78 +641,62 @@
/* restore previously saved registers */
#ifndef CONFIG_XAENIAX
- SMC_outb( saved_pnr, PN_REG );
+ SMC_outb( dev, saved_pnr, PN_REG );
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
* the Allocate MMU command will end up written to the command register
* as well, which will lead to a problem.
*/
- SMC_outl(saved_pnr << 16, 0);
+ SMC_outl(dev, saved_pnr << 16, 0);
#endif
- SMC_outw( saved_ptr, PTR_REG );
+ SMC_outw( dev, saved_ptr, PTR_REG );
return length;
}
-/*-------------------------------------------------------------------------
- |
- | smc_destructor( struct net_device * dev )
- | Input parameters:
- | dev, pointer to the device structure
- |
- | Output:
- | None.
- |
- ---------------------------------------------------------------------------
-*/
-void smc_destructor()
-{
- PRINTK2(CARDNAME ": smc_destructor\n");
-}
-
-
/*
* Open and Initialize the board
*
* Set up everything, reset the card, etc ..
*
*/
-static int smc_open (bd_t * bd)
+static int smc_init(struct eth_device *dev, bd_t *bd)
{
- int i, err;
+ int i;
- PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME);
+ swap_to(ETHERNET);
+
+ PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
/* reset the hardware */
- smc_reset ();
- smc_enable ();
+ smc_reset (dev);
+ smc_enable (dev);
/* Configure the PHY */
#ifndef CONFIG_SMC91111_EXT_PHY
- smc_phy_configure ();
+ smc_phy_configure (dev);
#endif
/* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
-/* SMC_SELECT_BANK(0); */
-/* SMC_outw(0, RPC_REG); */
- SMC_SELECT_BANK (1);
+/* SMC_SELECT_BANK(dev, 0); */
+/* SMC_outw(dev, 0, RPC_REG); */
+ SMC_SELECT_BANK (dev, 1);
- err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */
- if (err < 0)
- return -1;
#ifdef USE_32_BIT
for (i = 0; i < 6; i += 2) {
word address;
- address = smc_mac_addr[i + 1] << 8;
- address |= smc_mac_addr[i];
- SMC_outw (address, (ADDR0_REG + i));
+ address = dev->enetaddr[i + 1] << 8;
+ address |= dev->enetaddr[i];
+ SMC_outw(dev, address, (ADDR0_REG + i));
}
#else
for (i = 0; i < 6; i++)
- SMC_outb (smc_mac_addr[i], (ADDR0_REG + i));
+ SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
#endif
+ printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
+
return 0;
}
@@ -864,7 +712,7 @@
. o otherwise, read in the packet
--------------------------------------------------------------
*/
-static int smc_rcv()
+static int smc_rcv(struct eth_device *dev)
{
int packet_number;
word status;
@@ -876,12 +724,12 @@
byte saved_pnr;
word saved_ptr;
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(dev, 2);
/* save PTR and PTR registers */
- saved_pnr = SMC_inb( PN_REG );
- saved_ptr = SMC_inw( PTR_REG );
+ saved_pnr = SMC_inb( dev, PN_REG );
+ saved_ptr = SMC_inw( dev, PTR_REG );
- packet_number = SMC_inw( RXFIFO_REG );
+ packet_number = SMC_inw( dev, RXFIFO_REG );
if ( packet_number & RXFIFO_REMPTY ) {
@@ -890,16 +738,16 @@
PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
/* start reading from the start of the packet */
- SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
+ SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
/* First two words are status and packet_length */
#ifdef USE_32_BIT
- stat_len = SMC_inl(SMC91111_DATA_REG);
+ stat_len = SMC_inl(dev, SMC91111_DATA_REG);
status = stat_len & 0xffff;
packet_length = stat_len >> 16;
#else
- status = SMC_inw( SMC91111_DATA_REG );
- packet_length = SMC_inw( SMC91111_DATA_REG );
+ status = SMC_inw( dev, SMC91111_DATA_REG );
+ packet_length = SMC_inw( dev, SMC91111_DATA_REG );
#endif
packet_length &= 0x07ff; /* mask off top bits */
@@ -923,20 +771,23 @@
to send the DWORDs or the bytes first, or some
mixture. A mixture might improve already slow PIO
performance */
- SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
+ SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0],
+ packet_length >> 2 );
/* read the left over bytes */
if (packet_length & 3) {
int i;
- byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
- dword leftover = SMC_inl(SMC91111_DATA_REG);
+ byte *tail = (byte *)(NetRxPackets[0] +
+ (packet_length & ~3));
+ dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
for (i=0; i<(packet_length & 3); i++)
*tail++ = (byte) (leftover >> (8*i)) & 0xff;
}
#else
PRINTK3(" Reading %d words and %d byte(s) \n",
(packet_length >> 1 ), packet_length & 1 );
- SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
+ SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0],
+ packet_length >> 1);
#endif /* USE_32_BIT */
@@ -950,26 +801,26 @@
is_error = 1;
}
- while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
+ while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
udelay(1); /* Wait until not busy */
/* error or good, tell the card to get rid of this packet */
- SMC_outw( MC_RELEASE, MMU_CMD_REG );
+ SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
- while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
+ while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
udelay(1); /* Wait until not busy */
/* restore saved registers */
#ifndef CONFIG_XAENIAX
- SMC_outb( saved_pnr, PN_REG );
+ SMC_outb( dev, saved_pnr, PN_REG );
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
* the Allocate MMU command will end up written to the command register
* as well, which will lead to a problem.
*/
- SMC_outl( saved_pnr << 16, 0);
+ SMC_outl( dev, saved_pnr << 16, 0);
#endif
- SMC_outw( saved_ptr, PTR_REG );
+ SMC_outw( dev, saved_ptr, PTR_REG );
if (!is_error) {
/* Pass the packet up to the protocol layers. */
@@ -982,43 +833,24 @@
}
-/*----------------------------------------------------
- . smc_close
- .
- . this makes the board clean up everything that it can
- . and not talk to the outside world. Caused by
- . an 'ifconfig ethX down'
- .
- -----------------------------------------------------*/
-static int smc_close()
-{
- PRINTK2("%s: smc_close\n", SMC_DEV_NAME);
-
- /* clear everything */
- smc_shutdown();
-
- return 0;
-}
-
-
#if 0
/*------------------------------------------------------------
. Modify a bit in the LAN91C111 register set
.-------------------------------------------------------------*/
-static word smc_modify_regbit(int bank, int ioaddr, int reg,
+static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
unsigned int bit, int val)
{
word regval;
- SMC_SELECT_BANK( bank );
+ SMC_SELECT_BANK( dev, bank );
- regval = SMC_inw( reg );
+ regval = SMC_inw( dev, reg );
if (val)
regval |= bit;
else
regval &= ~bit;
- SMC_outw( regval, 0 );
+ SMC_outw( dev, regval, 0 );
return(regval);
}
@@ -1026,10 +858,10 @@
/*------------------------------------------------------------
. Retrieve a bit in the LAN91C111 register set
.-------------------------------------------------------------*/
-static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
+static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
{
- SMC_SELECT_BANK( bank );
- if ( SMC_inw( reg ) & bit)
+ SMC_SELECT_BANK( dev, bank );
+ if ( SMC_inw( dev, reg ) & bit)
return(1);
else
return(0);
@@ -1039,20 +871,20 @@
/*------------------------------------------------------------
. Modify a LAN91C111 register (word access only)
.-------------------------------------------------------------*/
-static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
+static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
{
- SMC_SELECT_BANK( bank );
- SMC_outw( val, reg );
+ SMC_SELECT_BANK( dev, bank );
+ SMC_outw( dev, val, reg );
}
/*------------------------------------------------------------
. Retrieve a LAN91C111 register (word access only)
.-------------------------------------------------------------*/
-static int smc_get_reg(int bank, int ioaddr, int reg)
+static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
{
- SMC_SELECT_BANK( bank );
- return(SMC_inw( reg ));
+ SMC_SELECT_BANK( dev, bank );
+ return(SMC_inw( dev, reg ));
}
#endif /* 0 */
@@ -1105,7 +937,7 @@
. Reads a register from the MII Management serial interface
.-------------------------------------------------------------*/
#ifndef CONFIG_SMC91111_EXT_PHY
-static word smc_read_phy_register (byte phyreg)
+static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
{
int oldBank;
int i;
@@ -1168,13 +1000,13 @@
bits[clk_idx++] = 0;
/* Save the current bank */
- oldBank = SMC_inw (BANK_SELECT);
+ oldBank = SMC_inw (dev, BANK_SELECT);
/* Select bank 3 */
- SMC_SELECT_BANK (3);
+ SMC_SELECT_BANK (dev, 3);
/* Get the current MII register value */
- mii_reg = SMC_inw (MII_REG);
+ mii_reg = SMC_inw (dev, MII_REG);
/* Turn off all MII Interface bits */
mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
@@ -1182,23 +1014,23 @@
/* Clock all 64 cycles */
for (i = 0; i < sizeof bits; ++i) {
/* Clock Low - output data */
- SMC_outw (mii_reg | bits[i], MII_REG);
+ SMC_outw (dev, mii_reg | bits[i], MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Clock Hi - input data */
- SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
+ SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
- bits[i] |= SMC_inw (MII_REG) & MII_MDI;
+ bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
}
/* Return to idle state */
/* Set clock to low, data to low, and output tristated */
- SMC_outw (mii_reg, MII_REG);
+ SMC_outw (dev, mii_reg, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Restore original bank select */
- SMC_SELECT_BANK (oldBank);
+ SMC_SELECT_BANK (dev, oldBank);
/* Recover input data */
phydata = 0;
@@ -1222,7 +1054,8 @@
/*------------------------------------------------------------
. Writes a register to the MII Management serial interface
.-------------------------------------------------------------*/
-static void smc_write_phy_register (byte phyreg, word phydata)
+static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
+ word phydata)
{
int oldBank;
int i;
@@ -1288,13 +1121,13 @@
bits[clk_idx++] = 0;
/* Save the current bank */
- oldBank = SMC_inw (BANK_SELECT);
+ oldBank = SMC_inw (dev, BANK_SELECT);
/* Select bank 3 */
- SMC_SELECT_BANK (3);
+ SMC_SELECT_BANK (dev, 3);
/* Get the current MII register value */
- mii_reg = SMC_inw (MII_REG);
+ mii_reg = SMC_inw (dev, MII_REG);
/* Turn off all MII Interface bits */
mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
@@ -1302,23 +1135,23 @@
/* Clock all cycles */
for (i = 0; i < sizeof bits; ++i) {
/* Clock Low - output data */
- SMC_outw (mii_reg | bits[i], MII_REG);
+ SMC_outw (dev, mii_reg | bits[i], MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Clock Hi - input data */
- SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
+ SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
- bits[i] |= SMC_inw (MII_REG) & MII_MDI;
+ bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
}
/* Return to idle state */
/* Set clock to low, data to low, and output tristated */
- SMC_outw (mii_reg, MII_REG);
+ SMC_outw (dev, mii_reg, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Restore original bank select */
- SMC_SELECT_BANK (oldBank);
+ SMC_SELECT_BANK (dev, oldBank);
#if (SMC_DEBUG > 2 )
printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
@@ -1345,7 +1178,7 @@
. smc_phy_fixed() if the user has requested a certain config.
.-------------------------------------------------------------*/
#ifndef CONFIG_SMC91111_EXT_PHY
-static void smc_phy_configure ()
+static void smc_phy_configure (struct eth_device *dev)
{
int timeout;
byte phyaddr;
@@ -1361,12 +1194,12 @@
phyaddr = SMC_PHY_ADDR;
/* Reset the PHY, setting all other bits to zero */
- smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST);
+ smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
/* Wait for the reset to complete, or time out */
timeout = 6; /* Wait up to 3 seconds */
while (timeout--) {
- if (!(smc_read_phy_register (PHY_CNTL_REG)
+ if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
& PHY_CNTL_RST)) {
/* reset complete */
break;
@@ -1385,14 +1218,14 @@
/* Enable PHY Interrupts (for register 18) */
/* Interrupts listed here are disabled */
- smc_write_phy_register (PHY_MASK_REG, 0xffff);
+ smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
/* Configure the Receive/Phy Control register */
- SMC_SELECT_BANK (0);
- SMC_outw (RPC_DEFAULT, RPC_REG);
+ SMC_SELECT_BANK (dev, 0);
+ SMC_outw (dev, RPC_DEFAULT, RPC_REG);
/* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
- my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
+ my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
if (my_phy_caps & PHY_STAT_CAP_T4)
@@ -1411,18 +1244,18 @@
my_ad_caps |= PHY_AD_10_HDX;
/* Update our Auto-Neg Advertisement Register */
- smc_write_phy_register (PHY_AD_REG, my_ad_caps);
+ smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
/* Read the register back. Without this, it appears that when */
/* auto-negotiation is restarted, sometimes it isn't ready and */
/* the link does not come up. */
- smc_read_phy_register(PHY_AD_REG);
+ smc_read_phy_register(dev, PHY_AD_REG);
PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
/* Restart auto-negotiation process in order to advertise my caps */
- smc_write_phy_register (PHY_CNTL_REG,
+ smc_write_phy_register (dev, PHY_CNTL_REG,
PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
/* Wait for the auto-negotiation to complete. This may take from */
@@ -1431,7 +1264,7 @@
timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
while (timeout--) {
- status = smc_read_phy_register (PHY_STAT_REG);
+ status = smc_read_phy_register (dev, PHY_STAT_REG);
if (status & PHY_STAT_ANEG_ACK) {
/* auto-negotiate complete */
break;
@@ -1447,7 +1280,7 @@
/* Restart auto-negotiation */
printf ("%s: PHY restarting auto-negotiation\n",
SMC_DEV_NAME);
- smc_write_phy_register (PHY_CNTL_REG,
+ smc_write_phy_register (dev, PHY_CNTL_REG,
PHY_CNTL_ANEG_EN |
PHY_CNTL_ANEG_RST |
PHY_CNTL_SPEED |
@@ -1467,7 +1300,7 @@
}
/* Re-Configure the Receive/Phy Control register */
- SMC_outw (RPC_DEFAULT, RPC_REG);
+ SMC_outw (dev, RPC_DEFAULT, RPC_REG);
smc_phy_configure_exit: ;
@@ -1512,61 +1345,37 @@
}
#endif
-int eth_init(bd_t *bd) {
-#ifdef SHARED_RESOURCES
- swap_to(ETHERNET);
-#endif
- return (smc_open(bd));
-}
-
-void eth_halt() {
- smc_close();
-}
-
-int eth_rx() {
- return smc_rcv();
-}
-
-int eth_send(volatile void *packet, int length) {
- return smc_send_packet(packet, length);
-}
-
-int smc_get_ethaddr (bd_t * bd)
+int smc91111_initialize(u8 dev_num, int base_addr)
{
- uchar v_mac[6];
-
- if (!eth_getenv_enetaddr("ethaddr", v_mac)) {
- /* get ROM mac value if any */
- if (!get_rom_mac(v_mac)) {
- printf("\n*** ERROR: ethaddr is NOT set !!\n");
- return -1;
- }
- eth_setenv_enetaddr("ethaddr", v_mac);
- }
-
- smc_set_mac_addr(v_mac); /* use old function to update smc default */
- PRINTK("Using MAC Address %pM\n", v_mac);
- return 0;
-}
-
-int get_rom_mac (uchar *v_rom_mac)
-{
-#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
- char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
-
- memcpy (v_rom_mac, hw_mac_addr, 6);
- return (1);
-#else
+ struct smc91111_priv *priv;
+ struct eth_device *dev;
int i;
- int valid_mac = 0;
- SMC_SELECT_BANK (1);
- for (i=0; i<6; i++)
- {
- v_rom_mac[i] = SMC_inb ((ADDR0_REG + i));
- valid_mac |= v_rom_mac[i];
+ priv = malloc(sizeof(*priv));
+ if (!priv)
+ return 0;
+ dev = malloc(sizeof(*dev));
+ if (!dev) {
+ free(priv);
+ return 0;
}
- return (valid_mac ? 1 : 0);
-#endif
+ priv->dev_num = dev_num;
+ dev->priv = priv;
+ dev->iobase = base_addr;
+
+ swap_to(ETHERNET);
+ SMC_SELECT_BANK(dev, 1);
+ for (i = 0; i < 6; ++i)
+ dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
+ swap_to(FLASH);
+
+ dev->init = smc_init;
+ dev->halt = smc_halt;
+ dev->send = smc_send;
+ dev->recv = smc_rcv;
+ sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
+
+ eth_register(dev);
+ return 0;
}
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index 967addd..bb45241 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -58,6 +58,10 @@
typedef unsigned short word;
typedef unsigned long int dword;
+struct smc91111_priv{
+ u8 dev_num;
+};
+
/*
. DEBUGGING LEVELS
.
@@ -77,32 +81,32 @@
#ifdef CONFIG_PXA250
#ifdef CONFIG_XSENGINE
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))))
-#define SMC_inb(p) ({ \
- unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r<<1))))
+#define SMC_inb(a,p) ({ \
+ unsigned int __p = (unsigned int)((a)->iobase + (p<<1)); \
unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
if (__p & 2) __v >>= 8; \
else __v &= 0xff; \
__v; })
#elif defined(CONFIG_XAENIAX)
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
-#define SMC_inw(z) ({ \
- unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
+#define SMC_inw(a,z) ({ \
+ unsigned int __p = (unsigned int)((a)->iobase + (z)); \
unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \
if (__p & 3) __v >>= 16; \
else __v &= 0xffff; \
__v; })
-#define SMC_inb(p) ({ \
- unsigned int ___v = SMC_inw((p) & ~1); \
+#define SMC_inb(a,p) ({ \
+ unsigned int ___v = SMC_inw((a),(p) & ~1); \
if (p & 1) ___v >>= 8; \
else ___v &= 0xff; \
___v; })
#else
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
-#define SMC_inb(p) ({ \
- unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
+#define SMC_inb(a,p) ({ \
+ unsigned int __p = (unsigned int)((a)->iobase + (p)); \
unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
if (__p & 1) __v >>= 8; \
else __v &= 0xff; \
@@ -110,69 +114,69 @@
#endif
#ifdef CONFIG_XSENGINE
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
+#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d)
#elif defined (CONFIG_XAENIAX)
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
-#define SMC_outw(d,p) ({ \
- dword __dwo = SMC_inl((p) & ~3); \
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
+#define SMC_outw(a,d,p) ({ \
+ dword __dwo = SMC_inl((a),(p) & ~3); \
dword __dwn = (word)(d); \
__dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \
__dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \
- SMC_outl(__dwo, (p) & ~3); \
+ SMC_outl((a), __dwo, (p) & ~3); \
})
#else
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
+#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
#endif
-#define SMC_outb(d,r) ({ word __d = (byte)(d); \
- word __w = SMC_inw((r)&~1); \
+#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
+ word __w = SMC_inw((a),(r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(__w,(r)&~1); \
+ SMC_outw((a),__w,(r)&~1); \
})
-#define SMC_outsl(r,b,l) ({ int __i; \
+#define SMC_outsl(a,r,b,l) ({ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outl( *(__b2 + __i), r); \
+ SMC_outl((a), *(__b2 + __i), r); \
} \
})
-#define SMC_outsw(r,b,l) ({ int __i; \
+#define SMC_outsw(a,r,b,l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outw( *(__b2 + __i), r); \
+ SMC_outw((a), *(__b2 + __i), r); \
} \
})
-#define SMC_insl(r,b,l) ({ int __i ; \
+#define SMC_insl(a,r,b,l) ({ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl(r); \
- SMC_inl(0); \
+ *(__b2 + __i) = SMC_inl((a),(r)); \
+ SMC_inl((a),0); \
}; \
})
-#define SMC_insw(r,b,l) ({ int __i ; \
+#define SMC_insw(a,r,b,l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(r); \
- SMC_inw(0); \
+ *(__b2 + __i) = SMC_inw((a),(r)); \
+ SMC_inw((a),0); \
}; \
})
-#define SMC_insb(r,b,l) ({ int __i ; \
+#define SMC_insb(a,r,b,l) ({ int __i ; \
byte *__b2; \
__b2 = (byte *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inb(r); \
- SMC_inb(0); \
+ *(__b2 + __i) = SMC_inb((a),(r)); \
+ SMC_inb((a),0); \
}; \
})
@@ -187,61 +191,61 @@
((0x00FF0000UL & _x) >> 8) | \
(_x >> 24)); })
-#define SMC_inl(r) (SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))))
-#define SMC_inl_nosw(r) ((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))
-#define SMC_inw(r) (SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))))
-#define SMC_inw_nosw(r) ((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))
-#define SMC_inb(p) ({ \
- word ___v = SMC_inw((p) & ~1); \
+#define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0)))))
+#define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0))))
+#define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0)))))
+#define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0))))
+#define SMC_inb(a,p) ({ \
+ word ___v = SMC_inw((a),(p) & ~1); \
if ((p) & 1) ___v >>= 8; \
else ___v &= 0xff; \
___v; })
-#define SMC_outl(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP32(d))
-#define SMC_outl_nosw(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=(d))
-#define SMC_outw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP16(d))
-#define SMC_outw_nosw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=(d))
-#define SMC_outb(d,r) do{ word __d = (byte)(d); \
- word __w = SMC_inw((r)&~1); \
+#define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d))
+#define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d))
+#define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d))
+#define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d))
+#define SMC_outb(a,d,r) do{ word __d = (byte)(d); \
+ word __w = SMC_inw((a),(r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(__w,(r)&~1); \
+ SMC_outw((a),__w,(r)&~1); \
}while(0)
-#define SMC_outsl(r,b,l) do{ int __i; \
+#define SMC_outsl(a,r,b,l) do{ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outl_nosw( *(__b2 + __i), r); \
+ SMC_outl_nosw((a), *(__b2 + __i), r); \
} \
}while(0)
-#define SMC_outsw(r,b,l) do{ int __i; \
+#define SMC_outsw(a,r,b,l) do{ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outw_nosw( *(__b2 + __i), r); \
+ SMC_outw_nosw((a), *(__b2 + __i), r); \
} \
}while(0)
-#define SMC_insl(r,b,l) do{ int __i ; \
+#define SMC_insl(a,r,b,l) do{ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl_nosw(r); \
+ *(__b2 + __i) = SMC_inl_nosw((a),(r)); \
}; \
}while(0)
-#define SMC_insw(r,b,l) do{ int __i ; \
+#define SMC_insw(a,r,b,l) do{ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw_nosw(r); \
+ *(__b2 + __i) = SMC_inw_nosw((a),(r)); \
}; \
}while(0)
-#define SMC_insb(r,b,l) do{ int __i ; \
+#define SMC_insb(a,r,b,l) do{ int __i ; \
byte *__b2; \
__b2 = (byte *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inb(r); \
+ *(__b2 + __i) = SMC_inb((a),(r)); \
}; \
}while(0)
@@ -253,48 +257,48 @@
*/
#ifdef CONFIG_ADNPESC1
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
#elif CONFIG_BLACKFIN
-#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;})
+#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
#else
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
#endif
-#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
+#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
#ifdef CONFIG_ADNPESC1
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
+#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d)
#elif CONFIG_BLACKFIN
-#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d); SSYNC();}
+#define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();}
#else
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
#endif
-#define SMC_outb(d,r) ({ word __d = (byte)(d); \
- word __w = SMC_inw((r)&~1); \
+#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
+ word __w = SMC_inw((a),(r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(__w,(r)&~1); \
+ SMC_outw((a),__w,(r)&~1); \
})
#if 0
-#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l))
+#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l))
#else
-#define SMC_outsw(r,b,l) ({ int __i; \
+#define SMC_outsw(a,r,b,l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outw( *(__b2 + __i), r); \
+ SMC_outw((a), *(__b2 + __i), r); \
} \
})
#endif
#if 0
-#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l))
+#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l))
#else
-#define SMC_insw(r,b,l) ({ int __i ; \
+#define SMC_insw(a,r,b,l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(r); \
- SMC_inw(0); \
+ *(__b2 + __i) = SMC_inw((a),(r)); \
+ SMC_inw((a),0); \
}; \
})
#endif
@@ -304,30 +308,30 @@
#if defined(CONFIG_SMC_USE_32_BIT)
#ifdef CONFIG_XSENGINE
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
#else
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
#endif
-#define SMC_insl(r,b,l) ({ int __i ; \
+#define SMC_insl(a,r,b,l) ({ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl(r); \
- SMC_inl(0); \
+ *(__b2 + __i) = SMC_inl((a),(r)); \
+ SMC_inl((a),0); \
}; \
})
#ifdef CONFIG_XSENGINE
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
#else
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
#endif
-#define SMC_outsl(r,b,l) ({ int __i; \
+#define SMC_outsl(a,r,b,l) ({ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outl( *(__b2 + __i), r); \
+ SMC_outl((a), *(__b2 + __i), r); \
} \
})
@@ -752,25 +756,25 @@
/* select a register bank, 0 to 3 */
-#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); }
+#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); }
/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(x) {\
+#define SMC_ENABLE_INT(a,x) {\
unsigned char mask;\
- SMC_SELECT_BANK(2);\
- mask = SMC_inb( IM_REG );\
+ SMC_SELECT_BANK((a),2);\
+ mask = SMC_inb((a), IM_REG );\
mask |= (x);\
- SMC_outb( mask, IM_REG ); \
+ SMC_outb( (a), mask, IM_REG ); \
}
/* this disables an interrupt from the interrupt mask register */
-#define SMC_DISABLE_INT(x) {\
+#define SMC_DISABLE_INT(a,x) {\
unsigned char mask;\
SMC_SELECT_BANK(2);\
- mask = SMC_inb( IM_REG );\
+ mask = SMC_inb( (a), IM_REG );\
mask &= ~(x);\
- SMC_outb( mask, IM_REG ); \
+ SMC_outb( (a), mask, IM_REG ); \
}
/*----------------------------------------------------------------------
diff --git a/examples/standalone/smc91111_eeprom.c b/examples/standalone/smc91111_eeprom.c
index 39e5306..89afc87 100644
--- a/examples/standalone/smc91111_eeprom.c
+++ b/examples/standalone/smc91111_eeprom.c
@@ -29,9 +29,11 @@
#include <common.h>
#include <exports.h>
+/* the smc91111.h gets base addr through eth_device' iobase */
+struct eth_device { unsigned long iobase; };
#include "../drivers/net/smc91111.h"
-#ifdef CONFIG_DRIVER_SMC91111
+#ifdef CONFIG_SMC91111
#ifndef SMC91111_EEPROM_INIT
# define SMC91111_EEPROM_INIT()
@@ -42,19 +44,23 @@
#define MAC 0x2
#define UNKNOWN 0x4
-void dump_reg (void);
-void dump_eeprom (void);
-int write_eeprom_reg (int, int);
-void copy_from_eeprom (void);
-void print_MAC (void);
-int read_eeprom_reg (int);
-void print_macaddr (void);
+void dump_reg (struct eth_device *dev);
+void dump_eeprom (struct eth_device *dev);
+int write_eeprom_reg (struct eth_device *dev, int value, int reg);
+void copy_from_eeprom (struct eth_device *dev);
+void print_MAC (struct eth_device *dev);
+int read_eeprom_reg (struct eth_device *dev, int reg);
+void print_macaddr (struct eth_device *dev);
int smc91111_eeprom (int argc, char *argv[])
{
int c, i, j, done, line, reg, value, start, what;
char input[50];
+ struct eth_device dev = {
+ .iobase = CONFIG_SMC91111_BASE
+ };
+
/* Print the ABI version */
app_startup (argv);
if (XF_VERSION != (int) get_version ()) {
@@ -67,7 +73,7 @@
SMC91111_EEPROM_INIT();
- if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+ if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
printf ("Can't find SMSC91111\n");
return (0);
}
@@ -211,12 +217,12 @@
switch (what) {
case 1:
printf ("Writing EEPROM register %02x with %04x\n", reg, value);
- write_eeprom_reg (value, reg);
+ write_eeprom_reg (&dev, value, reg);
break;
case 2:
printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
- SMC_SELECT_BANK (reg >> 4);
- SMC_outw (value, reg & 0xE);
+ SMC_SELECT_BANK (&dev, reg >> 4);
+ SMC_outw (&dev, value, reg & 0xE);
break;
default:
printf ("Wrong\n");
@@ -224,16 +230,16 @@
}
break;
case ('D'):
- dump_eeprom ();
+ dump_eeprom (&dev);
break;
case ('M'):
- dump_reg ();
+ dump_reg (&dev);
break;
case ('C'):
- copy_from_eeprom ();
+ copy_from_eeprom (&dev);
break;
case ('P'):
- print_macaddr ();
+ print_macaddr (&dev);
break;
default:
break;
@@ -244,15 +250,15 @@
return (0);
}
-void copy_from_eeprom (void)
+void copy_from_eeprom (struct eth_device *dev)
{
int i;
- SMC_SELECT_BANK (1);
- SMC_outw ((SMC_inw (CTL_REG) & !CTL_EEPROM_SELECT) | CTL_RELOAD,
- CTL_REG);
+ SMC_SELECT_BANK (dev, 1);
+ SMC_outw (dev, (SMC_inw (dev, CTL_REG) & !CTL_EEPROM_SELECT) |
+ CTL_RELOAD, CTL_REG);
i = 100;
- while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --i)
+ while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i)
udelay (100);
if (i == 0) {
printf ("Timeout Refreshing EEPROM registers\n");
@@ -262,21 +268,21 @@
}
-void print_macaddr (void)
+void print_macaddr (struct eth_device *dev)
{
int i, j, k, mac[6];
printf ("Current MAC Address in SMSC91111 ");
- SMC_SELECT_BANK (1);
+ SMC_SELECT_BANK (dev, 1);
for (i = 0; i < 5; i++) {
- printf ("%02x:", SMC_inb (ADDR0_REG + i));
+ printf ("%02x:", SMC_inb (dev, ADDR0_REG + i));
}
- printf ("%02x\n", SMC_inb (ADDR0_REG + 5));
+ printf ("%02x\n", SMC_inb (dev, ADDR0_REG + 5));
i = 0;
for (j = 0x20; j < 0x23; j++) {
- k = read_eeprom_reg (j);
+ k = read_eeprom_reg (dev, j);
mac[i] = k & 0xFF;
i++;
mac[i] = k >> 8;
@@ -289,7 +295,7 @@
printf ("%02x\n", mac[5]);
}
-void dump_eeprom (void)
+void dump_eeprom (struct eth_device *dev)
{
int j, k;
@@ -307,7 +313,8 @@
if ((k == 2) || (k == 3))
printf (" ");
for (j = 0; j < 0x20; j += 4) {
- printf ("%02x:%04x ", j + k, read_eeprom_reg (j + k));
+ printf ("%02x:%04x ", j + k,
+ read_eeprom_reg (dev, j + k));
}
printf ("\n");
}
@@ -315,46 +322,47 @@
for (j = 0x20; j < 0x40; j++) {
if ((j & 0x07) == 0)
printf ("\n");
- printf ("%02x:%04x ", j, read_eeprom_reg (j));
+ printf ("%02x:%04x ", j, read_eeprom_reg (dev, j));
}
printf ("\n");
}
-int read_eeprom_reg (int reg)
+int read_eeprom_reg (struct eth_device *dev, int reg)
{
int timeout;
- SMC_SELECT_BANK (2);
- SMC_outw (reg, PTR_REG);
+ SMC_SELECT_BANK (dev, 2);
+ SMC_outw (dev, reg, PTR_REG);
- SMC_SELECT_BANK (1);
- SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
- CTL_REG);
+ SMC_SELECT_BANK (dev, 1);
+ SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
+ CTL_RELOAD, CTL_REG);
timeout = 100;
- while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+ while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay (100);
if (timeout == 0) {
printf ("Timeout Reading EEPROM register %02x\n", reg);
return 0;
}
- return SMC_inw (GP_REG);
+ return SMC_inw (dev, GP_REG);
}
-int write_eeprom_reg (int value, int reg)
+int write_eeprom_reg (struct eth_device *dev, int value, int reg)
{
int timeout;
- SMC_SELECT_BANK (2);
- SMC_outw (reg, PTR_REG);
+ SMC_SELECT_BANK (dev, 2);
+ SMC_outw (dev, reg, PTR_REG);
- SMC_SELECT_BANK (1);
- SMC_outw (value, GP_REG);
- SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+ SMC_SELECT_BANK (dev, 1);
+ SMC_outw (dev, value, GP_REG);
+ SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
+ CTL_STORE, CTL_REG);
timeout = 100;
- while ((SMC_inw (CTL_REG) & CTL_STORE) && --timeout)
+ while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
if (timeout == 0) {
printf ("Timeout Writing EEPROM register %02x\n", reg);
@@ -365,7 +373,7 @@
}
-void dump_reg (void)
+void dump_reg (struct eth_device *dev)
{
int i, j;
@@ -377,8 +385,8 @@
for (i = 0; i < 0xF; i += 2) {
printf ("%02x ", i);
for (j = 0; j < 4; j++) {
- SMC_SELECT_BANK (j);
- printf ("%04x ", SMC_inw (i));
+ SMC_SELECT_BANK (dev, j);
+ printf ("%04x ", SMC_inw (dev, i));
}
printf ("\n");
}
diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h
index f0e772c..070657f 100644
--- a/include/4xx_i2c.h
+++ b/include/4xx_i2c.h
@@ -63,7 +63,7 @@
#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index 79cdd80..bdc6ff2 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -347,6 +347,16 @@
#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF
/*
+ * DDR Memory Controller Configuration settings
+ */
+typedef struct ddr512x_config {
+ u32 ddr_sys_config; /* System Configuration Register */
+ u32 ddr_time_config0; /* Timing Configuration Register */
+ u32 ddr_time_config1; /* Timing Configuration Register */
+ u32 ddr_time_config2; /* Timing Configuration Register */
+} ddr512x_config_t;
+
+/*
* DMA/Messaging Unit
*/
typedef struct dma512x {
diff --git a/include/asm-ppc/mpc512x.h b/include/asm-ppc/mpc512x.h
index 8ef0d9c..960e229 100644
--- a/include/asm-ppc/mpc512x.h
+++ b/include/asm-ppc/mpc512x.h
@@ -50,7 +50,8 @@
/*
* Prototypes
*/
-extern long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz);
+extern long int fixed_sdram(ddr512x_config_t *mddrc_config,
+ u32 *dram_init_seq, int seq_sz);
extern int mpc5121_diu_init(void);
extern void ide_set_reset(int idereset);
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index b6182d4..92be514 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -117,6 +117,7 @@
#define SDRAM_MCSTS_MRSC 0x80000000
#define SDRAM_MCSTS_SRMS 0x40000000
#define SDRAM_MCSTS_CIS 0x20000000
+#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */
/*
* SDRAM Refresh Timer Register
@@ -416,8 +417,7 @@
#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
#define SDRAM_MMODE 0x88 /* memory mode */
#define SDRAM_MEMODE 0x89 /* memory extended mode */
-#define SDRAM_ECCCR 0x98 /* ECC error status */
-#define SDRAM_ECCES SDRAM_ECCCR
+#define SDRAM_ECCES 0x98 /* ECC error status */
#define SDRAM_CID 0xA4 /* core ID */
#ifndef CONFIG_405EX
#define SDRAM_RID 0xA8 /* revision ID */
@@ -1397,7 +1397,6 @@
/*
* Prototypes
*/
-void inline blank_string(int size);
inline void ppc4xx_ibm_ddr2_register_dump(void);
u32 mfdcr_any(u32);
void mtdcr_any(u32, u32);
@@ -1405,6 +1404,8 @@
u32 ddr_clktr(u32);
void spd_ddr_init_hang(void);
u32 DQS_autocalibration(void);
+phys_size_t sdram_memsize(void);
+void dcbz_area(u32 start_address, u32 num_bytes);
#endif /* __ASSEMBLY__ */
#endif /* _PPC4xx_SDRAM_H_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index d009957..f61778f 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -863,14 +863,16 @@
#define PVR_405EP_RA 0x51210950
#define PVR_405GPR_RB 0x50910951
#define PVR_405EZ_RA 0x41511460
-#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */
#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
-#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */
#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
+#define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */
+#define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */
+#define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */
+#define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
index 8941e4d..61d8e20 100644
--- a/include/configs/EP1C20.h
+++ b/include/configs/EP1C20.h
@@ -151,7 +151,8 @@
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
index 53bd0d8..41e64e6 100644
--- a/include/configs/EP1S10.h
+++ b/include/configs/EP1S10.h
@@ -145,7 +145,8 @@
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
index 9e9a8a4..5b332e4 100644
--- a/include/configs/EP1S40.h
+++ b/include/configs/EP1S40.h
@@ -145,7 +145,8 @@
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index 3853574..6083892 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -50,7 +50,8 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0xB0000000)
/* MEMORY */
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index 522349f..cf6f7a9 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -151,7 +151,8 @@
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 012ae79..d6e2f6b 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -215,7 +215,6 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index a4336a7..2154c78 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -540,6 +540,8 @@
* 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
* Extended POST test is not available.
* Use for STK52xx, FO300 and CAM5200 boards.
+ * WARNING: When the extended POST is enabled, these bits will
+ * be overridden by this code as GPIOs!
* use PCI_DIS: Bit 16 (mask 0x00008000):
* 1 -> disable PCI controller (on CAM5200 board).
* use USB: Bits 18-19 (mask 0x00003000):
@@ -552,7 +554,7 @@
* 000 -> All PSC2 pins are GPIOs.
* 100 -> UART (on CAM5200 board).
* 001 -> CAN1/2 on PSC2 pins.
- * Use for REV100 STK52xx boards
+ * Use for REV100 STK52xx boards
* 01x -> Use AC97 (on FO300 board).
* use PSC1: Bits 29-31 (mask: 0x00000007):
* 100 -> UART (on all boards).
@@ -711,20 +713,20 @@
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
-/* Offset for data I/O */
+/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
-/* Offset for normal register accesses */
+/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
-/* Offset for alternate registers */
+/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
-/* Interval between registers */
+/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
/* Support ATAPI devices */
-#define CONFIG_ATAPI 1
+#define CONFIG_ATAPI 1
/*-----------------------------------------------------------------------
* Open firmware flat tree support
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index f896cb0..c80ddca 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -65,12 +65,14 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20310300
#define SMC91111_EEPROM_INIT() \
do { \
- *pFIO_DIR |= PF1; \
- *pFIO_FLAG_S = PF1; \
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
+ bfin_write_FIO_FLAG_C(PF1); \
+ bfin_write_FIO_FLAG_S(PF0); \
SSYNC(); \
} while (0)
#define CONFIG_HOSTNAME bf533-ezkit
@@ -85,7 +87,7 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 3
#define CONFIG_SYS_MAX_FLASH_SECT 40
#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR 0x20020000
+#define CONFIG_ENV_ADDR 0x20030000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define FLASH_TOT_SECT 40
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 4be2a5c..0006b02 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -60,12 +60,14 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20300300
#define SMC91111_EEPROM_INIT() \
do { \
- *pFIO_DIR |= PF1; \
- *pFIO_FLAG_S = PF1; \
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
+ bfin_write_FIO_FLAG_C(PF1); \
+ bfin_write_FIO_FLAG_S(PF0); \
SSYNC(); \
} while (0)
#define CONFIG_HOSTNAME bf533-stamp
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 535687f..c4d899d 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -60,7 +60,8 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20310300
#define CONFIG_HOSTNAME bf538f-ezkit
/* Uncomment next line to use fixed MAC address */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 4779a97..a1fa80b 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -60,7 +60,8 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x2C010300
#define CONFIG_SMC_USE_32_BIT 1
#define CONFIG_HOSTNAME bf561-ezkit
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 00bfc6e..0b87418 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -138,7 +138,7 @@
"uart" MK_STR(CONFIG_UART_CONSOLE) "," \
MK_STR(CONFIG_BAUDRATE) " " \
CONFIG_BOOTARGS_VIDEO \
- "console=ttyBF0," MK_STR(CONFIG_BAUDRATE)
+ "console=ttyBF" MK_STR(CONFIG_UART_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
#if defined(CONFIG_CMD_NAND)
# define NAND_ENV_SETTINGS \
"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index 887f3fb..aa33933 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -30,7 +30,8 @@
/*
* Board settings
*/
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20300300
/* FLASH/ETHERNET uses the same address range
@@ -69,7 +70,7 @@
* Network settings
*/
-#ifdef CONFIG_DRIVER_SMC91111
+#ifdef CONFIG_SMC91111
#define CONFIG_IPADDR 192.168.0.15
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_GATEWAYIP 192.168.0.1
@@ -108,7 +109,7 @@
#include <config_cmd_default.h>
-#ifdef CONFIG_DRIVER_SMC91111
+#ifdef CONFIG_SMC91111
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
#else
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index b924758..477b94a 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -53,7 +53,8 @@
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#define CONFIG_SMC_USE_32_BIT
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
index ea548e9..06eb288 100644
--- a/include/configs/cm-bf533.h
+++ b/include/configs/cm-bf533.h
@@ -60,7 +60,8 @@
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20200300
#define CONFIG_HOSTNAME cm-bf533
/* Uncomment next line to use fixed MAC address */
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index 59dc8d2..4a77435 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -61,7 +61,8 @@
*/
#define ADI_CMDS_NETWORK 1
/* The next 2 lines are for use with DEV-BF5xx */
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x28000300
/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */
/* #define CONFIG_DRIVER_SMC911X 1 */
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index b150c22..200b61e 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -49,7 +49,8 @@
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x10000300
#define CONFIG_SMC91111_EXT_PHY
#define CONFIG_SMC_USE_32_BIT
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
index b6cfc67..e48e20f 100644
--- a/include/configs/dnp1110.h
+++ b/include/configs/dnp1110.h
@@ -54,7 +54,8 @@
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x20000300
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index bbe635b..d188439 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -292,7 +292,8 @@
/*
* Ethernet configuration uses on board SMC91C111
*/
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 7b0a08f..3a568ff 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -267,7 +267,8 @@
#ifndef USE_GRETH
/* USE SMC91C111 MAC */
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index ed03ad3..9cb0d42 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -157,7 +157,8 @@
/*
* SMSC91C111 Network Card
*/
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index e38d569..caafc93 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -53,7 +53,8 @@
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC91111_BASE 0xC8000000
#undef CONFIG_SMC91111_EXT_PHY
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
index 5b903f0..0535ee1 100644
--- a/include/configs/logodl.h
+++ b/include/configs/logodl.h
@@ -133,7 +133,8 @@
* SMSC91C111 Network Card
*/
#if 0
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */
#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h
index 6145c37..5f57c3a 100644
--- a/include/configs/lpd7a400-10.h
+++ b/include/configs/lpd7a400-10.h
@@ -72,7 +72,8 @@
* Default IO base of chip is 0x300, Card Engine has this address lines
* (LAN chip) tied to Vcc, so we just care about the chip select
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC_USE_IOFUNCS
diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h
index ce23f3d..9074e28 100644
--- a/include/configs/lpd7a404-10.h
+++ b/include/configs/lpd7a404-10.h
@@ -72,7 +72,8 @@
* Default IO base of chip is 0x300, Card Engine has this address lines
* (LAN chip) tied to Vcc, so we just care about the chip select
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC_USE_IOFUNCS
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 6755af3..0251428 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -48,7 +48,8 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0xB8000000)
/* MEMORY */
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index f0b4207..7bddf24 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -93,7 +93,8 @@
#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h
index 027e8e1..a00c2fb 100644
--- a/include/configs/nhk8815.h
+++ b/include/configs/nhk8815.h
@@ -132,7 +132,8 @@
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111*/
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111*/
#define CONFIG_SMC91111_BASE 0x34000300
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 2cae8ca..6c1defc 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -87,7 +87,8 @@
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
#define CONFIG_SMC_USE_32_BIT 1
/* #define CONFIG_SMC_USE_IOFUNCS */
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
index a9b70cc..4273b84 100644
--- a/include/configs/versatile.h
+++ b/include/configs/versatile.h
@@ -82,7 +82,8 @@
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC91111_BASE 0x10010000
#undef CONFIG_SMC91111_EXT_PHY
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index c9c3132..0dde65d 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -94,7 +94,8 @@
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x08000300
#define CONFIG_HARD_I2C
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 83883f6..1329f0f 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -196,7 +196,8 @@
/*
* SMSC91C111 Network Card
*/
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */
#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index f18701a..cd56ce7 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -50,7 +50,8 @@
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#undef CONFIG_SMC91111_EXT_PHY
#define CONFIG_SMC_USE_32_BIT
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
index 2697cca..f68461b 100644
--- a/include/configs/xsengine.h
+++ b/include/configs/xsengine.h
@@ -94,7 +94,8 @@
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/* Hardware drivers */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#define CONFIG_SMC_USE_32_BIT 1
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 86b6ea1..36c341e 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -62,7 +62,7 @@
#undef TURN_ON_ETHERNET
#ifdef TURN_ON_ETHERNET
-# define CONFIG_DRIVER_SMC91111 1
+# define CONFIG_SMC91111 1
# define CONFIG_SMC91111_BASE 0x14000300
# define CONFIG_SMC91111_EXT_PHY
# define CONFIG_SMC_USE_32_BIT
diff --git a/include/net.h b/include/net.h
index 4873000..1c8ab12 100644
--- a/include/net.h
+++ b/include/net.h
@@ -517,6 +517,9 @@
/* copy a filename (allow for "..." notation, limit length) */
extern void copy_filename (char *dst, char *src, int size);
+/* get a random source port */
+extern unsigned int random_port(void);
+
/**********************************************************************/
#endif /* __NET_H__ */
diff --git a/include/netdev.h b/include/netdev.h
index a50ec67..a91368e 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -75,6 +75,7 @@
int scc_initialize(bd_t *bis);
int skge_initialize(bd_t *bis);
int smc911x_initialize(u8 dev_num, int base_addr);
+int smc91111_initialize(u8 dev_num, int base_addr);
int tsi108_eth_initialize(bd_t *bis);
int uec_initialize(int index);
int uec_standard_init(bd_t *bis);
diff --git a/include/ppc405.h b/include/ppc405.h
index 5e56897..508c77b 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -29,9 +29,9 @@
#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
#ifndef CONFIG_IOP480
-#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
+#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
#else
-#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */
+#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/
#endif
/******************************************************************************
@@ -71,10 +71,10 @@
* Decompression Controller
******************************************************************************/
#define DECOMP_DCR_BASE 0x14
-#define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
-#define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
+#define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
+#define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
/* values for kiar register - indirect addressing of these regs */
-#define KCONF 0x40 /* decompression core config register */
+#define KCONF 0x40 /* decompression core config register */
#endif
/******************************************************************************
@@ -85,61 +85,61 @@
#else
#define POWERMAN_DCR_BASE 0xb8
#endif
-#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */
-#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */
-#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */
+#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */
+#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */
+#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */
/******************************************************************************
* Extrnal Bus Controller
******************************************************************************/
/* values for EBC0_CFGADDR register - indirect addressing of these regs */
- #define PB0CR 0x00 /* periph bank 0 config reg */
- #define PB1CR 0x01 /* periph bank 1 config reg */
- #define PB2CR 0x02 /* periph bank 2 config reg */
- #define PB3CR 0x03 /* periph bank 3 config reg */
- #define PB4CR 0x04 /* periph bank 4 config reg */
+ #define PB0CR 0x00 /* periph bank 0 config reg */
+ #define PB1CR 0x01 /* periph bank 1 config reg */
+ #define PB2CR 0x02 /* periph bank 2 config reg */
+ #define PB3CR 0x03 /* periph bank 3 config reg */
+ #define PB4CR 0x04 /* periph bank 4 config reg */
#ifndef CONFIG_405EP
- #define PB5CR 0x05 /* periph bank 5 config reg */
- #define PB6CR 0x06 /* periph bank 6 config reg */
- #define PB7CR 0x07 /* periph bank 7 config reg */
+ #define PB5CR 0x05 /* periph bank 5 config reg */
+ #define PB6CR 0x06 /* periph bank 6 config reg */
+ #define PB7CR 0x07 /* periph bank 7 config reg */
#endif
- #define PB0AP 0x10 /* periph bank 0 access parameters */
- #define PB1AP 0x11 /* periph bank 1 access parameters */
- #define PB2AP 0x12 /* periph bank 2 access parameters */
- #define PB3AP 0x13 /* periph bank 3 access parameters */
- #define PB4AP 0x14 /* periph bank 4 access parameters */
+ #define PB0AP 0x10 /* periph bank 0 access parameters */
+ #define PB1AP 0x11 /* periph bank 1 access parameters */
+ #define PB2AP 0x12 /* periph bank 2 access parameters */
+ #define PB3AP 0x13 /* periph bank 3 access parameters */
+ #define PB4AP 0x14 /* periph bank 4 access parameters */
#ifndef CONFIG_405EP
- #define PB5AP 0x15 /* periph bank 5 access parameters */
- #define PB6AP 0x16 /* periph bank 6 access parameters */
- #define PB7AP 0x17 /* periph bank 7 access parameters */
+ #define PB5AP 0x15 /* periph bank 5 access parameters */
+ #define PB6AP 0x16 /* periph bank 6 access parameters */
+ #define PB7AP 0x17 /* periph bank 7 access parameters */
#endif
- #define PBEAR 0x20 /* periph bus error addr reg */
- #define PBESR0 0x21 /* periph bus error status reg 0 */
- #define PBESR1 0x22 /* periph bus error status reg 1 */
-#define EBC0_CFG 0x23 /* external bus configuration reg */
+ #define PBEAR 0x20 /* periph bus error addr reg */
+ #define PBESR0 0x21 /* periph bus error status reg 0 */
+ #define PBESR1 0x22 /* periph bus error status reg 1 */
+#define EBC0_CFG 0x23 /* external bus configuration reg */
#ifdef CONFIG_405EP
/******************************************************************************
* Control
******************************************************************************/
#define CNTRL_DCR_BASE 0x0f0
-#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
-#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */
-#define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
-#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
-#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */
-#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */
+#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
+#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */
+#define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
+#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
+#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */
+#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */
-#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
-#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
-#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
-#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
-#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
-#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
-#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
-#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
+#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
+#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
+#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
+#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
+#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
+#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
+#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
+#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
+#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
+#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
/* Bit definitions */
#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
@@ -160,13 +160,13 @@
#define PLLMR0_OPB_PLB_DIV_3 0x00002000
#define PLLMR0_OPB_PLB_DIV_4 0x00003000
-#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
+#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
#define PLLMR0_EXB_PLB_DIV_2 0x00000000
#define PLLMR0_EXB_PLB_DIV_3 0x00000100
#define PLLMR0_EXB_PLB_DIV_4 0x00000200
#define PLLMR0_EXB_PLB_DIV_5 0x00000300
-#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
+#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
#define PLLMR0_MAL_PLB_DIV_1 0x00000000
#define PLLMR0_MAL_PLB_DIV_2 0x00000010
#define PLLMR0_MAL_PLB_DIV_3 0x00000020
@@ -180,7 +180,7 @@
#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
-#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
+#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
#define PLLMR1_FBMUL_DIV_16 0x00000000
#define PLLMR1_FBMUL_DIV_1 0x00100000
#define PLLMR1_FBMUL_DIV_2 0x00200000
@@ -198,7 +198,7 @@
#define PLLMR1_FBMUL_DIV_14 0x00E00000
#define PLLMR1_FBMUL_DIV_15 0x00F00000
-#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
+#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
#define PLLMR1_FWDVA_DIV_8 0x00000000
#define PLLMR1_FWDVA_DIV_7 0x00010000
#define PLLMR1_FWDVA_DIV_6 0x00020000
@@ -207,132 +207,132 @@
#define PLLMR1_FWDVA_DIV_3 0x00050000
#define PLLMR1_FWDVA_DIV_2 0x00060000
#define PLLMR1_FWDVA_DIV_1 0x00070000
-#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
-#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
+#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
+#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
/* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE 0x80000000
-#define CPC0_EPRCSR_E1NFE 0x40000000
-#define CPC0_EPRCSR_E1RPP 0x00000080
-#define CPC0_EPRCSR_E0RPP 0x00000040
-#define CPC0_EPRCSR_E1ERP 0x00000020
-#define CPC0_EPRCSR_E0ERP 0x00000010
-#define CPC0_EPRCSR_E1PCI 0x00000002
-#define CPC0_EPRCSR_E0PCI 0x00000001
+#define CPC0_EPRCSR_E0NFE 0x80000000
+#define CPC0_EPRCSR_E1NFE 0x40000000
+#define CPC0_EPRCSR_E1RPP 0x00000080
+#define CPC0_EPRCSR_E0RPP 0x00000040
+#define CPC0_EPRCSR_E1ERP 0x00000020
+#define CPC0_EPRCSR_E0ERP 0x00000010
+#define CPC0_EPRCSR_E1PCI 0x00000002
+#define CPC0_EPRCSR_E0PCI 0x00000001
/* Defines for CPC0_PCI Register */
-#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
-#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
-#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
+#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
+#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
+#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */
/* Defines for CPC0_BOOR Register */
-#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
+#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
- /* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
- /* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
- /* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
- /* PLL tune bits */
+#define PLL_ACTIVE 0x80000000
+#define CPC0_PLLMR1_SSCS 0x80000000
+#define PLL_RESET 0x40000000
+#define CPC0_PLLMR1_PLLR 0x40000000
+ /* Feedback multiplier */
+#define PLL_FBKDIV 0x00F00000
+#define CPC0_PLLMR1_FBDV 0x00F00000
+#define PLL_FBKDIV_16 0x00000000
+#define PLL_FBKDIV_1 0x00100000
+#define PLL_FBKDIV_2 0x00200000
+#define PLL_FBKDIV_3 0x00300000
+#define PLL_FBKDIV_4 0x00400000
+#define PLL_FBKDIV_5 0x00500000
+#define PLL_FBKDIV_6 0x00600000
+#define PLL_FBKDIV_7 0x00700000
+#define PLL_FBKDIV_8 0x00800000
+#define PLL_FBKDIV_9 0x00900000
+#define PLL_FBKDIV_10 0x00A00000
+#define PLL_FBKDIV_11 0x00B00000
+#define PLL_FBKDIV_12 0x00C00000
+#define PLL_FBKDIV_13 0x00D00000
+#define PLL_FBKDIV_14 0x00E00000
+#define PLL_FBKDIV_15 0x00F00000
+ /* Forward A divisor */
+#define PLL_FWDDIVA 0x00070000
+#define CPC0_PLLMR1_FWDVA 0x00070000
+#define PLL_FWDDIVA_8 0x00000000
+#define PLL_FWDDIVA_7 0x00010000
+#define PLL_FWDDIVA_6 0x00020000
+#define PLL_FWDDIVA_5 0x00030000
+#define PLL_FWDDIVA_4 0x00040000
+#define PLL_FWDDIVA_3 0x00050000
+#define PLL_FWDDIVA_2 0x00060000
+#define PLL_FWDDIVA_1 0x00070000
+ /* Forward B divisor */
+#define PLL_FWDDIVB 0x00007000
+#define CPC0_PLLMR1_FWDVB 0x00007000
+#define PLL_FWDDIVB_8 0x00000000
+#define PLL_FWDDIVB_7 0x00001000
+#define PLL_FWDDIVB_6 0x00002000
+#define PLL_FWDDIVB_5 0x00003000
+#define PLL_FWDDIVB_4 0x00004000
+#define PLL_FWDDIVB_3 0x00005000
+#define PLL_FWDDIVB_2 0x00006000
+#define PLL_FWDDIVB_1 0x00007000
+ /* PLL tune bits */
#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
+#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
+#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
+#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
+#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
+#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
+#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
+#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
/* Defines for CPC0_PLLMR0 Register fields */
- /* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
- /* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
- /* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
- /* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
- /* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
- /* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
+ /* CPU divisor */
+#define PLL_CPUDIV 0x00300000
+#define CPC0_PLLMR0_CCDV 0x00300000
+#define PLL_CPUDIV_1 0x00000000
+#define PLL_CPUDIV_2 0x00100000
+#define PLL_CPUDIV_3 0x00200000
+#define PLL_CPUDIV_4 0x00300000
+ /* PLB divisor */
+#define PLL_PLBDIV 0x00030000
+#define CPC0_PLLMR0_CBDV 0x00030000
+#define PLL_PLBDIV_1 0x00000000
+#define PLL_PLBDIV_2 0x00010000
+#define PLL_PLBDIV_3 0x00020000
+#define PLL_PLBDIV_4 0x00030000
+ /* OPB divisor */
+#define PLL_OPBDIV 0x00003000
+#define CPC0_PLLMR0_OPDV 0x00003000
+#define PLL_OPBDIV_1 0x00000000
+#define PLL_OPBDIV_2 0x00001000
+#define PLL_OPBDIV_3 0x00002000
+#define PLL_OPBDIV_4 0x00003000
+ /* EBC divisor */
+#define PLL_EXTBUSDIV 0x00000300
+#define CPC0_PLLMR0_EPDV 0x00000300
+#define PLL_EXTBUSDIV_2 0x00000000
+#define PLL_EXTBUSDIV_3 0x00000100
+#define PLL_EXTBUSDIV_4 0x00000200
+#define PLL_EXTBUSDIV_5 0x00000300
+ /* MAL divisor */
+#define PLL_MALDIV 0x00000030
+#define CPC0_PLLMR0_MPDV 0x00000030
+#define PLL_MALDIV_1 0x00000000
+#define PLL_MALDIV_2 0x00000010
+#define PLL_MALDIV_3 0x00000020
+#define PLL_MALDIV_4 0x00000030
+ /* PCI divisor */
+#define PLL_PCIDIV 0x00000003
+#define CPC0_PLLMR0_PPFD 0x00000003
+#define PLL_PCIDIV_1 0x00000000
+#define PLL_PCIDIV_2 0x00000001
+#define PLL_PCIDIV_3 0x00000002
+#define PLL_PCIDIV_4 0x00000003
/*
- *-------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
* assuming a 33.3MHz input clock to the 405EP.
- *-------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
*/
#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
@@ -427,25 +427,25 @@
#define CPC0_PERD1 0x0e1 /* CPR_PERD1 */
#define CPC0_PERC0 0x180 /* CPR_PERC0 */
-#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
-#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
-#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
+#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
+#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
+#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
+#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
-#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
-#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
+#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
+#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
+#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
-#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
-#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
-#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
-#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
+#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
+#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
+#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
+#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
-#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
-#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
-#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
-#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
+#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
+#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
+#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
+#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
#else /* #ifdef CONFIG_405EP */
/******************************************************************************
@@ -462,13 +462,13 @@
#define CPC0_ECR 0xaa /* edge conditioner register */
/* Bit definitions */
-#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
+#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
#define PLLMR_FWD_DIV_BYPASS 0xE0000000
#define PLLMR_FWD_DIV_3 0xA0000000
#define PLLMR_FWD_DIV_4 0x80000000
#define PLLMR_FWD_DIV_6 0x40000000
-#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
+#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
#define PLLMR_FB_DIV_1 0x02000000
#define PLLMR_FB_DIV_2 0x04000000
#define PLLMR_FB_DIV_3 0x06000000
@@ -476,32 +476,32 @@
#define PLLMR_TUNING_MASK 0x01F80000
-#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
+#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
#define PLLMR_CPU_PLB_DIV_1 0x00000000
#define PLLMR_CPU_PLB_DIV_2 0x00020000
#define PLLMR_CPU_PLB_DIV_3 0x00040000
#define PLLMR_CPU_PLB_DIV_4 0x00060000
-#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
+#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
#define PLLMR_OPB_PLB_DIV_1 0x00000000
#define PLLMR_OPB_PLB_DIV_2 0x00008000
#define PLLMR_OPB_PLB_DIV_3 0x00010000
#define PLLMR_OPB_PLB_DIV_4 0x00018000
-#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
+#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
#define PLLMR_PCI_PLB_DIV_1 0x00000000
#define PLLMR_PCI_PLB_DIV_2 0x00002000
#define PLLMR_PCI_PLB_DIV_3 0x00004000
#define PLLMR_PCI_PLB_DIV_4 0x00006000
-#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
+#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
#define PLLMR_EXB_PLB_DIV_2 0x00000000
#define PLLMR_EXB_PLB_DIV_3 0x00000800
#define PLLMR_EXB_PLB_DIV_4 0x00001000
#define PLLMR_EXB_PLB_DIV_5 0x00001800
/* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
+#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
#define PSR_PLL_FWD_MASK 0xC0000000
#define PSR_PLL_FDBACK_MASK 0x30000000
@@ -513,15 +513,15 @@
#define PSR_ROM_WIDTH_MASK 0x00018000
#define PSR_ROM_LOC 0x00004000
#define PSR_PCI_ASYNC_EN 0x00001000
-#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
+#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
#define PSR_PCI_ARBIT_EN 0x00000400
-#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
+#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
#ifndef CONFIG_IOP480
/*
* PLL Voltage Controlled Oscillator (VCO) definitions
* Maximum and minimum values (in MHz) for correct PLL operation.
- */
+*/
#define VCO_MIN 400
#define VCO_MAX 800
#endif /* #ifndef CONFIG_IOP480 */
@@ -535,35 +535,35 @@
#else
#define MAL_DCR_BASE 0x180
#endif
-#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
-#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear)*/
-#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
-#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set)*/
-#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset)*/
-#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/
-#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */
-#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
-#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
-#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/
-#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */
-#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */
-#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */
-#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */
-#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */
-#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */
-#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */
-#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */
-#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */
-#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */
-#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */
-#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */
-#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */
-#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */
-#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */
-#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */
-#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */
-#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
-#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
+#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
+#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear) */
+#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
+#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
+#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
+#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */
+#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */
+#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
+#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
+#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */
+#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */
+#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */
+#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */
+#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */
+#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */
+#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */
+#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */
+#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */
+#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */
+#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */
+#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */
+#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */
+#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */
+#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */
+#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */
+#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */
+#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */
+#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
+#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
/*-----------------------------------------------------------------------------
| IIC Register Offsets
@@ -578,7 +578,7 @@
#define IICEXTSTS 0x09
#define IICLSADR 0x0A
#define IICHSADR 0x0B
-#define IICCLKDIV 0x0C
+#define IIC0_CLKDIV 0x0C
#define IICINTRMSK 0x0D
#define IICXFRCNT 0x0E
#define IICXTCNTLSS 0x0F
@@ -610,7 +610,7 @@
#define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */
#define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */
#define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */
-#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk*/
+#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk */
#else
#define OCM_DCR_BASE 0x018
#define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
@@ -746,21 +746,21 @@
#define SDR0_MFR 0x4300 /* SDR0_MFR reg */
/* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE 0x80000000
-#define CPC0_EPRCSR_E1NFE 0x40000000
-#define CPC0_EPRCSR_E1RPP 0x00000080
-#define CPC0_EPRCSR_E0RPP 0x00000040
-#define CPC0_EPRCSR_E1ERP 0x00000020
-#define CPC0_EPRCSR_E0ERP 0x00000010
-#define CPC0_EPRCSR_E1PCI 0x00000002
-#define CPC0_EPRCSR_E0PCI 0x00000001
+#define CPC0_EPRCSR_E0NFE 0x80000000
+#define CPC0_EPRCSR_E1NFE 0x40000000
+#define CPC0_EPRCSR_E1RPP 0x00000080
+#define CPC0_EPRCSR_E0RPP 0x00000040
+#define CPC0_EPRCSR_E1ERP 0x00000020
+#define CPC0_EPRCSR_E0ERP 0x00000010
+#define CPC0_EPRCSR_E1PCI 0x00000002
+#define CPC0_EPRCSR_E0PCI 0x00000001
#define CPR0_CLKUPD 0x020
#define CPR0_PLLC 0x040
#define CPR0_PLLD 0x060
#define CPR0_CPUD 0x080
#define CPR0_PLBD 0x0a0
-#define CPR0_OPBD 0x0c0
+#define CPR0_OPBD0 0x0c0
#define CPR0_PERD 0x0e0
#define SDR0_PINSTP 0x0040
@@ -770,46 +770,46 @@
/* CUST0 Customer Configuration Register0 */
#define SDR0_CUST0 0x4000
-#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
+#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
+#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
+#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
+#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
-#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
+#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
+#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
+#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
-#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
+#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
+#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */
+#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */
-#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
+#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
-#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
+#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
+#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
-#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
+#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
-#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
+#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
-#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
-#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
+#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
+#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
+#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
-#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Sel Gating Mask */
+#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Sel Gating Disable */
+#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Sel Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Sel0 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Sel1 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Sel2 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Sel3 Gating Enable */
#define SDR0_PFC0 0x4100
#define SDR0_PFC1 0x4101
diff --git a/include/ppc440.h b/include/ppc440.h
index 378a9de..fe0db93 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -48,7 +48,7 @@
#ifndef __PPC440_H__
#define __PPC440_H__
-#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
+#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
/******************************************************************************
* DCRs & Related
@@ -60,9 +60,9 @@
/* values for clkcfga register - indirect addressing of these regs */
#define CPR0_PLLC 0x0040
#define CPR0_PLLD 0x0060
-#define CPR0_PRIMAD 0x0080
-#define CPR0_PRIMBD 0x00a0
-#define CPR0_OPBD 0x00c0
+#define CPR0_PRIMAD0 0x0080
+#define CPR0_PRIMBD0 0x00a0
+#define CPR0_OPBD0 0x00c0
#define CPR0_PERD 0x00e0
#define CPR0_MALD 0x0100
#define CPR0_SPCID 0x0120
@@ -86,8 +86,8 @@
#define SDR0_XPLLC 0x01c1
#define SDR0_XPLLD 0x01c2
#define SDR0_SRST 0x0200
-#define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
-#define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
+#define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
+#define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_PCI0 0x01c0
#else
@@ -100,7 +100,7 @@
#define SDR0_PFC1 0x4101 /* Pin Function 1 */
#define SDR0_MFR 0x4300 /* SDR0_MFR reg */
-#ifdef CONFIG_440GX
+#if defined(CONFIG_440GX)
#define SD0_AMP 0x0240
#define SDR0_XPLLC 0x01c1
#define SDR0_XPLLD 0x01c2
@@ -145,10 +145,10 @@
#define SDR0_XCR2 0x01c6
#define SDR0_XPLLC0 0x01c1
#define SDR0_XPLLD0 0x01c2
-#define SDR0_XPLLC1 0x01c4 /*notRCW - SG */
-#define SDR0_XPLLD1 0x01c5 /*notRCW - SG */
-#define SDR0_XPLLC2 0x01c7 /*notRCW - SG */
-#define SDR0_XPLLD2 0x01c8 /*notRCW - SG */
+#define SDR0_XPLLC1 0x01c4 /* notRCW - SG */
+#define SDR0_XPLLD1 0x01c5 /* notRCW - SG */
+#define SDR0_XPLLC2 0x01c7 /* notRCW - SG */
+#define SDR0_XPLLD2 0x01c8 /* dnotRCW - SG */
#define SD0_AMP0 0x0240
#define SD0_AMP1 0x0241
#define SDR0_CUST2 0x4004
@@ -187,80 +187,91 @@
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-/* PLB3 Arbiter */
+ /* PLB3 Arbiter */
#define PLB3_DCR_BASE 0x070
#define PLB3_ACR (PLB3_DCR_BASE + 0x7)
-/* PLB4 Arbiter - PowerPC440EP Pass1 */
+ /* PLB4 Arbiter - PowerPC440EP Pass1 */
#define PLB4_DCR_BASE 0x080
#define PLB4_ACR (PLB4_DCR_BASE + 0x1)
#define PLB4_ACR_WRP (0x80000000 >> 7)
-/* Pin Function Control Register 1 */
+ /* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
-#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
-#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
-#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
-#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
-#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
-#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
-#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
-#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
-#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
-#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
-#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
-#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
-#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
-#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
-#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
-#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
-#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
-#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
-#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
-#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
-#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
-#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
-#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
-#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
+#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
+#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold
+ Req Selection */
+#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
+ Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
+ Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En.
+ Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
+ Selection */
+#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
+ Disable */
+#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
+ Enable */
-#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
-#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
-#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
-#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
+#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
+ Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor
+ Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor
+ Enable */
+#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
+ Gated In */
-/* USB Control Register */
+ /* USB Control Register */
#define SDR0_USB0 0x0320
-#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
-#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
-#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
-#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
-#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
-#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
+#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
+#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
+#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
+#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
+#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
+#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
-/* Miscealleneaous Function Reg. */
+ /* Miscealleneaous Function Reg. */
#define SDR0_MFR 0x4300
-#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
-#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
-#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
-#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
-#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
-#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
-#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
-#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
-#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
-#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
-#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
-#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
+#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
+#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
+#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
+#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
+#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
-#define SDR0_MFR_ERRATA3_EN0 0x00800000
-#define SDR0_MFR_ERRATA3_EN1 0x00400000
-#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
-#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
-#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
-#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
-#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
+#define SDR0_MFR_ERRATA3_EN0 0x00800000
+#define SDR0_MFR_ERRATA3_EN1 0x00400000
+#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
#define GPT0_COMP6 0x00000098
#define GPT0_COMP5 0x00000094
@@ -278,245 +289,296 @@
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_USB2D0CR 0x0320
-#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
-#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
-#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
+#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC
+ Master Selection */
+#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/
+#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
-#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
-#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
-#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
+#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface
+ Selection */
+#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
+#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
-#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
-#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
-#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
+#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
+#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
+#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
-/* USB2 Host Control Register */
-#define SDR0_USB2H0CR 0x0340
-#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
-#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
-#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
-#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
+ /* USB2 Host Control Register */
+#define SDR0_USB2H0CR 0x0340
+#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/
+#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
+#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
+#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length
+ Adjustment */
-/* Pin Function Control Register 1 */
-#define SDR0_PFC1 0x4101
-#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
-#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
-#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
+ /* Pin Function Control Register 1 */
+#define SDR0_PFC1 0x4101
+#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
-#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
-#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
-#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
-#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
-#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
-#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
-#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
-#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
+#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select
+ EMAC 0 */
+#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII
+ bridge */
+#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII
+ bridge */
+#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII
+ bridge */
+#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII
+ bridge */
+#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII
+ bridge */
+#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII
+ bridge */
+#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII
+ bridge */
-#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
-#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
-#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
-#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
-#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
-#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
-#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
-#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
-#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
-#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
-#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
-#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
-#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
-#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
-#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
-#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
-#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
-#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
-#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
-#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
-#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
+#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req
+ Selection */
+#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
+ Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
+ Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
+ Selection */
+#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
+ Disable */
+#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
+ Enable */
-#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
-#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
-#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
-#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
+#define SDR0_PFC1_PLB_PME_MASK 0x00001000
+ /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000
+ /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000
+ /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
+ Gated In */
-/* Ethernet PLL Configuration Register */
-#define SDR0_PFC2 0x4102
-#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
-#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
-#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
-#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
+ /* Ethernet PLL Configuration Register */
+#define SDR0_PFC2 0x4102
+#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
+#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication
+ selector */
+#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
+#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
-#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
-#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
-#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
+#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
+#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
#define SDR0_PFC4 0x4104
-/* USB2PHY0 Control Register */
-#define SDR0_USB2PHY0CR 0x4103
-#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
-#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
-#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
+ /* USB2PHY0 Control Register */
+#define SDR0_USB2PHY0CR 0x4103
+#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000
-#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
-#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
-#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
+ /* PHY UTMI interface connection */
+#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
+#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
-#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
-#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
-#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
+#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
+#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
+#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
-#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
-#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
-#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
+#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000
+ /* VBus detect (Device mode only) */
+#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000
+ /* Pull-up resistance on D+ is disabled */
+#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000
+ /* Pull-up resistance on D+ is enabled */
-#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
-#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
-#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
+#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000
+ /* PHY UTMI data width and clock select */
+#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
+#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
-#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
-#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
-#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
+#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
+#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
+#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000
+ /* Loop back enabled (only test purposes) */
-#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
-#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
-#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
+#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000
+ /* Force XO block on during a suspend */
+#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
+#define SDR0_USB2PHY0CR_XO_OFF 0x04000000
+ /* PHY XO block is powered-off when all ports are suspended */
-#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
-#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
-#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
+#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
+#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
+#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only
+ for full-speed operation */
-#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
-#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
-#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
+#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock
+ source */
+#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal
+ 48M clock as a reference */
+#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO
+ block output as a reference */
-#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
-#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
-#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
-#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
+#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO
+ block*/
+#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external
+ clock */
+#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock
+ from a crystal */
-/* Miscealleneaous Function Reg. */
-#define SDR0_MFR 0x4300
-#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
-#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
-#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
-#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
-#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
-#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
-#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
-#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
-#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
-#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
+#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
+#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq
+ = 12 MHz */
+#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq
+ = 48 MHz */
+#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq
+ = 24 MHz */
-#define SDR0_MFR_ERRATA3_EN0 0x00800000
-#define SDR0_MFR_ERRATA3_EN1 0x00400000
-#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
-#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
-#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
-#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
-#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
+ /* Miscealleneaous Function Reg. */
+#define SDR0_MFR 0x4300
+#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
+#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
+#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
+
+#define SDR0_MFR_ERRATA3_EN0 0x00800000
+#define SDR0_MFR_ERRATA3_EN1 0x00400000
+#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
-/* CUST1 Customer Configuration Register1 */
-#define SDR0_CUST1 0x4002
-#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
-#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
-#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
+ /* CUST1 Customer Configuration Register1 */
+#define SDR0_CUST1 0x4002
+#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
+#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
+#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
-/* Pin Function Control Register 0 */
-#define SDR0_PFC0 0x4100
-#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
-#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
-#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
-#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
-#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
+ /* Pin Function Control Register 0 */
+#define SDR0_PFC0 0x4100
+#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
+#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
+#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
+#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
+#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
-/* Pin Function Control Register 1 */
-#define SDR0_PFC1 0x4101
-#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
-#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
-#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
-#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
-#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
-#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
-#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
-#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
-#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
-#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
-#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
-#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
-#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
-#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
-#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
-#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
-#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
-#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
-#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
-#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
-#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
-#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
-#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
-#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
+ /* Pin Function Control Register 1 */
+#define SDR0_PFC1 0x4101
+#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
+#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req
+ Selection */
+#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
+ Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
+ Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
+ Selection */
+#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
+ Disable */
+#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
+ Enable */
-#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
-#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
-#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
-#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
+#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En.
+ Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor
+ Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor
+ Enable */
+#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
+ Gated In */
#endif /* 440EP || 440GR || 440EPX || 440GRX */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0 0x4000
-#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
+ /* CUST0 Customer Configuration Register0 */
+#define SDR0_CUST0 0x4000
+#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
+#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
+#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
+#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
-#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
+#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
+#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
+#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
-#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
+#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
+#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
+#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
-#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
+#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
-#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
+#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
+#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
-#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
+#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
+#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
-#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
+#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
+#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
+#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
-#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
-#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
+#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
+#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
+#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
-#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
+#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
+#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/
+#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
+#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
#endif
/*-----------------------------------------------------------------------------
@@ -534,16 +596,16 @@
#define CNTRL_DCR_BASE 0x0b0
#endif
-#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
-#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
+#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
+#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
-#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
-#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
+#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
+#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
-#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
+#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
-#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
+#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
+#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
/*-----------------------------------------------------------------------------
| DMA
@@ -572,12 +634,12 @@
#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
-#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */
+#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/
#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */
#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/
#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
-#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */
+#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/
#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */
#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */
#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */
@@ -658,7 +720,7 @@
#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
-#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
+#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
@@ -732,8 +794,8 @@
#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
-#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
-#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
+#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
+#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
#define SDR0_SDSTP1_ETH_MASK 0x00000004
#define SDR0_SDSTP1_ETH_10_100 0x00000000
#define SDR0_SDSTP1_ETH_GIGA 0x00000004
@@ -816,10 +878,14 @@
#define SDR0_PINSTP 0x0040
#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
-#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
-#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
-#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
-#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
+#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0
+ (EBC boot) */
+#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1
+ (PCI boot) */
+#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled -
+ Addr = 0x54 */
+#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled -
+ Addr = 0x50 */
#define SDR0_SDCS 0x0060
#define SDR0_ECID0 0x0080
#define SDR0_ECID1 0x0081
@@ -960,8 +1026,10 @@
#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
#define SDR0_PFC1_CPU_NO_TRACE 0x00000000
#define SDR0_PFC1_CPU_TRACE 0x00080000
-#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
-#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
+#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19)
+ /* $218C */
+#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03)
+ /* $218C */
#define SDR0_MFR 0x4300
#endif /* CONFIG_440SPE */
@@ -1023,34 +1091,43 @@
/* Ethernet Configuration Register (SDR0_ETH_CFG) */
#define SDR0_ETH_CFG 0x4103
-#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */
-#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */
-#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */
-#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */
-#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */
-#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */
-#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */
-#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */
-#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */
-#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */
-#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */
-#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */
-#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */
-#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */
-#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */
-#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */
-#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */
-#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */
-#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */
-#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */
-#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */
-#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */
-#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */
-#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */
-#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */
+#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /*SGMII3 port loopback
+ enable */
+#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /*SGMII2 port loopback
+ enable */
+#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /*SGMII1 port loopback
+ enable */
+#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /*SGMII0 port loopback
+ enable */
+#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /*SGMII Mask */
+#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /*SGMII2 port enable */
+#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /*SGMII1 port enable */
+#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /*SGMII0 port enable */
+#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /*TAHOE1 Bypass selector */
+#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /*TAHOE0 Bypass selector */
+#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /*EMAC 3 PHY clock selector*/
+#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /*EMAC 2 PHY clock selector*/
+#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /*EMAC 1 PHY clock selector*/
+#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /*EMAC 0 PHY clock selector*/
+#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /*Swap EMAC2 with EMAC1 */
+#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /*Swap EMAC0 with EMAC3 */
+#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /*MDIO source selector mask*/
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /*MDIO source - EMAC0 */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /*MDIO source - EMAC1 */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /*MDIO source - EMAC2 */
+#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /*MDIO source - EMAC3 */
+#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /*ZMII bridge mode selector
+ mask */
+#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /*ZMII bridge mode - MII */
+#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /*ZMII bridge mode - SMII */
+#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /*ZMII bridge mode - RMII
+ (10 Mbps) */
+#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /*ZMII bridge mode - RMII
+ (100 Mbps) */
+#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /*GMC Port 1 bridge
+ selector */
+#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /*GMC Port 0 bridge
+ selector */
#define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4
#define SDR0_ETH_CFG_ZMII_MII_MODE 0x00
@@ -1063,26 +1140,46 @@
/* Miscealleneaous Function Reg. (SDR0_MFR) */
#define SDR0_MFR 0x4300
-#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
-#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */
-#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */
-#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */
-#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */
-#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */
-#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */
-#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */
-#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */
-#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */
-#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */
-#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */
-#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */
-#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */
-#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */
-#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */
-#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */
-#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */
-#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */
-#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */
+#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx
+ FIFO bits 0:63 */
+#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx
+ FIFO bits 64:127 */
+#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx
+ FIFO bits 0:63 */
+#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx
+ FIFO bits 64:127 */
+#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx
+ FIFO bits 0:63 */
+#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx
+ FIFO bits 64:127 */
+#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx
+ FIFO bits 0:63 */
+#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx
+ FIFO bits 64:127 */
+#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx
+ FIFO bits 0:63 */
+#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx
+ FIFO bits 64:127 */
+#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx
+ FIFO bits 0:63 */
+#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx
+ FIFO bits 64:127 */
+#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx
+ FIFO bits 0:63 */
+#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx
+ FIFO bits 64:127 */
+#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx
+ FIFO bits 0:63 */
+#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx
+ FIFO bits 64:127 */
+#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx
+ FIFO bits 0:63 */
+#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx
+ FIFO bits 64:127 */
+#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx
+ FIFO bits 0:63 */
+#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx
+ FIFO bits 64:127 */
/* EMACx TX Status Register (SDR0_EMACxTXST)*/
#define SDR0_EMAC0TXST 0x4400
@@ -1090,30 +1187,30 @@
#define SDR0_EMAC2TXST 0x4402
#define SDR0_EMAC3TXST 0x4403
-#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
-#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
-#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
-#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
-#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
-#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */
-#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
-#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
-#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
-#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
-#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
-#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
-#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
-#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
-#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
-#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
-#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
-#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
-#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
-#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
-#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
-#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
-#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
-#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
+#define SDR0_EMACxTXST_FUR 0x02000000 /*TX FIFO underrun */
+#define SDR0_EMACxTXST_BC 0x01000000 /*broadcase address */
+#define SDR0_EMACxTXST_MC 0x00800000 /*multicast address */
+#define SDR0_EMACxTXST_UC 0x00400000 /*unicast address */
+#define SDR0_EMACxTXST_FP 0x00200000 /*frame paused by control packet */
+#define SDR0_EMACxTXST_BFCS 0x00100000 /*bad FCS in the transmitted frame */
+#define SDR0_EMACxTXST_CPF 0x00080000 /*TX control pause frame */
+#define SDR0_EMACxTXST_CF 0x00040000 /*TX control frame */
+#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
+#define SDR0_EMACxTXST_1023 0x00010000 /*512-1023 bytes transmitted */
+#define SDR0_EMACxTXST_511 0x00008000 /*256-511 bytes transmitted */
+#define SDR0_EMACxTXST_255 0x00004000 /*128-255 bytes transmitted */
+#define SDR0_EMACxTXST_127 0x00002000 /*65-127 bytes transmitted */
+#define SDR0_EMACxTXST_64 0x00001000 /*64 bytes transmitted */
+#define SDR0_EMACxTXST_SQE 0x00000800 /*SQE indication */
+#define SDR0_EMACxTXST_LOC 0x00000400 /*loss of carrier sense */
+#define SDR0_EMACxTXST_IERR 0x00000080 /*EMAC internal error */
+#define SDR0_EMACxTXST_EDF 0x00000040 /*excessive deferral */
+#define SDR0_EMACxTXST_ECOL 0x00000020 /*excessive collisions */
+#define SDR0_EMACxTXST_LCOL 0x00000010 /*late collision */
+#define SDR0_EMACxTXST_DFFR 0x00000008 /*deferred frame */
+#define SDR0_EMACxTXST_MCOL 0x00000004 /*multiple collision frame */
+#define SDR0_EMACxTXST_SCOL 0x00000002 /*single collision frame */
+#define SDR0_EMACxTXST_TXOK 0x00000001 /*transmit OK */
/* EMACx RX Status Register (SDR0_EMACxRXST)*/
#define SDR0_EMAC0RXST 0x4404
@@ -1146,8 +1243,9 @@
#define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */
#define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */
#define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */
-#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */
-#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */
+#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal
+ EMAC receive error */
+#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */
#define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */
/* EMACx TX Status Register (SDR0_EMACxREJCNT)*/
@@ -1300,23 +1398,37 @@
#define SDR0_MFR_ECS_MASK 0x10000000
#define SDR0_MFR_ECS_INTERNAL 0x10000000
-#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
-#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
-#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
-#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
-#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
-#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
-#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
-#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
-#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
-#define SDR0_MFR_ERRATA3_EN0 0x00800000
-#define SDR0_MFR_ERRATA3_EN1 0x00400000
+#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
+#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs*/
+#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ERRATA3_EN0 0x00800000
+#define SDR0_MFR_ERRATA3_EN1 0x00400000
#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
-#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
-#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
-#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
-#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
-#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
+#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3
+ 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
+#endif
+
+
+#if defined(CONFIG_440EPX)
+#define CPM0_ER 0x000000B0
+#define CPM1_ER 0x000000F0
+#define PLB4A0_ACR 0x00000081
+#define PLB4A1_ACR 0x00000089
+#define PLB3A0_ACR 0x00000077
+#define OPB2PLB40_BCTRL 0x00000350
+#define P4P3BO0_CFG 0x00000026
+#define SPI0_MODE 0xEF600090 /* SPI Mode Regsgiter */
+
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -1330,61 +1442,74 @@
#define SDR0_MFR_ECS_INTERNAL 0x10000000
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define SDR0_SRST0 0x200
-#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
-#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
-#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
-#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
-#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
-#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
-#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
-#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
-#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
-#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
-#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
-#define SDR0_SRST0_PCI 0x00100000 /* PCI */
-#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
-#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
-#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
-#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
-#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
-#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
-#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
-#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
-#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
-#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
-#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
-#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
-#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
-#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
-#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
-#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
-#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
-#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
-#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
+#define SDR0_SRST0 0x200
+#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
+#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
+#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
+#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
+#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/
+ transmitter 0 */
+#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/
+ transmitter 1 */
+#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
+#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
+#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
+#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
+#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
+#define SDR0_SRST0_PCI 0x00100000 /* PCI */
+#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
+#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
+#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
+#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
+#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
+#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
+#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
+#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
+#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
+#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
+#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
+#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
+#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
+#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
+#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
+#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
+#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
+#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/
+ transmitter 2 */
+#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/
+ transmitter 3 */
-#define SDR0_SRST1 0x201
-#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
-#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
-#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
+#define SDR0_SRST1 0x201
+#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
+#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
+#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
-#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
-#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
-#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
-#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
-#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
-#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
-#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
-#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
-#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
-#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
-#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
-#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
-#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
-#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
-#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
-#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
+#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
+#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
+#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4
+ USB 2.0 Host */
+#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to
+ USB 2.0 Host */
+#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to
+ USB 2.0 Host */
+#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
+#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/
+#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
+#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
+#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
+#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
+#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
+#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
+#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
+#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
+#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
+#define SDR0_EMAC0RXST 0x00004301 /* */
+#define SDR0_EMAC0TXST 0x00004302 /* */
+#define SDR0_CRYP0 0x00004500
+#define SDR0_EBC0 0x00000100
+#define SDR0_SDSTP2 0x00004001
+#define SDR0_SDSTP3 0x00004001
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_SRST0 SDR0_SRST /* for compatability reasons */
@@ -1392,8 +1517,10 @@
#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
-#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
-#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
+#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/
+ transmitter 0 */
+#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/
+ transmitter 1 */
#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */
#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */
@@ -1408,11 +1535,13 @@
#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/
#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/
#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/
-#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */
+#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/
+ transmitter 2 */
#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */
-#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */
+#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/
+ transmitter 3 */
#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */
#define SDR0_SRST1 0x201
@@ -1421,17 +1550,22 @@
#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */
#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */
#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */
-#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */
-#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */
-#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */
-#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */
+#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access
+ controller 0 */
+#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access
+ controller 1 */
+#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access
+ controller 2 */
+#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access
+ controller 3 */
#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */
#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */
#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */
#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */
#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */
#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */
-#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */
+#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and
+ serdes */
#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */
#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */
#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */
@@ -1520,7 +1654,7 @@
#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
-#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
+#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
@@ -1528,7 +1662,7 @@
#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
-#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
+#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
@@ -1586,7 +1720,7 @@
#define IICEXTSTS 0x09
#define IICLSADR 0x0A
#define IICHSADR 0x0B
-#define IICCLKDIV 0x0C
+#define IIC0_CLKDIV 0x0C
#define IICINTRMSK 0x0D
#define IICXFRCNT 0x0E
#define IICXTCNTLSS 0x0F
@@ -1595,95 +1729,123 @@
/*-----------------------------------------------------------------------------
| PCI Internal Registers et. al. (accessed via plb)
+----------------------------------------------------------------------------*/
-#define PCIX0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
-#define PCIX0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
-#define PCIX0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
-#define PCIX0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
+#define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
+#define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
+#define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
+#define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* PCI Local Configuration Registers
--------------------------------- */
-#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
+#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
+ 0x0EF400000 */
/* PCI Master Local Configuration Registers */
-#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
-#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
-#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
-#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
-#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
-#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
-#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
-#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
-#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
-#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
-#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
-#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
+#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
+#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
+#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
+#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
+#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
+#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
+#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
+#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
+#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
+#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
+#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
+#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
/* PCI Target Local Configuration Registers */
-#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
-#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
-#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
-#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
+#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
+ Attribute */
+#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
+#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
+ Attribute */
+#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
#else
-#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
-#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
-#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
-#define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
-#define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
-#define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
-#define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
-#define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
-#define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
-#define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
-#define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
-#define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
-#define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
-#define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
-#define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
-#define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
-#define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
-#define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
-#define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
-#define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
-#define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
-#define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
-#define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
-#define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
-#define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
-#define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
-#define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
-#define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
+#define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID )
+#define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID )
+#define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND )
+#define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS )
+#define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID )
+#define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE)
+#define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
+#define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER )
+#define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE )
+#define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
+#define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
+#define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
+#define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
+#define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
+#define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
+#define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
+#define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS )
+#define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
+#define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
+#define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS )
+#define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
+#define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
+#define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
+#define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
+#define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
+#define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
+#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
+#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
+#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
+#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
+#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
+#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame*/
+#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
+#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
+#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
+#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
+#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
+#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
+#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
+#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
+#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
+#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
+#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
+#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
+#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
+#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
+#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
+#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
+#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
+#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
-#define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
-#define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
+#define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT )
+#define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT )
-#define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
-#define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
-#define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
-#define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
-#define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
-#define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
-#define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
-#define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
-#define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
-#define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
-#define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
+#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040)
+#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044)
-#define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
-#define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
-#define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
-#define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
-#define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
-#define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
-#define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
-#define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
-#define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
+#define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068)
+#define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c)
+#define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
+#define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074)
+#define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078)
+#define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c)
+#define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080)
+#define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
+#define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088)
+#define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c)
+#define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
-#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
+#define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
+#define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c)
+#define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0)
+#define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
+#define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8)
+#define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac)
+#define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
+#define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4)
+#define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8)
+
+#define PCIL0_STS (PCIL0_CFGBASE + 0x00e0)
#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
@@ -1694,24 +1856,41 @@
#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
-#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
-#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
-#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
-#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
-#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
-#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
-#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
-#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
-#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
-#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
+#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for
+ Endpoint 0 plus IN Endpoints 1 to 3 */
+#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management
+ register */
+#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address
+ register */
+#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable
+ register for USB2D0_INTRIN */
+#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for
+ OUT Endpoints 1 to 3 */
+#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable
+ register for USB2D0_INTRUSB */
+#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for
+ common USB interrupts */
+#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable
+ register for IntrOut */
+#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0
+ test modes */
+#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for
+ selecting the Endpoint status/control registers */
#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
-#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
-#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
-#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
-#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
+#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status
+ register for Endpoint 0. (Index register set to select Endpoint 0) */
+#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status
+ register for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet
+ size for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status
+ register for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet
+ size for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received
+ bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
+#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in
+ OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
#endif
/******************************************************************************
@@ -1720,55 +1899,55 @@
#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460SX)
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700)
+#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700)
-#define GPIO0_OR (GPIO0_BASE+0x0)
-#define GPIO0_TCR (GPIO0_BASE+0x4)
-#define GPIO0_ODR (GPIO0_BASE+0x18)
-#define GPIO0_IR (GPIO0_BASE+0x1C)
+#define GPIO0_OR (GPIO0_BASE+0x0)
+#define GPIO0_TCR (GPIO0_BASE+0x4)
+#define GPIO0_ODR (GPIO0_BASE+0x18)
+#define GPIO0_IR (GPIO0_BASE+0x1C)
#endif /* CONFIG_440GP */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00)
-#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00)
+#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00)
+#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00)
-#define GPIO0_OR (GPIO0_BASE+0x0)
-#define GPIO0_TCR (GPIO0_BASE+0x4)
-#define GPIO0_OSRL (GPIO0_BASE+0x8)
-#define GPIO0_OSRH (GPIO0_BASE+0xC)
-#define GPIO0_TSRL (GPIO0_BASE+0x10)
-#define GPIO0_TSRH (GPIO0_BASE+0x14)
-#define GPIO0_ODR (GPIO0_BASE+0x18)
-#define GPIO0_IR (GPIO0_BASE+0x1C)
-#define GPIO0_RR1 (GPIO0_BASE+0x20)
-#define GPIO0_RR2 (GPIO0_BASE+0x24)
-#define GPIO0_RR3 (GPIO0_BASE+0x28)
-#define GPIO0_ISR1L (GPIO0_BASE+0x30)
-#define GPIO0_ISR1H (GPIO0_BASE+0x34)
-#define GPIO0_ISR2L (GPIO0_BASE+0x38)
-#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
-#define GPIO0_ISR3L (GPIO0_BASE+0x40)
-#define GPIO0_ISR3H (GPIO0_BASE+0x44)
+#define GPIO0_OR (GPIO0_BASE+0x0)
+#define GPIO0_TCR (GPIO0_BASE+0x4)
+#define GPIO0_OSRL (GPIO0_BASE+0x8)
+#define GPIO0_OSRH (GPIO0_BASE+0xC)
+#define GPIO0_TSRL (GPIO0_BASE+0x10)
+#define GPIO0_TSRH (GPIO0_BASE+0x14)
+#define GPIO0_ODR (GPIO0_BASE+0x18)
+#define GPIO0_IR (GPIO0_BASE+0x1C)
+#define GPIO0_RR1 (GPIO0_BASE+0x20)
+#define GPIO0_RR2 (GPIO0_BASE+0x24)
+#define GPIO0_RR3 (GPIO0_BASE+0x28)
+#define GPIO0_ISR1L (GPIO0_BASE+0x30)
+#define GPIO0_ISR1H (GPIO0_BASE+0x34)
+#define GPIO0_ISR2L (GPIO0_BASE+0x38)
+#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
+#define GPIO0_ISR3L (GPIO0_BASE+0x40)
+#define GPIO0_ISR3H (GPIO0_BASE+0x44)
-#define GPIO1_OR (GPIO1_BASE+0x0)
-#define GPIO1_TCR (GPIO1_BASE+0x4)
-#define GPIO1_OSRL (GPIO1_BASE+0x8)
-#define GPIO1_OSRH (GPIO1_BASE+0xC)
-#define GPIO1_TSRL (GPIO1_BASE+0x10)
-#define GPIO1_TSRH (GPIO1_BASE+0x14)
-#define GPIO1_ODR (GPIO1_BASE+0x18)
-#define GPIO1_IR (GPIO1_BASE+0x1C)
-#define GPIO1_RR1 (GPIO1_BASE+0x20)
-#define GPIO1_RR2 (GPIO1_BASE+0x24)
-#define GPIO1_RR3 (GPIO1_BASE+0x28)
-#define GPIO1_ISR1L (GPIO1_BASE+0x30)
-#define GPIO1_ISR1H (GPIO1_BASE+0x34)
-#define GPIO1_ISR2L (GPIO1_BASE+0x38)
-#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
-#define GPIO1_ISR3L (GPIO1_BASE+0x40)
-#define GPIO1_ISR3H (GPIO1_BASE+0x44)
+#define GPIO1_OR (GPIO1_BASE+0x0)
+#define GPIO1_TCR (GPIO1_BASE+0x4)
+#define GPIO1_OSRL (GPIO1_BASE+0x8)
+#define GPIO1_OSRH (GPIO1_BASE+0xC)
+#define GPIO1_TSRL (GPIO1_BASE+0x10)
+#define GPIO1_TSRH (GPIO1_BASE+0x14)
+#define GPIO1_ODR (GPIO1_BASE+0x18)
+#define GPIO1_IR (GPIO1_BASE+0x1C)
+#define GPIO1_RR1 (GPIO1_BASE+0x20)
+#define GPIO1_RR2 (GPIO1_BASE+0x24)
+#define GPIO1_RR3 (GPIO1_BASE+0x28)
+#define GPIO1_ISR1L (GPIO1_BASE+0x30)
+#define GPIO1_ISR1H (GPIO1_BASE+0x34)
+#define GPIO1_ISR2L (GPIO1_BASE+0x38)
+#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
+#define GPIO1_ISR3L (GPIO1_BASE+0x40)
+#define GPIO1_ISR3H (GPIO1_BASE+0x44)
#endif
#ifndef __ASSEMBLY__
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 086f8fb..3bff00a 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -136,12 +136,12 @@
* Common stuff for 4xx (405 and 440)
*/
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
+#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
#define RESET_VECTOR 0xfffffffc
-#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
- line aligned data. */
+#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
+ cache line aligned data. */
#define CPR0_DCR_BASE 0x0C
#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
@@ -162,17 +162,25 @@
/*
* Macros for indirect DCR access
*/
-#define mtcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);mtdcr(CPR0_CFGDATA,d); } while (0)
-#define mfcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);d = mfdcr(CPR0_CFGDATA); } while (0)
+#define mtcpr(reg, d) \
+ do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
+#define mfcpr(reg, d) \
+ do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
-#define mtebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);mtdcr(EBC0_CFGDATA,d); } while (0)
-#define mfebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);d = mfdcr(EBC0_CFGDATA); } while (0)
+#define mtebc(reg, d) \
+ do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
+#define mfebc(reg, d) \
+ do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
-#define mtsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,d); } while (0)
-#define mfsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);d = mfdcr(SDRAM0_CFGDATA); } while (0)
+#define mtsdram(reg, d) \
+ do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
+#define mfsdram(reg, d) \
+ do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
-#define mtsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);mtdcr(SDR0_CFGDATA,d); } while (0)
-#define mfsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);d = mfdcr(SDR0_CFGDATA); } while (0)
+#define mtsdr(reg, d) \
+ do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
+#define mfsdr(reg, d) \
+ do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
#ifndef __ASSEMBLY__
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 7588e93..3095aed 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -119,11 +119,11 @@
int first_init;
int tx_err_index;
int rx_err_index;
- int rx_slot; /* MAL Receive Slot */
- int rx_i_index; /* Receive Interrupt Queue Index */
- int rx_u_index; /* Receive User Queue Index */
- int tx_slot; /* MAL Transmit Slot */
- int tx_i_index; /* Transmit Interrupt Queue Index */
+ int rx_slot; /* MAL Receive Slot */
+ int rx_i_index; /* Receive Interrupt Queue Index */
+ int rx_u_index; /* Receive User Queue Index */
+ int tx_slot; /* MAL Transmit Slot */
+ int tx_i_index; /* Transmit Interrupt Queue Index */
int tx_u_index; /* Transmit User Queue Index */
int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
@@ -173,13 +173,13 @@
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ZMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
+#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
#else
-#define ZMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
+#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
#endif
-#define ZMII_FER (ZMII_BASE)
-#define ZMII_SSR (ZMII_BASE + 4)
-#define ZMII_SMIISR (ZMII_BASE + 8)
+#define ZMII0_FER (ZMII0_BASE)
+#define ZMII0_SSR (ZMII0_BASE + 4)
+#define ZMII0_SMIISR (ZMII0_BASE + 8)
/* ZMII FER Register Bit Definitions */
#define ZMII_FER_DIS (0x0)
@@ -196,25 +196,25 @@
/* ZMII Speed Selection Register Bit Definitions */
-#define ZMII_SSR_SCI (0x4)
-#define ZMII_SSR_FSS (0x2)
-#define ZMII_SSR_SP (0x1)
-#define ZMII_SSR_RSVD16_31 (0x0000FFFF)
+#define ZMII0_SSR_SCI (0x4)
+#define ZMII0_SSR_FSS (0x2)
+#define ZMII0_SSR_SP (0x1)
+#define ZMII0_SSR_RSVD16_31 (0x0000FFFF)
-#define ZMII_SSR_V(__x) (((3 - __x) * 4) + 16)
+#define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16)
/* ZMII SMII Status Register Bit Definitions */
-#define ZMII_SMIISR_E1 (0x80)
-#define ZMII_SMIISR_EC (0x40)
-#define ZMII_SMIISR_EN (0x20)
-#define ZMII_SMIISR_EJ (0x10)
-#define ZMII_SMIISR_EL (0x08)
-#define ZMII_SMIISR_ED (0x04)
-#define ZMII_SMIISR_ES (0x02)
-#define ZMII_SMIISR_EF (0x01)
+#define ZMII0_SMIISR_E1 (0x80)
+#define ZMII0_SMIISR_EC (0x40)
+#define ZMII0_SMIISR_EN (0x20)
+#define ZMII0_SMIISR_EJ (0x10)
+#define ZMII0_SMIISR_EL (0x08)
+#define ZMII0_SMIISR_ED (0x04)
+#define ZMII0_SMIISR_ES (0x02)
+#define ZMII0_SMIISR_EF (0x01)
-#define ZMII_SMIISR_V(__x) ((3 - __x) * 8)
+#define ZMII0_SMIISR_V(__x) ((3 - __x) * 8)
/* RGMII Register Addresses */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -262,16 +262,16 @@
| TCP/IP Acceleration Hardware (TAH) 440GX Only
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440GX)
-#define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
-#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
-#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
-#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
-#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
-#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
-#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
-#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
-#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
-#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
+#define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
+#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
+#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
+#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
+#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
+#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
+#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
+#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
+#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
+#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
/* TAH Revision */
#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
@@ -281,45 +281,45 @@
#define TAH_REV_BN_V (0)
/* TAH Mode Register */
-#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
-#define TAH_MR_SR (0x40000000) /* Software reset */
-#define TAH_MR_ST (0x3F000000) /* Send Threshold */
-#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
-#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
-#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
-#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
+#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
+#define TAH_MR_SR (0x40000000) /* Software reset */
+#define TAH_MR_ST (0x3F000000) /* Send Threshold */
+#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
+#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
+#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
+#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
-#define TAH_MR_ST_V (20)
-#define TAH_MR_TFS_V (17)
+#define TAH_MR_ST_V (20)
+#define TAH_MR_TFS_V (17)
-#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
-#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
-#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
-#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
-#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
+#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
+#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
+#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
+#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
+#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
/* TAH Segment Size Registers 0:5 */
-#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
-#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
-#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
+#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
+#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
+#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
/* TAH Transmit Status Register */
-#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
-#define TAH_TSR_UH (0x40000000) /* Unrecognized header */
-#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
-#define TAH_TSR_IPOP (0x10000000) /* IP option present */
-#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
-#define TAH_TSR_ILTS (0x04000000) /* IP length too short */
-#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
-#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
-#define TAH_TSR_TFP (0x00800000) /* TCP flags present */
-#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
-#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
-#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
-#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
-#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
-#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
+#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
+#define TAH_TSR_UH (0x40000000) /* Unrecognized header */
+#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
+#define TAH_TSR_IPOP (0x10000000) /* IP option present */
+#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
+#define TAH_TSR_ILTS (0x04000000) /* IP length too short */
+#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
+#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
+#define TAH_TSR_TFP (0x00800000) /* TCP flags present */
+#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
+#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
+#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
+#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
+#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
+#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
#endif /* CONFIG_440GX */
@@ -328,41 +328,49 @@
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define EMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
+#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
#else
-#define EMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
+#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
#endif
#else
#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
-#define EMAC_BASE 0xEF600900
+#define EMAC0_BASE 0xEF600900
#else
-#define EMAC_BASE 0xEF600800
+#define EMAC0_BASE 0xEF600800
#endif
#endif
-#define EMAC_M0 (EMAC_BASE)
-#define EMAC_M1 (EMAC_BASE + 4)
-#define EMAC_TXM0 (EMAC_BASE + 8)
-#define EMAC_TXM1 (EMAC_BASE + 12)
-#define EMAC_RXM (EMAC_BASE + 16)
-#define EMAC_ISR (EMAC_BASE + 20)
-#define EMAC_IER (EMAC_BASE + 24)
-#define EMAC_IAH (EMAC_BASE + 28)
-#define EMAC_IAL (EMAC_BASE + 32)
-#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
-#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
-#define EMAC_STACR (EMAC_BASE + 92)
-#define EMAC_TRTR (EMAC_BASE + 96)
-#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
+#if defined(CONFIG_440EPX)
+#define EMAC1_BASE 0xEF600F00
+#define EMAC1_MR1 (EMAC1_BASE + 0x04)
+#endif
+
+#define EMAC0_MR0 (EMAC0_BASE)
+#define EMAC0_MR1 (EMAC0_BASE + 0x04)
+#define EMAC0_TMR0 (EMAC0_BASE + 0x08)
+#define EMAC0_TMR1 (EMAC0_BASE + 0x0c)
+#define EMAC0_RXM (EMAC0_BASE + 0x10)
+#define EMAC0_ISR (EMAC0_BASE + 0x14)
+#define EMAC0_IER (EMAC0_BASE + 0x18)
+#define EMAC0_IAH (EMAC0_BASE + 0x1c)
+#define EMAC0_IAL (EMAC0_BASE + 0x20)
+#define EMAC0_PTR (EMAC0_BASE + 0x2c)
+#define EMAC0_PAUSE_TIME_REG EMAC0_PTR
+#define EMAC0_IPGVR (EMAC0_BASE + 0x58)
+#define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR
+#define EMAC0_STACR (EMAC0_BASE + 0x5c)
+#define EMAC0_TRTR (EMAC0_BASE + 0x60)
+#define EMAC0_RWMR (EMAC0_BASE + 0x64)
+#define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR
/* bit definitions */
/* MODE REG 0 */
-#define EMAC_M0_RXI (0x80000000)
-#define EMAC_M0_TXI (0x40000000)
-#define EMAC_M0_SRST (0x20000000)
-#define EMAC_M0_TXE (0x10000000)
-#define EMAC_M0_RXE (0x08000000)
-#define EMAC_M0_WKE (0x04000000)
+#define EMAC_MR0_RXI (0x80000000)
+#define EMAC_MR0_TXI (0x40000000)
+#define EMAC_MR0_SRST (0x20000000)
+#define EMAC_MR0_TXE (0x10000000)
+#define EMAC_MR0_RXE (0x08000000)
+#define EMAC_MR0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440GX) || \
@@ -371,82 +379,82 @@
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
/* MODE Reg 1 */
-#define EMAC_M1_FDE (0x80000000)
-#define EMAC_M1_ILE (0x40000000)
-#define EMAC_M1_VLE (0x20000000)
-#define EMAC_M1_EIFC (0x10000000)
-#define EMAC_M1_APP (0x08000000)
-#define EMAC_M1_RSVD (0x06000000)
-#define EMAC_M1_IST (0x01000000)
-#define EMAC_M1_MF_1000GPCS (0x00C00000)
-#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS (0x00400000)
-#define EMAC_M1_RFS_MASK (0x00380000)
-#define EMAC_M1_RFS_16K (0x00280000)
-#define EMAC_M1_RFS_8K (0x00200000)
-#define EMAC_M1_RFS_4K (0x00180000)
-#define EMAC_M1_RFS_2K (0x00100000)
-#define EMAC_M1_RFS_1K (0x00080000)
-#define EMAC_M1_TX_FIFO_MASK (0x00070000)
-#define EMAC_M1_TX_FIFO_16K (0x00050000)
-#define EMAC_M1_TX_FIFO_8K (0x00040000)
-#define EMAC_M1_TX_FIFO_4K (0x00030000)
-#define EMAC_M1_TX_FIFO_2K (0x00020000)
-#define EMAC_M1_TX_FIFO_1K (0x00010000)
-#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
-#define EMAC_M1_MWSW (0x00007000)
-#define EMAC_M1_JUMBO_ENABLE (0x00000800)
-#define EMAC_M1_IPPA (0x000007c0)
-#define EMAC_M1_IPPA_SET(id) (((id) & 0x1f) << 6)
-#define EMAC_M1_IPPA_GET(id) (((id) >> 6) & 0x1f)
-#define EMAC_M1_OBCI_GT100 (0x00000020)
-#define EMAC_M1_OBCI_100 (0x00000018)
-#define EMAC_M1_OBCI_83 (0x00000010)
-#define EMAC_M1_OBCI_66 (0x00000008)
-#define EMAC_M1_RSVD1 (0x00000007)
+#define EMAC_MR1_FDE (0x80000000)
+#define EMAC_MR1_ILE (0x40000000)
+#define EMAC_MR1_VLE (0x20000000)
+#define EMAC_MR1_EIFC (0x10000000)
+#define EMAC_MR1_APP (0x08000000)
+#define EMAC_MR1_RSVD (0x06000000)
+#define EMAC_MR1_IST (0x01000000)
+#define EMAC_MR1_MF_1000GPCS (0x00C00000)
+#define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
+#define EMAC_MR1_MF_100MBPS (0x00400000)
+#define EMAC_MR1_RFS_MASK (0x00380000)
+#define EMAC_MR1_RFS_16K (0x00280000)
+#define EMAC_MR1_RFS_8K (0x00200000)
+#define EMAC_MR1_RFS_4K (0x00180000)
+#define EMAC_MR1_RFS_2K (0x00100000)
+#define EMAC_MR1_RFS_1K (0x00080000)
+#define EMAC_MR1_TX_FIFO_MASK (0x00070000)
+#define EMAC_MR1_TX_FIFO_16K (0x00050000)
+#define EMAC_MR1_TX_FIFO_8K (0x00040000)
+#define EMAC_MR1_TX_FIFO_4K (0x00030000)
+#define EMAC_MR1_TX_FIFO_2K (0x00020000)
+#define EMAC_MR1_TX_FIFO_1K (0x00010000)
+#define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */
+#define EMAC_MR1_MWSW (0x00007000)
+#define EMAC_MR1_JUMBO_ENABLE (0x00000800)
+#define EMAC_MR1_IPPA (0x000007c0)
+#define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6)
+#define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f)
+#define EMAC_MR1_OBCI_GT100 (0x00000020)
+#define EMAC_MR1_OBCI_100 (0x00000018)
+#define EMAC_MR1_OBCI_83 (0x00000010)
+#define EMAC_MR1_OBCI_66 (0x00000008)
+#define EMAC_MR1_RSVD1 (0x00000007)
#else /* defined(CONFIG_440GX) */
/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
-#define EMAC_M1_FDE 0x80000000
-#define EMAC_M1_ILE 0x40000000
-#define EMAC_M1_VLE 0x20000000
-#define EMAC_M1_EIFC 0x10000000
-#define EMAC_M1_APP 0x08000000
-#define EMAC_M1_AEMI 0x02000000
-#define EMAC_M1_IST 0x01000000
-#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS 0x00400000
-#define EMAC_M1_RFS_MASK 0x00300000
-#define EMAC_M1_RFS_4K 0x00300000
-#define EMAC_M1_RFS_2K 0x00200000
-#define EMAC_M1_RFS_1K 0x00100000
-#define EMAC_M1_RFS_512 0x00000000
-#define EMAC_M1_TX_FIFO_MASK 0x000c0000
-#define EMAC_M1_TX_FIFO_2K 0x00080000
-#define EMAC_M1_TX_FIFO_1K 0x00040000
-#define EMAC_M1_TX_FIFO_512 0x00000000
-#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
-#define EMAC_M1_TR0_MULTI 0x00008000
-#define EMAC_M1_TR1_DEPEND 0x00004000
-#define EMAC_M1_TR1_MULTI 0x00002000
+#define EMAC_MR1_FDE 0x80000000
+#define EMAC_MR1_ILE 0x40000000
+#define EMAC_MR1_VLE 0x20000000
+#define EMAC_MR1_EIFC 0x10000000
+#define EMAC_MR1_APP 0x08000000
+#define EMAC_MR1_AEMI 0x02000000
+#define EMAC_MR1_IST 0x01000000
+#define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
+#define EMAC_MR1_MF_100MBPS 0x00400000
+#define EMAC_MR1_RFS_MASK 0x00300000
+#define EMAC_MR1_RFS_4K 0x00300000
+#define EMAC_MR1_RFS_2K 0x00200000
+#define EMAC_MR1_RFS_1K 0x00100000
+#define EMAC_MR1_RFS_512 0x00000000
+#define EMAC_MR1_TX_FIFO_MASK 0x000c0000
+#define EMAC_MR1_TX_FIFO_2K 0x00080000
+#define EMAC_MR1_TX_FIFO_1K 0x00040000
+#define EMAC_MR1_TX_FIFO_512 0x00000000
+#define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
+#define EMAC_MR1_TR0_MULTI 0x00008000
+#define EMAC_MR1_TR1_DEPEND 0x00004000
+#define EMAC_MR1_TR1_MULTI 0x00002000
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define EMAC_M1_JUMBO_ENABLE 0x00001000
+#define EMAC_MR1_JUMBO_ENABLE 0x00001000
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#endif /* defined(CONFIG_440GX) */
-#define EMAC_MR1_FIFO_MASK (EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK)
+#define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
#if defined(CONFIG_405EZ)
/* 405EZ only supports 512 bytes fifos */
-#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512)
+#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
#else
/* Set receive fifo to 4k and tx fifo to 2k */
-#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K)
+#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
#endif
/* Transmit Mode Register 0 */
-#define EMAC_TXM0_GNP0 (0x80000000)
-#define EMAC_TXM0_GNP1 (0x40000000)
-#define EMAC_TXM0_GNPD (0x20000000)
-#define EMAC_TXM0_FC (0x10000000)
+#define EMAC_TMR0_GNP0 (0x80000000)
+#define EMAC_TMR0_GNP1 (0x40000000)
+#define EMAC_TMR0_GNPD (0x20000000)
+#define EMAC_TMR0_FC (0x10000000)
/* Receive Mode Register */
#define EMAC_RMR_SP (0x80000000)
diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c
index c3665da..a58db04 100644
--- a/post/cpu/ppc4xx/ether.c
+++ b/post/cpu/ppc4xx/ether.c
@@ -115,11 +115,11 @@
sync ();
#endif
/* reset emac */
- out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
+ out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
sync ();
for (i = 0;; i++) {
- if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST))
+ if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
break;
if (i >= 1000) {
printf ("Timeout resetting EMAC\n");
@@ -134,15 +134,15 @@
mode_reg = 0x0;
if (sysinfo.freqOPB <= 50000000);
else if (sysinfo.freqOPB <= 66666667)
- mode_reg |= EMAC_M1_OBCI_66;
+ mode_reg |= EMAC_MR1_OBCI_66;
else if (sysinfo.freqOPB <= 83333333)
- mode_reg |= EMAC_M1_OBCI_83;
+ mode_reg |= EMAC_MR1_OBCI_83;
else if (sysinfo.freqOPB <= 100000000)
- mode_reg |= EMAC_M1_OBCI_100;
+ mode_reg |= EMAC_MR1_OBCI_100;
else
- mode_reg |= EMAC_M1_OBCI_GT100;
+ mode_reg |= EMAC_MR1_OBCI_GT100;
- out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg);
+ out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
@@ -210,40 +210,40 @@
/* set internal loopback mode */
#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
- out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 |
- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
- in_be32 ((void*)(EMAC_M1 + hw_addr)));
+ out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 |
+ EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
+ EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
+ in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
#else
- out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE |
- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
- in_be32 ((void*)(EMAC_M1 + hw_addr)));
+ out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE |
+ EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
+ EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
+ in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
#endif
/* set transmit enable & receive enable */
- out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE);
+ out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE);
/* enable broadcast address */
- out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE);
+ out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);
/* set transmit request threshold register */
- out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
+ out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440s has a 64 byte burst length */
- out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000);
+ out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
#else
/* 405s have a 16 byte burst length */
- out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
+ out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
#endif /* defined(CONFIG_440) */
- out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000);
+ out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
- out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003);
+ out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
/* Frame gap set */
- out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008);
+ out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
sync ();
}
@@ -270,7 +270,7 @@
udelay (1000);
}
/* emac reset */
- out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
+ out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* remove clocks for EMAC internal loopback */
@@ -300,7 +300,7 @@
flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
sync ();
- out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0);
+ out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0);
sync ();
}