Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
ARM: MX5: Fix broken leftover TO-2 errata workaround
MX31: Cleanup clock function
scb9328: Add ARM relocation support
am3517evm: change console device from ttyS2 to ttyO2
Remove volatile qualifier in get_ram_size() calls
TI: TNETV107X Fix Build Error
ARM: add missing CONFIG_SKIP_LOWLEVEL_INIT for armv7
arm: add CONFIG_MACH_TYPE setting and documentation
arm: add __ilog2 function
Timer: Fix misuse of ARM *timer_masked() functions outside arch/arm
EfikaMX: Enable EXT2 booting
EfikaMX: Add missing CONFIG_SYS_TEXT_BASE
EfikaMX: Use correct imximage.cfg
MX27: Update to autogenerated asm-offsets.h
MX5: Update to autogenerated asm-offsets.h
imx: Add support for zmx25 board
imx: Make imx25 compatible to mxc_gpio driver and fix in tx25
imx: Add auto generation of asm-offsets.h for imx25
imx: Add support for USB EHCI on imx25
imx: Use correct imx25 reset.c
imx: Add get_tbclk() function for imx25
ARM: Update maintainer of board scb9328
mx27: Make the UART port number explicit
build: Add targets for auto gen of asm-offsets.h and use it in imx35
mx31pdk: cosmetic: Fix line over 80 characters
diff --git a/MAINTAINERS b/MAINTAINERS
index 143f31b..6e6affa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -697,9 +697,6 @@
edb9315 ARM920T (EP9315)
edb9315a ARM920T (EP9315)
-Konstantin Kletschke <kletschke@synertronixx.de>
- scb9328 ARM920T
-
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
@@ -714,6 +711,9 @@
SMDKV310 ARM ARMV7 (S5PC210 SoC)
+Torsten Koschorrek <koschorrek@synertronixx.de>
+ scb9328 ARM920T (i.MXL)
+
Frederik Kriewitz <frederik@kriewitz.eu>
devkit8000 ARM ARMV7 (OMAP3530 SoC)
@@ -904,6 +904,7 @@
Matthias Weisser <weisserm@arcor.de>
jadecpu ARM926EJS (MB86R01 SoC)
+ zmx25 ARM926EJS (imx25 SoC)
Richard Woodruff <r-woodruff2@ti.com>
diff --git a/README b/README
index 6a601d2..3239985 100644
--- a/README
+++ b/README
@@ -442,6 +442,16 @@
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.
+ CONFIG_MACH_TYPE [relevant for ARM only][mandatory]
+
+ This setting is mandatory for all boards that have only one
+ machine type and must be used to specify the machine type
+ number as it appears in the ARM machine registry
+ (see http://www.arm.linux.org.uk/developer/machines/).
+ Only boards that have multiple machine types supported
+ in a single configuration file and the machine type is
+ runtime discoverable, do not have to use this setting.
+
- vxWorks boot parameters:
bootvx constructs a valid bootline using the following
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 4ebf38d..248431b 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
#include <asm/io.h>
static u32 mx31_decode_pll(u32 reg, u32 infreq)
@@ -60,7 +61,7 @@
return mx31_get_mpl_dpdgck_clk();
}
-u32 mx31_get_ipg_clk(void)
+static u32 mx31_get_ipg_clk(void)
{
u32 freq = mx31_get_mcu_main_clk();
u32 pdr0 = __REG(CCM_PDR0);
@@ -78,6 +79,24 @@
printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
}
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return mx31_get_mcu_main_clk();
+ case MXC_IPG_CLK:
+ case MXC_CSPI_CLK:
+ case MXC_UART_CLK:
+ return mx31_get_ipg_clk();
+ }
+ return -1;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return mxc_get_clock(MXC_UART_CLK);
+}
+
void mx31_gpio_mux(unsigned long mode)
{
unsigned long reg, shift, tmp;
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index 20f36e3..284cdc5 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -50,14 +50,3 @@
sinclude $(obj).depend
#########################################################################
-
-$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \
- ./asm-offsets.s
- @echo Generating $@
- $(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@
-
-asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \
- ./asm-offsets.c
- $(CC) -DDO_DEPS_ONLY \
- $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
- -o $@ ./asm-offsets.c -c -S
diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile
index 38d7f03..9219c06 100644
--- a/arch/arm/cpu/arm926ejs/mx25/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx25/Makefile
@@ -24,18 +24,18 @@
LIB = $(obj)lib$(SOC).o
-COBJS = generic.o timer.o
-MX27OBJS = reset.o
+COBJS = generic.o timer.o reset.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-SRCS += $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
#########################################################################
# defines $(obj).depend target
diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
new file mode 100644
index 0000000..ba8dfd4
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
@@ -0,0 +1,60 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ /* Clock Control Module */
+ DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
+ DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
+ DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
+ DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
+ DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
+ DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
+
+ /* Enhanced SDRAM Controller */
+ DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
+ DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
+ DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
+
+ /* Multi-Layer AHB Crossbar Switch */
+ DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+ DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+ DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+ DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+ DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+ DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+ DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+ DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+ DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+ DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+ DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+ DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+ DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+ DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+ DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+
+ /* AHB <-> IP-Bus Interface */
+ DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+ DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+
+ return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c
index 14f0c2d..7c8a71b 100644
--- a/arch/arm/cpu/arm926ejs/mx25/timer.c
+++ b/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -187,3 +187,15 @@
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ ulong tbclk;
+
+ tbclk = CONFIG_MX25_CLK32;
+ return tbclk;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 0e112b3..7ac1a21 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -34,6 +34,8 @@
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
#########################################################################
# defines $(obj).depend target
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
new file mode 100644
index 0000000..f3a8d7b
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
@@ -0,0 +1,45 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
+ DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
+ DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
+ DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
+
+ DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
+ DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
+ DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
+ DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
+ DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+ DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+ DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
+
+ DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+ DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+ DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
+ DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+ DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
+ return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c
index 27642bf..222a8e9 100644
--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx27/generic.c
@@ -271,7 +271,7 @@
}
#ifdef CONFIG_MXC_UART
-void mx27_uart_init_pins(void)
+void mx27_uart1_init_pins(void)
{
int i;
unsigned int mode[] = {
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c
index 3e1ff7d..5cc31a9 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c
@@ -53,7 +53,7 @@
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (volatile long *) orion5x_sdram_bar(0),
+ (long *) orion5x_sdram_bar(0),
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
@@ -65,7 +65,7 @@
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
gd->bd->bi_dram[i].size = get_ram_size(
- (volatile long *) (gd->bd->bi_dram[i].start),
+ (long *) (gd->bd->bi_dram[i].start),
CONFIG_MAX_RAM_BANK_SIZE);
}
}
diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index e8be9c9..6e13cc3 100644
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
@@ -45,4 +45,6 @@
sinclude $(obj).depend
+lowlevel_init.o : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
#########################################################################
diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c
new file mode 100644
index 0000000..f972498
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx5/asm-offsets.c
@@ -0,0 +1,76 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+
+ /* Round up to make sure size gives nice stack alignment */
+ DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
+ DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
+ DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
+ DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
+ DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
+ DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
+ DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
+ DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
+ DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
+ DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
+ DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
+ DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
+ DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
+ DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
+ DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
+ DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
+ DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
+ DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
+ DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
+ DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
+ DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
+ DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
+ DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
+ DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
+ DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
+ DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
+ DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
+ DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
+ DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
+ DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
+ DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
+ DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
+ DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
+ DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
+#if defined(CONFIG_MX53)
+ DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
+#endif
+
+ /* DPLL */
+ DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
+ DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
+ DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
+ DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
+ DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
+ DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
+ DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
+ DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 96ebfe2..94de9f1 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -39,10 +39,14 @@
orr r0, r0, #(1 << 23) /* disable write allocate combine */
orr r0, r0, #(1 << 22) /* disable write allocate */
- cmp r3, #0x10 /* r3 contains the silicon rev */
+#if defined(CONFIG_MX51)
+ ldr r1, =0x0
+ ldr r3, [r1, #ROM_SI_REV]
+ cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
orrls r0, r0, #(1 << 25)
+#endif
mcr 15, 1, r0, c9, c0, 2
.endm /* init_l2cc */
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 0e698b6..eee648b 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -283,6 +283,7 @@
_dynsym_start_ofs:
.word __dynsym_start - _start
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
*
* CPU_init_critical registers
@@ -327,6 +328,7 @@
bl lowlevel_init @ go setup pll,mux,memory
mov lr, ip @ restore link
mov pc, lr @ back to my caller
+#endif
/*
*************************************************************************
*
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 55ad115..2ccb445 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -86,8 +86,8 @@
/* GPIO registers */
struct gpio_regs {
- u32 dr; /* data */
- u32 dir; /* direction */
+ u32 gpio_dr; /* data */
+ u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
@@ -141,6 +141,45 @@
u32 mac_addr[6];
};
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+ u32 mpr0;
+ u32 pad00[3];
+ u32 sgpcr0;
+ u32 pad01[59];
+ u32 mpr1;
+ u32 pad02[3];
+ u32 sgpcr1;
+ u32 pad03[59];
+ u32 mpr2;
+ u32 pad04[3];
+ u32 sgpcr2;
+ u32 pad05[59];
+ u32 mpr3;
+ u32 pad06[3];
+ u32 sgpcr3;
+ u32 pad07[59];
+ u32 mpr4;
+ u32 pad08[3];
+ u32 sgpcr4;
+ u32 pad09[251];
+ u32 mgpcr0;
+ u32 pad10[63];
+ u32 mgpcr1;
+ u32 pad11[63];
+ u32 mgpcr2;
+ u32 pad12[63];
+ u32 mgpcr3;
+ u32 pad13[63];
+ u32 mgpcr4;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+ u32 mpr_0_7;
+ u32 mpr_8_15;
+};
+
#endif
/* AIPS 1 */
@@ -318,4 +357,10 @@
#define WSR_UNLOCK1 0x5555
#define WSR_UNLOCK2 0xAAAA
+/* Names used in GPIO driver */
+#define GPIO1_BASE_ADDR IMX_GPIO1_BASE
+#define GPIO2_BASE_ADDR IMX_GPIO2_BASE
+#define GPIO3_BASE_ADDR IMX_GPIO3_BASE
+#define GPIO4_BASE_ADDR IMX_GPIO4_BASE
+
#endif /* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h
new file mode 100644
index 0000000..276c71c
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx25/macro.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Common asm macros for imx25
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_MACRO_H__
+#define __ASM_ARM_ARCH_MACRO_H__
+#ifdef __ASSEMBLY__
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+.macro init_aips
+ write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777
+ write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777
+ write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777
+ write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777
+.endm
+
+.macro init_max
+ write32 IMX_MAX_BASE + MAX_MPR0, 0x43210
+ write32 IMX_MAX_BASE + MAX_MPR1, 0x43210
+ write32 IMX_MAX_BASE + MAX_MPR2, 0x43210
+ write32 IMX_MAX_BASE + MAX_MPR3, 0x43210
+ write32 IMX_MAX_BASE + MAX_MPR4, 0x43210
+
+ write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10
+ write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10
+ write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10
+ write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10
+ write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10
+
+ write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0
+ write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0
+ write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0
+ write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0
+ write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_ARCH_MACRO_H__ */
diff --git a/arch/arm/include/asm/arch-mx27/asm-offsets.h b/arch/arm/include/asm/arch-mx27/asm-offsets.h
deleted file mode 100644
index 497afe5..0000000
--- a/arch/arm/include/asm/arch-mx27/asm-offsets.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#define AIPI1_PSR0 0x10000000
-#define AIPI1_PSR1 0x10000004
-#define AIPI2_PSR0 0x10020000
-#define AIPI2_PSR1 0x10020004
-#define CSCR 0x10027000
-#define MPCTL0 0x10027004
-#define SPCTL0 0x1002700c
-#define PCDR0 0x10027018
-#define PCDR1 0x1002701c
-#define PCCR0 0x10027020
-#define PCCR1 0x10027024
-#define ESDCTL0_ROF 0x00
-#define ESDCFG0_ROF 0x04
-#define ESDCTL1_ROF 0x08
-#define ESDCFG1_ROF 0x0C
-#define ESDMISC_ROF 0x10
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index 8f40aa7..b4b2fe6 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -29,7 +29,7 @@
extern void imx_gpio_mode (int gpio_mode);
#ifdef CONFIG_MXC_UART
-extern void mx27_uart_init_pins(void);
+extern void mx27_uart1_init_pins(void);
#endif /* CONFIG_MXC_UART */
#ifdef CONFIG_FEC_MXC
diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
index 9f7ae80..fb035c4 100644
--- a/arch/arm/include/asm/arch-mx31/clock.h
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -24,8 +24,15 @@
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
-extern u32 mx31_get_ipg_clk(void);
-#define imx_get_uartclk mx31_get_ipg_clk
+enum mxc_clock {
+ MXC_ARM_CLK,
+ MXC_IPG_CLK,
+ MXC_CSPI_CLK,
+ MXC_UART_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+extern u32 imx_get_uartclk();
extern void mx31_gpio_mux(unsigned long mode);
extern void mx31_set_pad(enum iomux_pins pin, u32 config);
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 306f966..3c8d607 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -746,7 +746,7 @@
#define IRAM_SIZE (16 * 1024)
#define MX31_AIPS1_BASE_ADDR 0x43f00000
-#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
/* USB portsc */
/* values for portsc field */
diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h
deleted file mode 100644
index 793f69c..0000000
--- a/arch/arm/include/asm/arch-mx5/asm-offsets.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
- *
- * These should be auto-generated
- */
-/* CCM */
-#define CLKCTL_CCR 0x00
-#define CLKCTL_CCDR 0x04
-#define CLKCTL_CSR 0x08
-#define CLKCTL_CCSR 0x0C
-#define CLKCTL_CACRR 0x10
-#define CLKCTL_CBCDR 0x14
-#define CLKCTL_CBCMR 0x18
-#define CLKCTL_CSCMR1 0x1C
-#define CLKCTL_CSCMR2 0x20
-#define CLKCTL_CSCDR1 0x24
-#define CLKCTL_CS1CDR 0x28
-#define CLKCTL_CS2CDR 0x2C
-#define CLKCTL_CDCDR 0x30
-#define CLKCTL_CHSCCDR 0x34
-#define CLKCTL_CSCDR2 0x38
-#define CLKCTL_CSCDR3 0x3C
-#define CLKCTL_CSCDR4 0x40
-#define CLKCTL_CWDR 0x44
-#define CLKCTL_CDHIPR 0x48
-#define CLKCTL_CDCR 0x4C
-#define CLKCTL_CTOR 0x50
-#define CLKCTL_CLPCR 0x54
-#define CLKCTL_CISR 0x58
-#define CLKCTL_CIMR 0x5C
-#define CLKCTL_CCOSR 0x60
-#define CLKCTL_CGPR 0x64
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6C
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7C
-#define CLKCTL_CCGR6 0x80
-#if defined(CONFIG_MX53)
-#define CLKCTL_CCGR7 0x84
-#define CLKCTL_CMEOR 0x88
-#elif defined(CONFIG_MX51)
-#define CLKCTL_CMEOR 0x84
-#endif
-
-/* DPLL */
-#define PLL_DP_CTL 0x00
-#define PLL_DP_CONFIG 0x04
-#define PLL_DP_OP 0x08
-#define PLL_DP_MFD 0x0C
-#define PLL_DP_MFN 0x10
-#define PLL_DP_HFS_OP 0x1C
-#define PLL_DP_HFS_MFD 0x20
-#define PLL_DP_HFS_MFN 0x24
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 9589a62..e83ca29 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -317,9 +317,27 @@
u32 ccgr4;
u32 ccgr5;
u32 ccgr6;
+#if defined(CONFIG_MX53)
+ u32 ccgr7;
+#endif
u32 cmeor;
};
+/* DPLL registers */
+struct dpll {
+ u32 dp_ctl;
+ u32 dp_config;
+ u32 dp_op;
+ u32 dp_mfd;
+ u32 dp_mfn;
+ u32 dp_mfn_minus;
+ u32 dp_mfn_plus;
+ u32 dp_hfs_op;
+ u32 dp_hfs_mfd;
+ u32 dp_hfs_mfn;
+ u32 dp_mfn_togc;
+ u32 dp_destat;
+};
/* WEIM registers */
struct weim {
u32 cs0gcr1;
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index 270f163..879e20e 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -106,6 +106,11 @@
return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
}
+static inline int __ilog2(unsigned int x)
+{
+ return generic_fls(x) - 1;
+}
+
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index fc52a26..6bbedf4 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -281,6 +281,10 @@
gd->mon_len = _bss_end_ofs;
+#ifdef CONFIG_MACH_TYPE
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
+#endif
+
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
index a918b04..856d798 100644
--- a/board/BuS/eb_cpux9k2/cpux9k2.c
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -141,7 +141,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c
index cdbbfd0..cf7d7f6 100644
--- a/board/armadillo/flash.c
+++ b/board/armadillo/flash.c
@@ -162,6 +162,7 @@
int rc = ERR_OK;
unsigned long base;
unsigned long addr;
+ ulong start;
if ((info->flash_id & FLASH_VENDMASK) !=
(FUJ_MANUFACT & FLASH_VENDMASK)) {
@@ -192,7 +193,7 @@
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
/* ARM simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
@@ -232,6 +233,7 @@
{
int flag;
unsigned long base;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
@@ -250,7 +252,7 @@
flag = disable_interrupts ();
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
base = dest & 0xF0000000;
FL_WORD (base + (0x555 << 1)) = 0xAA;
diff --git a/board/atmel/at91rm9200dk/flash.c b/board/atmel/at91rm9200dk/flash.c
index 902c3c4..be22743 100644
--- a/board/atmel/at91rm9200dk/flash.c
+++ b/board/atmel/at91rm9200dk/flash.c
@@ -285,6 +285,7 @@
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip1;
+ ulong start;
/* first look for protection bits */
@@ -325,7 +326,7 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
volatile u16 *addr = (volatile u16 *) (info->start[sect]);
@@ -345,7 +346,7 @@
result = *addr;
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
break;
@@ -400,6 +401,7 @@
int rc = ERR_OK;
int cflag, iflag;
int chip1;
+ ulong start;
/*
* Check if Flash is (sufficiently) erased
@@ -425,7 +427,7 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait until flash is ready */
chip1 = 0;
@@ -433,7 +435,7 @@
result = *addr;
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip1 = ERR | TMO;
break;
}
diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c
index ec0daba..2b4d845 100644
--- a/board/atmel/at91rm9200ek/at91rm9200ek.c
+++ b/board/atmel/at91rm9200ek/at91rm9200ek.c
@@ -64,7 +64,7 @@
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c
index a4b201e..e1e7807 100644
--- a/board/cerf250/flash.c
+++ b/board/cerf250/flash.c
@@ -221,7 +221,7 @@
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -254,9 +254,6 @@
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -269,14 +266,14 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
@@ -393,6 +390,7 @@
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -406,11 +404,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c
index 2e66872..d6fd519 100644
--- a/board/cm4008/flash.c
+++ b/board/cm4008/flash.c
@@ -209,6 +209,7 @@
int flag, prot, sect;
ulong type;
int rcode = 0;
+ ulong start;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
@@ -250,7 +251,7 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
addr = (volatile unsigned char *) (info->start[sect]);
*addr = 0x50; /* clear status register */
@@ -258,7 +259,7 @@
*addr = 0xD0; /* erase confirm */
while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xB0; /* suspend erase */
@@ -370,6 +371,7 @@
volatile unsigned char *addr = (volatile unsigned char *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -384,11 +386,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = 0xFF; /* restore read mode */
return (1);
}
diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c
index 2e66872..d6fd519 100644
--- a/board/cm41xx/flash.c
+++ b/board/cm41xx/flash.c
@@ -209,6 +209,7 @@
int flag, prot, sect;
ulong type;
int rcode = 0;
+ ulong start;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
@@ -250,7 +251,7 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
addr = (volatile unsigned char *) (info->start[sect]);
*addr = 0x50; /* clear status register */
@@ -258,7 +259,7 @@
*addr = 0xD0; /* erase confirm */
while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xB0; /* suspend erase */
@@ -370,6 +371,7 @@
volatile unsigned char *addr = (volatile unsigned char *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -384,11 +386,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = 0xFF; /* restore read mode */
return (1);
}
diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c
index d832e62..d10faab 100644
--- a/board/cmc_pu2/flash.c
+++ b/board/cmc_pu2/flash.c
@@ -264,7 +264,7 @@
{
vu_short *addr = (vu_short *)(info->start[0]);
int flag, prot, sect, ssect, l_sect;
- ulong now, last;
+ ulong now, last, start;
debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
@@ -335,11 +335,11 @@
if (l_sect < 0)
goto DONE;
- reset_timer_masked ();
+ start = get_timer(0);
last = 0;
addr = (vu_short *)(info->start[l_sect]);
while ((addr[0] & 0x0080) != 0x0080) {
- if ((now = get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@@ -434,6 +434,7 @@
{
int flag;
vu_short *base; /* first address in flash bank */
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
@@ -455,11 +456,11 @@
if (flag)
enable_interrupts();
- reset_timer_masked ();
+ start = get_timer(0);
/* data polling for D7 */
while ((*dest & 0x0080) != (data & 0x0080)) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = 0x00F0; /* reset bank */
return (1);
}
diff --git a/board/cradle/flash.c b/board/cradle/flash.c
index b5635fb..1601782 100644
--- a/board/cradle/flash.c
+++ b/board/cradle/flash.c
@@ -136,6 +136,7 @@
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
@@ -173,7 +174,7 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_short *addr = (vu_short *) (info->start[sect]);
@@ -182,7 +183,7 @@
*addr = 0xD0; /* erase confirm */
while ((*addr & 0x80) != 0x80) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0xB0; /* suspend erase */
*addr = 0xFF; /* reset to read mode */
@@ -221,6 +222,7 @@
vu_short *addr = (vu_short *) dest, val;
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
@@ -246,11 +248,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((val = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0xB0;
diff --git a/board/csb226/flash.c b/board/csb226/flash.c
index 02ded1c..e103470 100644
--- a/board/csb226/flash.c
+++ b/board/csb226/flash.c
@@ -141,6 +141,7 @@
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
@@ -175,7 +176,7 @@
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
u32 * volatile addr = (u32 * volatile)(info->start[sect]);
@@ -189,7 +190,7 @@
*addr = 0x00D000D0; /* erase confirm */
while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0x00B000B0; /* suspend erase*/
*addr = 0x00FF00FF; /* read mode */
rc = ERR_TIMOUT;
@@ -221,6 +222,7 @@
u32 * volatile addr = (u32 * volatile)dest, val;
int rc = ERR_OK;
int flag;
+ ulong start;
/* read array command - just for the case... */
*addr = 0x00FF00FF;
@@ -247,11 +249,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait while polling the status register */
while(((val = *addr) & 0x00800080) != 0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0x00B000B0;
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index b1238d5..ec22627 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -44,7 +44,7 @@
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c
index 2bfdf23..6103339 100644
--- a/board/davinci/common/misc.c
+++ b/board/davinci/common/misc.c
@@ -38,7 +38,7 @@
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
- (volatile void *)CONFIG_SYS_SDRAM_BASE,
+ (void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
diff --git a/board/dnp1110/flash.c b/board/dnp1110/flash.c
index c81abc5..53f89ee 100644
--- a/board/dnp1110/flash.c
+++ b/board/dnp1110/flash.c
@@ -212,7 +212,7 @@
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -245,9 +245,6 @@
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -260,14 +257,14 @@
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
*addr = (FPW)0x00500050; /* clear status register */
*addr = (FPW)0x00200020; /* erase setup */
*addr = (FPW)0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW)0x00B000B0; /* suspend erase */
*addr = (FPW)0x00FF00FF; /* reset to read mode */
@@ -385,6 +382,7 @@
FPWV *addr = (FPWV *)dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -398,11 +396,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (start = get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW)0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 16be532..4b36918 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -113,7 +113,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/ep7312/flash.c b/board/ep7312/flash.c
index 0c2b3ae..2ed9c9a 100644
--- a/board/ep7312/flash.c
+++ b/board/ep7312/flash.c
@@ -119,6 +119,7 @@
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
@@ -156,7 +157,7 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_short *addr = (vu_short *) (info->start[sect]);
@@ -165,7 +166,7 @@
*addr = 0xD0; /* erase confirm */
while ((*addr & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0xB0; /* suspend erase */
*addr = 0xFF; /* reset to read mode */
rc = ERR_TIMOUT;
@@ -203,6 +204,7 @@
vu_short *addr = (vu_short *) dest, val;
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
@@ -228,11 +230,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((val = *addr) & 0x80) != 0x80) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0xB0;
diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c
index 0959c5c..402f19f 100644
--- a/board/eukrea/cpu9260/cpu9260.c
+++ b/board/eukrea/cpu9260/cpu9260.c
@@ -174,7 +174,7 @@
int dram_init(void)
{
- gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c
index 5d05414..f654f87 100644
--- a/board/eukrea/cpuat91/cpuat91.c
+++ b/board/eukrea/cpuat91/cpuat91.c
@@ -63,7 +63,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
index 9bf9c18..7637c92 100644
--- a/board/freescale/mx31ads/mx31ads.c
+++ b/board/freescale/mx31ads/mx31ads.c
@@ -31,7 +31,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index 08addd2..f6e190a 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -42,7 +42,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index e2d3d74..fd7342f 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -53,7 +53,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index b51d209..134603a 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -46,8 +46,8 @@
{
u32 size1, size2;
- size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index a89aa25..88095dc 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -46,7 +46,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index d032428..18b388e 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -47,8 +47,8 @@
{
u32 size1, size2;
- size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index f3c433f..21b5d14 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -44,8 +44,8 @@
{
u32 size1, size2;
- size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
diff --git a/board/gcplus/flash.c b/board/gcplus/flash.c
index 8511582..ab567e8 100644
--- a/board/gcplus/flash.c
+++ b/board/gcplus/flash.c
@@ -225,7 +225,7 @@
flash_erase(flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -258,9 +258,6 @@
printf("\n");
}
- start = get_timer(0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -273,7 +270,7 @@
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
@@ -282,7 +279,7 @@
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
@@ -401,6 +398,7 @@
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -414,11 +412,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/impa7/flash.c b/board/impa7/flash.c
index d0c5880..6eae428 100644
--- a/board/impa7/flash.c
+++ b/board/impa7/flash.c
@@ -128,6 +128,7 @@
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
@@ -165,7 +166,7 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *) (info->start[sect]);
@@ -174,7 +175,7 @@
*addr = 0x00D000D0; /* erase confirm */
while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0x00B000B0; /* suspend erase */
*addr = 0x00FF00FF; /* reset to read mode */
@@ -211,6 +212,7 @@
ulong barf;
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
@@ -236,14 +238,14 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* read status register command */
*addr = 0x00700070;
/* wait while polling the status register */
while ((*addr & 0x00800080) != 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
/* suspend program command */
*addr = 0x00B000B0;
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index ca7d6e2..773900e 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -33,7 +33,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/innokom/flash.c b/board/innokom/flash.c
index 8c95341..ed4b987 100644
--- a/board/innokom/flash.c
+++ b/board/innokom/flash.c
@@ -182,6 +182,7 @@
{
int flag, prot, sect;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
@@ -218,7 +219,7 @@
PRINTK("\n");
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
u16 * volatile addr = (u16 * volatile)(info->start[sect]);
@@ -235,7 +236,7 @@
while ((*addr & 0x0080) != 0x0080) {
PRINTK(".");
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = 0x00B0; /* suspend erase*/
*addr = 0x00FF; /* read mode */
rc = ERR_TIMOUT;
@@ -279,6 +280,7 @@
volatile u16 *addr = (u16 *)dest, val;
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) return ERR_NOT_ERASED;
@@ -302,11 +304,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait while polling the status register */
while(((val = *addr) & 0x80) != 0x80) {
- if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
rc = ERR_TIMOUT;
*addr = 0xB0; /* suspend program command */
goto outahere;
diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c
index 269858c..25b99e8 100644
--- a/board/karo/tx25/tx25.c
+++ b/board/karo/tx25/tx25.c
@@ -70,18 +70,18 @@
writel(0x0, &padctl->pad_d11);
/* drop PHY power and assert reset (low) */
- val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9));
- writel(val, &gpio4->dr);
- val = readl(&gpio4->dir) | (1 << 7) | (1 << 9);
- writel(val, &gpio4->dir);
+ val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9));
+ writel(val, &gpio4->gpio_dr);
+ val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9);
+ writel(val, &gpio4->gpio_dir);
mdelay(5);
debug("resetting phy\n");
/* turn on PHY power leaving reset asserted */
- val = readl(&gpio4->dr) | 1 << 9;
- writel(val, &gpio4->dr);
+ val = readl(&gpio4->gpio_dr) | 1 << 9;
+ writel(val, &gpio4->gpio_dr);
mdelay(10);
@@ -111,19 +111,19 @@
/*
* set each to 1 and make each an output
*/
- val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12);
- writel(val, &gpio3->dr);
- val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12);
- writel(val, &gpio3->dir);
+ val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12);
+ writel(val, &gpio3->gpio_dr);
+ val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12);
+ writel(val, &gpio3->gpio_dir);
mdelay(22); /* this value came from RedBoot */
/*
* deassert PHY reset
*/
- val = readl(&gpio4->dr) | 1 << 7;
- writel(val, &gpio4->dr);
- writel(val, &gpio4->dr);
+ val = readl(&gpio4->gpio_dr) | 1 << 7;
+ writel(val, &gpio4->gpio_dr);
+ writel(val, &gpio4->gpio_dr);
mdelay(5);
@@ -160,7 +160,7 @@
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
@@ -168,11 +168,11 @@
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
#if CONFIG_NR_DRAM_BANKS > 1
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
#else
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 5da856f..a8f2b23 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -321,7 +321,7 @@
{
/* dram_init must store complete ramsize in gd->ram_size */
/* Fix this */
- gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
+ gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
kw_sdram_bs(0));
return 0;
}
diff --git a/board/lart/flash.c b/board/lart/flash.c
index 29a331e..408c884 100644
--- a/board/lart/flash.c
+++ b/board/lart/flash.c
@@ -250,6 +250,7 @@
ulong result;
int iflag, cflag, prot, sect;
int rc = ERR_OK;
+ ulong start;
/* first look for protection bits */
@@ -291,7 +292,7 @@
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0)
{ /* not protected */
@@ -305,7 +306,7 @@
do
{
/* check timeout */
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
{
*addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
result = BIT_TIMEOUT;
@@ -354,6 +355,7 @@
ulong result;
int rc = ERR_OK;
int cflag, iflag;
+ ulong start;
/* Check if Flash is (sufficiently) erased
*/
@@ -377,13 +379,13 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait until flash is ready */
do
{
/* check timeout */
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
{
*addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
result = BIT_TIMEOUT;
diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c
index 6eb5cc2..2b273ac 100644
--- a/board/logicpd/imx27lite/imx27lite.c
+++ b/board/logicpd/imx27lite/imx27lite.c
@@ -38,7 +38,7 @@
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
#ifdef CONFIG_MXC_UART
- mx27_uart_init_pins();
+ mx27_uart1_init_pins();
#endif
#ifdef CONFIG_FEC_MXC
mx27_fec_init_pins();
@@ -67,7 +67,7 @@
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
@@ -75,11 +75,11 @@
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
#if CONFIG_NR_DRAM_BANKS > 1
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2,
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
#endif
}
diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c
index bf635c3..09cc9c5 100644
--- a/board/logicpd/imx31_litekit/imx31_litekit.c
+++ b/board/logicpd/imx31_litekit/imx31_litekit.c
@@ -32,7 +32,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c
index a3ba75b..f5c0713 100644
--- a/board/lpd7a40x/flash.c
+++ b/board/lpd7a40x/flash.c
@@ -229,6 +229,7 @@
ulong result, result1;
int iflag, prot, sect;
int rc = ERR_OK;
+ ulong start;
#ifdef USE_920T_MMU
int cflag;
@@ -284,7 +285,7 @@
sect, info->start[sect]);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *) (info->start[sect]);
@@ -297,7 +298,7 @@
/* wait until flash is ready */
do {
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = CMD_STATUS_RESET;
result = BIT_TIMEOUT;
break;
@@ -357,6 +358,7 @@
ulong result;
int rc = ERR_OK;
int iflag;
+ ulong start;
#ifdef USE_920T_MMU
int cflag;
@@ -387,12 +389,12 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait until flash is ready */
do {
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = CMD_SUSPEND;
result = BIT_TIMEOUT;
break;
diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c
index a4b201e..1ea2893 100644
--- a/board/lubbock/flash.c
+++ b/board/lubbock/flash.c
@@ -221,7 +221,7 @@
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -254,9 +254,6 @@
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -269,14 +266,14 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
@@ -393,6 +390,7 @@
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -406,11 +404,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c
index 4c31143..4834e21 100644
--- a/board/modnet50/flash.c
+++ b/board/modnet50/flash.c
@@ -291,6 +291,7 @@
{
int flag, sect, setup_offset = 0;
int rc = ERR_OK;
+ ulong start;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
@@ -338,14 +339,14 @@
(__u16) SECERASE_CMD;
/* wait some time */
- reset_timer_masked ();
- while (get_timer_masked () < 1000) {
+ start = get_timer(0);
+ while (get_timer(start) < 1000) {
}
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
while (flash_check_erase_amd (info->start[sect])) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("timeout!\n");
/* OOPS: reach timeout,
* try to reset chip
@@ -411,6 +412,7 @@
{
int rc = ERR_OK;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*(__u16 *) (dest) & data) != data)
@@ -446,10 +448,10 @@
}
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
while (flash_check_write_amd (dest)) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
printf ("timeout! @ %08lX\n", dest);
/* OOPS: reach timeout,
* try to reset chip */
diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
index c11c0fe..86b49fb 100644
--- a/board/mx1ads/mx1ads.c
+++ b/board/mx1ads/mx1ads.c
@@ -169,7 +169,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c
index 47f613c..7331efa 100644
--- a/board/mx1ads/syncflash.c
+++ b/board/mx1ads/syncflash.c
@@ -276,7 +276,7 @@
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ get_timer(0);
SF_NvmodeErase();
SF_NvmodeWrite();
diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c
index 5b56b98..185bc2d 100644
--- a/board/ns9750dev/flash.c
+++ b/board/ns9750dev/flash.c
@@ -261,7 +261,7 @@
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -294,10 +294,6 @@
printf ("\n");
}
-
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -312,7 +308,7 @@
flash_unprotect_sectors (addr);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050;/* clear status register */
*addr = (FPW) 0x00200020;/* erase setup */
@@ -321,7 +317,7 @@
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
@@ -441,6 +437,7 @@
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -454,11 +451,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c
index a8897dc..2406c5f 100644
--- a/board/pleb2/flash.c
+++ b/board/pleb2/flash.c
@@ -472,7 +472,7 @@
FPWV *addr;
int flag, prot, sect;
int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong now, last;
+ ulong start, now, last;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -516,8 +516,6 @@
printf ("\n");
}
- reset_timer_masked ();
-
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
@@ -527,7 +525,7 @@
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
- reset_timer_masked ();
+ start = get_timer(0);
last = 0;
addr = (FPWV *) (info->start[sect]);
@@ -559,7 +557,7 @@
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
if ((now =
- get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
if (intel) {
@@ -661,6 +659,7 @@
int flag;
int res = 0; /* result, assume success */
FPWV *base; /* first address in flash bank */
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
@@ -683,12 +682,12 @@
if (flag)
enable_interrupts ();
- reset_timer_masked ();
+ start = get_timer(0);
/* data polling for D7 */
while (res == 0
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00F000F0; /* reset bank */
res = 1;
}
@@ -711,6 +710,7 @@
{
int flag;
int res = 0; /* result, assume success */
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
@@ -730,10 +730,10 @@
if (flag)
enable_interrupts ();
- reset_timer_masked ();
+ start = get_timer(0);
while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00B000B0; /* Suspend program */
res = 1;
}
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index e0f44dd..2c50fe8 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -282,7 +282,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index ec9f865..8071600 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -379,7 +379,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 79b7c9d..fa69599 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -160,7 +160,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/samsung/smdk2400/flash.c b/board/samsung/smdk2400/flash.c
index fb69c21..47382fe 100644
--- a/board/samsung/smdk2400/flash.c
+++ b/board/samsung/smdk2400/flash.c
@@ -231,6 +231,7 @@
ulong result, result1;
int iflag, prot, sect;
int rc = ERR_OK;
+ ulong start;
#ifdef USE_920T_MMU
int cflag;
@@ -286,7 +287,7 @@
sect, info->start[sect]);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_long *addr = (vu_long *) (info->start[sect]);
@@ -299,7 +300,7 @@
/* wait until flash is ready */
do {
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = CMD_STATUS_RESET;
result = BIT_TIMEOUT;
break;
@@ -359,6 +360,7 @@
ulong result;
int rc = ERR_OK;
int iflag;
+ ulong start;
#ifdef USE_920T_MMU
int cflag;
@@ -389,12 +391,12 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait until flash is ready */
do {
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = CMD_SUSPEND;
result = BIT_TIMEOUT;
break;
diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c
index abb0935..d209a6f 100644
--- a/board/sbc2410x/flash.c
+++ b/board/sbc2410x/flash.c
@@ -173,6 +173,7 @@
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip;
+ ulong start;
/* first look for protection bits */
@@ -213,7 +214,7 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
if (info->protect[sect] == 0) { /* not protected */
vu_short *addr = (vu_short *) (info->start[sect]);
@@ -233,7 +234,7 @@
result = *addr;
/* check timeout */
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip = TMO;
@@ -295,6 +296,7 @@
int rc = ERR_OK;
int cflag, iflag;
int chip;
+ ulong start;
/*
* Check if Flash is (sufficiently) erased
@@ -322,7 +324,7 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ get_timer(start);
/* wait until flash is ready */
chip = 0;
@@ -330,7 +332,7 @@
result = *addr;
/* check timeout */
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip = ERR | TMO;
break;
}
diff --git a/board/scb9328/config.mk b/board/scb9328/config.mk
deleted file mode 100644
index 7c5e067..0000000
--- a/board/scb9328/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# This config file is used for compilation of scb93328 sources
-#
-# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
-# This allows for example having one copy located at the end of ram and stored
-# in flash device and later on while developing use other location to test
-# the code in RAM device only.
-#
-
-CONFIG_SYS_TEXT_BASE = 0x08f00000
diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c
index c6f94ae..00c660a 100644
--- a/board/scb9328/flash.c
+++ b/board/scb9328/flash.c
@@ -97,11 +97,12 @@
static int flash_ready (ulong timeout)
{
int ok = 1;
+ ulong start;
- reset_timer_masked ();
+ start = get_timer(0);
while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
FLASH_CMD (CFI_INTEL_SR_READY)) {
- if (get_timer_masked () > timeout && timeout != 0) {
+ if (get_timer(start) > timeout && timeout != 0) {
ok = 0;
break;
}
diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c
index 428e8c9..2e31e8c 100644
--- a/board/scb9328/scb9328.c
+++ b/board/scb9328/scb9328.c
@@ -39,23 +39,17 @@
int dram_init (void)
{
-#if ( CONFIG_NR_DRAM_BANKS > 0 )
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)SCB9328_SDRAM_1,
+ SCB9328_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 1 )
- gd->bd->bi_dram[1].start = SCB9328_SDRAM_2;
- gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 2 )
- gd->bd->bi_dram[2].start = SCB9328_SDRAM_3;
- gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 3 )
- gd->bd->bi_dram[3].start = SCB9328_SDRAM_4;
- gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE;
-#endif
- return 0;
}
/**
diff --git a/board/shannon/flash.c b/board/shannon/flash.c
index 0455afa..179ec5f 100644
--- a/board/shannon/flash.c
+++ b/board/shannon/flash.c
@@ -190,6 +190,7 @@
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip1, chip2;
+ ulong start;
/* first look for protection bits */
@@ -231,7 +232,7 @@
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
if (info->protect[sect] == 0)
{ /* not protected */
@@ -253,7 +254,7 @@
result = *addr;
/* check timeout */
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
{
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip1 = TMO;
@@ -322,6 +323,7 @@
int rc = ERR_OK;
int cflag, iflag;
int chip1, chip2;
+ ulong start;
/*
* Check if Flash is (sufficiently) erased
@@ -349,7 +351,7 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked();
+ start = get_timer(0);
/* wait until flash is ready */
chip1 = chip2 = 0;
@@ -358,7 +360,7 @@
result = *addr;
/* check timeout */
- if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
{
chip1 = ERR | TMO;
break;
diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c
index a7b6e70..63a0d33 100644
--- a/board/syteco/jadecpu/jadecpu.c
+++ b/board/syteco/jadecpu/jadecpu.c
@@ -152,7 +152,7 @@
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile
new file mode 100644
index 0000000..5a0e5b3
--- /dev/null
+++ b/board/syteco/zmx25/Makefile
@@ -0,0 +1,51 @@
+#
+# (c) 2010 Graf-Syteco, Matthias Weisser
+# <weisserm@arcor.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += zmx25.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S
new file mode 100644
index 0000000..8e63de0
--- /dev/null
+++ b/board/syteco/zmx25/lowlevel_init.S
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on U-Boot and RedBoot sources for several different i.mx
+ * platforms.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/macro.h>
+#include <asm/arch/macro.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+/*
+ * clocks
+ */
+.macro init_clocks
+
+ /* disable clock output */
+ write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
+ write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
+
+ /*
+ * enable all implemented clocks in all three
+ * clock control registers
+ */
+ write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
+ write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
+ write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
+
+ /* Devide NAND clock by 32 */
+ write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
+.endm
+
+/*
+ * sdram controller init
+ */
+.macro init_lpddr
+ ldr r0, =IMX_ESDRAMC_BASE
+ ldr r2, =IMX_SDRAM_BANK0_BASE
+
+ /*
+ * reset SDRAM controller
+ * then wait for initialization to complete
+ */
+ ldr r1, =(1 << 1) | (1 << 2)
+ str r1, [r0, #ESDRAMC_ESDMISC]
+1: ldr r3, [r0, #ESDRAMC_ESDMISC]
+ tst r3, #(1 << 31)
+ beq 1b
+ ldr r1, =(1 << 2)
+ str r1, [r0, #ESDRAMC_ESDMISC]
+
+ ldr r1, =0x002a7420
+ str r1, [r0, #ESDRAMC_ESDCFG0]
+
+ /* control | precharge */
+ ldr r1, =0x92216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+ /* dram command encoded in address */
+ str r1, [r2, #0x400]
+
+ /* auto refresh */
+ ldr r1, =0xa2216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+ /* read dram twice to auto refresh */
+ ldr r3, [r2]
+ ldr r3, [r2]
+
+ /* control | load mode */
+ ldr r1, =0xb2216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+
+ /* mode register of lpddram */
+ strb r1, [r2, #0x33]
+
+ /* extended mode register of lpddrram */
+ ldr r2, =0x81000000
+ strb r1, [r2]
+
+ /* control | normal */
+ ldr r1, =0x82216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ init_aips
+ init_max
+ init_clocks
+ init_lpddr
+ mov pc, lr
diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c
new file mode 100644
index 0000000..f055038
--- /dev/null
+++ b/board/syteco/zmx25/zmx25.c
@@ -0,0 +1,203 @@
+/*
+ * (c) 2011 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * Based on tx25.c:
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on imx27lite.c:
+ * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ * And:
+ * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mxc_gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/imx25-pinmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init()
+{
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ struct iomuxc_pad_input_select *inputselect;
+ u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+ u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
+ u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
+ u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
+ u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
+ u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
+
+ icache_enable();
+
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+ inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
+
+ /* Setup of core volatage selection pin to run at 1.4V */
+ writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1);
+
+ /* Setup of input daisy chains for SD card pins*/
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
+
+ /* Setup of digital output for USB power and OC */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1);
+
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN);
+
+ /* Setup of digital output control pins */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
+
+ writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
+ writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
+
+ /* Switch both output drivers off */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT);
+
+ /* Setup of key input pin GPIO2[29]*/
+ writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
+ writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN);
+
+ /* Setup of status LED outputs */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
+ writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
+
+ /* Switch both LEDs off */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT);
+
+ /* Setup of CAN1 and CAN2 signals */
+ writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
+ writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
+ writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
+ writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
+
+ /* Setup of input daisy chains for CAN signals*/
+ writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
+ writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
+
+ /* Setup of I2C3 signals */
+ writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
+ writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
+
+ /* Setup of input daisy chains for I2C3 signals*/
+ writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
+ writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
+
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_ZMX25;
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ const char *e;
+
+#ifdef CONFIG_FEC_MXC
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
+ u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
+
+ /*
+ * fec pin init is generic
+ */
+ mx25_fec_init_pins();
+
+ /*
+ * Set up LAN-RESET and FEC_RX_ERR
+ *
+ * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
+ * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
+ */
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+
+ writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
+ writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
+
+ /* assert PHY reset (low) */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0);
+ mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT);
+
+ udelay(5000);
+
+ /* deassert PHY reset */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1);
+
+ udelay(5000);
+#endif
+
+ e = getenv("gs_base_board");
+ if (e != NULL) {
+ if (strcmp(e, "G283") == 0) {
+ int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29));
+
+ if (key) {
+ /* Switch on both LEDs to inidcate boot mode */
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
+ mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
+
+ setenv("preboot", "run gs_slow_boot");
+ } else
+ setenv("preboot", "run gs_fast_boot");
+ }
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
diff --git a/board/ti/omap1610inn/flash.c b/board/ti/omap1610inn/flash.c
index 36200ad..1b67d08 100644
--- a/board/ti/omap1610inn/flash.c
+++ b/board/ti/omap1610inn/flash.c
@@ -278,7 +278,7 @@
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -311,10 +311,6 @@
printf ("\n");
}
-
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -329,7 +325,7 @@
flash_unprotect_sectors (addr);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050;/* clear status register */
*addr = (FPW) 0x00200020;/* erase setup */
@@ -338,7 +334,7 @@
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
@@ -458,6 +454,7 @@
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -470,11 +467,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/ti/omap730p2/flash.c b/board/ti/omap730p2/flash.c
index 5b56b98..185bc2d 100644
--- a/board/ti/omap730p2/flash.c
+++ b/board/ti/omap730p2/flash.c
@@ -261,7 +261,7 @@
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -294,10 +294,6 @@
printf ("\n");
}
-
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -312,7 +308,7 @@
flash_unprotect_sectors (addr);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050;/* clear status register */
*addr = (FPW) 0x00200020;/* erase setup */
@@ -321,7 +317,7 @@
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer(start) >
CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
@@ -441,6 +437,7 @@
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -454,11 +451,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c
index b051c89..6cb0aca 100644
--- a/board/xaeniax/flash.c
+++ b/board/xaeniax/flash.c
@@ -221,7 +221,7 @@
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -254,9 +254,6 @@
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -269,14 +266,14 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
@@ -393,6 +390,7 @@
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -406,11 +404,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/board/xm250/flash.c b/board/xm250/flash.c
index b02149c..e825aba 100644
--- a/board/xm250/flash.c
+++ b/board/xm250/flash.c
@@ -250,7 +250,7 @@
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -283,9 +283,6 @@
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -298,14 +295,14 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
@@ -422,6 +419,7 @@
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -435,11 +433,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
@@ -470,6 +468,7 @@
int rc = 0;
vu_long *addr = (vu_long *)(info->start[sector]);
int flag = disable_interrupts();
+ ulong start;
*addr = INTEL_CLEAR; /* Clear status register */
if (prot) { /* Set sector lock bit */
@@ -481,10 +480,10 @@
*addr = INTEL_CONFIRM; /* clear */
}
- reset_timer_masked ();
+ start = get_timer(0);
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
printf("Flash lock bit operation timed out\n");
rc = 1;
break;
@@ -510,13 +509,13 @@
{
if (info->protect[i])
{
- reset_timer_masked ();
+ start = get_timer(0);
addr = (vu_long *)(info->start[i]);
*addr = INTEL_LOCKBIT; /* Sector lock bit */
*addr = INTEL_PROTECT; /* set */
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
{
- if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT)
{
printf("Flash lock bit operation timed out\n");
rc = 1;
diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c
index 5ba84c6..3ee0ab8 100644
--- a/board/zylonite/flash.c
+++ b/board/zylonite/flash.c
@@ -224,7 +224,7 @@
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@@ -257,9 +257,6 @@
printf ("\n");
}
- start = get_timer (0);
- last = start;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@@ -272,14 +269,14 @@
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW) 0x00B000B0; /* suspend erase */
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
@@ -396,6 +393,7 @@
FPWV *addr = (FPWV *) dest;
ulong status;
int flag;
+ ulong start;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
@@ -409,11 +407,11 @@
*addr = data;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
+ start = get_timer(0);
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
diff --git a/boards.cfg b/boards.cfg
index 5127e23..5cfaa78 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -131,6 +131,7 @@
sheevaplug arm arm926ejs - Marvell kirkwood
dockstar arm arm926ejs - Seagate kirkwood
jadecpu arm arm926ejs jadecpu syteco mb86r0x
+zmx25 arm arm926ejs zmx25 syteco mx25
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
nhk8815 arm arm926ejs nhk8815 st nomadik
@@ -139,7 +140,7 @@
edminiv2 arm arm926ejs - LaCie orion5x
dkb arm arm926ejs - Marvell pantheon
ca9x4_ct_vxp arm armv7 vexpress armltd
-efikamx arm armv7 efikamx - mx5 mx51evk:IMX_CONFIG=board/efikamx/imximage.cfg
+efikamx arm armv7 efikamx - mx5 efikamx:IMX_CONFIG=board/efikamx/imximage.cfg
mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg
mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
diff --git a/common/memsize.c b/common/memsize.c
index 6c275c9..963e4f3 100644
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -37,7 +37,7 @@
* the actually available RAM size between addresses `base' and
* `base + maxsize'.
*/
-long get_ram_size(volatile long *base, long maxsize)
+long get_ram_size(long *base, long maxsize)
{
volatile long *addr;
long save[32];
diff --git a/drivers/mtd/spi/eeprom_m95xxx.c b/drivers/mtd/spi/eeprom_m95xxx.c
index 632db4e..ef8ed6f 100644
--- a/drivers/mtd/spi/eeprom_m95xxx.c
+++ b/drivers/mtd/spi/eeprom_m95xxx.c
@@ -75,6 +75,7 @@
{
struct spi_slave *slave;
char buf[3];
+ ulong start;
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
CONFIG_DEFAULT_SPI_MODE);
@@ -102,7 +103,7 @@
if(spi_xfer(slave, len * 8, buffer, NULL, SPI_XFER_END))
return -1;
- reset_timer_masked();
+ start = get_timer(0);
do {
buf[0] = SPI_EEPROM_RDSR;
buf[1] = 0;
@@ -111,7 +112,7 @@
if (!(buf[1] & 1))
break;
- } while (get_timer_masked() < CONFIG_SYS_SPI_WRITE_TOUT);
+ } while (get_timer(start) < CONFIG_SYS_SPI_WRITE_TOUT);
if (buf[1] & 1)
printf ("*** spi_write: Time out while writing!\n");
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4e4cd27..ab90afa 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -86,7 +86,7 @@
/*
* wait for the related interrupt
*/
- start = get_timer_masked();
+ start = get_timer(0);
while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
printf("Read MDIO failed...\n");
@@ -138,7 +138,7 @@
/*
* wait for the MII interrupt
*/
- start = get_timer_masked();
+ start = get_timer(0);
while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
printf("Write MDIO failed...\n");
@@ -189,7 +189,7 @@
/*
* Wait for AN completion
*/
- start = get_timer_masked();
+ start = get_timer(0);
do {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("%s: Autonegotiation timeout\n", dev->name);
diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c
index c9e324e..f54817e 100644
--- a/drivers/net/netarm_eth.c
+++ b/drivers/net/netarm_eth.c
@@ -81,9 +81,10 @@
static int na_mii_poll_busy (void)
{
+ ulong start;
/* arm simple, non interrupt dependent timer */
- reset_timer_masked ();
- while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) {
+ start = get_timer(0));
+ while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) {
if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
return 1;
}
@@ -164,19 +165,20 @@
static int reset_eth (void)
{
int pt;
+ ulong start;
na_get_mac_addr ();
pt = na_mii_identify_phy ();
/* reset the phy */
na_mii_write (MII_PHY_CONTROL, 0x8000);
- reset_timer_masked ();
- while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) {
+ start = get_timer(0);
+ while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) {
if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) {
break;
}
}
- if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY)
+ if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY)
printf ("phy reset timeout\n");
/* set the PCS reg */
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 698e726..81381d9 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -60,8 +60,6 @@
0x53f84000,
};
-#define mxc_get_clock(x) mx31_get_ipg_clk()
-
#elif defined(CONFIG_MX51)
#define MXC_CSPICTRL_EN (1 << 0)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 6af35ab..a0cfbb7 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -29,6 +29,14 @@
#define USBCTRL_OTGBASE_OFFSET 0x600
+#ifdef CONFIG_MX25
+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
+#define MX25_USB_CTRL_HSTD_BIT (1<<5)
+#define MX25_USB_CTRL_USBTE_BIT (1<<4)
+#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
+#endif
+
+#ifdef CONFIG_MX31
#define MX31_OTG_SIC_SHIFT 29
#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
#define MX31_OTG_PM_BIT (1 << 24)
@@ -42,12 +50,19 @@
#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
#define MX31_H1_PM_BIT (1 << 8)
#define MX31_H1_DT_BIT (1 << 4)
+#endif
static int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
+
+#ifdef CONFIG_MX25
+ v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
+ MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
+#endif
+
#ifdef CONFIG_MX31
- v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET);
+ v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
switch (port) {
case 0: /* OTG port */
@@ -85,36 +100,38 @@
default:
return -EINVAL;
}
-
- writel(v, MX31_OTG_BASE_ADDR +
- USBCTRL_OTGBASE_OFFSET);
#endif
- return 0;
+
+ writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+ return 0;
}
int ehci_hcd_init(void)
{
- u32 tmp;
struct usb_ehci *ehci;
+#ifdef CONFIG_MX31
+ u32 tmp;
struct clock_control_regs *sc_regs =
(struct clock_control_regs *)CCM_BASE;
tmp = __raw_readl(&sc_regs->ccmr);
__raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
+#endif
udelay(80);
/* Take USB2 */
- ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR +
+ ehci = (struct usb_ehci *)(IMX_USB_BASE +
(0x200 * CONFIG_MXC_USB_PORT));
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
+#ifdef CONFIG_MX31
setbits_le32(&ehci->control, USB_EN);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
-
+#endif
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
udelay(10000);
diff --git a/include/common.h b/include/common.h
index 2c8513a..c5d2dce 100644
--- a/include/common.h
+++ b/include/common.h
@@ -317,7 +317,7 @@
void api_init (void);
/* common/memsize.c */
-long get_ram_size (volatile long *, long);
+long get_ram_size (long *, long);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 80ad342..18aaadf 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -190,7 +190,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
- "console=ttyS2,115200n8\0" \
+ "console=ttyO2,115200n8\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index a04ac49..7d3363a 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -38,6 +38,8 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_TEXT_BASE 0x97800000
+
#define CONFIG_SYS_L2CACHE_OFF
/*
@@ -47,6 +49,7 @@
#define CONFIG_CMD_SF
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
#undef CONFIG_CMD_IMLS
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 5f70023..35ceacd 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -162,8 +162,10 @@
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
/*-----------------------------------------------------------------------
* FLASH and environment organization
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
index 6a92ec3..1b5d931 100644
--- a/include/configs/scb9328.h
+++ b/include/configs/scb9328.h
@@ -126,6 +126,11 @@
#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
+#define CONFIG_SYS_TEXT_BASE 0x10000000
+
+#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
+
/*
* Configuration for FLASH memory for the Synertronixx board
*/
diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h
index 3627ce7..4bced0c 100644
--- a/include/configs/tnetv107x_evm.h
+++ b/include/configs/tnetv107x_evm.h
@@ -57,6 +57,12 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_STACKSIZE (256*1024)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
/* Serial Driver Info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
new file mode 100644
index 0000000..374c88a
--- /dev/null
+++ b/include/configs/zmx25.h
@@ -0,0 +1,180 @@
+/*
+ * (c) 2011 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * Configuation settings for the zmx25 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_MX25
+#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "gs_fast_boot=setenv bootdelay 5\0" \
+ "gs_slow_boot=setenv bootdelay 10\0" \
+ "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
+ "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
+ "bootm 0x81000000; bootelf 0x81000000\0"
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define BOARD_LATE_INIT
+
+/*
+ * Compressions
+ */
+#define CONFIG_LZO
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * GPIO
+ */
+#define CONFIG_MXC_GPIO
+
+/*
+ * Serial
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX25_UART2
+#define CONFIG_CONS_INDEX 1 /* use UART2 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR 0x00
+#define CONFIG_MII
+#define CONFIG_NET_MULTI
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/*
+ * Additional command
+ */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORT 2
+#define CONFIG_MXC_USB_PORTSC 0xC0000000
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE 0xA0000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE (128 * 1024)
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
+
+#define CONFIG_SYS_PROMPT "zmx25> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_PREBOOT ""
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
+#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#endif /* __CONFIG_H */
diff --git a/include/mxc_gpio.h b/include/mxc_gpio.h
index 002ba61..f673dce 100644
--- a/include/mxc_gpio.h
+++ b/include/mxc_gpio.h
@@ -24,6 +24,11 @@
#ifndef __MXC_GPIO_H
#define __MXC_GPIO_H
+/* Converts a GPIO port number and the internal bit position
+ * to the GPIO number
+ */
+#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f))
+
enum mxc_gpio_direction {
MXC_GPIO_DIRECTION_IN,
MXC_GPIO_DIRECTION_OUT,
diff --git a/rules.mk b/rules.mk
index c2860e5..5fd12a0 100644
--- a/rules.mk
+++ b/rules.mk
@@ -42,4 +42,14 @@
$(NOPEDOBJS): $(obj)%.o: %.c
$(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c
+$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \
+ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s
+ @echo Generating $@
+ $(TOPDIR)/tools/scripts/make-asm-offsets $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s $@
+
+$(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \
+ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c
+ $(CC) -DDO_DEPS_ONLY \
+ $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
+ -o $@ $(TOPDIR)/$(CPUDIR)/$(SOC)/asm-offsets.c -c -S
#########################################################################