| commit | c19a8bc5711ec63e905ef91f045a1489f0aa3cb0 | [log] [tgz] |
|---|---|---|
| author | Anthony Felice <tony.felice@timesys.com> | Sat Sep 06 19:47:06 2014 +0200 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Tue Oct 07 13:08:31 2014 +0200 |
| tree | a29aaf854053be0d81157e8ee1dc106cc9956b8d | |
| parent | 1454ba8e56d88a8b95ac8050cde2c07c651cd0ae [diff] |
vf610twr: Tune DDR initialization settings Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice <tony.felice@timesys.com> [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner <stefan@agner.ch>