tree 29daad933328ec9d6d20b8861399ec8f68319e45
parent 7aa6c455c357f6d767acec747bbecb23664eeacb
author Zang Roy-R61911 <tie-fei.zang@freescale.com> 1385616217 +0800
committer York Sun <yorksun@freescale.com> 1386197682 -0800

T4240: Address T4240/T4160 Rev2.0 DDR clock change

MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>