Merge branch 'master' of git://www.denx.de/git/u-boot
diff --git a/README b/README
index f14fb7b..f3957f1 100644
--- a/README
+++ b/README
@@ -786,6 +786,21 @@
 			Define this to use i/o functions instead of macros
 			(some hardware wont work with macros)
 
+		CONFIG_DRIVER_SMC911X
+		Support for SMSC's LAN911x and LAN921x chips
+
+			CONFIG_DRIVER_SMC911X_BASE
+			Define this to hold the physical address
+			of the device (I/O space)
+
+			CONFIG_DRIVER_SMC911X_32_BIT
+			Define this if data bus is 32 bits
+
+			CONFIG_DRIVER_SMC911X_16_BIT
+			Define this if data bus is 16 bits. If your processor
+			automatically converts one 32 bit word to two 16 bit
+			words you may also try CONFIG_DRIVER_SMC911X_32_BIT.
+
 - USB Support:
 		At the moment only the UHCI host controller is
 		supported (PIP405, MIP405, MPC5200); define
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index c53c226..40a781f 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -83,6 +83,7 @@
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
 };
 
 /* Function forward declarations */
@@ -646,6 +647,7 @@
 		hw->mac_type = e1000_82546;
 		break;
 	case E1000_DEV_ID_82541ER:
+	case E1000_DEV_ID_82541GI_LF:
 		hw->mac_type = e1000_82541_rev_2;
 		break;
 	default:
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index 851467d..23b2eb9 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -222,7 +222,8 @@
 #define E1000_DEV_ID_82546EB_COPPER 0x1010
 #define E1000_DEV_ID_82546EB_FIBER  0x1012
 #define E1000_DEV_ID_82541ER	    0x1078
-#define NUM_DEV_IDS 14
+#define E1000_DEV_ID_82541GI_LF	    0x107C
+#define NUM_DEV_IDS 15
 
 #define NODE_ADDRESS_SIZE 6
 #define ETH_LENGTH_OF_ADDRESS 6
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 5ab4726..8d4e248 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -125,11 +125,17 @@
 	}
 
 	if ((dup_spd & 0xFFFF) == _100BASET) {
+#ifdef CONFIG_MCF5445x
+		fecp->rcr &= ~0x200;	/* disabled 10T base */
+#endif
 #ifdef MII_DEBUG
 		printf("100Mbps\n");
 #endif
 		bd->bi_ethspeed = 100;
 	} else {
+#ifdef CONFIG_MCF5445x
+		fecp->rcr |= 0x200;	/* enabled 10T base */
+#endif
 #ifdef MII_DEBUG
 		printf("10Mbps\n");
 #endif
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 5302cb5..6d93bf0 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -30,6 +30,12 @@
 #include <net.h>
 #include <miiphy.h>
 
+#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \
+	defined (CONFIG_DRIVER_SMC911X_16_BIT)
+#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \
+	CONFIG_DRIVER_SMC911X_16_BIT shall be set"
+#endif
+
 #ifdef CONFIG_DRIVER_SMC911X_32_BIT
 static inline u32 reg_read(u32 addr)
 {
@@ -39,9 +45,20 @@
 {
 	*(volatile u32*)addr = val;
 }
+#elif CONFIG_DRIVER_SMC911X_16_BIT
+static inline u32 reg_read(u32 addr)
+{
+	volatile u16 *addr_16 = (u16 *)addr;
+	return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
+}
+static inline void reg_write(u32 addr, u32 val)
+{
+	*(volatile u16*)addr = (u16)val;
+	*(volatile u16*)(addr + 2) = (u16)(val >> 16);
+}
 #else
-#error "SMC911X: Only 32-bit bus is supported"
-#endif
+#error "SMC911X: undefined bus width"
+#endif /* CONFIG_DRIVER_SMC911X_16_BIT */
 
 #define mdelay(n)       udelay((n)*1000)
 
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index c7af930..397ae71 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -1128,6 +1128,36 @@
 			   },
 };
 
+struct phy_info phy_info_M88E1118 = {
+	0x01410e1,
+	"Marvell 88E1118",
+	4,
+	(struct phy_cmd[]){	/* config */
+		/* Reset and configure the PHY */
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{0x16, 0x0002, NULL}, /* Change Page Number */
+		{0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
+		{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+		{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+		{miim_end,}
+		},
+	(struct phy_cmd[]){	/* startup */
+		{0x16, 0x0000, NULL}, /* Change Page Number */
+		/* Status is read once to clear old link state */
+		{MIIM_STATUS, miim_read, NULL},
+		/* Auto-negotiate */
+		/* Read the status */
+		{MIIM_88E1011_PHY_STATUS, miim_read,
+		 &mii_parse_88E1011_psr},
+		{miim_end,}
+		},
+	(struct phy_cmd[]){	/* shutdown */
+		{miim_end,}
+		},
+};
+
 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
 {
 	uint mii_data = read_phy_reg(priv, mii_reg);
@@ -1492,6 +1522,7 @@
 	&phy_info_BCM5464S,
 	&phy_info_M88E1011S,
 	&phy_info_M88E1111S,
+	&phy_info_M88E1118,
 	&phy_info_M88E1145,
 	&phy_info_M88E1149S,
 	&phy_info_dm9161,
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 61c2203..d061017 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1812,7 +1812,8 @@
 #define PCI_DEVICE_ID_INTEL_82434	0x04a3
 #define PCI_DEVICE_ID_INTEL_I960	0x0960
 #define PCI_DEVICE_ID_INTEL_I960RM	0x0962
-#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
+#define PCI_DEVICE_ID_INTEL_82541ER	0x1078
+#define PCI_DEVICE_ID_INTEL_82541GI_LF	0x107c
 #define PCI_DEVICE_ID_INTEL_82542	0x1000
 #define PCI_DEVICE_ID_INTEL_82543GC_FIBER	0x1001
 #define PCI_DEVICE_ID_INTEL_82543GC_COPPER	0x1004