diff --git a/MAINTAINERS b/MAINTAINERS
index f796872..17befd0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1102,6 +1102,8 @@
 	AP325RXA	SH7723
 	SHMIN		SH7706
 	ECOVEC		SH7724
+	R0P7734     SH7734
+	AP_SH4A_4A  SH7734
 
 Mark Jonas <mark.jonas@de.bosch.com>
 
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index b390a6c..d7a64b4 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -254,7 +254,6 @@
 #ifndef CONFIG_ENV_IS_NOWHERE
 	extern char * env_name_spec;
 #endif
-	char *s;
 	bd_t *bd;
 
 	gd = new_gd;
diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
new file mode 100644
index 0000000..6f26dfa
--- /dev/null
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -0,0 +1,11 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de
+ */
+
+extern ulong uboot_end_data;
+extern ulong uboot_end;
+
+extern int incaip_set_cpuclk(void);
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index 59a8001..62d47a8 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -38,13 +38,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern int timer_init(void);
-
-extern int incaip_set_cpuclk(void);
-
-extern ulong uboot_end_data;
-extern ulong uboot_end;
-
 ulong monitor_flash_len;
 
 static char *failed = "*** failed ***\n";
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 9930abf..608c1a7 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -33,22 +33,23 @@
 #define	LINUX_MAX_ENVS		256
 #define	LINUX_MAX_ARGS		256
 
-static int	linux_argc;
-static char **	linux_argv;
+static int linux_argc;
+static char **linux_argv;
 
-static char **	linux_env;
-static char *	linux_env_p;
-static int	linux_env_idx;
+static char **linux_env;
+static char *linux_env_p;
+static int linux_env_idx;
 
-static void linux_params_init (ulong start, char * commandline);
-static void linux_env_set (char * env_name, char * env_val);
+static void linux_params_init(ulong start, char *commandline);
+static void linux_env_set(char *env_name, char *env_val);
 
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
+int do_bootm_linux(int flag, int argc, char * const argv[],
+			bootm_headers_t *images)
 {
-	void	(*theKernel) (int, char **, char **, int *);
-	char	*commandline = getenv ("bootargs");
-	char	env_buf[12];
-	char	*cp;
+	void (*theKernel) (int, char **, char **, int *);
+	char *commandline = getenv("bootargs");
+	char env_buf[12];
+	char *cp;
 
 	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
 		return 1;
@@ -59,53 +60,53 @@
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
 #ifdef DEBUG
-	printf ("## Transferring control to Linux (at address %08lx) ...\n",
+	printf("## Transferring control to Linux (at address %08lx) ...\n",
 		(ulong) theKernel);
 #endif
 
-	linux_params_init (UNCACHED_SDRAM (gd->bd->bi_boot_params), commandline);
+	linux_params_init(UNCACHED_SDRAM(gd->bd->bi_boot_params), commandline);
 
 #ifdef CONFIG_MEMSIZE_IN_BYTES
-	sprintf (env_buf, "%lu", (ulong)gd->ram_size);
-	debug ("## Giving linux memsize in bytes, %lu\n", (ulong)gd->ram_size);
+	sprintf(env_buf, "%lu", (ulong)gd->ram_size);
+	debug("## Giving linux memsize in bytes, %lu\n", (ulong)gd->ram_size);
 #else
-	sprintf (env_buf, "%lu", (ulong)(gd->ram_size >> 20));
-	debug ("## Giving linux memsize in MB, %lu\n", (ulong)(gd->ram_size >> 20));
+	sprintf(env_buf, "%lu", (ulong)(gd->ram_size >> 20));
+	debug("## Giving linux memsize in MB, %lu\n",
+		(ulong)(gd->ram_size >> 20));
 #endif /* CONFIG_MEMSIZE_IN_BYTES */
 
-	linux_env_set ("memsize", env_buf);
+	linux_env_set("memsize", env_buf);
 
-	sprintf (env_buf, "0x%08X", (uint) UNCACHED_SDRAM (images->rd_start));
-	linux_env_set ("initrd_start", env_buf);
+	sprintf(env_buf, "0x%08X", (uint) UNCACHED_SDRAM(images->rd_start));
+	linux_env_set("initrd_start", env_buf);
 
-	sprintf (env_buf, "0x%X", (uint) (images->rd_end - images->rd_start));
-	linux_env_set ("initrd_size", env_buf);
+	sprintf(env_buf, "0x%X", (uint) (images->rd_end - images->rd_start));
+	linux_env_set("initrd_size", env_buf);
 
-	sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart));
-	linux_env_set ("flash_start", env_buf);
+	sprintf(env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart));
+	linux_env_set("flash_start", env_buf);
 
-	sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize));
-	linux_env_set ("flash_size", env_buf);
+	sprintf(env_buf, "0x%X", (uint) (gd->bd->bi_flashsize));
+	linux_env_set("flash_size", env_buf);
 
 	cp = getenv("ethaddr");
-	if (cp != NULL) {
+	if (cp)
 		linux_env_set("ethaddr", cp);
-	}
 
 	cp = getenv("eth1addr");
-	if (cp != NULL) {
+	if (cp)
 		linux_env_set("eth1addr", cp);
-	}
 
 	/* we assume that the kernel is in place */
-	printf ("\nStarting kernel ...\n\n");
+	printf("\nStarting kernel ...\n\n");
 
-	theKernel (linux_argc, linux_argv, linux_env, 0);
+	theKernel(linux_argc, linux_argv, linux_env, 0);
+
 	/* does not return */
 	return 1;
 }
 
-static void linux_params_init (ulong start, char *line)
+static void linux_params_init(ulong start, char *line)
 {
 	char *next, *quote, *argp;
 
@@ -117,26 +118,25 @@
 	next = line;
 
 	while (line && *line && linux_argc < LINUX_MAX_ARGS) {
-		quote = strchr (line, '"');
-		next = strchr (line, ' ');
+		quote = strchr(line, '"');
+		next = strchr(line, ' ');
 
-		while (next != NULL && quote != NULL && quote < next) {
+		while (next && quote && quote < next) {
 			/* we found a left quote before the next blank
 			 * now we have to find the matching right quote
 			 */
-			next = strchr (quote + 1, '"');
-			if (next != NULL) {
-				quote = strchr (next + 1, '"');
-				next = strchr (next + 1, ' ');
+			next = strchr(quote + 1, '"');
+			if (next) {
+				quote = strchr(next + 1, '"');
+				next = strchr(next + 1, ' ');
 			}
 		}
 
-		if (next == NULL) {
-			next = line + strlen (line);
-		}
+		if (!next)
+			next = line + strlen(line);
 
 		linux_argv[linux_argc] = argp;
-		memcpy (argp, line, next - line);
+		memcpy(argp, line, next - line);
 		argp[next - line] = 0;
 
 		argp += next - line + 1;
@@ -154,19 +154,19 @@
 	linux_env_idx = 0;
 }
 
-static void linux_env_set (char *env_name, char *env_val)
+static void linux_env_set(char *env_name, char *env_val)
 {
 	if (linux_env_idx < LINUX_MAX_ENVS - 1) {
 		linux_env[linux_env_idx] = linux_env_p;
 
-		strcpy (linux_env_p, env_name);
-		linux_env_p += strlen (env_name);
+		strcpy(linux_env_p, env_name);
+		linux_env_p += strlen(env_name);
 
-		strcpy (linux_env_p, "=");
+		strcpy(linux_env_p, "=");
 		linux_env_p += 1;
 
-		strcpy (linux_env_p, env_val);
-		linux_env_p += strlen (env_val);
+		strcpy(linux_env_p, env_val);
+		linux_env_p += strlen(env_val);
 
 		linux_env_p++;
 		linux_env[++linux_env_idx] = 0;
diff --git a/arch/mips/lib/bootm_qemu_mips.c b/arch/mips/lib/bootm_qemu_mips.c
index bb6442a..0815c9c 100644
--- a/arch/mips/lib/bootm_qemu_mips.c
+++ b/arch/mips/lib/bootm_qemu_mips.c
@@ -29,30 +29,31 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
+int do_bootm_linux(int flag, int argc, char * const argv[],
+			bootm_headers_t *images)
 {
-	void	(*theKernel) (int, char **, char **, int *);
-	char	*bootargs = getenv ("bootargs");
-	char	*start;
-	uint	len;
+	void (*theKernel) (int, char **, char **, int *);
+	char *bootargs = getenv("bootargs");
+	char *start;
+	uint len;
 
 	/* find kernel entry point */
 	theKernel = (void (*)(int, char **, char **, int *))images->ep;
 
 	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
-	debug ("## Transferring control to Linux (at address %08lx) ...\n",
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
 		(ulong) theKernel);
 
 	gd->bd->bi_boot_params = gd->bd->bi_memstart + (16 << 20) - 256;
-	debug ("%-12s= 0x%08lX\n", "boot_params", (ulong)gd->bd->bi_boot_params);
+	debug("%-12s= 0x%08lX\n", "boot_params", (ulong)gd->bd->bi_boot_params);
 
 	/* set Magic */
 	*(int32_t *)(gd->bd->bi_boot_params - 4) = 0x12345678;
 	/* set ram_size */
 	*(int32_t *)(gd->bd->bi_boot_params - 8) = gd->ram_size;
 
-	start = (char*)gd->bd->bi_boot_params;
+	start = (char *)gd->bd->bi_boot_params;
 
 	len = strlen(bootargs);
 
@@ -62,15 +63,16 @@
 
 	len = images->rd_end - images->rd_start;
 	if (len > 0) {
-		start += sprintf(start," rd_start=0x%08X rd_size=0x%0X",
-		(uint) UNCACHED_SDRAM (images->rd_start),
+		start += sprintf(start, " rd_start=0x%08X rd_size=0x%0X",
+		(uint) UNCACHED_SDRAM(images->rd_start),
 		(uint) len);
 	}
 
 	/* we assume that the kernel is in place */
-	printf ("\nStarting kernel ...\n\n");
+	printf("\nStarting kernel ...\n\n");
 
-	theKernel (0, NULL, NULL, 0);
+	theKernel(0, NULL, NULL, 0);
+
 	/* does not return */
 	return 1;
 }
diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index 4a4bc0d..b53232f 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -41,6 +41,9 @@
 COBJS-$(CONFIG_IIM) += iim.o
 COBJS-$(CONFIG_PCI) += pci.o
 
+# Stub implementations of cache management functions for USB
+COBJS-$(CONFIG_USB_EHCI) += cache.o
+
 COBJS	:= $(COBJS-y)
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/powerpc/cpu/mpc512x/cache.c b/arch/powerpc/cpu/mpc512x/cache.c
new file mode 100644
index 0000000..2a08b65
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/cache.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * This file contains stub implementation of
+ *   invalidate_dcache_range()
+ *   flush_dcache_range()
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index b5c499d..012ab6b0 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -41,6 +41,9 @@
 COBJS-$(CONFIG_PCIE) += pcie.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
+# Stub implementations of cache management functions for USB
+COBJS-$(CONFIG_USB_EHCI) += cache.o
+
 ifdef CONFIG_FSL_DDR2
 COBJS_LN-$(CONFIG_MPC8349) += ddr-gen2.o
 else
diff --git a/arch/powerpc/cpu/mpc83xx/cache.c b/arch/powerpc/cpu/mpc83xx/cache.c
new file mode 100644
index 0000000..2a08b65
--- /dev/null
+++ b/arch/powerpc/cpu/mpc83xx/cache.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * This file contains stub implementation of
+ *   invalidate_dcache_range()
+ *   flush_dcache_range()
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 058d609..c512b33 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -129,6 +129,9 @@
 COBJS	+= tlb.o
 COBJS	+= traps.o
 
+# Stub implementations of cache management functions for USB
+COBJS-$(CONFIG_USB_EHCI) += cache.o
+
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 START	:= $(addprefix $(obj),$(START))
diff --git a/arch/powerpc/cpu/mpc85xx/cache.c b/arch/powerpc/cpu/mpc85xx/cache.c
new file mode 100644
index 0000000..2a08b65
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/cache.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * This file contains stub implementation of
+ *   invalidate_dcache_range()
+ *   flush_dcache_range()
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
index 767e189..28be591 100644
--- a/arch/sh/include/asm/cpu_sh2.h
+++ b/arch/sh/include/asm/cpu_sh2.h
@@ -35,6 +35,8 @@
 # include <asm/cpu_sh7203.h>
 #elif defined(CONFIG_CPU_SH7264)
 # include <asm/cpu_sh7264.h>
+#elif defined(CONFIG_CPU_SH7269)
+# include <asm/cpu_sh7269.h>
 #else
 # error "Unknown SH2 variant"
 #endif
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index 4351e8e..f1f49fe 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -46,6 +46,8 @@
 # include <asm/cpu_sh7723.h>
 #elif defined (CONFIG_CPU_SH7724)
 # include <asm/cpu_sh7724.h>
+#elif defined (CONFIG_CPU_SH7734)
+# include <asm/cpu_sh7734.h>
 #elif defined (CONFIG_CPU_SH7757)
 # include <asm/cpu_sh7757.h>
 #elif defined (CONFIG_CPU_SH7763)
diff --git a/arch/sh/include/asm/cpu_sh7269.h b/arch/sh/include/asm/cpu_sh7269.h
new file mode 100644
index 0000000..4dea708
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7269.h
@@ -0,0 +1,26 @@
+#ifndef _ASM_CPU_SH7269_H_
+#define _ASM_CPU_SH7269_H_
+
+/* Cache */
+#define CCR1		0xFFFC1000
+#define CCR		CCR1
+
+/* SCIF */
+#define SCSMR_0		0xE8007000
+#define SCIF0_BASE	SCSMR_0
+#define SCSMR_1		0xE8007800
+#define SCIF1_BASE	SCSMR_1
+#define SCSMR_2		0xE8008000
+#define SCIF2_BASE	SCSMR_2
+#define SCSMR_3		0xE8008800
+#define SCIF3_BASE	SCSMR_3
+#define SCSMR_7		0xE800A800
+#define SCIF7_BASE	SCSMR_7
+
+/* Timer(CMT) */
+#define CMSTR		0xFFFEC000
+#define CMCSR_0		0xFFFEC002
+#define CMCNT_0		0xFFFEC004
+#define CMCOR_0		0xFFFEC006
+
+#endif	/* _ASM_CPU_SH7269_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7734.h b/arch/sh/include/asm/cpu_sh7734.h
new file mode 100644
index 0000000..0f84b4f
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7734.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2008, 2011 Renesas Solutions Corp.
+ *
+ * SH7734 Internal I/O register
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CPU_SH7734_H_
+#define _ASM_CPU_SH7734_H_
+
+#define CCR 0xFF00001C
+
+#define CACHE_OC_NUM_WAYS	4
+#define CCR_CACHE_INIT	0x0000090d
+
+/* SCIF */
+#define SCIF0_BASE  0xFFE40000
+#define SCIF1_BASE  0xFFE41000
+#define SCIF2_BASE  0xFFE42000
+#define SCIF3_BASE  0xFFE43000
+#define SCIF4_BASE  0xFFE44000
+#define SCIF5_BASE  0xFFE45000
+
+/* Timer */
+#define TSTR	0xFFD80004
+#define TCNT0	0xFFD8000C
+#define TCR0	0xFFD80010
+
+/* PFC */
+#define PMMR    (0xFFFC0000)
+#define MODESEL0    (0xFFFC004C)
+#define MODESEL2    (MODESEL0 + 0x4)
+#define MODESEL2_INIT   (0x00003000)
+
+#define IPSR0	(0xFFFC001C)
+#define IPSR1	(IPSR0 + 0x4)
+#define IPSR2	(IPSR0 + 0x8)
+#define IPSR3	(IPSR0 + 0xC)
+#define IPSR4	(IPSR0 + 0x10)
+#define IPSR5	(IPSR0 + 0x14)
+#define IPSR6	(IPSR0 + 0x18)
+#define IPSR7	(IPSR0 + 0x1C)
+#define IPSR8	(IPSR0 + 0x20)
+#define IPSR9	(IPSR0 + 0x24)
+#define IPSR10	(IPSR0 + 0x28)
+#define IPSR11	(IPSR0 + 0x2C)
+
+#define GPSR0	(0xFFFC0004)
+#define GPSR1	(GPSR0 + 0x4)
+#define GPSR2	(GPSR0 + 0x8)
+#define GPSR3	(GPSR0 + 0xC)
+#define GPSR4	(GPSR0 + 0x10)
+#define GPSR5	(GPSR0 + 0x14)
+
+
+#endif /* _ASM_CPU_SH7734_H_ */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index ca598a6..0a00db3 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -147,13 +147,13 @@
  */
 #ifdef iomem_valid_addr
 #define __arch_ioremap(off, sz, nocache)				\
- ({								\
+({								\
 	unsigned long _off = (off), _size = (sz);		\
 	void *_ret = (void *)0;					\
 	if (iomem_valid_addr(_off, _size))			\
 		_ret = __ioremap(iomem_to_phys(_off), _size, 0);	\
 	_ret;							\
- })
+})
 
 #define __arch_iounmap __iounmap
 #endif
@@ -238,6 +238,43 @@
 }
 
 /*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+		out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+		out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+		out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+/*
  * Given a physical address and a length, return a virtual address
  * that can be used to access the memory range with the caching
  * properties specified by "flags".
@@ -261,7 +298,7 @@
 
 }
 
-static inline phys_addr_t virt_to_phys(void * vaddr)
+static inline phys_addr_t virt_to_phys(void *vaddr)
 {
 	return (phys_addr_t)(vaddr);
 }
diff --git a/board/alphaproject/ap_sh4a_4a/Makefile b/board/alphaproject/ap_sh4a_4a/Makefile
new file mode 100644
index 0000000..0008c25
--- /dev/null
+++ b/board/alphaproject/ap_sh4a_4a/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ap_sh4a_4a.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
new file mode 100644
index 0000000..77cadea
--- /dev/null
+++ b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MODEMR			(0xFFCC0020)
+#define MODEMR_MASK		(0x6)
+#define MODEMR_533MHZ	(0x2)
+
+int checkboard(void)
+{
+	u32 r = readl(MODEMR);
+	if ((r & MODEMR_MASK) & MODEMR_533MHZ)
+		puts("CPU Clock: 533MHz\n");
+	else
+		puts("CPU Clock: 400MHz\n");
+
+	puts("BOARD: Alpha Project. AP-SH4A-4A\n");
+	return 0;
+}
+
+#define MSTPSR1			(0xFFC80044)
+#define MSTPCR1			(0xFFC80034)
+#define MSTPSR1_GETHER	(1 << 14)
+
+/* IPSR3 */
+#define ET0_ETXD0 (0x4 << 3)
+#define ET0_GTX_CLK_A (0x4 << 6)
+#define ET0_ETXD1_A (0x4 << 9)
+#define ET0_ETXD2_A (0x4 << 12)
+#define ET0_ETXD3_A (0x4 << 15)
+#define ET0_ETXD4 (0x3 << 18)
+#define ET0_ETXD5_A (0x5 << 21)
+#define ET0_ETXD6_A (0x5 << 24)
+#define ET0_ETXD7 (0x4 << 27)
+#define IPSR3_ETH_ENABLE \
+	(ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
+	ET0_ETXD3_A | ET0_ETXD4 | ET0_ETXD5_A | ET0_ETXD6_A | ET0_ETXD7)
+
+/* IPSR4 */
+#define ET0_ERXD7	(0x4)
+#define ET0_RX_DV	(0x4 << 3)
+#define ET0_RX_ER	(0x4 << 6)
+#define ET0_CRS		(0x4 << 9)
+#define ET0_COL		(0x4 << 12)
+#define ET0_MDC		(0x4 << 15)
+#define ET0_MDIO_A	(0x3 << 18)
+#define ET0_LINK_A	(0x3 << 20)
+#define ET0_PHY_INT_A (0x3 << 24)
+
+#define IPSR4_ETH_ENABLE \
+	(ET0_ERXD7 | ET0_RX_DV | ET0_RX_ER | ET0_CRS | ET0_COL | \
+	ET0_MDC | ET0_MDIO_A | ET0_LINK_A | ET0_PHY_INT_A)
+
+/* IPSR8 */
+#define ET0_ERXD0	(0x4 << 20)
+#define ET0_ERXD1	(0x4 << 23)
+#define ET0_ERXD2_A (0x3 << 26)
+#define ET0_ERXD3_A (0x3 << 28)
+#define IPSR8_ETH_ENABLE \
+	(ET0_ERXD0 | ET0_ERXD1 | ET0_ERXD2_A | ET0_ERXD3_A)
+
+/* IPSR10 */
+#define RX4_D	(0x1 << 22)
+#define TX4_D	(0x1 << 23)
+#define IPSR10_SCIF_ENABLE (RX4_D | TX4_D)
+
+/* IPSR11 */
+#define ET0_ERXD4	(0x4 <<  4)
+#define ET0_ERXD5	(0x4 <<  7)
+#define ET0_ERXD6	(0x4 <<  4)
+#define ET0_TX_EN	(0x2 << 19)
+#define ET0_TX_ER	(0x2 << 21)
+#define ET0_TX_CLK_A (0x4 << 23)
+#define ET0_RX_CLK_A (0x3 << 26)
+#define IPSR11_ETH_ENABLE \
+	(ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \
+	ET0_TX_CLK_A | ET0_RX_CLK_A)
+
+#define GPSR1_INIT (0xFFBF7FFF)
+#define GPSR2_INIT (0x4005FEFF)
+#define GPSR3_INIT (0x2EFFFFFF)
+#define GPSR4_INIT (0xC7000000)
+
+int board_init(void)
+{
+	u32 data;
+
+	/* Set IPSR register */
+	data = readl(IPSR3);
+	data |= IPSR3_ETH_ENABLE;
+	writel(~data, PMMR);
+	writel(data, IPSR3);
+
+	data = readl(IPSR4);
+	data |= IPSR4_ETH_ENABLE;
+	writel(~data, PMMR);
+	writel(data, IPSR4);
+
+	data = readl(IPSR8);
+	data |= IPSR8_ETH_ENABLE;
+	writel(~data, PMMR);
+	writel(data, IPSR8);
+
+	data = readl(IPSR10);
+	data |= IPSR10_SCIF_ENABLE;
+	writel(~data, PMMR);
+	writel(data, IPSR10);
+
+	data = readl(IPSR11);
+	data |= IPSR11_ETH_ENABLE;
+	writel(~data, PMMR);
+	writel(data, IPSR11);
+
+	/* GPIO select */
+	data = GPSR1_INIT;
+	writel(~data, PMMR);
+	writel(data, GPSR1);
+
+	data = GPSR2_INIT;
+	writel(~data, PMMR);
+	writel(data, GPSR2);
+
+	data = GPSR3_INIT;
+	writel(~data, PMMR);
+	writel(data, GPSR3);
+
+	data = GPSR4_INIT;
+	writel(~data, PMMR);
+	writel(data, GPSR4);
+
+	data = 0x0;
+	writel(~data, PMMR);
+	writel(data, GPSR5);
+
+	/* mode select */
+	data = MODESEL2_INIT;
+	writel(~data, PMMR);
+	writel(data, MODESEL2);
+
+#if defined(CONFIG_SH_ETHER)
+	u32 r = readl(MSTPSR1);
+	if (r & MSTPSR1_GETHER)
+		writel((r & ~MSTPSR1_GETHER), MSTPCR1);
+#endif
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u8 mac[6];
+
+	/* Read Mac Address and set*/
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
+
+	/* Read MAC address */
+	i2c_read(0x50, 0x0, 0, mac, 6);
+
+	if (is_valid_ether_addr(mac))
+		eth_setenv_enetaddr("ethaddr", mac);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+
+	return 0;
+}
diff --git a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
new file mode 100644
index 0000000..f04b36b
--- /dev/null
+++ b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
@@ -0,0 +1,459 @@
+/*
+ * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2011, 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+#include <asm/processor.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	/* WDT */
+	write32 WDTCSR_A, WDTCSR_D
+
+	/* MMU */
+	write32 MMUCR_A, MMUCR_D
+
+	write32 FRQCR2_A, FRQCR2_D
+	write32 FRQCR0_A, FRQCR0_D
+
+	write32 CS0CTRL_A, CS0CTRL_D
+	write32 CS1CTRL_A, CS1CTRL_D
+	write32 CS0CTRL2_A, CS0CTRL2_D
+
+	write32 CSPWCR0_A, CSPWCR0_D
+	write32 CSPWCR1_A, CSPWCR1_D
+	write32 CS1GDST_A, CS1GDST_D
+
+	# clock mode check
+	mov.l   MODEMR, r1
+	mov.l   @r1, r0
+	and		#6, r0 /* Check 1 and 2 bit.*/
+	cmp/eq  #2, r0 /* 0x02 is 533Mhz mode */
+	bt      init_lbsc_533
+
+init_lbsc_400:
+
+	write32 CSWCR0_A, CSWCR0_D_400
+	write32 CSWCR1_A, CSWCR1_D
+
+	bra	init_dbsc3_400_pad
+	nop
+
+	.align 2
+
+MODEMR:		.long	0xFFCC0020
+WDTCSR_A:	.long	0xFFCC0004
+WDTCSR_D:	.long	0xA5000000
+MMUCR_A:	.long	0xFF000010
+MMUCR_D:	.long	0x00000004
+
+FRQCR2_A:	.long	0xFFC80008
+FRQCR2_D:	.long	0x00000000
+FRQCR0_A:	.long	0xFFC80000
+FRQCR0_D:	.long	0xCF000001
+
+CS0CTRL_A:	.long	0xFF800200
+CS0CTRL_D:	.long	0x00000020
+CS1CTRL_A:	.long	0xFF800204
+CS1CTRL_D:	.long	0x00000020
+
+CS0CTRL2_A:	.long	0xFF800220
+CS0CTRL2_D:	.long	0x00004000
+
+CSPWCR0_A:	.long	0xFF800280
+CSPWCR0_D:	.long	0x00000000
+CSPWCR1_A:	.long	0xFF800284
+CSPWCR1_D:	.long	0x00000000
+CS1GDST_A:	.long	0xFF8002C0
+CS1GDST_D:	.long	0x00000011
+
+init_lbsc_533:
+
+	write32 CSWCR0_A, CSWCR0_D_533
+	write32 CSWCR1_A, CSWCR1_D
+
+	bra	init_dbsc3_533_pad
+	nop
+
+	.align 2
+
+CSWCR0_A:	.long	0xFF800230
+CSWCR0_D_533:	.long	0x01120104
+CSWCR0_D_400:	.long	0x02120114
+CSWCR1_A:	.long	0xFF800234
+CSWCR1_D:	.long	0x077F077F
+
+init_dbsc3_400_pad:
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D
+	wait_timer	WAIT_200US_400
+
+	write32 DBPDCNT0_A,	DBPDCNT0_D_400
+	write32 DBPDCNT3_A,	DBPDCNT3_D0
+	write32 DBPDCNT1_A,	DBPDCNT1_D
+
+	write32 DBPDCNT3_A,	DBPDCNT3_D1
+	wait_timer WAIT_32MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D2
+	wait_timer WAIT_100US_400
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D3
+	wait_timer WAIT_16MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D4
+	wait_timer WAIT_200US_400
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D5
+	wait_timer WAIT_1MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D6
+	wait_timer WAIT_10KMCLK
+
+	bra init_dbsc3_ctrl_400
+	nop
+
+	.align 2
+
+init_dbsc3_533_pad:
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D
+	wait_timer	WAIT_200US_533
+
+	write32 DBPDCNT0_A,	DBPDCNT0_D_533
+	write32 DBPDCNT3_A,	DBPDCNT3_D0
+	write32 DBPDCNT1_A,	DBPDCNT1_D
+
+	write32 DBPDCNT3_A,	DBPDCNT3_D1
+	wait_timer WAIT_32MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D2
+	wait_timer WAIT_100US_533
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D3
+	wait_timer WAIT_16MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D4
+	wait_timer WAIT_200US_533
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D5
+	wait_timer WAIT_1MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D6
+	wait_timer	WAIT_10KMCLK
+
+	bra init_dbsc3_ctrl_533
+	nop
+
+	.align 2
+
+WAIT_200US_400:	.long	40000
+WAIT_200US_533:	.long	53300
+WAIT_100US_400:	.long	20000
+WAIT_100US_533:	.long	26650
+WAIT_32MCLK:	.long	32
+WAIT_16MCLK:	.long	16
+WAIT_1MCLK:		.long	1
+WAIT_10KMCLK:	.long	10000
+
+DBPDCNT0_A:		.long	0xFE800200
+DBPDCNT0_D_533:	.long	0x00010245
+DBPDCNT0_D_400:	.long	0x00010235
+DBPDCNT1_A:		.long	0xFE800204
+DBPDCNT1_D:		.long	0x00000014
+DBPDCNT3_A:		.long	0xFE80020C
+DBPDCNT3_D:		.long	0x80000000
+DBPDCNT3_D0:	.long	0x800F0000
+DBPDCNT3_D1:	.long	0x800F1000
+DBPDCNT3_D2:	.long	0x820F1000
+DBPDCNT3_D3:	.long	0x860F1000
+DBPDCNT3_D4:	.long	0x870F1000
+DBPDCNT3_D5:	.long	0x870F3000
+DBPDCNT3_D6:	.long	0x870F7000
+
+init_dbsc3_ctrl_400:
+
+	write32 DBKIND_A, DBKIND_D
+	write32 DBCONF_A, DBCONF_D
+
+	write32 DBTR0_A,	DBTR0_D_400
+	write32 DBTR1_A,	DBTR1_D_400
+	write32 DBTR2_A,	DBTR2_D
+	write32 DBTR3_A,	DBTR3_D_400
+	write32 DBTR4_A,	DBTR4_D_400
+	write32 DBTR5_A,	DBTR5_D_400
+	write32 DBTR6_A,	DBTR6_D_400
+	write32 DBTR7_A,	DBTR7_D
+	write32 DBTR8_A,	DBTR8_D_400
+	write32 DBTR9_A,	DBTR9_D
+	write32 DBTR10_A,	DBTR10_D_400
+	write32 DBTR11_A,	DBTR11_D
+	write32 DBTR12_A,	DBTR12_D_400
+	write32 DBTR13_A,	DBTR13_D_400
+	write32 DBTR14_A,	DBTR14_D
+	write32 DBTR15_A,	DBTR15_D
+	write32 DBTR16_A,	DBTR16_D_400
+	write32 DBTR17_A,	DBTR17_D_400
+	write32 DBTR18_A,	DBTR18_D_400
+
+	write32	DBBL_A,	DBBL_D
+	write32	DBRNK0_A,	DBRNK0_D
+
+	write32 DBCMD_A,	DBCMD_D0_400
+	write32 DBCMD_A,	DBCMD_D1
+	write32 DBCMD_A,	DBCMD_D2
+	write32 DBCMD_A,	DBCMD_D3
+	write32 DBCMD_A,	DBCMD_D4
+	write32 DBCMD_A,	DBCMD_D5_400
+	write32 DBCMD_A,	DBCMD_D6
+	write32 DBCMD_A,	DBCMD_D7
+	write32 DBCMD_A,	DBCMD_D8
+	write32 DBCMD_A,	DBCMD_D9_400
+	write32 DBCMD_A,	DBCMD_D10
+	write32 DBCMD_A,	DBCMD_D11
+	write32 DBCMD_A,	DBCMD_D12
+
+	write32	DBRFCNF0_A,	DBRFCNF0_D
+	write32	DBRFCNF1_A,	DBRFCNF1_D_400
+	write32	DBRFCNF2_A,	DBRFCNF2_D
+	write32	DBRFEN_A,	DBRFEN_D
+	write32	DBACEN_A,	DBACEN_D
+	write32	DBACEN_A,	DBACEN_D
+
+	/* Dummy read */
+	mov.l DBWAIT_A, r1
+	synco
+	mov.l @r1, r0
+	synco
+
+	/* Dummy read */
+	mov.l SDRAM_A, r1
+	synco
+	mov.l @r1, r0
+	synco
+
+	/* need sleep 186A0 */
+
+	bra	finish_init_sh7734
+	nop
+
+	.align 2
+
+init_dbsc3_ctrl_533:
+
+	write32 DBKIND_A, DBKIND_D
+	write32 DBCONF_A, DBCONF_D
+
+	write32 DBTR0_A,	DBTR0_D_533
+	write32 DBTR1_A,	DBTR1_D_533
+	write32 DBTR2_A,	DBTR2_D
+	write32 DBTR3_A,	DBTR3_D_533
+	write32 DBTR4_A,	DBTR4_D_533
+	write32 DBTR5_A,	DBTR5_D_533
+	write32 DBTR6_A,	DBTR6_D_533
+	write32 DBTR7_A,	DBTR7_D
+	write32 DBTR8_A,	DBTR8_D_533
+	write32 DBTR9_A,	DBTR9_D
+	write32 DBTR10_A,	DBTR10_D_533
+	write32 DBTR11_A,	DBTR11_D
+	write32 DBTR12_A,	DBTR12_D_533
+	write32 DBTR13_A,	DBTR13_D_533
+	write32 DBTR14_A,	DBTR14_D
+	write32 DBTR15_A,	DBTR15_D
+	write32 DBTR16_A,	DBTR16_D_533
+	write32 DBTR17_A,	DBTR17_D_533
+	write32 DBTR18_A,	DBTR18_D_533
+
+	write32	DBBL_A,	DBBL_D
+	write32	DBRNK0_A,	DBRNK0_D
+
+	write32 DBCMD_A,	DBCMD_D0_533
+	write32 DBCMD_A,	DBCMD_D1
+	write32 DBCMD_A,	DBCMD_D2
+	write32 DBCMD_A,	DBCMD_D3
+	write32 DBCMD_A,	DBCMD_D4
+	write32 DBCMD_A,	DBCMD_D5_533
+	write32 DBCMD_A,	DBCMD_D6
+	write32 DBCMD_A,	DBCMD_D7
+	write32 DBCMD_A,	DBCMD_D8
+	write32 DBCMD_A,	DBCMD_D9_533
+	write32 DBCMD_A,	DBCMD_D10
+	write32 DBCMD_A,	DBCMD_D11
+	write32 DBCMD_A,	DBCMD_D12
+
+	write32	DBRFCNF0_A,	DBRFCNF0_D
+	write32	DBRFCNF1_A,	DBRFCNF1_D_533
+	write32	DBRFCNF2_A,	DBRFCNF2_D
+	write32	DBRFEN_A,	DBRFEN_D
+	write32	DBACEN_A,	DBACEN_D
+	write32	DBACEN_A,	DBACEN_D
+
+	/* Dummy read */
+	mov.l DBWAIT_A, r1
+	synco
+	mov.l @r1, r0
+	synco
+
+	/* Dummy read */
+	mov.l SDRAM_A, r1
+	synco
+	mov.l @r1, r0
+	synco
+
+	/* need sleep 186A0 */
+
+	bra	finish_init_sh7734
+	nop
+
+	.align 2
+
+DBKIND_A:	.long	0xFE800020
+DBKIND_D:	.long	0x00000005
+DBCONF_A:	.long	0xFE800024
+DBCONF_D:	.long	0x0D020901
+
+DBTR0_A:	.long	0xFE800040
+DBTR0_D_533:.long	0x00000004
+DBTR0_D_400:.long	0x00000003
+DBTR1_A:	.long	0xFE800044
+DBTR1_D_533:.long	0x00000003
+DBTR1_D_400:.long	0x00000002
+DBTR2_A:	.long	0xFE800048
+DBTR2_D:	.long	0x00000000
+DBTR3_A:	.long	0xFE800050
+DBTR3_D_533:.long	0x00000004
+DBTR3_D_400:.long	0x00000003
+
+DBTR4_A:	.long	0xFE800054
+DBTR4_D_533:.long	0x00050004
+DBTR4_D_400:.long	0x00050003
+
+DBTR5_A:	.long	0xFE800058
+DBTR5_D_533:.long	0x0000000F
+DBTR5_D_400:.long	0x0000000B
+
+DBTR6_A:	.long	0xFE80005C
+DBTR6_D_533:.long	0x0000000B
+DBTR6_D_400:.long	0x00000008
+
+DBTR7_A:	.long	0xFE800060
+DBTR7_D:	.long	0x00000002
+
+DBTR8_A:	.long	0xFE800064
+DBTR8_D_533:.long	0x0000000D
+DBTR8_D_400:.long	0x0000000A
+
+DBTR9_A:	.long	0xFE800068
+DBTR9_D:	.long	0x00000002
+
+DBTR10_A:	.long	0xFE80006C
+DBTR10_D_533:.long	0x00000004
+DBTR10_D_400:.long	0x00000003
+
+DBTR11_A:	.long	0xFE800070
+DBTR11_D:	.long	0x00000008
+
+DBTR12_A:	.long	0xFE800074
+DBTR12_D_533:.long	0x00000009
+DBTR12_D_400:.long	0x00000008
+
+DBTR13_A:	.long	0xFE800078
+DBTR13_D_533:.long	0x00000022
+DBTR13_D_400:.long	0x0000001A
+
+DBTR14_A:	.long	0xFE80007C
+DBTR14_D:	.long	0x00070002
+
+DBTR15_A:	.long	0xFE800080
+DBTR15_D:	.long	0x00000003
+
+DBTR16_A:	.long	0xFE800084
+DBTR16_D_533:.long	0x120A1001
+DBTR16_D_400:.long	0x12091001
+
+DBTR17_A:	.long	0xFE800088
+DBTR17_D_533:.long	0x00040000
+DBTR17_D_400:.long	0x00030000
+
+DBTR18_A:	.long	0xFE80008C
+DBTR18_D_533:.long	0x02010200
+DBTR18_D_400:.long	0x02000207
+
+DBBL_A:	.long	0xFE8000B0
+DBBL_D:	.long	0x00000000
+
+DBRNK0_A:		.long	0xFE800100
+DBRNK0_D:		.long	0x00000001
+
+DBCMD_A:		.long	0xFE800018
+DBCMD_D0_533:	.long	0x1100006B
+DBCMD_D0_400:	.long	0x11000050
+DBCMD_D1:		.long	0x0B000000
+DBCMD_D2:		.long	0x2A004000
+DBCMD_D3:		.long	0x2B006000
+DBCMD_D4:		.long	0x29002044
+DBCMD_D5_533:	.long	0x28000743
+DBCMD_D5_400:	.long	0x28000533
+DBCMD_D6:		.long	0x0B000000
+DBCMD_D7:		.long	0x0C000000
+DBCMD_D8:		.long	0x0C000000
+DBCMD_D9_533:	.long	0x28000643
+DBCMD_D9_400:	.long	0x28000433
+DBCMD_D10:		.long	0x000000C8
+DBCMD_D11:		.long	0x290023C4
+DBCMD_D12:		.long	0x29002004
+
+DBRFCNF0_A:		.long	0xFE8000E0
+DBRFCNF0_D:		.long	0x000001FF
+DBRFCNF1_A:		.long	0xFE8000E4
+DBRFCNF1_D_533:	.long	0x00000805
+DBRFCNF1_D_400:	.long	0x00000618
+
+DBRFCNF2_A:		.long	0xFE8000E8
+DBRFCNF2_D:		.long	0x00000000
+
+DBRFEN_A:		.long	0xFE800014
+DBRFEN_D:		.long	0x00000001
+
+DBACEN_A:		.long	0xFE800010
+DBACEN_D:		.long	0x00000001
+
+DBWAIT_A:		.long	0xFE80001C
+SDRAM_A:		.long	0x0C000000
+
+finish_init_sh7734:
+	write32 CCR_A,  CCR_D
+
+	stc sr, r0
+	mov.l  SR_MASK_D, r1
+	and r1, r0
+	ldc r0, sr
+
+	rts
+	nop
+
+	.align  2
+
+CCR_A:	.long	0xFF00001C
+CCR_D:	.long	0x0000090B
+SR_MASK_D:	.long	0xEFFFFF0F
diff --git a/board/in-circuit/grasshopper/grasshopper.c b/board/in-circuit/grasshopper/grasshopper.c
index 475a759..222fe43 100644
--- a/board/in-circuit/grasshopper/grasshopper.c
+++ b/board/in-circuit/grasshopper/grasshopper.c
@@ -72,6 +72,13 @@
 	portmux_enable_usart0(PORTMUX_DRIVE_MIN);
 	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
 #if defined(CONFIG_MACB)
+	/* set PHY reset and pwrdown to low */
+	portmux_select_gpio(PORTMUX_PORT_B, (1 << 29) | (1 << 30),
+		PORTMUX_DIR_OUTPUT | PORTMUX_INIT_LOW);
+	udelay(100);
+	/* release PHYs reset */
+	gpio_set_value(GPIO_PIN_PB(29), 1);
+
 	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
 #endif
 
diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile
new file mode 100644
index 0000000..b8c0353
--- /dev/null
+++ b/board/renesas/r0p7734/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= r0p7734.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/renesas/r0p7734/lowlevel_init.S b/board/renesas/r0p7734/lowlevel_init.S
new file mode 100644
index 0000000..1a7f1ac
--- /dev/null
+++ b/board/renesas/r0p7734/lowlevel_init.S
@@ -0,0 +1,606 @@
+/*
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+#include <asm/processor.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+
+	/* WDT */
+	write32 WDTCSR_A, WDTCSR_D
+
+	/* MMU */
+	write32 MMUCR_A, MMUCR_D
+
+	write32 FRQCR2_A, FRQCR2_D
+	write32 FRQCR0_A, FRQCR0_D
+
+	write32 CS0CTRL_A, CS0CTRL_D
+	write32 CS1CTRL_A, CS1CTRL_D
+	write32 CS0CTRL2_A, CS0CTRL2_D
+
+	write32 CSPWCR0_A, CSPWCR0_D
+	write32 CSPWCR1_A, CSPWCR1_D
+	write32 CS1GDST_A, CS1GDST_D
+
+	# clock mode check
+	mov.l   MODEMR, r1
+	mov.l   @r1, r0
+	and		#6, r0 /* Check 1 and 2 bit.*/
+	cmp/eq  #2, r0 /* 0x02 is 533Mhz mode */
+	bt      init_lbsc_533
+
+init_lbsc_400:
+
+	write32 CSWCR0_A, CSWCR0_D_400
+	write32 CSWCR1_A, CSWCR1_D
+
+	bra	init_dbsc3_400_pad
+	nop
+
+	.align 2
+
+MODEMR:		.long	0xFFCC0020
+WDTCSR_A:	.long	0xFFCC0004
+WDTCSR_D:	.long	0xA5000000
+MMUCR_A:	.long	0xFF000010
+MMUCR_D:	.long	0x00000004
+
+FRQCR2_A:	.long	0xFFC80008
+FRQCR2_D:	.long	0x00000000
+FRQCR0_A:	.long	0xFFC80000
+FRQCR0_D:	.long	0xCF000001
+
+CS0CTRL_A:	.long	0xFF800200
+CS0CTRL_D:	.long	0x00000020
+CS1CTRL_A:	.long	0xFF800204
+CS1CTRL_D:	.long	0x00000020
+
+CS0CTRL2_A:	.long	0xFF800220
+CS0CTRL2_D:	.long	0x00004000
+
+CSPWCR0_A:	.long	0xFF800280
+CSPWCR0_D:	.long	0x00000000
+CSPWCR1_A:	.long	0xFF800284
+CSPWCR1_D:	.long	0x00000000
+CS1GDST_A:	.long	0xFF8002C0
+CS1GDST_D:	.long	0x00000011
+
+init_lbsc_533:
+
+	write32 CSWCR0_A, CSWCR0_D_533
+	write32 CSWCR1_A, CSWCR1_D
+
+	bra	init_dbsc3_533_pad
+	nop
+
+	.align 2
+
+CSWCR0_A:	.long	0xFF800230
+CSWCR0_D_533:	.long	0x01120104
+CSWCR0_D_400:	.long	0x02120114
+/* CSWCR0_D_400:	.long	0x01160116 */
+CSWCR1_A:	.long	0xFF800234
+CSWCR1_D:	.long	0x077F077F
+/* CSWCR1_D_400:	.long	0x00120012 */
+
+init_dbsc3_400_pad:
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D
+	wait_timer	WAIT_200US_400
+
+	write32 DBPDCNT0_A,	DBPDCNT0_D_400
+	write32 DBPDCNT3_A,	DBPDCNT3_D0
+	write32 DBPDCNT1_A,	DBPDCNT1_D
+
+	write32 DBPDCNT3_A,	DBPDCNT3_D1
+	wait_timer WAIT_32MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D2
+	wait_timer WAIT_100US_400
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D3
+	wait_timer WAIT_16MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D4
+	wait_timer WAIT_200US_400
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D5
+	wait_timer WAIT_1MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D6
+	wait_timer WAIT_10KMCLK
+
+	bra init_dbsc3_ctrl_400
+	nop
+
+	.align 2
+
+init_dbsc3_533_pad:
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D
+	wait_timer	WAIT_200US_533
+
+	write32 DBPDCNT0_A,	DBPDCNT0_D_533
+	write32 DBPDCNT3_A,	DBPDCNT3_D0
+	write32 DBPDCNT1_A,	DBPDCNT1_D
+
+	write32 DBPDCNT3_A,	DBPDCNT3_D1
+	wait_timer WAIT_32MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D2
+	wait_timer WAIT_100US_533
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D3
+	wait_timer WAIT_16MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D4
+	wait_timer WAIT_200US_533
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D5
+	wait_timer WAIT_1MCLK
+
+	write32	DBPDCNT3_A,	DBPDCNT3_D6
+	wait_timer	WAIT_10KMCLK
+
+	bra init_dbsc3_ctrl_533
+	nop
+
+	.align 2
+
+WAIT_200US_400:	.long	40000
+WAIT_200US_533:	.long	53300
+WAIT_100US_400:	.long	20000
+WAIT_100US_533:	.long	26650
+WAIT_32MCLK:	.long	32
+WAIT_16MCLK:	.long	16
+WAIT_1MCLK:		.long	1
+WAIT_10KMCLK:	.long	10000
+
+DBPDCNT0_A:		.long	0xFE800200
+DBPDCNT0_D_533:	.long	0x00010245
+DBPDCNT0_D_400:	.long	0x00010235
+DBPDCNT1_A:		.long	0xFE800204
+DBPDCNT1_D:		.long	0x00000014
+DBPDCNT3_A:		.long	0xFE80020C
+DBPDCNT3_D:		.long	0x80000000
+DBPDCNT3_D0:	.long	0x800F0000
+DBPDCNT3_D1:	.long	0x800F1000
+DBPDCNT3_D2:	.long	0x820F1000
+DBPDCNT3_D3:	.long	0x860F1000
+DBPDCNT3_D4:	.long	0x870F1000
+DBPDCNT3_D5:	.long	0x870F3000
+DBPDCNT3_D6:	.long	0x870F7000
+
+init_dbsc3_ctrl_400:
+
+	write32 DBKIND_A, DBKIND_D
+	write32 DBCONF_A, DBCONF_D
+
+	write32 DBTR0_A,	DBTR0_D_400
+	write32 DBTR1_A,	DBTR1_D_400
+	write32 DBTR2_A,	DBTR2_D
+	write32 DBTR3_A,	DBTR3_D_400
+	write32 DBTR4_A,	DBTR4_D_400
+	write32 DBTR5_A,	DBTR5_D_400
+	write32 DBTR6_A,	DBTR6_D_400
+	write32 DBTR7_A,	DBTR7_D
+	write32 DBTR8_A,	DBTR8_D_400
+	write32 DBTR9_A,	DBTR9_D
+	write32 DBTR10_A,	DBTR10_D_400
+	write32 DBTR11_A,	DBTR11_D
+	write32 DBTR12_A,	DBTR12_D_400
+	write32 DBTR13_A,	DBTR13_D_400
+	write32 DBTR14_A,	DBTR14_D
+	write32 DBTR15_A,	DBTR15_D
+	write32 DBTR16_A,	DBTR16_D_400
+	write32 DBTR17_A,	DBTR17_D_400
+	write32 DBTR18_A,	DBTR18_D_400
+
+	write32	DBBL_A,	DBBL_D
+	write32	DBRNK0_A,	DBRNK0_D
+
+	write32 DBCMD_A,	DBCMD_D0_400
+	write32 DBCMD_A,	DBCMD_D1
+	write32 DBCMD_A,	DBCMD_D2
+	write32 DBCMD_A,	DBCMD_D3
+	write32 DBCMD_A,	DBCMD_D4
+	write32 DBCMD_A,	DBCMD_D5_400
+	write32 DBCMD_A,	DBCMD_D6
+	write32 DBCMD_A,	DBCMD_D7
+	write32 DBCMD_A,	DBCMD_D8
+	write32 DBCMD_A,	DBCMD_D9_400
+	write32 DBCMD_A,	DBCMD_D10
+	write32 DBCMD_A,	DBCMD_D11
+	write32 DBCMD_A,	DBCMD_D12
+
+	write32 DBBS0CNT1_A,	DBBS0CNT1_D
+	write32 DBPDNCNF_A,		DBPDNCNF_D
+
+	write32	DBRFCNF0_A,	DBRFCNF0_D
+	write32	DBRFCNF1_A,	DBRFCNF1_D_400
+	write32	DBRFCNF2_A,	DBRFCNF2_D
+	write32	DBRFEN_A,	DBRFEN_D
+	write32	DBACEN_A,	DBACEN_D
+	write32	DBACEN_A,	DBACEN_D
+
+	/* Dummy read */
+	mov.l DBWAIT_A, r1
+	synco
+	mov.l @r1, r0
+	synco
+
+	/* Dummy read */
+	mov.l SDRAM_A, r1
+	synco
+	mov.l @r1, r0
+	synco
+
+	/* need sleep 186A0 */
+
+	bra	init_pfc_sh7734
+	nop
+
+	.align 2
+
+init_dbsc3_ctrl_533:
+
+	write32 DBKIND_A, DBKIND_D
+	write32 DBCONF_A, DBCONF_D
+
+	write32 DBTR0_A,	DBTR0_D_533
+	write32 DBTR1_A,	DBTR1_D_533
+	write32 DBTR2_A,	DBTR2_D
+	write32 DBTR3_A,	DBTR3_D_533
+	write32 DBTR4_A,	DBTR4_D_533
+	write32 DBTR5_A,	DBTR5_D_533
+	write32 DBTR6_A,	DBTR6_D_533
+	write32 DBTR7_A,	DBTR7_D
+	write32 DBTR8_A,	DBTR8_D_533
+	write32 DBTR9_A,	DBTR9_D
+	write32 DBTR10_A,	DBTR10_D_533
+	write32 DBTR11_A,	DBTR11_D
+	write32 DBTR12_A,	DBTR12_D_533
+	write32 DBTR13_A,	DBTR13_D_533
+	write32 DBTR14_A,	DBTR14_D
+	write32 DBTR15_A,	DBTR15_D
+	write32 DBTR16_A,	DBTR16_D_533
+	write32 DBTR17_A,	DBTR17_D_533
+	write32 DBTR18_A,	DBTR18_D_533
+
+	write32	DBBL_A,	DBBL_D
+	write32	DBRNK0_A,	DBRNK0_D
+
+	write32 DBCMD_A,	DBCMD_D0_533
+	write32 DBCMD_A,	DBCMD_D1
+	write32 DBCMD_A,	DBCMD_D2
+	write32 DBCMD_A,	DBCMD_D3
+	write32 DBCMD_A,	DBCMD_D4
+	write32 DBCMD_A,	DBCMD_D5_533
+	write32 DBCMD_A,	DBCMD_D6
+	write32 DBCMD_A,	DBCMD_D7
+	write32 DBCMD_A,	DBCMD_D8
+	write32 DBCMD_A,	DBCMD_D9_533
+	write32 DBCMD_A,	DBCMD_D10
+	write32 DBCMD_A,	DBCMD_D11
+	write32 DBCMD_A,	DBCMD_D12
+
+	write32 DBBS0CNT1_A,	DBBS0CNT1_D
+	write32 DBPDNCNF_A,		DBPDNCNF_D
+
+	write32	DBRFCNF0_A,	DBRFCNF0_D
+	write32	DBRFCNF1_A,	DBRFCNF1_D_533
+	write32	DBRFCNF2_A,	DBRFCNF2_D
+	write32	DBRFEN_A,	DBRFEN_D
+	write32	DBACEN_A,	DBACEN_D
+	write32	DBACEN_A,	DBACEN_D
+
+	/* Dummy read */
+	mov.l DBWAIT_A, r1
+	synco
+	mov.l @r1, r0
+	synco
+
+	/* Dummy read */
+	mov.l SDRAM_A, r1
+	synco
+	mov.l @r1, r0
+	synco
+
+	/* need sleep 186A0 */
+
+	bra	init_pfc_sh7734
+	nop
+
+	.align 2
+
+DBKIND_A:	.long	0xFE800020
+DBKIND_D:	.long	0x00000005
+DBCONF_A:	.long	0xFE800024
+DBCONF_D:	.long	0x0D030A01
+
+DBTR0_A:	.long	0xFE800040
+DBTR0_D_533:.long	0x00000004
+DBTR0_D_400:.long	0x00000003
+DBTR1_A:	.long	0xFE800044
+DBTR1_D_533:.long	0x00000003
+DBTR1_D_400:.long	0x00000002
+DBTR2_A:	.long	0xFE800048
+DBTR2_D:	.long	0x00000000
+DBTR3_A:	.long	0xFE800050
+DBTR3_D_533:.long	0x00000004
+DBTR3_D_400:.long	0x00000003
+
+DBTR4_A:	.long	0xFE800054
+DBTR4_D_533:.long	0x00050004
+DBTR4_D_400:.long	0x00050003
+
+DBTR5_A:	.long	0xFE800058
+DBTR5_D_533:.long	0x0000000F
+DBTR5_D_400:.long	0x0000000B
+
+DBTR6_A:	.long	0xFE80005C
+DBTR6_D_533:.long	0x0000000B
+DBTR6_D_400:.long	0x00000008
+
+DBTR7_A:	.long	0xFE800060
+DBTR7_D:	.long	0x00000002 /* common value */
+
+DBTR8_A:	.long	0xFE800064
+DBTR8_D_533:.long	0x0000000D
+DBTR8_D_400:.long	0x0000000A
+
+DBTR9_A:	.long	0xFE800068
+DBTR9_D:	.long	0x00000002 /* common value */
+
+DBTR10_A:	.long	0xFE80006C
+DBTR10_D_533:.long	0x00000004
+DBTR10_D_400:.long	0x00000003
+
+DBTR11_A:	.long	0xFE800070
+DBTR11_D:	.long	0x00000008 /* common value */
+
+DBTR12_A:	.long	0xFE800074
+DBTR12_D_533:.long	0x00000009
+DBTR12_D_400:.long	0x00000008
+
+DBTR13_A:	.long	0xFE800078
+DBTR13_D_533:.long	0x00000022
+DBTR13_D_400:.long	0x0000001A
+
+DBTR14_A:	.long	0xFE80007C
+DBTR14_D:	.long	0x00070002 /* common value */
+
+DBTR15_A:	.long	0xFE800080
+DBTR15_D:	.long	0x00000003 /* common value */
+
+DBTR16_A:	.long	0xFE800084
+DBTR16_D_533:.long	0x120A1001
+DBTR16_D_400:.long	0x12091001
+
+DBTR17_A:	.long	0xFE800088
+DBTR17_D_533:.long	0x00040000
+DBTR17_D_400:.long	0x00030000
+
+DBTR18_A:	.long	0xFE80008C
+DBTR18_D_533:.long	0x02010200
+DBTR18_D_400:.long	0x02000207
+
+DBBL_A:	.long	0xFE8000B0
+DBBL_D:	.long	0x00000000
+
+DBRNK0_A:		.long	0xFE800100
+DBRNK0_D:		.long	0x00000001
+
+DBCMD_A:		.long	0xFE800018
+DBCMD_D0_533:	.long	0x1100006B
+DBCMD_D0_400:	.long	0x11000050
+DBCMD_D1:		.long	0x0B000000 /* common value */
+DBCMD_D2:		.long	0x2A004000 /* common value */
+DBCMD_D3:		.long	0x2B006000 /* common value */
+DBCMD_D4:		.long	0x29002004 /* common value */
+DBCMD_D5_533:	.long	0x28000743
+DBCMD_D5_400:	.long	0x28000533
+DBCMD_D6:		.long	0x0B000000 /* common value */
+DBCMD_D7:		.long	0x0C000000 /* common value */
+DBCMD_D8:		.long	0x0C000000 /* common value */
+DBCMD_D9_533:	.long	0x28000643
+DBCMD_D9_400:	.long	0x28000433
+DBCMD_D10:		.long	0x000000C8 /* common value */
+DBCMD_D11:		.long	0x29002384 /* common value */
+DBCMD_D12:		.long	0x29002004 /* common value */
+
+DBBS0CNT1_A:	.long	0xFE800304
+DBBS0CNT1_D:	.long	0x00000000
+DBPDNCNF_A:		.long	0xFE800180
+DBPDNCNF_D:		.long	0x00000200
+
+DBRFCNF0_A:		.long	0xFE8000E0
+DBRFCNF0_D:		.long	0x000001FF
+DBRFCNF1_A:		.long	0xFE8000E4
+DBRFCNF1_D_533:	.long	0x00000805
+DBRFCNF1_D_400:	.long	0x00000618
+
+DBRFCNF2_A:		.long	0xFE8000E8
+DBRFCNF2_D:		.long	0x00000000
+
+DBRFEN_A:		.long	0xFE800014
+DBRFEN_D:		.long	0x00000001
+
+DBACEN_A:		.long	0xFE800010
+DBACEN_D:		.long	0x00000001
+
+DBWAIT_A:		.long	0xFE80001C
+SDRAM_A:		.long	0x0C000000
+
+init_pfc_sh7734:
+	write32	PFC_PMMR_A, PFC_PMMR_MODESEL1
+	write32 PFC_MODESEL1_A, PFC_MODESEL1_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_MODESEL2
+	write32 PFC_MODESEL2_A, PFC_MODESEL2_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_IPSR3
+	write32 PFC_IPSR3_A, PFC_IPSR3_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_IPSR4
+	write32 PFC_IPSR4_A, PFC_IPSR4_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_IPSR11
+	write32 PFC_IPSR11_A, PFC_IPSR11_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_GPSR0
+	write32 PFC_GPSR0_A, PFC_GPSR0_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_GPSR1
+	write32 PFC_GPSR1_A, PFC_GPSR1_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_GPSR2
+	write32 PFC_GPSR2_A, PFC_GPSR2_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_GPSR3
+	write32 PFC_GPSR3_A, PFC_GPSR3_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_GPSR4
+	write32 PFC_GPSR4_A, PFC_GPSR4_D
+
+	write32	PFC_PMMR_A, PFC_PMMR_GPSR5
+	write32 PFC_GPSR5_A, PFC_GPSR5_D
+
+	/* sleep 186A0 */
+
+	write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D
+	write32 GPIO1_OUTDT1_A,	GPIO1_OUTDT1_D
+	write32	GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D
+	write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D
+	write32 GPIO4_INOUTSEL4_A,	GPIO4_INOUTSEL4_D
+	write32 GPIO4_OUTDT4_A,	GPIO4_OUTDT4_D
+
+	write32 CCR_A,  CCR_D
+
+	stc sr, r0
+	mov.l  SR_MASK_D, r1
+	and r1, r0
+	ldc r0, sr
+
+	rts
+	nop
+
+	.align  2
+
+PFC_PMMR_A:		.long	0xFFFC0000
+
+/* MODESEL
+ * 28: Select IEBUS Group B
+ */
+PFC_MODESEL1_A:	.long	0xFFFC004C
+PFC_MODESEL1_D:	.long	0x10000000
+PFC_PMMR_MODESEL1:	.long	0xEFFFFFFF
+
+/* MODESEL
+ * 9: Select SCIF3 Group B
+ * 7: Select SCIF2 Group B
+ * 4: Select SCIF1 Group B
+ */
+PFC_MODESEL2_A:	.long	0xFFFC0050
+PFC_MODESEL2_D:	.long	0x00000290
+PFC_PMMR_MODESEL2:	.long	0xFFFFFD6F
+
+# Enable functios
+# SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A,
+# EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A,
+# SD1_CD_A, TX3_B, RX3_B, CS1, D15
+PFC_IPSR3_A:	.long	0xFFFC0028
+PFC_IPSR3_D:	.long	0x09209248
+PFC_PMMR_IPSR3:	.long	0xF6DF6DB7
+
+# Enable functios
+# RMII0_MDIO_A , RMII0_MDC_A,
+# RMII0_CRS_DV_A, RMII0_RX_ER_A,
+# RMII0_TXD_EN_A, MII0_RXD1_A
+PFC_IPSR4_A:	.long	0xFFFC002C
+PFC_IPSR4_D:	.long	0x0001B6DB
+PFC_PMMR_IPSR4:	.long	0xFFFE4924
+
+# Enable functios
+# DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B,
+# IETX_B, TX0_A, RMII0_TXD0_A,
+# RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1
+PFC_IPSR11_A:	.long	0xFFFC0048
+PFC_IPSR11_D:	.long	0x002C89B0
+PFC_PMMR_IPSR11:.long	0xFFD3764F
+
+PFC_GPSR0_A:	.long	0xFFFC0004
+PFC_GPSR0_D:	.long	0xFFFFFFFF
+PFC_PMMR_GPSR0:	.long	0x00000000
+
+PFC_GPSR1_A:	.long	0xFFFC0008
+PFC_GPSR1_D:	.long	0x7FBF7FFF
+PFC_PMMR_GPSR1:	.long	0x80408000
+
+PFC_GPSR2_A:	.long	0xFFFC000C
+PFC_GPSR2_D:	.long	0xBFC07EDF
+PFC_PMMR_GPSR2:	.long	0x403F8120
+
+PFC_GPSR3_A:	.long	0xFFFC0010
+PFC_GPSR3_D:	.long	0xFFFFFFFF
+PFC_PMMR_GPSR3:	.long	0x00000000
+
+PFC_GPSR4_A:	.long	0xFFFC0014
+#if 0 /* orig */
+PFC_GPSR4_D:	.long	0xFFFFFFFF
+PFC_PMMR_GPSR4:	.long	0x00000000
+#else
+PFC_GPSR4_D:	.long	0xFBFFFFFF
+PFC_PMMR_GPSR4:	.long	0x04000000
+#endif
+
+PFC_GPSR5_A:	.long	0xFFFC0018
+PFC_GPSR5_D:	.long	0x00000C01
+PFC_PMMR_GPSR5:	.long	0xFFFFF3FE
+
+I2C_ICCR2_A: .long	0xFFC70001
+I2C_ICCR2_D: .long	0x00
+I2C_ICCR2_D1: .long	0x20
+
+GPIO2_INOUTSEL1_A:	.long	0xFFC41004
+GPIO2_INOUTSEL1_D:	.long	0x80408000
+GPIO1_OUTDT1_A:		.long	0xFFC41008	/* bit15: LED4, bit22: LED5 */
+GPIO1_OUTDT1_D:		.long	0x80408000
+GPIO2_INOUTSEL2_A:	.long	0xFFC42004
+GPIO2_INOUTSEL2_D:	.long	0x40000120
+GPIO2_OUTDT2_A:		.long	0xFFC42008
+GPIO2_OUTDT2_D:		.long	0x40000120
+GPIO4_INOUTSEL4_A:	.long	0xFFC44004
+GPIO4_INOUTSEL4_D:	.long	0x04000000
+GPIO4_OUTDT4_A:		.long	0xFFC44008
+GPIO4_OUTDT4_D:		.long	0x04000000
+
+CCR_A:	.long	0xFF00001C
+CCR_D:	.long	0x0000090B
+SR_MASK_D:	.long	0xEFFFFF0F
diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c
new file mode 100644
index 0000000..c1bde54
--- /dev/null
+++ b/board/renesas/r0p7734/r0p7734.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MODEMR			(0xFFCC0020)
+#define MODEMR_MASK		(0x6)
+#define MODEMR_533MHZ	(0x2)
+
+int checkboard(void)
+{
+	u32 r = readl(MODEMR);
+	if ((r & MODEMR_MASK) & MODEMR_533MHZ)
+		puts("CPU Clock: 533MHz\n");
+	else
+		puts("CPU Clock: 400MHz\n");
+
+	puts("BOARD: Renesas Technology Corp. R0P7734C00000RZ\n");
+	return 0;
+}
+
+#define MSTPSR1			(0xFFC80044)
+#define MSTPCR1			(0xFFC80034)
+#define MSTPSR1_GETHER	(1 << 14)
+
+int board_init(void)
+{
+#if defined(CONFIG_SH_ETHER)
+	u32 r = readl(MSTPSR1);
+	if (r & MSTPSR1_GETHER)
+		writel((r & ~MSTPSR1_GETHER), MSTPCR1);
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u8 mac[6];
+
+	/* Read Mac Address and set*/
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
+
+	/* Read MAC address */
+	i2c_read(0x50, 0x10, 0, mac, 6);
+
+	if (is_valid_ether_addr(mac))
+		eth_setenv_enetaddr("ethaddr", mac);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+
+	return 0;
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+	return rc;
+}
+#endif
diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile
new file mode 100644
index 0000000..2ba04ec
--- /dev/null
+++ b/board/renesas/rsk7269/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2012 Renesas Electronics Europe Ltd.
+# Copyright (C) 2012 Phil Edworthy
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).o
+
+OBJS	:= rsk7269.o
+SOBJS	:= lowlevel_init.o
+
+LIB	:= $(addprefix $(obj),$(LIB))
+OBJS	:= $(addprefix $(obj),$(OBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/renesas/rsk7269/lowlevel_init.S b/board/renesas/rsk7269/lowlevel_init.S
new file mode 100644
index 0000000..399beb8
--- /dev/null
+++ b/board/renesas/rsk7269/lowlevel_init.S
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2012 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2012 Phil Edworthy
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ *
+ * Based on board/renesas/rsk7264/lowlevel_init.S
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	/* Flush and enable caches (data cache in write-through mode) */
+	write32	CCR1_A ,CCR1_D
+
+	/* Disable WDT */
+	write16	WTCSR_A, WTCSR_D
+	write16	WTCNT_A, WTCNT_D
+
+	/* Disable Register Bank interrupts */
+	write16 IBNR_A, IBNR_D
+
+	/* Set clocks based on 13.225MHz xtal */
+	write16	FRQCR_A, FRQCR_D	/* CPU=266MHz, I=133MHz, P=66MHz */
+
+	/* Enable all peripherals */
+	write8 STBCR3_A, STBCR3_D
+	write8 STBCR4_A, STBCR4_D
+	write8 STBCR5_A, STBCR5_D
+	write8 STBCR6_A, STBCR6_D
+	write8 STBCR7_A, STBCR7_D
+	write8 STBCR8_A, STBCR8_D
+	write8 STBCR9_A, STBCR9_D
+	write8 STBCR10_A, STBCR10_D
+
+	/* SCIF7 and IIC2 */
+	write16 PJCR3_A, PJCR3_D	/* TXD7 */
+	write16 PECR1_A, PECR1_D	/* RXD7, SDA2, SCL2 */
+
+	/* Configure bus (CS0) */
+	write16 PFCR3_A, PFCR3_D	/* A24 */
+	write16 PFCR2_A, PFCR2_D	/* A23 and CS1# */
+	write16 PBCR5_A, PBCR5_D	/* A22, A21, A20 */
+	write16 PCCR0_A, PCCR0_D	/* DQMLL#, RD/WR# */
+	write32 CS0WCR_A, CS0WCR_D
+	write32 CS0BCR_A, CS0BCR_D
+
+	/* Configure SDRAM (CS3) */
+	write16 PCCR2_A, PCCR2_D	/* CS3# */
+	write16 PCCR1_A, PCCR1_D	/* CKE, CAS#, RAS#, DQMLU# */
+	write16 PCCR0_A, PCCR0_D	/* DQMLL#, RD/WR# */
+	write32	CS3BCR_A, CS3BCR_D
+	write32	CS3WCR_A, CS3WCR_D
+	write32	SDCR_A, SDCR_D
+	write32	RTCOR_A, RTCOR_D
+	write32	RTCSR_A, RTCSR_D
+
+	/* Configure ethernet (CS1) */
+	write16 PHCR1_A, PHCR1_D	/* PINT5 on PH5 */
+	write16 PHCR0_A, PHCR0_D
+	write16 PFCR2_A, PFCR2_D	/* CS1# */
+	write32	CS1BCR_A, CS1BCR_D	/* Big endian */
+	write32	CS1WCR_A, CS1WCR_D	/* 1 cycle */
+	write16 PJDR1_A, PJDR1_D	/* FIFO-SEL = 1 */
+	write16 PJIOR1_A, PJIOR1_D
+
+	/* wait 200us */
+	mov.l	REPEAT_D, r3
+	mov	#0, r2
+repeat0:
+	add	#1, r2
+	cmp/hs	r3, r2
+	bf	repeat0
+	nop
+
+	mov.l	SDRAM_MODE, r1
+	mov	#0, r0
+	mov.l	r0, @r1
+
+	nop
+	rts
+
+	.align 4
+
+CCR1_A:		.long CCR1
+CCR1_D:		.long 0x0000090B
+
+STBCR3_A:	.long 0xFFFE0408
+STBCR4_A:	.long 0xFFFE040C
+STBCR5_A:	.long 0xFFFE0410
+STBCR6_A:	.long 0xFFFE0414
+STBCR7_A:	.long 0xFFFE0418
+STBCR8_A:	.long 0xFFFE041C
+STBCR9_A:	.long 0xFFFE0440
+STBCR10_A:	.long 0xFFFE0444
+STBCR3_D:	.long 0x0000001A
+STBCR4_D:	.long 0x00000000
+STBCR5_D:	.long 0x00000000
+STBCR6_D:	.long 0x00000000
+STBCR7_D:	.long 0x00000012
+STBCR8_D:	.long 0x00000009
+STBCR9_D:	.long 0x00000000
+STBCR10_D:	.long 0x00000010
+
+WTCSR_A:	.long 0xFFFE0000
+WTCNT_A:	.long 0xFFFE0002
+WTCSR_D:	.word 0xA518
+WTCNT_D:	.word 0x5A00
+
+IBNR_A:		.long 0xFFFE080E
+IBNR_D:		.word 0x0000
+.align 2
+FRQCR_A:	.long 0xFFFE0010
+FRQCR_D:	.word 0x0015
+.align 2
+
+PJCR3_A:	.long 0xFFFE3908
+PJCR3_D:	.word 0x5000
+.align 2
+PECR1_A:	.long 0xFFFE388C
+PECR1_D:	.word 0x2011
+.align 2
+
+PFCR3_A:	.long 0xFFFE38A8
+PFCR2_A:	.long 0xFFFE38AA
+PBCR5_A:	.long 0xFFFE3824
+PFCR3_D:	.word 0x0010
+PFCR2_D:	.word 0x0101
+PBCR5_D:	.word 0x0111
+.align 2
+CS0WCR_A:	.long 0xFFFC0028
+CS0WCR_D:	.long 0x00000341
+CS0BCR_A:	.long 0xFFFC0004
+CS0BCR_D:	.long 0x00000400
+
+PCCR2_A:	.long 0xFFFE384A
+PCCR1_A:	.long 0xFFFE384C
+PCCR0_A:	.long 0xFFFE384E
+PCCR2_D:	.word 0x0001
+PCCR1_D:	.word 0x1111
+PCCR0_D:	.word 0x1111
+.align 2
+CS3BCR_A:	.long 0xFFFC0010
+CS3BCR_D:	.long 0x00004400
+CS3WCR_A:	.long 0xFFFC0034
+CS3WCR_D:	.long 0x00004912
+SDCR_A:		.long 0xFFFC004C
+SDCR_D:		.long 0x00000811
+RTCOR_A:	.long 0xFFFC0058
+RTCOR_D:	.long 0xA55A0035
+RTCSR_A:	.long 0xFFFC0050
+RTCSR_D:	.long 0xA55A0010
+.align 2
+SDRAM_MODE:	.long 0xFFFC5460
+REPEAT_D:	.long 0x000033F1
+
+PHCR1_A:	.long 0xFFFE38EC
+PHCR0_A:	.long 0xFFFE38EE
+PHCR1_D:	.word 0x2222
+PHCR0_D:	.word 0x2222
+.align 2
+CS1BCR_A:	.long 0xFFFC0008
+CS1BCR_D:	.long 0x00000400
+CS1WCR_A:	.long 0xFFFC002C
+CS1WCR_D:	.long 0x00000080
+PJDR1_A:	.long 0xFFFE3914
+PJDR1_D:	.word 0x0000
+.align 2
+PJIOR1_A:	.long 0xFFFE3910
+PJIOR1_D:	.word 0x8000
+.align 2
diff --git a/board/renesas/rsk7269/rsk7269.c b/board/renesas/rsk7269/rsk7269.c
new file mode 100644
index 0000000..842a154
--- /dev/null
+++ b/board/renesas/rsk7269/rsk7269.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2012 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2012 Phil Edworthy
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ *
+ * Based on u-boot/board/rsk7264/rsk7264.c
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas RSK7269\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+/*
+ * The RSK board has the SMSC89218 wired up 'incorrectly'.
+ * Byte-swapping is necessary, and so poor performance is inevitable.
+ * This problem cannot evade by the swap function of CHIP, this can
+ * evade by software Byte-swapping.
+ * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
+ * functions necessary to solve this problem.
+ */
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
+{
+	volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
+	return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
+				| swab16(*(addr_16 + 1));
+}
+
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
+{
+	addr += dev->iobase;
+	*(volatile u16 *)(addr + 2) = swab16((u16)val);
+	*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/boards.cfg b/boards.cfg
index 0dee43f..9ef903a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1013,6 +1013,7 @@
 sandbox                      sandbox     sandbox     sandbox             sandbox        -
 rsk7203                      sh          sh2         rsk7203             renesas        -
 rsk7264                      sh          sh2         rsk7264             renesas        -
+rsk7269                      sh          sh2         rsk7269             renesas        -
 mpr2                         sh          sh3         mpr2                -              -
 ms7720se                     sh          sh3         ms7720se            -              -
 shmin                        sh          sh3         shmin               -              -
@@ -1028,6 +1029,8 @@
 sh7763rdp                    sh          sh4         sh7763rdp           renesas        -
 sh7785lcr                    sh          sh4         sh7785lcr           renesas        -
 sh7785lcr_32bit              sh          sh4         sh7785lcr           renesas        -           sh7785lcr:SH_32BIT=1
+r0p7734                      sh          sh4         r0p7734             renesas        -
+ap_sh4a_4a                   sh          sh4         ap_sh4a_4a          alphaproject   -
 grsim_leon2                  sparc       leon2       -                   gaisler
 gr_cpci_ax2000               sparc       leon3       -                   gaisler
 gr_ep2s60                    sparc       leon3       -                   gaisler
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index fcf69ab..13919c6 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -35,6 +35,10 @@
 # define SCIF_BASE	SCIF4_BASE
 #elif defined(CONFIG_CONS_SCIF5)
 # define SCIF_BASE	SCIF5_BASE
+#elif defined(CONFIG_CONS_SCIF6)
+# define SCIF_BASE	SCIF6_BASE
+#elif defined(CONFIG_CONS_SCIF7)
+# define SCIF_BASE	SCIF7_BASE
 #else
 # error "Default SCIF doesn't set....."
 #endif
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 0b3e779..601da43 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -112,6 +112,15 @@
 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
 	0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
 	0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
+#elif defined(CONFIG_CPU_SH7734)
+# define SCSPTR0 0xFFE40020
+# define SCSPTR1 0xFFE41020
+# define SCSPTR2 0xFFE42020
+# define SCSPTR3 0xFFE43020
+# define SCSPTR4 0xFFE44020
+# define SCSPTR5 0xFFE45020
+# define SCIF_ORER 0x0001  /* overrun error bit */
+# define SCSCR_INIT(port) 0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SH4_202)
 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 # define SCIF_ORER 0x0001   /* overrun error bit */
@@ -190,6 +199,16 @@
 #  define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
 # endif
 # define SCSCR_INIT(port)	0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+#elif defined(CONFIG_CPU_SH7269)
+# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
+# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
+# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
+# define SCSPTR3 0xe8008820 /* 16 bit SCIF */
+# define SCSPTR4 0xe8009020 /* 16 bit SCIF */
+# define SCSPTR5 0xe8009820 /* 16 bit SCIF */
+# define SCSPTR6 0xe800a020 /* 16 bit SCIF */
+# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
+# define SCSCR_INIT(port)	0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_CPU_SH7619)
 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
@@ -216,6 +235,7 @@
 	defined(CONFIG_CPU_SH7091)  || \
 	defined(CONFIG_CPU_SH7750R) || \
 	defined(CONFIG_CPU_SH7722)  || \
+	defined(CONFIG_CPU_SH7734)  || \
 	defined(CONFIG_CPU_SH7750S) || \
 	defined(CONFIG_CPU_SH7751)  || \
 	defined(CONFIG_CPU_SH7751R) || \
diff --git a/include/common.h b/include/common.h
index 8564a65..ecfa6c4 100644
--- a/include/common.h
+++ b/include/common.h
@@ -355,6 +355,9 @@
 # include <asm/mach-types.h>
 # include <asm/u-boot-nds32.h>
 #endif /* CONFIG_NDS32 */
+#ifdef CONFIG_MIPS
+# include <asm/u-boot-mips.h>
+#endif /* CONFIG_MIPS */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
new file mode 100644
index 0000000..f63061b
--- /dev/null
+++ b/include/configs/ap_sh4a_4a.h
@@ -0,0 +1,176 @@
+/*
+ * Configuation settings for the Alpha Project AP-SH4A-4A board
+ *
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __AP_SH4A_4A_H
+#define __AP_SH4A_4A_H
+
+#undef DEBUG
+#define CONFIG_SH		1
+#define CONFIG_SH4		1
+#define CONFIG_SH4A		1
+#define CONFIG_CPU_SH7734	1
+#define CONFIG_AP_SH4A_4A	1
+#define CONFIG_400MHZ_MODE	1
+/* #define CONFIG_533MHZ_MODE	1 */
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_TEXT_BASE 0x8BFC0000
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC4,115200"
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* Ether */
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (0)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
+#define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
+#define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL 1
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SH_SH7734_I2C	1
+#define CONFIG_HARD_I2C			1
+#define CONFIG_I2C_MULTI_BUS	1
+#define CONFIG_SYS_MAX_I2C_BUS	2
+#define CONFIG_SYS_I2C_MODULE	0
+#define CONFIG_SYS_I2C_SPEED	400000 /* 400 kHz */
+#define CONFIG_SYS_I2C_SLAVE	0x50
+#define CONFIG_SH_I2C_DATA_HIGH	4
+#define CONFIG_SH_I2C_DATA_LOW	5
+#define CONFIG_SH_I2C_CLOCK		500000000
+#define CONFIG_SH_I2C_BASE0		0xFFC70000
+#define CONFIG_SH_I2C_BASE1		0xFFC71000
+
+/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"=> "
+/* Buffer size for input from the Console */
+#define CONFIG_SYS_CBSIZE		256
+/* Buffer size for Console output */
+#define CONFIG_SYS_PBSIZE		256
+/* max args accepted for monitor commands */
+#define CONFIG_SYS_MAXARGS		16
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_SCIF			1
+#define CONFIG_CONS_SCIF4	1
+
+/* Suppress display of console information at boot */
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE	(0x88000000)
+#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE)
+/* Enable alternate, more extensive, memory test */
+#undef  CONFIG_SYS_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE	(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+/*
+ * Use hardware flash sectors protection instead
+ * of U-Boot software protection
+ */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+/* Monitor size */
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#if defined(CONFIG_400MHZ_MODE)
+#define CONFIG_SYS_CLK_FREQ 50000000
+#else
+#define CONFIG_SYS_CLK_FREQ 44444444
+#endif
+#define CONFIG_SYS_TMU_CLK_DIV      4
+#define CONFIG_SYS_HZ       1000
+
+#endif	/* __AP_SH4A_4A_H */
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index 4d09132..f6aacd0 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -95,6 +95,7 @@
 #define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 
 /* USB / R8A66597 */
 #define CONFIG_USB_R8A66597_HCD
diff --git a/include/configs/espt.h b/include/configs/espt.h
index 3df1fae..f61e2d8 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -124,5 +124,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 
 #endif /* __SH7763RDP_H */
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
new file mode 100644
index 0000000..f143c3b
--- /dev/null
+++ b/include/configs/r0p7734.h
@@ -0,0 +1,186 @@
+/*
+ * Configuation settings for the Renesas Solutions r0p7734 board
+ *
+ * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __R0P7734_H
+#define __R0P7734_H
+
+#undef DEBUG
+#define CONFIG_SH		1
+#define CONFIG_SH4		1
+#define CONFIG_SH4A		1
+#define CONFIG_CPU_SH7734	1
+#define CONFIG_R0P7734		1
+#define CONFIG_400MHZ_MODE	1
+/* #define CONFIG_533MHZ_MODE	1 */
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC3,115200"
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* Ether */
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (0)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC 1
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#ifndef CONFIG_SH_ETHER
+# define CONFIG_SMC911X
+# define CONFIG_SMC911X_16_BIT
+# define CONFIG_SMC911X_BASE (0x84000000)
+#endif
+
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SH_SH7734_I2C	1
+#define CONFIG_HARD_I2C			1
+#define CONFIG_I2C_MULTI_BUS	1
+#define CONFIG_SYS_MAX_I2C_BUS	2
+#define CONFIG_SYS_I2C_MODULE	0
+#define CONFIG_SYS_I2C_SPEED	100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE	0x50
+#define CONFIG_SH_I2C_DATA_HIGH	4
+#define CONFIG_SH_I2C_DATA_LOW	5
+#define CONFIG_SH_I2C_CLOCK		500000000
+#define CONFIG_SH_I2C_BASE0		0xFFC70000
+#define CONFIG_SH_I2C_BASE1		0xFFC7100
+
+/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"=> "
+/* Buffer size for input from the Console */
+#define CONFIG_SYS_CBSIZE		256
+/* Buffer size for Console output */
+#define CONFIG_SYS_PBSIZE		256
+/* max args accepted for monitor commands */
+#define CONFIG_SYS_MAXARGS		16
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_SCIF			1
+#define CONFIG_CONS_SCIF3	1
+
+/* Suppress display of console information at boot */
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE	(0x88000000)
+#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
+/* Enable alternate, more extensive, memory test */
+#undef  CONFIG_SYS_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE	(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+/*
+ * Use hardware flash sectors protection instead
+ * of U-Boot software protection
+ */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+/* Monitor size */
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#if defined(CONFIG_400MHZ_MODE)
+#define CONFIG_SYS_CLK_FREQ 50000000
+#else
+#define CONFIG_SYS_CLK_FREQ 44444444
+#endif
+#define CONFIG_SYS_TMU_CLK_DIV      4
+#define CONFIG_SYS_HZ       1000
+
+#endif	/* __R0P7734_H */
diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h
new file mode 100644
index 0000000..26c1764
--- /dev/null
+++ b/include/configs/rsk7269.h
@@ -0,0 +1,76 @@
+/*
+ * Configuation settings for the Renesas RSK2+SH7269 board
+ *
+ * Copyright (C) 2012 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2012 Phil Edworthy
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef __RSK7269_H
+#define __RSK7269_H
+
+#undef DEBUG
+#define CONFIG_SH		1
+#define CONFIG_SH2		1
+#define CONFIG_SH2A		1
+#define CONFIG_CPU_SH7269	1
+#define CONFIG_RSK7269		1
+
+#ifndef _CONFIG_CMD_DEFAULT_H
+# include <config_cmd_default.h>
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC7,115200"
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE	256	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+
+/* Serial */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF7
+
+/* Memory */
+/* u-boot relocated to top 256KB of ram */
+#define CONFIG_SYS_TEXT_BASE		0x0DFC0000
+#define CONFIG_SYS_SDRAM_BASE		0x0C000000
+#define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
+
+/* NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE		0x20000000 /* Non-cached */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	(128 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	66125000
+#define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
+#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+
+/* Network interface */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE	0x24000000
+
+#endif	/* __RSK7269_H */
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 708bff7..d5c7b72 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -109,6 +109,7 @@
 #define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 
 #define SH7757LCR_ETHERNET_MAC_BASE_SPI	0x000b0000
 #define SH7757LCR_SPI_SECTOR_SIZE	(64 * 1024)
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 59728f5..9efbbd0 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -124,5 +124,6 @@
 #define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 
 #endif /* __SH7763RDP_H */