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wdenk324f6cf2002-10-07 21:13:39 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
wdenk228f29a2002-12-08 09:53:23 +000022 *
23 * Be sure to mark tests to be run before relocation as such with the
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024 * CONFIG_SYS_POST_PREREL flag so that logging is done correctly if the
wdenk228f29a2002-12-08 09:53:23 +000025 * logbuffer support is enabled.
wdenk324f6cf2002-10-07 21:13:39 +000026 */
27
28#include <common.h>
29
wdenk324f6cf2002-10-07 21:13:39 +000030#include <post.h>
31
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020032extern int ocm_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000033extern int cache_post_test (int flags);
34extern int watchdog_post_test (int flags);
35extern int i2c_post_test (int flags);
36extern int rtc_post_test (int flags);
37extern int memory_post_test (int flags);
38extern int cpu_post_test (int flags);
Igor Lisitsina11e0692007-03-28 19:06:19 +040039extern int fpu_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000040extern int uart_post_test (int flags);
41extern int ether_post_test (int flags);
42extern int spi_post_test (int flags);
43extern int usb_post_test (int flags);
44extern int spr_post_test (int flags);
wdenk4532cb62003-04-27 22:52:51 +000045extern int sysmon_post_test (int flags);
wdenk5a8c51c2004-04-15 21:16:42 +000046extern int dsp_post_test (int flags);
wdenk79fa88f2004-06-07 23:46:25 +000047extern int codec_post_test (int flags);
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +020048extern int ecc_post_test (int flags);
Mike Frysingerf6f73952011-05-10 13:35:40 +000049extern int flash_post_test(int flags);
wdenk4532cb62003-04-27 22:52:51 +000050
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010051extern int dspic_init_post_test (int flags);
52extern int dspic_post_test (int flags);
53extern int gdc_post_test (int flags);
54extern int fpga_post_test (int flags);
55extern int lwmon5_watchdog_post_test(int flags);
56extern int sysmon1_post_test(int flags);
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +020057extern int coprocessor_post_test(int flags);
Mike Frysinger21513742011-05-10 16:22:25 -040058extern int led_post_test(int flags);
59extern int button_post_test(int flags);
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010060
wdenk4532cb62003-04-27 22:52:51 +000061extern int sysmon_init_f (void);
62
63extern void sysmon_reloc (void);
64
wdenk324f6cf2002-10-07 21:13:39 +000065
66struct post_test post_list[] =
67{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#if CONFIG_POST & CONFIG_SYS_POST_OCM
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020069 {
70 "OCM test",
71 "ocm",
72 "This test checks on chip memory (OCM).",
Yuri Tikhonov7845d492008-05-08 15:46:02 +020073 POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP,
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020074 &ocm_post_test,
75 NULL,
76 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 CONFIG_SYS_POST_OCM
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020078 },
79#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#if CONFIG_POST & CONFIG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000081 {
wdenk8bde7f72003-06-27 21:31:46 +000082 "Cache test",
83 "cache",
84 "This test verifies the CPU cache operation.",
85 POST_RAM | POST_ALWAYS,
86 &cache_post_test,
87 NULL,
88 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 CONFIG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000090 },
91#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010093#if defined(CONFIG_POST_WATCHDOG)
94 CONFIG_POST_WATCHDOG,
95#else
wdenk324f6cf2002-10-07 21:13:39 +000096 {
wdenk8bde7f72003-06-27 21:31:46 +000097 "Watchdog timer test",
98 "watchdog",
99 "This test checks the watchdog timer.",
wdenk8564acf2003-07-14 22:13:32 +0000100 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
wdenk8bde7f72003-06-27 21:31:46 +0000101 &watchdog_post_test,
102 NULL,
103 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104 CONFIG_SYS_POST_WATCHDOG
wdenk324f6cf2002-10-07 21:13:39 +0000105 },
106#endif
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100107#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#if CONFIG_POST & CONFIG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +0000109 {
wdenk8bde7f72003-06-27 21:31:46 +0000110 "I2C test",
111 "i2c",
112 "This test verifies the I2C operation.",
113 POST_RAM | POST_ALWAYS,
114 &i2c_post_test,
115 NULL,
116 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117 CONFIG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +0000118 },
119#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#if CONFIG_POST & CONFIG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000121 {
wdenk8bde7f72003-06-27 21:31:46 +0000122 "RTC test",
123 "rtc",
124 "This test verifies the RTC operation.",
wdenk8564acf2003-07-14 22:13:32 +0000125 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk8bde7f72003-06-27 21:31:46 +0000126 &rtc_post_test,
127 NULL,
128 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 CONFIG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000130 },
131#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000133 {
wdenk8bde7f72003-06-27 21:31:46 +0000134 "Memory test",
135 "memory",
136 "This test checks RAM.",
wdenk8564acf2003-07-14 22:13:32 +0000137 POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
wdenk8bde7f72003-06-27 21:31:46 +0000138 &memory_post_test,
139 NULL,
140 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 CONFIG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000142 },
143#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#if CONFIG_POST & CONFIG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000145 {
wdenk8bde7f72003-06-27 21:31:46 +0000146 "CPU test",
147 "cpu",
148 "This test verifies the arithmetic logic unit of"
149 " CPU.",
150 POST_RAM | POST_ALWAYS,
151 &cpu_post_test,
152 NULL,
153 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154 CONFIG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000155 },
156#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#if CONFIG_POST & CONFIG_SYS_POST_FPU
Igor Lisitsina11e0692007-03-28 19:06:19 +0400158 {
159 "FPU test",
160 "fpu",
161 "This test verifies the arithmetic logic unit of"
162 " FPU.",
163 POST_RAM | POST_ALWAYS,
164 &fpu_post_test,
165 NULL,
166 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167 CONFIG_SYS_POST_FPU
Igor Lisitsina11e0692007-03-28 19:06:19 +0400168 },
169#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#if CONFIG_POST & CONFIG_SYS_POST_UART
Stefan Roese834a45d2010-10-07 14:16:25 +0200171#if defined(CONFIG_POST_UART)
172 CONFIG_POST_UART,
173#else
wdenk324f6cf2002-10-07 21:13:39 +0000174 {
wdenk8bde7f72003-06-27 21:31:46 +0000175 "UART test",
176 "uart",
177 "This test verifies the UART operation.",
wdenk8564acf2003-07-14 22:13:32 +0000178 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk8bde7f72003-06-27 21:31:46 +0000179 &uart_post_test,
180 NULL,
181 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 CONFIG_SYS_POST_UART
wdenk324f6cf2002-10-07 21:13:39 +0000183 },
Stefan Roese834a45d2010-10-07 14:16:25 +0200184#endif /* CONFIG_POST_UART */
wdenk324f6cf2002-10-07 21:13:39 +0000185#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#if CONFIG_POST & CONFIG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000187 {
wdenk8bde7f72003-06-27 21:31:46 +0000188 "ETHERNET test",
189 "ethernet",
190 "This test verifies the ETHERNET operation.",
191 POST_RAM | POST_ALWAYS | POST_MANUAL,
192 &ether_post_test,
193 NULL,
194 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195 CONFIG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000196 },
197#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#if CONFIG_POST & CONFIG_SYS_POST_SPI
wdenk324f6cf2002-10-07 21:13:39 +0000199 {
wdenk8bde7f72003-06-27 21:31:46 +0000200 "SPI test",
201 "spi",
202 "This test verifies the SPI operation.",
203 POST_RAM | POST_ALWAYS | POST_MANUAL,
204 &spi_post_test,
205 NULL,
206 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207 CONFIG_SYS_POST_SPI
wdenk324f6cf2002-10-07 21:13:39 +0000208 },
209#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#if CONFIG_POST & CONFIG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000211 {
wdenk8bde7f72003-06-27 21:31:46 +0000212 "USB test",
213 "usb",
214 "This test verifies the USB operation.",
215 POST_RAM | POST_ALWAYS | POST_MANUAL,
216 &usb_post_test,
217 NULL,
218 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219 CONFIG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000220 },
221#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#if CONFIG_POST & CONFIG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000223 {
wdenk8bde7f72003-06-27 21:31:46 +0000224 "SPR test",
225 "spr",
226 "This test checks SPR contents.",
Stefan Roeseb2e21422008-01-09 10:38:58 +0100227 POST_RAM | POST_ALWAYS,
wdenk8bde7f72003-06-27 21:31:46 +0000228 &spr_post_test,
229 NULL,
230 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231 CONFIG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000232 },
233#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#if CONFIG_POST & CONFIG_SYS_POST_SYSMON
wdenk4532cb62003-04-27 22:52:51 +0000235 {
wdenk8bde7f72003-06-27 21:31:46 +0000236 "SYSMON test",
237 "sysmon",
238 "This test monitors system hardware.",
239 POST_RAM | POST_ALWAYS,
240 &sysmon_post_test,
241 &sysmon_init_f,
242 &sysmon_reloc,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243 CONFIG_SYS_POST_SYSMON
wdenk4532cb62003-04-27 22:52:51 +0000244 },
245#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#if CONFIG_POST & CONFIG_SYS_POST_DSP
wdenk5a8c51c2004-04-15 21:16:42 +0000247 {
248 "DSP test",
249 "dsp",
250 "This test checks any connected DSP(s).",
Sascha Laue5744ddc2008-05-30 09:48:14 +0200251 POST_RAM | POST_ALWAYS | POST_MANUAL,
wdenk5a8c51c2004-04-15 21:16:42 +0000252 &dsp_post_test,
253 NULL,
254 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255 CONFIG_SYS_POST_DSP
wdenk5a8c51c2004-04-15 21:16:42 +0000256 },
257#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#if CONFIG_POST & CONFIG_SYS_POST_CODEC
wdenk79fa88f2004-06-07 23:46:25 +0000259 {
260 "CODEC test",
261 "codec",
262 "This test checks any connected codec(s).",
263 POST_RAM | POST_MANUAL,
264 &codec_post_test,
265 NULL,
266 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267 CONFIG_SYS_POST_CODEC
wdenk79fa88f2004-06-07 23:46:25 +0000268 },
269#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#if CONFIG_POST & CONFIG_SYS_POST_ECC
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200271 {
272 "ECC test",
273 "ecc",
Larry Johnson8dafa872008-01-12 23:35:33 -0500274 "This test checks the ECC facility of memory.",
275 POST_ROM | POST_ALWAYS | POST_PREREL,
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200276 &ecc_post_test,
277 NULL,
278 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279 CONFIG_SYS_POST_ECC
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200280 },
281#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100283 CONFIG_POST_BSPEC1,
284#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100286 CONFIG_POST_BSPEC2,
287#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100289 CONFIG_POST_BSPEC3,
290#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100292 CONFIG_POST_BSPEC4,
293#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100295 CONFIG_POST_BSPEC5,
296#endif
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +0200297#if CONFIG_POST & CONFIG_SYS_POST_COPROC
298 {
299 "Coprocessors communication test",
300 "coproc_com",
301 "This test checks communication with coprocessors.",
302 POST_RAM | POST_ALWAYS | POST_CRITICAL,
303 &coprocessor_post_test,
304 NULL,
305 NULL,
306 CONFIG_SYS_POST_COPROC
Mike Frysingerf6f73952011-05-10 13:35:40 +0000307 },
308#endif
309#if CONFIG_POST & CONFIG_SYS_POST_FLASH
310 {
311 "Parallel NOR flash test",
312 "flash",
313 "This test verifies parallel flash operations.",
314 POST_RAM | POST_SLOWTEST | POST_MANUAL,
315 &flash_post_test,
316 NULL,
317 NULL,
318 CONFIG_SYS_POST_FLASH
319 },
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +0200320#endif
wdenk324f6cf2002-10-07 21:13:39 +0000321};
322
Mike Frysingerd2397812011-05-10 07:28:35 +0000323unsigned int post_list_size = ARRAY_SIZE(post_list);