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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This file contains structures and information for the communication
6 * processor channels. Some CPM control and status is available
7 * throught the MPC8xx internal memory map. See immap.h for details.
8 * This file only contains what I need for the moment, not the total
9 * CPM capabilities. I (or someone else) will add definitions as they
10 * are needed. -- Dan
11 *
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15 * or other use.
16 */
17#ifndef __CPM_8XX__
18#define __CPM_8XX__
19
20#include <linux/config.h>
21#include <asm/8xx_immap.h>
22
23/* CPM Command register.
24*/
wdenk7c7a23b2002-12-07 00:20:59 +000025#define CPM_CR_RST ((ushort)0x8000)
26#define CPM_CR_OPCODE ((ushort)0x0f00)
27#define CPM_CR_CHAN ((ushort)0x00f0)
28#define CPM_CR_FLG ((ushort)0x0001)
wdenkfe8c2802002-11-03 00:38:21 +000029
30/* Some commands (there are more...later)
31*/
32#define CPM_CR_INIT_TRX ((ushort)0x0000)
33#define CPM_CR_INIT_RX ((ushort)0x0001)
34#define CPM_CR_INIT_TX ((ushort)0x0002)
35#define CPM_CR_HUNT_MODE ((ushort)0x0003)
36#define CPM_CR_STOP_TX ((ushort)0x0004)
37#define CPM_CR_RESTART_TX ((ushort)0x0006)
38#define CPM_CR_SET_GADDR ((ushort)0x0008)
39
40/* Channel numbers.
41*/
wdenk7c7a23b2002-12-07 00:20:59 +000042#define CPM_CR_CH_SCC1 ((ushort)0x0000)
43#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
44#define CPM_CR_CH_SCC2 ((ushort)0x0004)
45#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
46#define CPM_CR_CH_SCC3 ((ushort)0x0008)
47#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
48#define CPM_CR_CH_SCC4 ((ushort)0x000c)
49#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
wdenkfe8c2802002-11-03 00:38:21 +000050
51#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
52
53/*
54 * DPRAM defines and allocation functions
55 */
56
57/* The dual ported RAM is multi-functional. Some areas can be (and are
58 * being) used for microcode. There is an area that can only be used
59 * as data ram for buffer descriptors, which is all we use right now.
60 * Currently the first 512 and last 256 bytes are used for microcode.
61 */
62#ifdef CFG_ALLOC_DPRAM
63
64#define CPM_DATAONLY_BASE ((uint)0x0800)
65#define CPM_DATAONLY_SIZE ((uint)0x0700)
66#define CPM_DP_NOSPACE ((uint)0x7fffffff)
67
68#else
69
70#define CPM_SERIAL_BASE 0x0800
71#define CPM_I2C_BASE 0x0820
72#define CPM_SPI_BASE 0x0840
73#define CPM_FEC_BASE 0x0860
74#define CPM_WLKBD_BASE 0x0880
75#define CPM_SCC_BASE 0x0900
76#define CPM_POST_BASE 0x0980
77
78#endif
79
wdenkea909b72002-11-21 23:11:29 +000080#ifndef CFG_CPM_POST_WORD_ADDR
wdenkfe8c2802002-11-03 00:38:21 +000081#define CPM_POST_WORD_ADDR 0x07FC
wdenkea909b72002-11-21 23:11:29 +000082#else
83#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
84#endif
wdenkfe8c2802002-11-03 00:38:21 +000085
86#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
87
88/* Export the base address of the communication processor registers
89 * and dual port ram.
90 */
91extern cpm8xx_t *cpmp; /* Pointer to comm processor */
92
93/* Buffer descriptors used by many of the CPM protocols.
94*/
95typedef struct cpm_buf_desc {
96 ushort cbd_sc; /* Status and Control */
97 ushort cbd_datlen; /* Data length in buffer */
98 uint cbd_bufaddr; /* Buffer address in host memory */
99} cbd_t;
100
101#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
102#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
103#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
104#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
105#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
106#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
107#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
108#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
109#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
110#define BD_SC_BR ((ushort)0x0020) /* Break received */
111#define BD_SC_FR ((ushort)0x0010) /* Framing error */
112#define BD_SC_PR ((ushort)0x0008) /* Parity error */
113#define BD_SC_OV ((ushort)0x0002) /* Overrun */
114#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
115
116/* Parameter RAM offsets.
117*/
118#define PROFF_SCC1 ((uint)0x0000)
119#define PROFF_IIC ((uint)0x0080)
120#define PROFF_SCC2 ((uint)0x0100)
121#define PROFF_SPI ((uint)0x0180)
122#define PROFF_SCC3 ((uint)0x0200)
123#define PROFF_SMC1 ((uint)0x0280)
124#define PROFF_SCC4 ((uint)0x0300)
125#define PROFF_SMC2 ((uint)0x0380)
126
127/* Define enough so I can at least use the serial port as a UART.
128 * The MBX uses SMC1 as the host serial port.
129 */
130typedef struct smc_uart {
131 ushort smc_rbase; /* Rx Buffer descriptor base address */
132 ushort smc_tbase; /* Tx Buffer descriptor base address */
133 u_char smc_rfcr; /* Rx function code */
134 u_char smc_tfcr; /* Tx function code */
135 ushort smc_mrblr; /* Max receive buffer length */
136 uint smc_rstate; /* Internal */
137 uint smc_idp; /* Internal */
138 ushort smc_rbptr; /* Internal */
139 ushort smc_ibc; /* Internal */
140 uint smc_rxtmp; /* Internal */
141 uint smc_tstate; /* Internal */
142 uint smc_tdp; /* Internal */
143 ushort smc_tbptr; /* Internal */
144 ushort smc_tbc; /* Internal */
145 uint smc_txtmp; /* Internal */
146 ushort smc_maxidl; /* Maximum idle characters */
147 ushort smc_tmpidl; /* Temporary idle counter */
148 ushort smc_brklen; /* Last received break length */
149 ushort smc_brkec; /* rcv'd break condition counter */
150 ushort smc_brkcr; /* xmt break count register */
151 ushort smc_rmask; /* Temporary bit mask */
152} smc_uart_t;
153
154/* Function code bits.
155*/
156#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
157
158/* SMC uart mode register.
159*/
160#define SMCMR_REN ((ushort)0x0001)
161#define SMCMR_TEN ((ushort)0x0002)
162#define SMCMR_DM ((ushort)0x000c)
163#define SMCMR_SM_GCI ((ushort)0x0000)
164#define SMCMR_SM_UART ((ushort)0x0020)
165#define SMCMR_SM_TRANS ((ushort)0x0030)
166#define SMCMR_SM_MASK ((ushort)0x0030)
167#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
168#define SMCMR_REVD SMCMR_PM_EVEN
169#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
170#define SMCMR_BS SMCMR_PEN
171#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
172#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
173#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
174
175/* SMC2 as Centronics parallel printer. It is half duplex, in that
176 * it can only receive or transmit. The parameter ram values for
177 * each direction are either unique or properly overlap, so we can
178 * include them in one structure.
179 */
180typedef struct smc_centronics {
181 ushort scent_rbase;
182 ushort scent_tbase;
183 u_char scent_cfcr;
184 u_char scent_smask;
185 ushort scent_mrblr;
186 uint scent_rstate;
187 uint scent_r_ptr;
188 ushort scent_rbptr;
189 ushort scent_r_cnt;
190 uint scent_rtemp;
191 uint scent_tstate;
192 uint scent_t_ptr;
193 ushort scent_tbptr;
194 ushort scent_t_cnt;
195 uint scent_ttemp;
196 ushort scent_max_sl;
197 ushort scent_sl_cnt;
198 ushort scent_character1;
199 ushort scent_character2;
200 ushort scent_character3;
201 ushort scent_character4;
202 ushort scent_character5;
203 ushort scent_character6;
204 ushort scent_character7;
205 ushort scent_character8;
206 ushort scent_rccm;
207 ushort scent_rccr;
208} smc_cent_t;
209
210/* Centronics Status Mask Register.
211*/
212#define SMC_CENT_F ((u_char)0x08)
213#define SMC_CENT_PE ((u_char)0x04)
214#define SMC_CENT_S ((u_char)0x02)
215
216/* SMC Event and Mask register.
217*/
218#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
219#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
220#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
221#define SMCM_BSY ((unsigned char)0x04)
222#define SMCM_TX ((unsigned char)0x02)
223#define SMCM_RX ((unsigned char)0x01)
224
225/* Baud rate generators.
226*/
227#define CPM_BRG_RST ((uint)0x00020000)
228#define CPM_BRG_EN ((uint)0x00010000)
229#define CPM_BRG_EXTC_INT ((uint)0x00000000)
230#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
231#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
232#define CPM_BRG_ATB ((uint)0x00002000)
233#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
234#define CPM_BRG_DIV16 ((uint)0x00000001)
235
236/* SI Clock Route Register
237*/
238#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
239#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
240#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
241#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
242#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
243#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
244#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
245#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
246
247/* SCCs.
248*/
249#define SCC_GSMRH_IRP ((uint)0x00040000)
250#define SCC_GSMRH_GDE ((uint)0x00010000)
251#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
252#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
253#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
254#define SCC_GSMRH_REVD ((uint)0x00002000)
255#define SCC_GSMRH_TRX ((uint)0x00001000)
256#define SCC_GSMRH_TTX ((uint)0x00000800)
257#define SCC_GSMRH_CDP ((uint)0x00000400)
258#define SCC_GSMRH_CTSP ((uint)0x00000200)
259#define SCC_GSMRH_CDS ((uint)0x00000100)
260#define SCC_GSMRH_CTSS ((uint)0x00000080)
261#define SCC_GSMRH_TFL ((uint)0x00000040)
262#define SCC_GSMRH_RFW ((uint)0x00000020)
263#define SCC_GSMRH_TXSY ((uint)0x00000010)
264#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
265#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
266#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
267#define SCC_GSMRH_RTSM ((uint)0x00000002)
268#define SCC_GSMRH_RSYN ((uint)0x00000001)
269
270#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
271#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
272#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
273#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
274#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
275#define SCC_GSMRL_TCI ((uint)0x10000000)
276#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
277#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
278#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
279#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
280#define SCC_GSMRL_RINV ((uint)0x02000000)
281#define SCC_GSMRL_TINV ((uint)0x01000000)
282#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
283#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
284#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
285#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
286#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
287#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
288#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
289#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
290#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
291#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
292#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
293#define SCC_GSMRL_TEND ((uint)0x00040000)
294#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
295#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
296#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
297#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
298#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
299#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
300#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
301#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
302#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
303#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
304#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
305#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
306#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
307#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
308#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
309#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
310#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
311#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
312#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
313#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
314#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
315#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
316#define SCC_GSMRL_ENR ((uint)0x00000020)
317#define SCC_GSMRL_ENT ((uint)0x00000010)
318#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
319#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
320#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
321#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
322#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
323#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
324#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
325#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
326#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
327#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
328
329#define SCC_TODR_TOD ((ushort)0x8000)
330
331/* SCC Event and Mask register.
332*/
333#define SCCM_TXE ((unsigned char)0x10)
334#define SCCM_BSY ((unsigned char)0x04)
335#define SCCM_TX ((unsigned char)0x02)
336#define SCCM_RX ((unsigned char)0x01)
337
338typedef struct scc_param {
339 ushort scc_rbase; /* Rx Buffer descriptor base address */
340 ushort scc_tbase; /* Tx Buffer descriptor base address */
341 u_char scc_rfcr; /* Rx function code */
342 u_char scc_tfcr; /* Tx function code */
343 ushort scc_mrblr; /* Max receive buffer length */
344 uint scc_rstate; /* Internal */
345 uint scc_idp; /* Internal */
346 ushort scc_rbptr; /* Internal */
347 ushort scc_ibc; /* Internal */
348 uint scc_rxtmp; /* Internal */
349 uint scc_tstate; /* Internal */
350 uint scc_tdp; /* Internal */
351 ushort scc_tbptr; /* Internal */
352 ushort scc_tbc; /* Internal */
353 uint scc_txtmp; /* Internal */
354 uint scc_rcrc; /* Internal */
355 uint scc_tcrc; /* Internal */
356} sccp_t;
357
358/* Function code bits.
359*/
360#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
361
362/* CPM Ethernet through SCCx.
363 */
364typedef struct scc_enet {
365 sccp_t sen_genscc;
366 uint sen_cpres; /* Preset CRC */
367 uint sen_cmask; /* Constant mask for CRC */
368 uint sen_crcec; /* CRC Error counter */
369 uint sen_alec; /* alignment error counter */
370 uint sen_disfc; /* discard frame counter */
371 ushort sen_pads; /* Tx short frame pad character */
372 ushort sen_retlim; /* Retry limit threshold */
373 ushort sen_retcnt; /* Retry limit counter */
374 ushort sen_maxflr; /* maximum frame length register */
375 ushort sen_minflr; /* minimum frame length register */
376 ushort sen_maxd1; /* maximum DMA1 length */
377 ushort sen_maxd2; /* maximum DMA2 length */
378 ushort sen_maxd; /* Rx max DMA */
379 ushort sen_dmacnt; /* Rx DMA counter */
380 ushort sen_maxb; /* Max BD byte count */
381 ushort sen_gaddr1; /* Group address filter */
382 ushort sen_gaddr2;
383 ushort sen_gaddr3;
384 ushort sen_gaddr4;
385 uint sen_tbuf0data0; /* Save area 0 - current frame */
386 uint sen_tbuf0data1; /* Save area 1 - current frame */
387 uint sen_tbuf0rba; /* Internal */
388 uint sen_tbuf0crc; /* Internal */
389 ushort sen_tbuf0bcnt; /* Internal */
390 ushort sen_paddrh; /* physical address (MSB) */
391 ushort sen_paddrm;
392 ushort sen_paddrl; /* physical address (LSB) */
393 ushort sen_pper; /* persistence */
394 ushort sen_rfbdptr; /* Rx first BD pointer */
395 ushort sen_tfbdptr; /* Tx first BD pointer */
396 ushort sen_tlbdptr; /* Tx last BD pointer */
397 uint sen_tbuf1data0; /* Save area 0 - current frame */
398 uint sen_tbuf1data1; /* Save area 1 - current frame */
399 uint sen_tbuf1rba; /* Internal */
400 uint sen_tbuf1crc; /* Internal */
401 ushort sen_tbuf1bcnt; /* Internal */
402 ushort sen_txlen; /* Tx Frame length counter */
403 ushort sen_iaddr1; /* Individual address filter */
404 ushort sen_iaddr2;
405 ushort sen_iaddr3;
406 ushort sen_iaddr4;
407 ushort sen_boffcnt; /* Backoff counter */
408
409 /* NOTE: Some versions of the manual have the following items
410 * incorrectly documented. Below is the proper order.
411 */
412 ushort sen_taddrh; /* temp address (MSB) */
413 ushort sen_taddrm;
414 ushort sen_taddrl; /* temp address (LSB) */
415} scc_enet_t;
416
417/**********************************************************************
418 *
419 * Board specific configuration settings.
420 *
421 * Please note that we use the presence of a #define SCC_ENET and/or
422 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
423 **********************************************************************/
424
425
426/*** ADS *************************************************************/
427
428#if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
429/* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
430 */
431
432#define PROFF_ENET PROFF_SCC1
433#define CPM_CR_ENET CPM_CR_CH_SCC1
434#define SCC_ENET 0
435
436#define PA_ENET_RXD ((ushort)0x0001)
437#define PA_ENET_TXD ((ushort)0x0002)
438#define PA_ENET_TCLK ((ushort)0x0100)
439#define PA_ENET_RCLK ((ushort)0x0200)
440
441#define PB_ENET_TENA ((uint)0x00001000)
442
443#define PC_ENET_CLSN ((ushort)0x0010)
444#define PC_ENET_RENA ((ushort)0x0020)
445
446#define SICR_ENET_MASK ((uint)0x000000ff)
447#define SICR_ENET_CLKRT ((uint)0x0000002c)
448
449/* 68160 PHY control */
450
451#define PC_ENET_ETHLOOP ((ushort)0x0800)
452#define PC_ENET_TPFLDL ((ushort)0x0400)
453#define PC_ENET_TPSQEL ((ushort)0x0200)
454
455#endif /* MPC860ADS */
456
457/*** AMX860 **********************************************/
458
459#if defined(CONFIG_AMX860)
460
461/* This ENET stuff is for the AMX860 with ethernet on SCC1.
462 */
463
464#define PROFF_ENET PROFF_SCC1
465#define CPM_CR_ENET CPM_CR_CH_SCC1
466#define SCC_ENET 0
467
468#define PA_ENET_RXD ((ushort)0x0001)
469#define PA_ENET_TXD ((ushort)0x0002)
470#define PA_ENET_TCLK ((ushort)0x0400)
471#define PA_ENET_RCLK ((ushort)0x0800)
472
473#define PB_ENET_TENA ((uint)0x00001000)
474
475#define PC_ENET_CLSN ((ushort)0x0010)
476#define PC_ENET_RENA ((ushort)0x0020)
477
478#define SICR_ENET_MASK ((uint)0x000000ff)
479#define SICR_ENET_CLKRT ((uint)0x0000003e)
480
481/* 68160 PHY control */
482
483#define PB_ENET_ETHLOOP ((uint)0x00020000)
484#define PB_ENET_TPFLDL ((uint)0x00010000)
485#define PB_ENET_TPSQEL ((uint)0x00008000)
486#define PD_ENET_ETH_EN ((ushort)0x0004)
487
488#endif /* CONFIG_AMX860 */
489
490/*** BSEIP **********************************************************/
491
492#ifdef CONFIG_BSEIP
493/* This ENET stuff is for the MPC823 with ethernet on SCC2.
494 * This is unique to the BSE ip-Engine board.
495 */
496#define PROFF_ENET PROFF_SCC2
497#define CPM_CR_ENET CPM_CR_CH_SCC2
498#define SCC_ENET 1
499#define PA_ENET_RXD ((ushort)0x0004)
500#define PA_ENET_TXD ((ushort)0x0008)
501#define PA_ENET_TCLK ((ushort)0x0100)
502#define PA_ENET_RCLK ((ushort)0x0200)
503#define PB_ENET_TENA ((uint)0x00002000)
504#define PC_ENET_CLSN ((ushort)0x0040)
505#define PC_ENET_RENA ((ushort)0x0080)
506
507/* BSE uses port B and C bits for PHY control also.
508*/
509#define PB_BSE_POWERUP ((uint)0x00000004)
510#define PB_BSE_FDXDIS ((uint)0x00008000)
511#define PC_BSE_LOOPBACK ((ushort)0x0800)
512
513#define SICR_ENET_MASK ((uint)0x0000ff00)
514#define SICR_ENET_CLKRT ((uint)0x00002c00)
515#endif /* CONFIG_BSEIP */
516
517/*** BSEIP **********************************************************/
518
519#ifdef CONFIG_FLAGADM
520/* Enet configuration for the FLAGADM */
521/* Enet on SCC2 */
522
523#define PROFF_ENET PROFF_SCC2
524#define CPM_CR_ENET CPM_CR_CH_SCC2
525#define SCC_ENET 1
wdenk7c7a23b2002-12-07 00:20:59 +0000526#define PA_ENET_RXD ((ushort)0x0004)
527#define PA_ENET_TXD ((ushort)0x0008)
wdenkfe8c2802002-11-03 00:38:21 +0000528#define PA_ENET_TCLK ((ushort)0x0100)
529#define PA_ENET_RCLK ((ushort)0x0400)
530#define PB_ENET_TENA ((uint)0x00002000)
531#define PC_ENET_CLSN ((ushort)0x0040)
532#define PC_ENET_RENA ((ushort)0x0080)
533
534#define SICR_ENET_MASK ((uint)0x0000ff00)
535#define SICR_ENET_CLKRT ((uint)0x00003400)
536#endif /* CONFIG_FLAGADM */
537
538/*** C2MON **********************************************************/
539
540#ifdef CONFIG_C2MON
541
542# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */
543# error "Ethernet on SCC not supported on C2MON Board!"
544# else /* Use FEC for Fast Ethernet */
545
546#undef SCC_ENET
547#define FEC_ENET
548
549#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
550#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
551#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
552#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
553#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
554#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
555#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
556#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
557#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
558#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
559#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
560#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
561#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
562
563#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
564
565# endif /* CONFIG_FEC_ENET */
566#endif /* CONFIG_C2MON */
567
568/*********************************************************************/
569
570
571/*** CCM and PCU E ***********************************************/
572
573/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */
574
575#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
576
577#define FEC_ENET /* use FEC for EThernet */
578#undef SCC_ENET
579
580#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
581#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
582#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
583#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
584#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
585#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
586#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
587#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
588#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
589#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
590#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
591#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
592#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
593
594#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
595
596#endif /* CONFIG_PCU_E, CONFIG_CCM */
597
598/*** ESTEEM 192E **************************************************/
599#ifdef CONFIG_ESTEEM192E
600/* ESTEEM192E
601 * This ENET stuff is for the MPC850 with ethernet on SCC2. This
602 * is very similar to the RPX-Lite configuration.
603 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
604 */
605
606#define PROFF_ENET PROFF_SCC2
607#define CPM_CR_ENET CPM_CR_CH_SCC2
608#define SCC_ENET 1
609
610#define PA_ENET_RXD ((ushort)0x0004)
611#define PA_ENET_TXD ((ushort)0x0008)
612#define PA_ENET_TCLK ((ushort)0x0200)
613#define PA_ENET_RCLK ((ushort)0x0800)
614#define PB_ENET_TENA ((uint)0x00002000)
615#define PC_ENET_CLSN ((ushort)0x0040)
616#define PC_ENET_RENA ((ushort)0x0080)
617
618#define SICR_ENET_MASK ((uint)0x0000ff00)
619#define SICR_ENET_CLKRT ((uint)0x00003d00)
620
621#define PB_ENET_LOOPBACK ((uint)0x00004000)
622#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
623
624#endif
625
626/*** FADS823 ********************************************************/
627
628#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
629/* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
630 */
631#ifdef CONFIG_SCC2_ENET
632#define PROFF_ENET PROFF_SCC2
633#define CPM_CR_ENET CPM_CR_CH_SCC2
634#define SCC_ENET 1
635#define CPMVEC_ENET CPMVEC_SCC2
636#endif
637
638#ifdef CONFIG_SCC1_ENET
639#define PROFF_ENET PROFF_SCC1
640#define CPM_CR_ENET CPM_CR_CH_SCC1
641#define SCC_ENET 0
642#define CPMVEC_ENET CPMVEC_SCC1
643#endif
644
645#define PA_ENET_RXD ((ushort)0x0004)
646#define PA_ENET_TXD ((ushort)0x0008)
647#define PA_ENET_TCLK ((ushort)0x0400)
648#define PA_ENET_RCLK ((ushort)0x0200)
649
650#define PB_ENET_TENA ((uint)0x00002000)
651
652#define PC_ENET_CLSN ((ushort)0x0040)
653#define PC_ENET_RENA ((ushort)0x0080)
654
655#define SICR_ENET_MASK ((uint)0x0000ff00)
656#define SICR_ENET_CLKRT ((uint)0x00002e00)
657
658#endif /* CONFIG_FADS823FADS */
659
660/*** FADS850SAR ********************************************************/
661
662#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
663/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of
664 * this may be unique to the FADS850SAR configuration.
665 * Note TENA is on Port B.
666 */
667#define PROFF_ENET PROFF_SCC2
668#define CPM_CR_ENET CPM_CR_CH_SCC2
669#define SCC_ENET 1
670#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
671#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
672#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
673#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
674#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
675#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
676#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
677
678#define SICR_ENET_MASK ((uint)0x0000ff00)
679#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */
680#endif /* CONFIG_FADS850SAR */
681
682/*** FADS860T********************************************************/
683
684#if defined(CONFIG_MPC860T) && defined(CONFIG_FADS)
685/* This ENET stuff is for the MPC860TFADS with ethernet on SCC1.
686 */
687
688#ifdef CONFIG_SCC1_ENET
689#define SCC_ENET 0
690#endif /* CONFIG_SCC1_ETHERNET */
691#define PROFF_ENET PROFF_SCC1
692#define CPM_CR_ENET CPM_CR_CH_SCC1
693
694#define PA_ENET_RXD ((ushort)0x0001)
695#define PA_ENET_TXD ((ushort)0x0002)
696#define PA_ENET_TCLK ((ushort)0x0100)
697#define PA_ENET_RCLK ((ushort)0x0200)
698
699#define PB_ENET_TENA ((uint)0x00001000)
700
701#define PC_ENET_CLSN ((ushort)0x0010)
702#define PC_ENET_RENA ((ushort)0x0020)
703
704#define SICR_ENET_MASK ((uint)0x000000ff)
705#define SICR_ENET_CLKRT ((uint)0x0000002c)
706
707/* This ENET stuff is for the MPC860TFADS with ethernet on FEC.
708 */
709
710#ifdef CONFIG_FEC_ENET
711#define FEC_ENET /* use FEC for EThernet */
712#endif /* CONFIG_FEC_ETHERNET */
713
714#endif /* CONFIG_FADS860T */
715
wdenk384ae022002-11-05 00:17:55 +0000716/*** FPS850L, FPS860L ************************************************/
wdenkfe8c2802002-11-03 00:38:21 +0000717
wdenk384ae022002-11-05 00:17:55 +0000718#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
wdenkfe8c2802002-11-03 00:38:21 +0000719/* Bits in parallel I/O port registers that have to be set/cleared
wdenk384ae022002-11-05 00:17:55 +0000720 * to configure the pins for SCC2 use.
wdenkfe8c2802002-11-03 00:38:21 +0000721 */
722#define PROFF_ENET PROFF_SCC2
723#define CPM_CR_ENET CPM_CR_CH_SCC2
724#define SCC_ENET 1
725#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
726#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
727#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
728#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
729
730#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
731#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
732#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
733
734/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
735 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
736 */
737#define SICR_ENET_MASK ((uint)0x0000ff00)
738#define SICR_ENET_CLKRT ((uint)0x00002600)
wdenk384ae022002-11-05 00:17:55 +0000739#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
wdenkfe8c2802002-11-03 00:38:21 +0000740
741/*** GEN860T **********************************************************/
742#if defined(CONFIG_GEN860T)
743#undef SCC_ENET
744#define FEC_ENET
745
746#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
747#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
748#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
749#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
750#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
751#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
752#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
753#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
754#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
755#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
756#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
757#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
758#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
759#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
760#endif /* CONFIG_GEN860T */
761
762/*** GENIETV ********************************************************/
763
764#if defined(CONFIG_GENIETV)
765/* Ethernet is only on SCC2 */
766
767#define CONFIG_SCC2_ENET
768#define PROFF_ENET PROFF_SCC2
769#define CPM_CR_ENET CPM_CR_CH_SCC2
770#define SCC_ENET 1
771#define CPMVEC_ENET CPMVEC_SCC2
772
773#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
774#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
775#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
776#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
777
778#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
779
780#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
781#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
782
783#define SICR_ENET_MASK ((uint)0x0000ff00)
784#define SICR_ENET_CLKRT ((uint)0x00002e00)
785
786#endif /* CONFIG_GENIETV */
787
788/*** GTH ******************************************************/
789
790#ifdef CONFIG_GTH
791#ifdef CONFIG_FEC_ENET
792#define FEC_ENET /* use FEC for EThernet */
793#endif /* CONFIG_FEC_ETHERNET */
794
795/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
796#define PROFF_ENET PROFF_SCC1
797#define CPM_CR_ENET CPM_CR_CH_SCC1
798#define SCC_ENET 0
799
800#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
801#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
802#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
803#define PA_ENET_RCLK ((ushort)0x0400) /* PA5 */
804
805#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
806
807#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
808#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
809
810/* NOTE. This is reset for 10Mbit port only */
811#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 */
812
813#define SICR_ENET_MASK ((uint)0x000000ff)
814
815/* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
816#define SICR_ENET_CLKRT ((uint)0x00000037)
817
818#endif /* CONFIG_GTH */
819
820/*** HERMES-PRO ******************************************************/
821
822/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
823
824#ifdef CONFIG_HERMES
825
826#define FEC_ENET /* use FEC for EThernet */
827#undef SCC_ENET
828
829
830#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
831#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
832#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
833#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
834#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
835#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
836#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
837#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
838#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
839#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
840#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
841#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
842#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
843
844#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
845
846#endif /* CONFIG_HERMES */
847
848/*** IAD210 **********************************************************/
849
850/* The IAD210 uses the FEC on a MPC860P for Ethernet */
851
852#if defined(CONFIG_IAD210)
853
854# define FEC_ENET /* use FEC for Ethernet */
855# undef SCC_ENET
856
857# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */
858# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */
859# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */
860# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */
861# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */
862# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */
863# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */
864# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */
865# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */
866# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */
867# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */
868# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */
869# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */
870
871# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */
872
873#endif /* CONFIG_IAD210 */
874
875/*** ICU862 **********************************************************/
876
877#if defined(CONFIG_ICU862)
878
879#ifdef CONFIG_FEC_ENET
880#define FEC_ENET /* use FEC for EThernet */
881#endif /* CONFIG_FEC_ETHERNET */
882
883#endif /* CONFIG_ICU862 */
884
885/*** IP860 **********************************************************/
886
887#if defined(CONFIG_IP860)
888/* Bits in parallel I/O port registers that have to be set/cleared
889 * to configure the pins for SCC1 use.
890 */
891#define PROFF_ENET PROFF_SCC1
892#define CPM_CR_ENET CPM_CR_CH_SCC1
893#define SCC_ENET 0
894#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
895#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
896#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
897#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
898
899#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
900#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
901#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
902
903#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
904#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
905
906/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
907 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
908 */
909#define SICR_ENET_MASK ((uint)0x000000ff)
910#define SICR_ENET_CLKRT ((uint)0x0000002C)
911#endif /* CONFIG_IP860 */
912
913/*** IVMS8 **********************************************************/
914
915/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
916
917#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
918
919#define FEC_ENET /* use FEC for EThernet */
920#undef SCC_ENET
921
922#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
923
924#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
925
926#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
927#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
928#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
929#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
930#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
931#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
932#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
933#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
934#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
935#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
936#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
937#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
938#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
939
940#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
941
942#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
943
wdenk56f94be2002-11-05 16:35:14 +0000944/*** KUP4K *********************************************************/
945/* The KUP4K uses the FEC on a MPC855T for Ethernet */
946
947#if defined(CONFIG_KUP4K)
948
949#define FEC_ENET /* use FEC for EThernet */
950#undef SCC_ENET
951
952#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
953
954#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
955
956#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
957#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
958#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
959#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
960#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
961#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
962#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
963#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
964#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
965#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
966#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
967#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
968#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
969
970#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
971
972#endif /* CONFIG_KUP4K */
973
974
wdenkfe8c2802002-11-03 00:38:21 +0000975/*** LANTEC *********************************************************/
976
977#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
978/* Bits in parallel I/O port registers that have to be set/cleared
979 * to configure the pins for SCC2 use.
980 */
981#define PROFF_ENET PROFF_SCC2
982#define CPM_CR_ENET CPM_CR_CH_SCC2
983#define SCC_ENET 1
984#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
985#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
986#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
987#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
988
989#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
990
991#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */
992#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
993#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
994
995/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
996 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
997 */
998#define SICR_ENET_MASK ((uint)0x0000FF00)
999#define SICR_ENET_CLKRT ((uint)0x00002E00)
1000#endif /* CONFIG_LANTEC v2 */
1001
1002/*** LWMON **********************************************************/
1003
1004#if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
1005/* Bits in parallel I/O port registers that have to be set/cleared
1006 * to configure the pins for SCC2 use.
1007 */
1008#define PROFF_ENET PROFF_SCC2
1009#define CPM_CR_ENET CPM_CR_CH_SCC2
1010#define SCC_ENET 1
1011#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1012#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1013#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
1014#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1015
1016#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1017
1018#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1019#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1020
1021/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
1022 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1023 */
1024#define SICR_ENET_MASK ((uint)0x0000ff00)
1025#define SICR_ENET_CLKRT ((uint)0x00003E00)
1026#endif /* CONFIG_LWMON */
1027
1028/*** NX823 ***********************************************/
1029
1030#if defined(CONFIG_NX823)
1031/* Bits in parallel I/O port registers that have to be set/cleared
1032 * to configure the pins for SCC1 use.
1033 */
1034#define PROFF_ENET PROFF_SCC2
1035#define CPM_CR_ENET CPM_CR_CH_SCC2
1036#define SCC_ENET 1
wdenk7c7a23b2002-12-07 00:20:59 +00001037#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1038#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1039#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1040#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
wdenkfe8c2802002-11-03 00:38:21 +00001041
wdenk7c7a23b2002-12-07 00:20:59 +00001042#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
wdenkfe8c2802002-11-03 00:38:21 +00001043
wdenk7c7a23b2002-12-07 00:20:59 +00001044#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1045#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
wdenkfe8c2802002-11-03 00:38:21 +00001046
1047/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1048 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1049 */
wdenk7c7a23b2002-12-07 00:20:59 +00001050#define SICR_ENET_MASK ((uint)0x0000ff00)
1051#define SICR_ENET_CLKRT ((uint)0x00002f00)
wdenkfe8c2802002-11-03 00:38:21 +00001052
1053#endif /* CONFIG_NX823 */
1054
1055/*** MBX ************************************************************/
1056
1057#ifdef CONFIG_MBX
1058/* Bits in parallel I/O port registers that have to be set/cleared
1059 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
1060 * to the MBX860 board. Any two of the four available clocks could be
1061 * used, and the MPC860 cookbook manual has an example using different
1062 * clock pins.
1063 */
1064#define PROFF_ENET PROFF_SCC1
1065#define CPM_CR_ENET CPM_CR_CH_SCC1
1066#define SCC_ENET 0
1067#define PA_ENET_RXD ((ushort)0x0001)
1068#define PA_ENET_TXD ((ushort)0x0002)
1069#define PA_ENET_TCLK ((ushort)0x0200)
1070#define PA_ENET_RCLK ((ushort)0x0800)
1071#define PC_ENET_TENA ((ushort)0x0001)
1072#define PC_ENET_CLSN ((ushort)0x0010)
1073#define PC_ENET_RENA ((ushort)0x0020)
1074
1075/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1076 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1077 */
1078#define SICR_ENET_MASK ((uint)0x000000ff)
1079#define SICR_ENET_CLKRT ((uint)0x0000003d)
1080#endif /* CONFIG_MBX */
1081
1082/*** MHPC ********************************************************/
1083
1084#if defined(CONFIG_MHPC)
1085/* This ENET stuff is for the MHPC with ethernet on SCC2.
1086 * Note TENA is on Port B.
1087 */
1088#define PROFF_ENET PROFF_SCC2
1089#define CPM_CR_ENET CPM_CR_CH_SCC2
1090#define SCC_ENET 1
1091#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1092#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1093#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1094#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1095#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1096#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1097#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1098
1099#define SICR_ENET_MASK ((uint)0x0000ff00)
1100#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
1101#endif /* CONFIG_MHPC */
1102
wdenk608c9142003-01-13 23:54:46 +00001103/*** NETVIA *******************************************************/
1104
1105#if defined(CONFIG_NETVIA)
1106/* Bits in parallel I/O port registers that have to be set/cleared
1107 * to configure the pins for SCC2 use.
1108 */
1109#define PROFF_ENET PROFF_SCC2
1110#define CPM_CR_ENET CPM_CR_CH_SCC2
1111#define SCC_ENET 1
1112#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1113#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1114#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1115#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
1116
1117#define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
1118#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
1119
1120#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1121#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1122
1123/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1124 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1125 */
1126#define SICR_ENET_MASK ((uint)0x0000ff00)
1127#define SICR_ENET_CLKRT ((uint)0x00002f00)
1128
1129#endif /* CONFIG_NETVIA */
1130
wdenkfe8c2802002-11-03 00:38:21 +00001131/*** RPXCLASSIC *****************************************************/
1132
1133#ifdef CONFIG_RPXCLASSIC
1134
1135#ifdef CONFIG_FEC_ENET
1136
1137# define FEC_ENET /* use FEC for EThernet */
1138# undef SCC_ENET
1139
1140#else /* ! CONFIG_FEC_ENET */
1141
1142/* Bits in parallel I/O port registers that have to be set/cleared
1143 * to configure the pins for SCC1 use.
1144 */
1145#define PROFF_ENET PROFF_SCC1
1146#define CPM_CR_ENET CPM_CR_CH_SCC1
1147#define SCC_ENET 0
1148#define PA_ENET_RXD ((ushort)0x0001)
1149#define PA_ENET_TXD ((ushort)0x0002)
1150#define PA_ENET_TCLK ((ushort)0x0200)
1151#define PA_ENET_RCLK ((ushort)0x0800)
1152#define PB_ENET_TENA ((uint)0x00001000)
1153#define PC_ENET_CLSN ((ushort)0x0010)
1154#define PC_ENET_RENA ((ushort)0x0020)
1155
1156/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1157 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1158 */
1159#define SICR_ENET_MASK ((uint)0x000000ff)
1160#define SICR_ENET_CLKRT ((uint)0x0000003d)
1161
1162#endif /* CONFIG_FEC_ENET */
1163
1164#endif /* CONFIG_RPXCLASSIC */
1165
1166/*** RPXLITE ********************************************************/
1167
1168#ifdef CONFIG_RPXLITE
1169/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
1170 * this may be unique to the RPX-Lite configuration.
1171 * Note TENA is on Port B.
1172 */
1173#define PROFF_ENET PROFF_SCC2
1174#define CPM_CR_ENET CPM_CR_CH_SCC2
1175#define SCC_ENET 1
1176#define PA_ENET_RXD ((ushort)0x0004)
1177#define PA_ENET_TXD ((ushort)0x0008)
1178#define PA_ENET_TCLK ((ushort)0x0200)
1179#define PA_ENET_RCLK ((ushort)0x0800)
1180#define PB_ENET_TENA ((uint)0x00002000)
1181#define PC_ENET_CLSN ((ushort)0x0040)
1182#define PC_ENET_RENA ((ushort)0x0080)
1183
1184#define SICR_ENET_MASK ((uint)0x0000ff00)
1185#define SICR_ENET_CLKRT ((uint)0x00003d00)
1186#endif /* CONFIG_RPXLITE */
1187
1188/*** SM850 *********************************************************/
1189
1190/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
1191
1192#ifdef CONFIG_SM850
1193#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
1194#define CPM_CR_ENET CPM_CR_CH_SCC3
1195#define SCC_ENET 2
1196#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
1197#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
1198#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1199#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1200
1201#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1202#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
1203
1204#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
1205#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
1206
1207/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1208 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1209 */
1210#define SICR_ENET_MASK ((uint)0x00FF0000)
1211#define SICR_ENET_CLKRT ((uint)0x00260000)
1212#endif /* CONFIG_SM850 */
1213
1214/*** SPD823TS ******************************************************/
1215
1216#ifdef CONFIG_SPD823TS
1217/* Bits in parallel I/O port registers that have to be set/cleared
1218 * to configure the pins for SCC2 use.
1219 */
1220#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
1221#define CPM_CR_ENET CPM_CR_CH_SCC2
1222#define SCC_ENET 1
1223#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
1224#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
1225#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1226#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1227#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1228#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1229
1230#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1231
1232#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1233#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1234#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
1235
1236/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1237 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1238 */
1239#define SICR_ENET_MASK ((uint)0x0000ff00)
1240#define SICR_ENET_CLKRT ((uint)0x00002E00)
1241#endif /* CONFIG_SPD823TS */
1242
1243/*** SXNI855T ******************************************************/
1244
1245#if defined(CONFIG_SXNI855T)
1246
1247#ifdef CONFIG_FEC_ENET
1248#define FEC_ENET /* use FEC for Ethernet */
1249#endif /* CONFIG_FEC_ETHERNET */
1250
1251#endif /* CONFIG_SXNI855T */
1252
1253/*** MVS1, TQM823L, TQM850L, ETX094, R360MPI ***********************/
1254
1255#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
1256 defined(CONFIG_R360MPI) || \
1257 defined(CONFIG_TQM823L) || \
1258 defined(CONFIG_TQM850L) || \
1259 defined(CONFIG_ETX094) || \
1260 defined(CONFIG_RRVISION)|| \
1261 (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
1262/* Bits in parallel I/O port registers that have to be set/cleared
1263 * to configure the pins for SCC2 use.
1264 */
1265#define PROFF_ENET PROFF_SCC2
1266#define CPM_CR_ENET CPM_CR_CH_SCC2
1267#define SCC_ENET 1
1268#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1269#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1270#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1271#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1272
1273#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1274
1275#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1276#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1277#if defined(CONFIG_R360MPI)
1278#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1279#endif /* CONFIG_R360MPI */
1280
1281/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1282 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1283 */
1284#define SICR_ENET_MASK ((uint)0x0000ff00)
1285#define SICR_ENET_CLKRT ((uint)0x00002600)
1286#endif /* CONFIG_MVS v1, CONFIG_TQM823L, CONFIG_TQM850L, etc. */
1287
1288/*** TQM860L, TQM855L ************************************************/
1289
1290#if (defined(CONFIG_TQM860L) || defined(CONFIG_TQM855L))
1291
1292# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
1293
1294/* Bits in parallel I/O port registers that have to be set/cleared
1295 * to configure the pins for SCC1 use.
1296 */
1297#define PROFF_ENET PROFF_SCC1
1298#define CPM_CR_ENET CPM_CR_CH_SCC1
1299#define SCC_ENET 0
1300#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
1301#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
1302#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1303#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1304
1305#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
1306#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
1307#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
1308
1309/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1310 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1311 */
1312#define SICR_ENET_MASK ((uint)0x000000ff)
1313#define SICR_ENET_CLKRT ((uint)0x00000026)
1314
1315# endif /* CONFIG_SCC1_ENET */
1316
1317# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1318
1319#define FEC_ENET
1320
1321#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
1322#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
1323#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
1324#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1325#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1326#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1327#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1328#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1329#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1330#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1331#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1332#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1333#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1334
1335#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1336
1337# endif /* CONFIG_FEC_ENET */
1338#endif /* CONFIG_TQM860L, CONFIG_TQM855L */
1339
wdenk608c9142003-01-13 23:54:46 +00001340/*** V37 **********************************************************/
1341
1342#ifdef CONFIG_V37
1343/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
1344 * this may be unique to the Marel V37 configuration.
1345 * Note TENA is on Port B.
wdenkfe8c2802002-11-03 00:38:21 +00001346 */
1347#define PROFF_ENET PROFF_SCC2
1348#define CPM_CR_ENET CPM_CR_CH_SCC2
1349#define SCC_ENET 1
wdenk608c9142003-01-13 23:54:46 +00001350#define PA_ENET_RXD ((ushort)0x0004)
1351#define PA_ENET_TXD ((ushort)0x0008)
1352#define PA_ENET_TCLK ((ushort)0x0400)
1353#define PA_ENET_RCLK ((ushort)0x0200)
1354#define PB_ENET_TENA ((uint)0x00002000)
1355#define PC_ENET_CLSN ((ushort)0x0040)
1356#define PC_ENET_RENA ((ushort)0x0080)
wdenkfe8c2802002-11-03 00:38:21 +00001357
wdenkfe8c2802002-11-03 00:38:21 +00001358#define SICR_ENET_MASK ((uint)0x0000ff00)
wdenk608c9142003-01-13 23:54:46 +00001359#define SICR_ENET_CLKRT ((uint)0x00002e00)
1360#endif /* CONFIG_V37 */
wdenkfe8c2802002-11-03 00:38:21 +00001361
1362/*********************************************************************/
1363
1364/* SCC Event register as used by Ethernet.
1365*/
1366#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
1367#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
1368#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
1369#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
1370#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
1371#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
1372
1373/* SCC Mode Register (PSMR) as used by Ethernet.
1374*/
1375#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
1376#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
1377#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
1378#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
1379#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
1380#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
1381#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
1382#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
1383#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
1384#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
1385#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
1386#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
1387#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
1388
1389/* Buffer descriptor control/status used by Ethernet receive.
1390*/
1391#define BD_ENET_RX_EMPTY ((ushort)0x8000)
1392#define BD_ENET_RX_WRAP ((ushort)0x2000)
1393#define BD_ENET_RX_INTR ((ushort)0x1000)
1394#define BD_ENET_RX_LAST ((ushort)0x0800)
1395#define BD_ENET_RX_FIRST ((ushort)0x0400)
1396#define BD_ENET_RX_MISS ((ushort)0x0100)
1397#define BD_ENET_RX_LG ((ushort)0x0020)
1398#define BD_ENET_RX_NO ((ushort)0x0010)
1399#define BD_ENET_RX_SH ((ushort)0x0008)
1400#define BD_ENET_RX_CR ((ushort)0x0004)
1401#define BD_ENET_RX_OV ((ushort)0x0002)
1402#define BD_ENET_RX_CL ((ushort)0x0001)
1403#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
1404
1405/* Buffer descriptor control/status used by Ethernet transmit.
1406*/
1407#define BD_ENET_TX_READY ((ushort)0x8000)
1408#define BD_ENET_TX_PAD ((ushort)0x4000)
1409#define BD_ENET_TX_WRAP ((ushort)0x2000)
1410#define BD_ENET_TX_INTR ((ushort)0x1000)
1411#define BD_ENET_TX_LAST ((ushort)0x0800)
1412#define BD_ENET_TX_TC ((ushort)0x0400)
1413#define BD_ENET_TX_DEF ((ushort)0x0200)
1414#define BD_ENET_TX_HB ((ushort)0x0100)
1415#define BD_ENET_TX_LC ((ushort)0x0080)
1416#define BD_ENET_TX_RL ((ushort)0x0040)
1417#define BD_ENET_TX_RCMASK ((ushort)0x003c)
1418#define BD_ENET_TX_UN ((ushort)0x0002)
1419#define BD_ENET_TX_CSL ((ushort)0x0001)
1420#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
1421
1422/* SCC as UART
1423*/
1424typedef struct scc_uart {
1425 sccp_t scc_genscc;
1426 uint scc_res1; /* Reserved */
1427 uint scc_res2; /* Reserved */
1428 ushort scc_maxidl; /* Maximum idle chars */
1429 ushort scc_idlc; /* temp idle counter */
1430 ushort scc_brkcr; /* Break count register */
1431 ushort scc_parec; /* receive parity error counter */
1432 ushort scc_frmec; /* receive framing error counter */
1433 ushort scc_nosec; /* receive noise counter */
1434 ushort scc_brkec; /* receive break condition counter */
1435 ushort scc_brkln; /* last received break length */
1436 ushort scc_uaddr1; /* UART address character 1 */
1437 ushort scc_uaddr2; /* UART address character 2 */
1438 ushort scc_rtemp; /* Temp storage */
1439 ushort scc_toseq; /* Transmit out of sequence char */
1440 ushort scc_char1; /* control character 1 */
1441 ushort scc_char2; /* control character 2 */
1442 ushort scc_char3; /* control character 3 */
1443 ushort scc_char4; /* control character 4 */
1444 ushort scc_char5; /* control character 5 */
1445 ushort scc_char6; /* control character 6 */
1446 ushort scc_char7; /* control character 7 */
1447 ushort scc_char8; /* control character 8 */
1448 ushort scc_rccm; /* receive control character mask */
1449 ushort scc_rccr; /* receive control character register */
1450 ushort scc_rlbc; /* receive last break character */
1451} scc_uart_t;
1452
1453/* SCC Event and Mask registers when it is used as a UART.
1454*/
1455#define UART_SCCM_GLR ((ushort)0x1000)
1456#define UART_SCCM_GLT ((ushort)0x0800)
1457#define UART_SCCM_AB ((ushort)0x0200)
1458#define UART_SCCM_IDL ((ushort)0x0100)
1459#define UART_SCCM_GRA ((ushort)0x0080)
1460#define UART_SCCM_BRKE ((ushort)0x0040)
1461#define UART_SCCM_BRKS ((ushort)0x0020)
1462#define UART_SCCM_CCR ((ushort)0x0008)
1463#define UART_SCCM_BSY ((ushort)0x0004)
1464#define UART_SCCM_TX ((ushort)0x0002)
1465#define UART_SCCM_RX ((ushort)0x0001)
1466
1467/* The SCC PSMR when used as a UART.
1468*/
1469#define SCU_PSMR_FLC ((ushort)0x8000)
1470#define SCU_PSMR_SL ((ushort)0x4000)
1471#define SCU_PSMR_CL ((ushort)0x3000)
1472#define SCU_PSMR_UM ((ushort)0x0c00)
1473#define SCU_PSMR_FRZ ((ushort)0x0200)
1474#define SCU_PSMR_RZS ((ushort)0x0100)
1475#define SCU_PSMR_SYN ((ushort)0x0080)
1476#define SCU_PSMR_DRT ((ushort)0x0040)
1477#define SCU_PSMR_PEN ((ushort)0x0010)
1478#define SCU_PSMR_RPM ((ushort)0x000c)
1479#define SCU_PSMR_REVP ((ushort)0x0008)
1480#define SCU_PSMR_TPM ((ushort)0x0003)
1481#define SCU_PSMR_TEVP ((ushort)0x0003)
1482
1483/* CPM Transparent mode SCC.
1484 */
1485typedef struct scc_trans {
1486 sccp_t st_genscc;
1487 uint st_cpres; /* Preset CRC */
1488 uint st_cmask; /* Constant mask for CRC */
1489} scc_trans_t;
1490
1491#define BD_SCC_TX_LAST ((ushort)0x0800)
1492
1493/* IIC parameter RAM.
1494*/
1495typedef struct iic {
1496 ushort iic_rbase; /* Rx Buffer descriptor base address */
1497 ushort iic_tbase; /* Tx Buffer descriptor base address */
1498 u_char iic_rfcr; /* Rx function code */
1499 u_char iic_tfcr; /* Tx function code */
1500 ushort iic_mrblr; /* Max receive buffer length */
1501 uint iic_rstate; /* Internal */
1502 uint iic_rdp; /* Internal */
1503 ushort iic_rbptr; /* Internal */
1504 ushort iic_rbc; /* Internal */
1505 uint iic_rxtmp; /* Internal */
1506 uint iic_tstate; /* Internal */
1507 uint iic_tdp; /* Internal */
1508 ushort iic_tbptr; /* Internal */
1509 ushort iic_tbc; /* Internal */
1510 uint iic_txtmp; /* Internal */
1511 uint iic_res; /* reserved */
1512 ushort iic_rpbase; /* Relocation pointer */
1513 ushort iic_res2; /* reserved */
1514} iic_t;
1515
1516/* SPI parameter RAM.
1517*/
1518typedef struct spi {
1519 ushort spi_rbase; /* Rx Buffer descriptor base address */
1520 ushort spi_tbase; /* Tx Buffer descriptor base address */
1521 u_char spi_rfcr; /* Rx function code */
1522 u_char spi_tfcr; /* Tx function code */
1523 ushort spi_mrblr; /* Max receive buffer length */
1524 uint spi_rstate; /* Internal */
1525 uint spi_rdp; /* Internal */
1526 ushort spi_rbptr; /* Internal */
1527 ushort spi_rbc; /* Internal */
1528 uint spi_rxtmp; /* Internal */
1529 uint spi_tstate; /* Internal */
1530 uint spi_tdp; /* Internal */
1531 ushort spi_tbptr; /* Internal */
1532 ushort spi_tbc; /* Internal */
1533 uint spi_txtmp; /* Internal */
1534 uint spi_res;
1535 ushort spi_rpbase; /* Relocation pointer */
1536 ushort spi_res2;
1537} spi_t;
1538
1539/* SPI Mode register.
1540*/
1541#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
1542#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
1543#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
1544#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
1545#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
1546#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
1547#define SPMODE_EN ((ushort)0x0100) /* Enable */
1548#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
1549#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
1550
1551#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
1552#define SPMODE_PM(x) ((x) &0xF)
1553
1554/* HDLC parameter RAM.
1555*/
1556
1557typedef struct hdlc_pram_s {
1558 /*
1559 * SCC parameter RAM
1560 */
1561 ushort rbase; /* Rx Buffer descriptor base address */
1562 ushort tbase; /* Tx Buffer descriptor base address */
1563 uchar rfcr; /* Rx function code */
1564 uchar tfcr; /* Tx function code */
1565 ushort mrblr; /* Rx buffer length */
1566 ulong rstate; /* Rx internal state */
1567 ulong rptr; /* Rx internal data pointer */
1568 ushort rbptr; /* rb BD Pointer */
1569 ushort rcount; /* Rx internal byte count */
1570 ulong rtemp; /* Rx temp */
1571 ulong tstate; /* Tx internal state */
1572 ulong tptr; /* Tx internal data pointer */
1573 ushort tbptr; /* Tx BD pointer */
1574 ushort tcount; /* Tx byte count */
1575 ulong ttemp; /* Tx temp */
1576 ulong rcrc; /* temp receive CRC */
1577 ulong tcrc; /* temp transmit CRC */
1578 /*
1579 * HDLC specific parameter RAM
1580 */
1581 uchar res[4]; /* reserved */
1582 ulong c_mask; /* CRC constant */
1583 ulong c_pres; /* CRC preset */
1584 ushort disfc; /* discarded frame counter */
1585 ushort crcec; /* CRC error counter */
1586 ushort abtsc; /* abort sequence counter */
1587 ushort nmarc; /* nonmatching address rx cnt */
1588 ushort retrc; /* frame retransmission cnt */
1589 ushort mflr; /* maximum frame length reg */
1590 ushort max_cnt; /* maximum length counter */
1591 ushort rfthr; /* received frames threshold */
1592 ushort rfcnt; /* received frames count */
1593 ushort hmask; /* user defined frm addr mask */
1594 ushort haddr1; /* user defined frm address 1 */
1595 ushort haddr2; /* user defined frm address 2 */
1596 ushort haddr3; /* user defined frm address 3 */
1597 ushort haddr4; /* user defined frm address 4 */
1598 ushort tmp; /* temp */
1599 ushort tmp_mb; /* temp */
1600} hdlc_pram_t;
1601
1602/* CPM interrupts. There are nearly 32 interrupts generated by CPM
1603 * channels or devices. All of these are presented to the PPC core
1604 * as a single interrupt. The CPM interrupt handler dispatches its
1605 * own handlers, in a similar fashion to the PPC core handler. We
1606 * use the table as defined in the manuals (i.e. no special high
1607 * priority and SCC1 == SCCa, etc...).
1608 */
1609#define CPMVEC_NR 32
wdenk7c7a23b2002-12-07 00:20:59 +00001610#define CPMVEC_OFFSET 0x00010000
1611#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
1612#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
1613#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
1614#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
1615#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
1616#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
1617#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
1618#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
1619#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
1620#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
1621#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
1622#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
1623#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
1624#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
1625#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
1626#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
1627#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
1628#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
1629#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
1630#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
1631#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
1632#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
1633#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
1634#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
1635#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
1636#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
1637#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
1638#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
1639#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
wdenkfe8c2802002-11-03 00:38:21 +00001640
1641extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1642
1643/* CPM interrupt configuration vector.
1644*/
1645#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
1646#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
1647#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
1648#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
1649#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
1650#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
1651#define CICR_IEN ((uint)0x00000080) /* Int. enable */
1652#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
1653#endif /* __CPM_8XX__ */