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gerrit.nordix.org / codeaurora / quic / qsdk / oss / boot / u-boot-2016 / 6d0f6bcf337c5261c08fabe12982178c2c489d76 / . / include / mpc5xxx.h
blob: 3a3282152a83f4538d2c6200d3167d7ba9c58c8e [file] [log] [blame]
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]1/*
2 * include/asm-ppc/mpc5xxx.h
3 *
4 * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
5 * embedded cpu chips
6 *
7 * 2003 (c) MontaVista, Software, Inc.
8 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
9 *
10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#ifndef __ASMPPC_MPC5XXX_H
31#define __ASMPPC_MPC5XXX_H
32
33/* Processor name */
34#if defined(CONFIG_MPC5200)
35#define CPU_ID_STR "MPC5200"
36#elif defined(CONFIG_MGT5100)
37#define CPU_ID_STR "MGT5100"
38#endif
39
40/* Exception offsets (PowerPC standard) */
41#define EXC_OFF_SYS_RESET 0x0100
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200[diff] [blame]42#define _START_OFFSET EXC_OFF_SYS_RESET
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]43
wdenk7152b1d2003-09-05 23:19:14 +0000[diff] [blame]44/* useful macros for manipulating CSx_START/STOP */
45#if defined(CONFIG_MGT5100)
46#define START_REG(start) ((start) >> 15)
47#define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
48#elif defined(CONFIG_MPC5200)
49#define START_REG(start) ((start) >> 16)
50#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
51#endif
52
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]53/* Internal memory map */
54
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]55#define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004)
56#define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008)
57#define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c)
58#define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010)
59#define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014)
60#define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018)
61#define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c)
62#define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020)
63#define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024)
64#define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028)
65#define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c)
66#define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030)
67#define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c)
68#define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050)
69#define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]70
71#if defined(CONFIG_MGT5100)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]72#define MPC5XXX_SDRAM_START (CONFIG_SYS_MBAR + 0x0034)
73#define MPC5XXX_SDRAM_STOP (CONFIG_SYS_MBAR + 0x0038)
74#define MPC5XXX_PCI1_START (CONFIG_SYS_MBAR + 0x003c)
75#define MPC5XXX_PCI1_STOP (CONFIG_SYS_MBAR + 0x0040)
76#define MPC5XXX_PCI2_START (CONFIG_SYS_MBAR + 0x0044)
77#define MPC5XXX_PCI2_STOP (CONFIG_SYS_MBAR + 0x0048)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]78#elif defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]79#define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058)
80#define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c)
81#define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060)
82#define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064)
83#define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034)
84#define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]85#endif
86
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]87#define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100)
88#define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200)
89#define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300)
90#define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500)
91#define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600)
92#define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00)
93#define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00)
94#define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00)
95#define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00)
96#define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000)
97#define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200)
98#define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]99
100#if defined(CONFIG_MGT5100)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]101#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
102#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2400)
103#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2800)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]104#elif defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]105#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
106#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200)
107#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400)
108#define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600)
109#define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800)
110#define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]111#endif
112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]113#define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000)
114#define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]116#define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00)
117#define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40)
wdenk531716e2003-09-13 19:01:12 +0000[diff] [blame]118
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]119#if defined(CONFIG_MGT5100)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]120#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x4000)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]121#define MPC5XXX_SRAM_SIZE (8*1024)
122#elif defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame^]123#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]124#define MPC5XXX_SRAM_SIZE (16*1024)
125#endif
126
127/* SDRAM Controller */
128#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
129#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
130#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
131#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
132#if defined(CONFIG_MGT5100)
133#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
134#endif
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200[diff] [blame]135#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]136
137/* Clock Distribution Module */
138#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
139#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
Axel Beierleinbef92e22008-08-16 00:30:48 +0200[diff] [blame]140#define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]141#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
wdenk80885a92004-02-26 23:46:20 +0000[diff] [blame]142#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]143#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
144
145/* Local Plus Bus interface */
146#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
147#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
148#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
149#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
150#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
151#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
152#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
153#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
154#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
155#if defined(CONFIG_MPC5200)
156#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
157#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
158#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
159#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
160#endif
161
wdenk4aeb2512003-09-16 17:06:05 +0000[diff] [blame]162#if defined(CONFIG_MPC5200)
163/* XLB Arbiter registers */
164#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
165#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
166#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
167#endif
168
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]169/* GPIO registers */
170#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
171
wdenk6c7a1402004-07-11 19:17:20 +0000[diff] [blame]172/* Standard GPIO registers (simple, output only and simple interrupt */
173#define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
174#define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008)
175#define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c)
176#define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010)
177#define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014)
178#define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018)
179#define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C)
180#define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020)
181#define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024)
182#define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028)
183#define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C)
184#define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030)
185#define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034)
186#define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038)
187#define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C)
188
wdenk132ba5f2004-02-27 08:20:54 +0000[diff] [blame]189/* WakeUp GPIO registers */
190#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
191#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
192#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100[diff] [blame]193#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
194#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
195
196/* GPIO pins */
197#define GPIO_WKUP_7 0x80000000UL
198#define GPIO_PSC6_0 0x10000000UL
199#define GPIO_PSC3_9 0x04000000UL
200#define GPIO_PSC1_4 0x01000000UL
wdenk132ba5f2004-02-27 08:20:54 +0000[diff] [blame]201
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200[diff] [blame]202#define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL
203#define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL
204#define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL
205#define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL
206#define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL
207#define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL
208#define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL
209#define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL
210#define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL
211#define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL
212#define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL
213#define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL
214#define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL
215#define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL
216#define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL
217#define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL
218
219#define MPC5XXX_GPIO_SINT_PSC3_5 0x02
220#define MPC5XXX_GPIO_SINT_PSC3_4 0x01
221
222#define MPC5XXX_GPIO_WKUP_7 0x80
223#define MPC5XXX_GPIO_WKUP_6 0x40
224#define MPC5XXX_GPIO_WKUP_PSC6_1 0x20
225#define MPC5XXX_GPIO_WKUP_PSC6_0 0x10
226#define MPC5XXX_GPIO_WKUP_ETH17 0x08
227#define MPC5XXX_GPIO_WKUP_PSC3_9 0x04
228#define MPC5XXX_GPIO_WKUP_PSC2_4 0x02
229#define MPC5XXX_GPIO_WKUP_PSC1_4 0x01
230
wdenk96e48cf2003-08-05 18:22:44 +0000[diff] [blame]231/* PCI registers */
232#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
233#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
234#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
235#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
236#if defined(CONFIG_MGT5100)
237#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
238#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
239#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
240#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
241#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
242#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
243#elif defined(CONFIG_MPC5200)
244#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
245#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
246#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
247#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
248#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
249#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
250#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
251#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
252#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
253#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
254#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
255#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
256#endif
257
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]258/* Interrupt Controller registers */
259#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
260#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
261#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
262#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
263#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
264#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
265#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
266#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
267#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
268#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
269#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
270#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
271#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
272
Detlev Zundel43835aa2006-09-01 11:59:23 +0200[diff] [blame]273#define NR_IRQS 64
274
275/* IRQ mapping - these are our logical IRQ numbers */
276#define MPC5XXX_CRIT_IRQ_NUM 4
277#define MPC5XXX_MAIN_IRQ_NUM 17
278#define MPC5XXX_SDMA_IRQ_NUM 17
279#define MPC5XXX_PERP_IRQ_NUM 23
280
281#define MPC5XXX_CRIT_IRQ_BASE 1
282#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
283#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
284#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
285
286#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
287#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
288#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
289#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
290
291#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
292#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
293#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
294#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
295#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
296#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
297#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
298#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
299#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
300#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
301#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
302#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
303#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
304#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
305#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
306
307#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
308#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
309#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
310#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
311#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
312#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
313#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
314#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
315#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
316#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
317#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
318#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
319#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
320#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
321#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
322#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
323#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
324#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
325#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
326#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
327#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
328#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
329#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
330#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
331
wdenkd94f92c2003-08-28 09:41:22 +0000[diff] [blame]332/* General Purpose Timers registers */
333#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
334#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200[diff] [blame]335#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
wdenkf4733a02005-03-06 01:21:30 +0000[diff] [blame]336#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
337#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200[diff] [blame]338#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
wdenkf4733a02005-03-06 01:21:30 +0000[diff] [blame]339#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
340#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200[diff] [blame]341#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
wdenkf4733a02005-03-06 01:21:30 +0000[diff] [blame]342#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
343#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200[diff] [blame]344#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
wdenkf4733a02005-03-06 01:21:30 +0000[diff] [blame]345#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
346#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200[diff] [blame]347#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
wdenkf4733a02005-03-06 01:21:30 +0000[diff] [blame]348#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200[diff] [blame]349#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
wdenkf4733a02005-03-06 01:21:30 +0000[diff] [blame]350#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
351#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
352#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200[diff] [blame]353#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
wdenkf4733a02005-03-06 01:21:30 +0000[diff] [blame]354#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
355#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
Marian Balakowicz6d3bc9b2006-08-18 19:14:46 +0200[diff] [blame]356#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
357
358#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
wdenkf4733a02005-03-06 01:21:30 +0000[diff] [blame]359
wdenka0bdf492005-03-14 13:14:58 +0000[diff] [blame]360#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)
wdenkd94f92c2003-08-28 09:41:22 +0000[diff] [blame]361
wdenk132ba5f2004-02-27 08:20:54 +0000[diff] [blame]362/* ATA registers */
363#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
364#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
365#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
366#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
367
wdenk531716e2003-09-13 19:01:12 +0000[diff] [blame]368/* I2Cn control register bits */
369#define I2C_EN 0x80
370#define I2C_IEN 0x40
371#define I2C_STA 0x20
372#define I2C_TX 0x10
373#define I2C_TXAK 0x08
374#define I2C_RSTA 0x04
375#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
376
377/* I2Cn status register bits */
378#define I2C_CF 0x80
379#define I2C_AAS 0x40
380#define I2C_BB 0x20
381#define I2C_AL 0x10
382#define I2C_SRW 0x04
383#define I2C_IF 0x02
384#define I2C_RXAK 0x01
385
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]386/* Programmable Serial Controller (PSC) status register bits */
387#define PSC_SR_CDE 0x0080
388#define PSC_SR_RXRDY 0x0100
389#define PSC_SR_RXFULL 0x0200
390#define PSC_SR_TXRDY 0x0400
391#define PSC_SR_TXEMP 0x0800
392#define PSC_SR_OE 0x1000
393#define PSC_SR_PE 0x2000
394#define PSC_SR_FE 0x4000
395#define PSC_SR_RB 0x8000
396
397/* PSC Command values */
398#define PSC_RX_ENABLE 0x0001
399#define PSC_RX_DISABLE 0x0002
400#define PSC_TX_ENABLE 0x0004
401#define PSC_TX_DISABLE 0x0008
402#define PSC_SEL_MODE_REG_1 0x0010
403#define PSC_RST_RX 0x0020
404#define PSC_RST_TX 0x0030
405#define PSC_RST_ERR_STAT 0x0040
406#define PSC_RST_BRK_CHG_INT 0x0050
407#define PSC_START_BRK 0x0060
408#define PSC_STOP_BRK 0x0070
409
410/* PSC Rx FIFO status bits */
411#define PSC_RX_FIFO_ERR 0x0040
412#define PSC_RX_FIFO_UF 0x0020
413#define PSC_RX_FIFO_OF 0x0010
414#define PSC_RX_FIFO_FR 0x0008
415#define PSC_RX_FIFO_FULL 0x0004
416#define PSC_RX_FIFO_ALARM 0x0002
417#define PSC_RX_FIFO_EMPTY 0x0001
418
419/* PSC interrupt mask bits */
420#define PSC_IMR_TXRDY 0x0100
421#define PSC_IMR_RXRDY 0x0200
422#define PSC_IMR_DB 0x0400
423#define PSC_IMR_IPC 0x8000
424
425/* PSC input port change bits */
426#define PSC_IPCR_CTS 0x01
427#define PSC_IPCR_DCD 0x02
428
429/* PSC mode fields */
430#define PSC_MODE_5_BITS 0x00
431#define PSC_MODE_6_BITS 0x01
432#define PSC_MODE_7_BITS 0x02
433#define PSC_MODE_8_BITS 0x03
434#define PSC_MODE_PAREVEN 0x00
435#define PSC_MODE_PARODD 0x04
436#define PSC_MODE_PARFORCE 0x08
437#define PSC_MODE_PARNONE 0x10
438#define PSC_MODE_ERR 0x20
439#define PSC_MODE_FFULL 0x40
440#define PSC_MODE_RXRTS 0x80
441
442#define PSC_MODE_ONE_STOP_5_BITS 0x00
443#define PSC_MODE_ONE_STOP 0x07
444#define PSC_MODE_TWO_STOP 0x0f
445
wdenk132ba5f2004-02-27 08:20:54 +0000[diff] [blame]446/* ATA config fields */
447#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
448 reset */
449#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
450#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
451 in PIO */
452#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
453 IORDY protocol */
454
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]455#ifndef __ASSEMBLY__
456struct mpc5xxx_psc {
457 volatile u8 mode; /* PSC + 0x00 */
458 volatile u8 reserved0[3];
459 union { /* PSC + 0x04 */
460 volatile u16 status;
461 volatile u16 clock_select;
462 } sr_csr;
463#define psc_status sr_csr.status
464#define psc_clock_select sr_csr.clock_select
465 volatile u16 reserved1;
466 volatile u8 command; /* PSC + 0x08 */
467 volatile u8 reserved2[3];
468 union { /* PSC + 0x0c */
469 volatile u8 buffer_8;
470 volatile u16 buffer_16;
471 volatile u32 buffer_32;
472 } buffer;
473#define psc_buffer_8 buffer.buffer_8
474#define psc_buffer_16 buffer.buffer_16
475#define psc_buffer_32 buffer.buffer_32
476 union { /* PSC + 0x10 */
477 volatile u8 ipcr;
478 volatile u8 acr;
479 } ipcr_acr;
480#define psc_ipcr ipcr_acr.ipcr
481#define psc_acr ipcr_acr.acr
482 volatile u8 reserved3[3];
483 union { /* PSC + 0x14 */
484 volatile u16 isr;
485 volatile u16 imr;
486 } isr_imr;
487#define psc_isr isr_imr.isr
488#define psc_imr isr_imr.imr
489 volatile u16 reserved4;
490 volatile u8 ctur; /* PSC + 0x18 */
491 volatile u8 reserved5[3];
492 volatile u8 ctlr; /* PSC + 0x1c */
Wolfgang Denk6617aae2005-08-19 00:46:54 +0200[diff] [blame]493 volatile u8 reserved6[3];
494 volatile u16 ccr; /* PSC + 0x20 */
495 volatile u8 reserved7[14];
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]496 volatile u8 ivr; /* PSC + 0x30 */
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]497 volatile u8 reserved8[3];
Wolfgang Denk6617aae2005-08-19 00:46:54 +0200[diff] [blame]498 volatile u8 ip; /* PSC + 0x34 */
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]499 volatile u8 reserved9[3];
Wolfgang Denk6617aae2005-08-19 00:46:54 +0200[diff] [blame]500 volatile u8 op1; /* PSC + 0x38 */
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]501 volatile u8 reserved10[3];
Wolfgang Denk6617aae2005-08-19 00:46:54 +0200[diff] [blame]502 volatile u8 op0; /* PSC + 0x3c */
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]503 volatile u8 reserved11[3];
Wolfgang Denk6617aae2005-08-19 00:46:54 +0200[diff] [blame]504 volatile u32 sicr; /* PSC + 0x40 */
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]505 volatile u8 ircr1; /* PSC + 0x44 */
506 volatile u8 reserved12[3];
507 volatile u8 ircr2; /* PSC + 0x44 */
508 volatile u8 reserved13[3];
509 volatile u8 irsdr; /* PSC + 0x4c */
510 volatile u8 reserved14[3];
511 volatile u8 irmdr; /* PSC + 0x50 */
512 volatile u8 reserved15[3];
513 volatile u8 irfdr; /* PSC + 0x54 */
514 volatile u8 reserved16[3];
515 volatile u16 rfnum; /* PSC + 0x58 */
516 volatile u16 reserved17;
517 volatile u16 tfnum; /* PSC + 0x5c */
518 volatile u16 reserved18;
519 volatile u32 rfdata; /* PSC + 0x60 */
520 volatile u16 rfstat; /* PSC + 0x64 */
521 volatile u16 reserved20;
522 volatile u8 rfcntl; /* PSC + 0x68 */
523 volatile u8 reserved21[5];
524 volatile u16 rfalarm; /* PSC + 0x6e */
525 volatile u16 reserved22;
526 volatile u16 rfrptr; /* PSC + 0x72 */
527 volatile u16 reserved23;
528 volatile u16 rfwptr; /* PSC + 0x76 */
529 volatile u16 reserved24;
530 volatile u16 rflrfptr; /* PSC + 0x7a */
531 volatile u16 reserved25;
532 volatile u16 rflwfptr; /* PSC + 0x7e */
533 volatile u32 tfdata; /* PSC + 0x80 */
534 volatile u16 tfstat; /* PSC + 0x84 */
535 volatile u16 reserved26;
536 volatile u8 tfcntl; /* PSC + 0x88 */
537 volatile u8 reserved27[5];
538 volatile u16 tfalarm; /* PSC + 0x8e */
539 volatile u16 reserved28;
540 volatile u16 tfrptr; /* PSC + 0x92 */
541 volatile u16 reserved29;
542 volatile u16 tfwptr; /* PSC + 0x96 */
543 volatile u16 reserved30;
544 volatile u16 tflrfptr; /* PSC + 0x9a */
545 volatile u16 reserved31;
546 volatile u16 tflwfptr; /* PSC + 0x9e */
547};
548
549struct mpc5xxx_intr {
550 volatile u32 per_mask; /* INTR + 0x00 */
551 volatile u32 per_pri1; /* INTR + 0x04 */
552 volatile u32 per_pri2; /* INTR + 0x08 */
553 volatile u32 per_pri3; /* INTR + 0x0c */
554 volatile u32 ctrl; /* INTR + 0x10 */
555 volatile u32 main_mask; /* INTR + 0x14 */
556 volatile u32 main_pri1; /* INTR + 0x18 */
557 volatile u32 main_pri2; /* INTR + 0x1c */
558 volatile u32 reserved1; /* INTR + 0x20 */
559 volatile u32 enc_status; /* INTR + 0x24 */
560 volatile u32 crit_status; /* INTR + 0x28 */
561 volatile u32 main_status; /* INTR + 0x2c */
562 volatile u32 per_status; /* INTR + 0x30 */
563 volatile u32 reserved2; /* INTR + 0x34 */
564 volatile u32 per_error; /* INTR + 0x38 */
565};
566
567struct mpc5xxx_gpio {
568 volatile u32 port_config; /* GPIO + 0x00 */
569 volatile u32 simple_gpioe; /* GPIO + 0x04 */
570 volatile u32 simple_ode; /* GPIO + 0x08 */
571 volatile u32 simple_ddr; /* GPIO + 0x0c */
572 volatile u32 simple_dvo; /* GPIO + 0x10 */
573 volatile u32 simple_ival; /* GPIO + 0x14 */
574 volatile u8 outo_gpioe; /* GPIO + 0x18 */
575 volatile u8 reserved1[3]; /* GPIO + 0x19 */
576 volatile u8 outo_dvo; /* GPIO + 0x1c */
577 volatile u8 reserved2[3]; /* GPIO + 0x1d */
578 volatile u8 sint_gpioe; /* GPIO + 0x20 */
579 volatile u8 reserved3[3]; /* GPIO + 0x21 */
580 volatile u8 sint_ode; /* GPIO + 0x24 */
581 volatile u8 reserved4[3]; /* GPIO + 0x25 */
582 volatile u8 sint_ddr; /* GPIO + 0x28 */
583 volatile u8 reserved5[3]; /* GPIO + 0x29 */
584 volatile u8 sint_dvo; /* GPIO + 0x2c */
585 volatile u8 reserved6[3]; /* GPIO + 0x2d */
586 volatile u8 sint_inten; /* GPIO + 0x30 */
587 volatile u8 reserved7[3]; /* GPIO + 0x31 */
588 volatile u16 sint_itype; /* GPIO + 0x34 */
589 volatile u16 reserved8; /* GPIO + 0x36 */
590 volatile u8 gpio_control; /* GPIO + 0x38 */
591 volatile u8 reserved9[3]; /* GPIO + 0x39 */
592 volatile u8 sint_istat; /* GPIO + 0x3c */
593 volatile u8 sint_ival; /* GPIO + 0x3d */
594 volatile u8 bus_errs; /* GPIO + 0x3e */
595 volatile u8 reserved10; /* GPIO + 0x3f */
596};
597
598struct mpc5xxx_sdma {
599 volatile u32 taskBar; /* SDMA + 0x00 */
600 volatile u32 currentPointer; /* SDMA + 0x04 */
601 volatile u32 endPointer; /* SDMA + 0x08 */
602 volatile u32 variablePointer; /* SDMA + 0x0c */
603
604 volatile u8 IntVect1; /* SDMA + 0x10 */
605 volatile u8 IntVect2; /* SDMA + 0x11 */
606 volatile u16 PtdCntrl; /* SDMA + 0x12 */
607
608 volatile u32 IntPend; /* SDMA + 0x14 */
609 volatile u32 IntMask; /* SDMA + 0x18 */
610
611 volatile u16 tcr_0; /* SDMA + 0x1c */
612 volatile u16 tcr_1; /* SDMA + 0x1e */
613 volatile u16 tcr_2; /* SDMA + 0x20 */
614 volatile u16 tcr_3; /* SDMA + 0x22 */
615 volatile u16 tcr_4; /* SDMA + 0x24 */
616 volatile u16 tcr_5; /* SDMA + 0x26 */
617 volatile u16 tcr_6; /* SDMA + 0x28 */
618 volatile u16 tcr_7; /* SDMA + 0x2a */
619 volatile u16 tcr_8; /* SDMA + 0x2c */
620 volatile u16 tcr_9; /* SDMA + 0x2e */
621 volatile u16 tcr_a; /* SDMA + 0x30 */
622 volatile u16 tcr_b; /* SDMA + 0x32 */
623 volatile u16 tcr_c; /* SDMA + 0x34 */
624 volatile u16 tcr_d; /* SDMA + 0x36 */
625 volatile u16 tcr_e; /* SDMA + 0x38 */
626 volatile u16 tcr_f; /* SDMA + 0x3a */
627
628 volatile u8 IPR0; /* SDMA + 0x3c */
629 volatile u8 IPR1; /* SDMA + 0x3d */
630 volatile u8 IPR2; /* SDMA + 0x3e */
631 volatile u8 IPR3; /* SDMA + 0x3f */
632 volatile u8 IPR4; /* SDMA + 0x40 */
633 volatile u8 IPR5; /* SDMA + 0x41 */
634 volatile u8 IPR6; /* SDMA + 0x42 */
635 volatile u8 IPR7; /* SDMA + 0x43 */
636 volatile u8 IPR8; /* SDMA + 0x44 */
637 volatile u8 IPR9; /* SDMA + 0x45 */
638 volatile u8 IPR10; /* SDMA + 0x46 */
639 volatile u8 IPR11; /* SDMA + 0x47 */
640 volatile u8 IPR12; /* SDMA + 0x48 */
641 volatile u8 IPR13; /* SDMA + 0x49 */
642 volatile u8 IPR14; /* SDMA + 0x4a */
643 volatile u8 IPR15; /* SDMA + 0x4b */
644 volatile u8 IPR16; /* SDMA + 0x4c */
645 volatile u8 IPR17; /* SDMA + 0x4d */
646 volatile u8 IPR18; /* SDMA + 0x4e */
647 volatile u8 IPR19; /* SDMA + 0x4f */
648 volatile u8 IPR20; /* SDMA + 0x50 */
649 volatile u8 IPR21; /* SDMA + 0x51 */
650 volatile u8 IPR22; /* SDMA + 0x52 */
651 volatile u8 IPR23; /* SDMA + 0x53 */
652 volatile u8 IPR24; /* SDMA + 0x54 */
653 volatile u8 IPR25; /* SDMA + 0x55 */
654 volatile u8 IPR26; /* SDMA + 0x56 */
655 volatile u8 IPR27; /* SDMA + 0x57 */
656 volatile u8 IPR28; /* SDMA + 0x58 */
657 volatile u8 IPR29; /* SDMA + 0x59 */
658 volatile u8 IPR30; /* SDMA + 0x5a */
659 volatile u8 IPR31; /* SDMA + 0x5b */
660
661 volatile u32 res1; /* SDMA + 0x5c */
662 volatile u32 res2; /* SDMA + 0x60 */
663 volatile u32 res3; /* SDMA + 0x64 */
664 volatile u32 MDEDebug; /* SDMA + 0x68 */
665 volatile u32 ADSDebug; /* SDMA + 0x6c */
666 volatile u32 Value1; /* SDMA + 0x70 */
667 volatile u32 Value2; /* SDMA + 0x74 */
668 volatile u32 Control; /* SDMA + 0x78 */
669 volatile u32 Status; /* SDMA + 0x7c */
670 volatile u32 EU00; /* SDMA + 0x80 */
671 volatile u32 EU01; /* SDMA + 0x84 */
672 volatile u32 EU02; /* SDMA + 0x88 */
673 volatile u32 EU03; /* SDMA + 0x8c */
674 volatile u32 EU04; /* SDMA + 0x90 */
675 volatile u32 EU05; /* SDMA + 0x94 */
676 volatile u32 EU06; /* SDMA + 0x98 */
677 volatile u32 EU07; /* SDMA + 0x9c */
678 volatile u32 EU10; /* SDMA + 0xa0 */
679 volatile u32 EU11; /* SDMA + 0xa4 */
680 volatile u32 EU12; /* SDMA + 0xa8 */
681 volatile u32 EU13; /* SDMA + 0xac */
682 volatile u32 EU14; /* SDMA + 0xb0 */
683 volatile u32 EU15; /* SDMA + 0xb4 */
684 volatile u32 EU16; /* SDMA + 0xb8 */
685 volatile u32 EU17; /* SDMA + 0xbc */
686 volatile u32 EU20; /* SDMA + 0xc0 */
687 volatile u32 EU21; /* SDMA + 0xc4 */
688 volatile u32 EU22; /* SDMA + 0xc8 */
689 volatile u32 EU23; /* SDMA + 0xcc */
690 volatile u32 EU24; /* SDMA + 0xd0 */
691 volatile u32 EU25; /* SDMA + 0xd4 */
692 volatile u32 EU26; /* SDMA + 0xd8 */
693 volatile u32 EU27; /* SDMA + 0xdc */
694 volatile u32 EU30; /* SDMA + 0xe0 */
695 volatile u32 EU31; /* SDMA + 0xe4 */
696 volatile u32 EU32; /* SDMA + 0xe8 */
697 volatile u32 EU33; /* SDMA + 0xec */
698 volatile u32 EU34; /* SDMA + 0xf0 */
699 volatile u32 EU35; /* SDMA + 0xf4 */
700 volatile u32 EU36; /* SDMA + 0xf8 */
701 volatile u32 EU37; /* SDMA + 0xfc */
702};
703
wdenk531716e2003-09-13 19:01:12 +0000[diff] [blame]704struct mpc5xxx_i2c {
705 volatile u32 madr; /* I2Cn + 0x00 */
706 volatile u32 mfdr; /* I2Cn + 0x04 */
707 volatile u32 mcr; /* I2Cn + 0x08 */
708 volatile u32 msr; /* I2Cn + 0x0C */
709 volatile u32 mdr; /* I2Cn + 0x10 */
710};
711
Wolfgang Denk6617aae2005-08-19 00:46:54 +0200[diff] [blame]712struct mpc5xxx_spi {
713 volatile u8 cr1; /* SPI + 0x0F00 */
714 volatile u8 cr2; /* SPI + 0x0F01 */
715 volatile u8 reserved1[2];
716 volatile u8 brr; /* SPI + 0x0F04 */
717 volatile u8 sr; /* SPI + 0x0F05 */
718 volatile u8 reserved2[3];
719 volatile u8 dr; /* SPI + 0x0F09 */
720 volatile u8 reserved3[3];
721 volatile u8 pdr; /* SPI + 0x0F0D */
722 volatile u8 reserved4[2];
723 volatile u8 ddr; /* SPI + 0x0F10 */
724};
725
726
727struct mpc5xxx_gpt {
728 volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */
729 volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */
730 volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */
731 volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */
732};
733
734struct mpc5xxx_gpt_0_7 {
735 struct mpc5xxx_gpt gpt0;
736 struct mpc5xxx_gpt gpt1;
737 struct mpc5xxx_gpt gpt2;
738 struct mpc5xxx_gpt gpt3;
739 struct mpc5xxx_gpt gpt4;
740 struct mpc5xxx_gpt gpt5;
741 struct mpc5xxx_gpt gpt6;
742 struct mpc5xxx_gpt gpt7;
743};
744
745struct mscan_buffer {
746 volatile u8 idr[0x8]; /* 0x00 */
747 volatile u8 dsr[0x10]; /* 0x08 */
748 volatile u8 dlr; /* 0x18 */
749 volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
750 volatile u16 rsrv1; /* 0x1A */
751 volatile u8 tsrh; /* 0x1C */
752 volatile u8 tsrl; /* 0x1D */
753 volatile u16 rsrv2; /* 0x1E */
754};
755
756struct mpc5xxx_mscan {
757 volatile u8 canctl0; /* MSCAN + 0x00 */
758 volatile u8 canctl1; /* MSCAN + 0x01 */
759 volatile u16 rsrv1; /* MSCAN + 0x02 */
760 volatile u8 canbtr0; /* MSCAN + 0x04 */
761 volatile u8 canbtr1; /* MSCAN + 0x05 */
762 volatile u16 rsrv2; /* MSCAN + 0x06 */
763 volatile u8 canrflg; /* MSCAN + 0x08 */
764 volatile u8 canrier; /* MSCAN + 0x09 */
765 volatile u16 rsrv3; /* MSCAN + 0x0A */
766 volatile u8 cantflg; /* MSCAN + 0x0C */
767 volatile u8 cantier; /* MSCAN + 0x0D */
768 volatile u16 rsrv4; /* MSCAN + 0x0E */
769 volatile u8 cantarq; /* MSCAN + 0x10 */
770 volatile u8 cantaak; /* MSCAN + 0x11 */
771 volatile u16 rsrv5; /* MSCAN + 0x12 */
772 volatile u8 cantbsel; /* MSCAN + 0x14 */
773 volatile u8 canidac; /* MSCAN + 0x15 */
774 volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
775 volatile u8 canrxerr; /* MSCAN + 0x1C */
776 volatile u8 cantxerr; /* MSCAN + 0x1D */
777 volatile u16 rsrv7; /* MSCAN + 0x1E */
778 volatile u8 canidar0; /* MSCAN + 0x20 */
779 volatile u8 canidar1; /* MSCAN + 0x21 */
780 volatile u16 rsrv8; /* MSCAN + 0x22 */
781 volatile u8 canidar2; /* MSCAN + 0x24 */
782 volatile u8 canidar3; /* MSCAN + 0x25 */
783 volatile u16 rsrv9; /* MSCAN + 0x26 */
784 volatile u8 canidmr0; /* MSCAN + 0x28 */
785 volatile u8 canidmr1; /* MSCAN + 0x29 */
786 volatile u16 rsrv10; /* MSCAN + 0x2A */
787 volatile u8 canidmr2; /* MSCAN + 0x2C */
788 volatile u8 canidmr3; /* MSCAN + 0x2D */
789 volatile u16 rsrv11; /* MSCAN + 0x2E */
790 volatile u8 canidar4; /* MSCAN + 0x30 */
791 volatile u8 canidar5; /* MSCAN + 0x31 */
792 volatile u16 rsrv12; /* MSCAN + 0x32 */
793 volatile u8 canidar6; /* MSCAN + 0x34 */
794 volatile u8 canidar7; /* MSCAN + 0x35 */
795 volatile u16 rsrv13; /* MSCAN + 0x36 */
796 volatile u8 canidmr4; /* MSCAN + 0x38 */
797 volatile u8 canidmr5; /* MSCAN + 0x39 */
798 volatile u16 rsrv14; /* MSCAN + 0x3A */
799 volatile u8 canidmr6; /* MSCAN + 0x3C */
800 volatile u8 canidmr7; /* MSCAN + 0x3D */
801 volatile u16 rsrv15; /* MSCAN + 0x3E */
802
803 struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
804 struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
805 };
806
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]807/* function prototypes */
808void loadtask(int basetask, int tasks);
809
810#endif /* __ASSEMBLY__ */
811
812#endif /* __ASMPPC_MPC5XXX_H */