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gerrit.nordix.org / codeaurora / quic / qsdk / oss / boot / u-boot-2016 / 96e48cf6c14319f87b38a1d3b6ec9139c9d0469d / . / include / mpc5xxx.h
blob: b803d03df41748768f9d755a445d7a2c7ef174ea [file] [log] [blame]
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]1/*
2 * include/asm-ppc/mpc5xxx.h
3 *
4 * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
5 * embedded cpu chips
6 *
7 * 2003 (c) MontaVista, Software, Inc.
8 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
9 *
10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#ifndef __ASMPPC_MPC5XXX_H
31#define __ASMPPC_MPC5XXX_H
32
33/* Processor name */
34#if defined(CONFIG_MPC5200)
35#define CPU_ID_STR "MPC5200"
36#elif defined(CONFIG_MGT5100)
37#define CPU_ID_STR "MGT5100"
38#endif
39
40/* Exception offsets (PowerPC standard) */
41#define EXC_OFF_SYS_RESET 0x0100
42
43/* Internal memory map */
44
45#define MPC5XXX_CS0_START (CFG_MBAR + 0x0004)
46#define MPC5XXX_CS0_STOP (CFG_MBAR + 0x0008)
47#define MPC5XXX_CS1_START (CFG_MBAR + 0x000c)
48#define MPC5XXX_CS1_STOP (CFG_MBAR + 0x0010)
49#define MPC5XXX_CS2_START (CFG_MBAR + 0x0014)
50#define MPC5XXX_CS2_STOP (CFG_MBAR + 0x0018)
51#define MPC5XXX_CS3_START (CFG_MBAR + 0x001c)
52#define MPC5XXX_CS3_STOP (CFG_MBAR + 0x0020)
53#define MPC5XXX_CS4_START (CFG_MBAR + 0x0024)
54#define MPC5XXX_CS4_STOP (CFG_MBAR + 0x0028)
55#define MPC5XXX_CS5_START (CFG_MBAR + 0x002c)
56#define MPC5XXX_CS5_STOP (CFG_MBAR + 0x0030)
57#define MPC5XXX_BOOTCS_START (CFG_MBAR + 0x004c)
58#define MPC5XXX_BOOTCS_STOP (CFG_MBAR + 0x0050)
59#define MPC5XXX_ADDECR (CFG_MBAR + 0x0054)
60
61#if defined(CONFIG_MGT5100)
62#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
63#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
wdenk96e48cf2003-08-05 18:22:44 +0000[diff] [blame^]64#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
65#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
66#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
67#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]68#elif defined(CONFIG_MPC5200)
69#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
70#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
71#define MPC5XXX_CS7_START (CFG_MBAR + 0x0060)
72#define MPC5XXX_CS7_STOP (CFG_MBAR + 0x0064)
73#define MPC5XXX_SDRAM_CS0CFG (CFG_MBAR + 0x0034)
74#define MPC5XXX_SDRAM_CS1CFG (CFG_MBAR + 0x0038)
75#endif
76
77#define MPC5XXX_SDRAM (CFG_MBAR + 0x0100)
78#define MPC5XXX_CDM (CFG_MBAR + 0x0200)
79#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
80#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
81#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
wdenk96e48cf2003-08-05 18:22:44 +0000[diff] [blame^]82#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]83#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
84#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
85
86#if defined(CONFIG_MGT5100)
87#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
88#define MPC5XXX_PSC2 (CFG_MBAR + 0x2400)
89#define MPC5XXX_PSC3 (CFG_MBAR + 0x2800)
90#elif defined(CONFIG_MPC5200)
91#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
92#define MPC5XXX_PSC2 (CFG_MBAR + 0x2200)
93#define MPC5XXX_PSC3 (CFG_MBAR + 0x2400)
94#define MPC5XXX_PSC4 (CFG_MBAR + 0x2600)
95#define MPC5XXX_PSC5 (CFG_MBAR + 0x2800)
96#define MPC5XXX_PSC6 (CFG_MBAR + 0x2c00)
97#endif
98
99#define MPC5XXX_FEC (CFG_MBAR + 0x3000)
100
101#if defined(CONFIG_MGT5100)
102#define MPC5XXX_SRAM (CFG_MBAR + 0x4000)
103#define MPC5XXX_SRAM_SIZE (8*1024)
104#elif defined(CONFIG_MPC5200)
105#define MPC5XXX_SRAM (CFG_MBAR + 0x8000)
106#define MPC5XXX_SRAM_SIZE (16*1024)
107#endif
108
109/* SDRAM Controller */
110#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
111#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
112#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
113#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
114#if defined(CONFIG_MGT5100)
115#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
116#endif
117
118/* Clock Distribution Module */
119#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
120#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
121#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
122#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
123
124/* Local Plus Bus interface */
125#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
126#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
127#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
128#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
129#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
130#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
131#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
132#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
133#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
134#if defined(CONFIG_MPC5200)
135#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
136#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
137#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
138#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
139#endif
140
141/* GPIO registers */
142#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
143
wdenk96e48cf2003-08-05 18:22:44 +0000[diff] [blame^]144/* PCI registers */
145#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
146#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
147#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
148#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
149#if defined(CONFIG_MGT5100)
150#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
151#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
152#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
153#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
154#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
155#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
156#elif defined(CONFIG_MPC5200)
157#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
158#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
159#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
160#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
161#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
162#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
163#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
164#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
165#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
166#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
167#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
168#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
169#endif
170
wdenk945af8d2003-07-16 21:53:01 +0000[diff] [blame]171/* Interrupt Controller registers */
172#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
173#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
174#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
175#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
176#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
177#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
178#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
179#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
180#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
181#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
182#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
183#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
184#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
185
186/* Programmable Serial Controller (PSC) status register bits */
187#define PSC_SR_CDE 0x0080
188#define PSC_SR_RXRDY 0x0100
189#define PSC_SR_RXFULL 0x0200
190#define PSC_SR_TXRDY 0x0400
191#define PSC_SR_TXEMP 0x0800
192#define PSC_SR_OE 0x1000
193#define PSC_SR_PE 0x2000
194#define PSC_SR_FE 0x4000
195#define PSC_SR_RB 0x8000
196
197/* PSC Command values */
198#define PSC_RX_ENABLE 0x0001
199#define PSC_RX_DISABLE 0x0002
200#define PSC_TX_ENABLE 0x0004
201#define PSC_TX_DISABLE 0x0008
202#define PSC_SEL_MODE_REG_1 0x0010
203#define PSC_RST_RX 0x0020
204#define PSC_RST_TX 0x0030
205#define PSC_RST_ERR_STAT 0x0040
206#define PSC_RST_BRK_CHG_INT 0x0050
207#define PSC_START_BRK 0x0060
208#define PSC_STOP_BRK 0x0070
209
210/* PSC Rx FIFO status bits */
211#define PSC_RX_FIFO_ERR 0x0040
212#define PSC_RX_FIFO_UF 0x0020
213#define PSC_RX_FIFO_OF 0x0010
214#define PSC_RX_FIFO_FR 0x0008
215#define PSC_RX_FIFO_FULL 0x0004
216#define PSC_RX_FIFO_ALARM 0x0002
217#define PSC_RX_FIFO_EMPTY 0x0001
218
219/* PSC interrupt mask bits */
220#define PSC_IMR_TXRDY 0x0100
221#define PSC_IMR_RXRDY 0x0200
222#define PSC_IMR_DB 0x0400
223#define PSC_IMR_IPC 0x8000
224
225/* PSC input port change bits */
226#define PSC_IPCR_CTS 0x01
227#define PSC_IPCR_DCD 0x02
228
229/* PSC mode fields */
230#define PSC_MODE_5_BITS 0x00
231#define PSC_MODE_6_BITS 0x01
232#define PSC_MODE_7_BITS 0x02
233#define PSC_MODE_8_BITS 0x03
234#define PSC_MODE_PAREVEN 0x00
235#define PSC_MODE_PARODD 0x04
236#define PSC_MODE_PARFORCE 0x08
237#define PSC_MODE_PARNONE 0x10
238#define PSC_MODE_ERR 0x20
239#define PSC_MODE_FFULL 0x40
240#define PSC_MODE_RXRTS 0x80
241
242#define PSC_MODE_ONE_STOP_5_BITS 0x00
243#define PSC_MODE_ONE_STOP 0x07
244#define PSC_MODE_TWO_STOP 0x0f
245
246#ifndef __ASSEMBLY__
247struct mpc5xxx_psc {
248 volatile u8 mode; /* PSC + 0x00 */
249 volatile u8 reserved0[3];
250 union { /* PSC + 0x04 */
251 volatile u16 status;
252 volatile u16 clock_select;
253 } sr_csr;
254#define psc_status sr_csr.status
255#define psc_clock_select sr_csr.clock_select
256 volatile u16 reserved1;
257 volatile u8 command; /* PSC + 0x08 */
258 volatile u8 reserved2[3];
259 union { /* PSC + 0x0c */
260 volatile u8 buffer_8;
261 volatile u16 buffer_16;
262 volatile u32 buffer_32;
263 } buffer;
264#define psc_buffer_8 buffer.buffer_8
265#define psc_buffer_16 buffer.buffer_16
266#define psc_buffer_32 buffer.buffer_32
267 union { /* PSC + 0x10 */
268 volatile u8 ipcr;
269 volatile u8 acr;
270 } ipcr_acr;
271#define psc_ipcr ipcr_acr.ipcr
272#define psc_acr ipcr_acr.acr
273 volatile u8 reserved3[3];
274 union { /* PSC + 0x14 */
275 volatile u16 isr;
276 volatile u16 imr;
277 } isr_imr;
278#define psc_isr isr_imr.isr
279#define psc_imr isr_imr.imr
280 volatile u16 reserved4;
281 volatile u8 ctur; /* PSC + 0x18 */
282 volatile u8 reserved5[3];
283 volatile u8 ctlr; /* PSC + 0x1c */
284 volatile u8 reserved6[19];
285 volatile u8 ivr; /* PSC + 0x30 */
286 volatile u8 reserved7[3];
287 volatile u8 ip; /* PSC + 0x34 */
288 volatile u8 reserved8[3];
289 volatile u8 op1; /* PSC + 0x38 */
290 volatile u8 reserved9[3];
291 volatile u8 op0; /* PSC + 0x3c */
292 volatile u8 reserved10[3];
293 volatile u8 sicr; /* PSC + 0x40 */
294 volatile u8 reserved11[3];
295 volatile u8 ircr1; /* PSC + 0x44 */
296 volatile u8 reserved12[3];
297 volatile u8 ircr2; /* PSC + 0x44 */
298 volatile u8 reserved13[3];
299 volatile u8 irsdr; /* PSC + 0x4c */
300 volatile u8 reserved14[3];
301 volatile u8 irmdr; /* PSC + 0x50 */
302 volatile u8 reserved15[3];
303 volatile u8 irfdr; /* PSC + 0x54 */
304 volatile u8 reserved16[3];
305 volatile u16 rfnum; /* PSC + 0x58 */
306 volatile u16 reserved17;
307 volatile u16 tfnum; /* PSC + 0x5c */
308 volatile u16 reserved18;
309 volatile u32 rfdata; /* PSC + 0x60 */
310 volatile u16 rfstat; /* PSC + 0x64 */
311 volatile u16 reserved20;
312 volatile u8 rfcntl; /* PSC + 0x68 */
313 volatile u8 reserved21[5];
314 volatile u16 rfalarm; /* PSC + 0x6e */
315 volatile u16 reserved22;
316 volatile u16 rfrptr; /* PSC + 0x72 */
317 volatile u16 reserved23;
318 volatile u16 rfwptr; /* PSC + 0x76 */
319 volatile u16 reserved24;
320 volatile u16 rflrfptr; /* PSC + 0x7a */
321 volatile u16 reserved25;
322 volatile u16 rflwfptr; /* PSC + 0x7e */
323 volatile u32 tfdata; /* PSC + 0x80 */
324 volatile u16 tfstat; /* PSC + 0x84 */
325 volatile u16 reserved26;
326 volatile u8 tfcntl; /* PSC + 0x88 */
327 volatile u8 reserved27[5];
328 volatile u16 tfalarm; /* PSC + 0x8e */
329 volatile u16 reserved28;
330 volatile u16 tfrptr; /* PSC + 0x92 */
331 volatile u16 reserved29;
332 volatile u16 tfwptr; /* PSC + 0x96 */
333 volatile u16 reserved30;
334 volatile u16 tflrfptr; /* PSC + 0x9a */
335 volatile u16 reserved31;
336 volatile u16 tflwfptr; /* PSC + 0x9e */
337};
338
339struct mpc5xxx_intr {
340 volatile u32 per_mask; /* INTR + 0x00 */
341 volatile u32 per_pri1; /* INTR + 0x04 */
342 volatile u32 per_pri2; /* INTR + 0x08 */
343 volatile u32 per_pri3; /* INTR + 0x0c */
344 volatile u32 ctrl; /* INTR + 0x10 */
345 volatile u32 main_mask; /* INTR + 0x14 */
346 volatile u32 main_pri1; /* INTR + 0x18 */
347 volatile u32 main_pri2; /* INTR + 0x1c */
348 volatile u32 reserved1; /* INTR + 0x20 */
349 volatile u32 enc_status; /* INTR + 0x24 */
350 volatile u32 crit_status; /* INTR + 0x28 */
351 volatile u32 main_status; /* INTR + 0x2c */
352 volatile u32 per_status; /* INTR + 0x30 */
353 volatile u32 reserved2; /* INTR + 0x34 */
354 volatile u32 per_error; /* INTR + 0x38 */
355};
356
357struct mpc5xxx_gpio {
358 volatile u32 port_config; /* GPIO + 0x00 */
359 volatile u32 simple_gpioe; /* GPIO + 0x04 */
360 volatile u32 simple_ode; /* GPIO + 0x08 */
361 volatile u32 simple_ddr; /* GPIO + 0x0c */
362 volatile u32 simple_dvo; /* GPIO + 0x10 */
363 volatile u32 simple_ival; /* GPIO + 0x14 */
364 volatile u8 outo_gpioe; /* GPIO + 0x18 */
365 volatile u8 reserved1[3]; /* GPIO + 0x19 */
366 volatile u8 outo_dvo; /* GPIO + 0x1c */
367 volatile u8 reserved2[3]; /* GPIO + 0x1d */
368 volatile u8 sint_gpioe; /* GPIO + 0x20 */
369 volatile u8 reserved3[3]; /* GPIO + 0x21 */
370 volatile u8 sint_ode; /* GPIO + 0x24 */
371 volatile u8 reserved4[3]; /* GPIO + 0x25 */
372 volatile u8 sint_ddr; /* GPIO + 0x28 */
373 volatile u8 reserved5[3]; /* GPIO + 0x29 */
374 volatile u8 sint_dvo; /* GPIO + 0x2c */
375 volatile u8 reserved6[3]; /* GPIO + 0x2d */
376 volatile u8 sint_inten; /* GPIO + 0x30 */
377 volatile u8 reserved7[3]; /* GPIO + 0x31 */
378 volatile u16 sint_itype; /* GPIO + 0x34 */
379 volatile u16 reserved8; /* GPIO + 0x36 */
380 volatile u8 gpio_control; /* GPIO + 0x38 */
381 volatile u8 reserved9[3]; /* GPIO + 0x39 */
382 volatile u8 sint_istat; /* GPIO + 0x3c */
383 volatile u8 sint_ival; /* GPIO + 0x3d */
384 volatile u8 bus_errs; /* GPIO + 0x3e */
385 volatile u8 reserved10; /* GPIO + 0x3f */
386};
387
388struct mpc5xxx_sdma {
389 volatile u32 taskBar; /* SDMA + 0x00 */
390 volatile u32 currentPointer; /* SDMA + 0x04 */
391 volatile u32 endPointer; /* SDMA + 0x08 */
392 volatile u32 variablePointer; /* SDMA + 0x0c */
393
394 volatile u8 IntVect1; /* SDMA + 0x10 */
395 volatile u8 IntVect2; /* SDMA + 0x11 */
396 volatile u16 PtdCntrl; /* SDMA + 0x12 */
397
398 volatile u32 IntPend; /* SDMA + 0x14 */
399 volatile u32 IntMask; /* SDMA + 0x18 */
400
401 volatile u16 tcr_0; /* SDMA + 0x1c */
402 volatile u16 tcr_1; /* SDMA + 0x1e */
403 volatile u16 tcr_2; /* SDMA + 0x20 */
404 volatile u16 tcr_3; /* SDMA + 0x22 */
405 volatile u16 tcr_4; /* SDMA + 0x24 */
406 volatile u16 tcr_5; /* SDMA + 0x26 */
407 volatile u16 tcr_6; /* SDMA + 0x28 */
408 volatile u16 tcr_7; /* SDMA + 0x2a */
409 volatile u16 tcr_8; /* SDMA + 0x2c */
410 volatile u16 tcr_9; /* SDMA + 0x2e */
411 volatile u16 tcr_a; /* SDMA + 0x30 */
412 volatile u16 tcr_b; /* SDMA + 0x32 */
413 volatile u16 tcr_c; /* SDMA + 0x34 */
414 volatile u16 tcr_d; /* SDMA + 0x36 */
415 volatile u16 tcr_e; /* SDMA + 0x38 */
416 volatile u16 tcr_f; /* SDMA + 0x3a */
417
418 volatile u8 IPR0; /* SDMA + 0x3c */
419 volatile u8 IPR1; /* SDMA + 0x3d */
420 volatile u8 IPR2; /* SDMA + 0x3e */
421 volatile u8 IPR3; /* SDMA + 0x3f */
422 volatile u8 IPR4; /* SDMA + 0x40 */
423 volatile u8 IPR5; /* SDMA + 0x41 */
424 volatile u8 IPR6; /* SDMA + 0x42 */
425 volatile u8 IPR7; /* SDMA + 0x43 */
426 volatile u8 IPR8; /* SDMA + 0x44 */
427 volatile u8 IPR9; /* SDMA + 0x45 */
428 volatile u8 IPR10; /* SDMA + 0x46 */
429 volatile u8 IPR11; /* SDMA + 0x47 */
430 volatile u8 IPR12; /* SDMA + 0x48 */
431 volatile u8 IPR13; /* SDMA + 0x49 */
432 volatile u8 IPR14; /* SDMA + 0x4a */
433 volatile u8 IPR15; /* SDMA + 0x4b */
434 volatile u8 IPR16; /* SDMA + 0x4c */
435 volatile u8 IPR17; /* SDMA + 0x4d */
436 volatile u8 IPR18; /* SDMA + 0x4e */
437 volatile u8 IPR19; /* SDMA + 0x4f */
438 volatile u8 IPR20; /* SDMA + 0x50 */
439 volatile u8 IPR21; /* SDMA + 0x51 */
440 volatile u8 IPR22; /* SDMA + 0x52 */
441 volatile u8 IPR23; /* SDMA + 0x53 */
442 volatile u8 IPR24; /* SDMA + 0x54 */
443 volatile u8 IPR25; /* SDMA + 0x55 */
444 volatile u8 IPR26; /* SDMA + 0x56 */
445 volatile u8 IPR27; /* SDMA + 0x57 */
446 volatile u8 IPR28; /* SDMA + 0x58 */
447 volatile u8 IPR29; /* SDMA + 0x59 */
448 volatile u8 IPR30; /* SDMA + 0x5a */
449 volatile u8 IPR31; /* SDMA + 0x5b */
450
451 volatile u32 res1; /* SDMA + 0x5c */
452 volatile u32 res2; /* SDMA + 0x60 */
453 volatile u32 res3; /* SDMA + 0x64 */
454 volatile u32 MDEDebug; /* SDMA + 0x68 */
455 volatile u32 ADSDebug; /* SDMA + 0x6c */
456 volatile u32 Value1; /* SDMA + 0x70 */
457 volatile u32 Value2; /* SDMA + 0x74 */
458 volatile u32 Control; /* SDMA + 0x78 */
459 volatile u32 Status; /* SDMA + 0x7c */
460 volatile u32 EU00; /* SDMA + 0x80 */
461 volatile u32 EU01; /* SDMA + 0x84 */
462 volatile u32 EU02; /* SDMA + 0x88 */
463 volatile u32 EU03; /* SDMA + 0x8c */
464 volatile u32 EU04; /* SDMA + 0x90 */
465 volatile u32 EU05; /* SDMA + 0x94 */
466 volatile u32 EU06; /* SDMA + 0x98 */
467 volatile u32 EU07; /* SDMA + 0x9c */
468 volatile u32 EU10; /* SDMA + 0xa0 */
469 volatile u32 EU11; /* SDMA + 0xa4 */
470 volatile u32 EU12; /* SDMA + 0xa8 */
471 volatile u32 EU13; /* SDMA + 0xac */
472 volatile u32 EU14; /* SDMA + 0xb0 */
473 volatile u32 EU15; /* SDMA + 0xb4 */
474 volatile u32 EU16; /* SDMA + 0xb8 */
475 volatile u32 EU17; /* SDMA + 0xbc */
476 volatile u32 EU20; /* SDMA + 0xc0 */
477 volatile u32 EU21; /* SDMA + 0xc4 */
478 volatile u32 EU22; /* SDMA + 0xc8 */
479 volatile u32 EU23; /* SDMA + 0xcc */
480 volatile u32 EU24; /* SDMA + 0xd0 */
481 volatile u32 EU25; /* SDMA + 0xd4 */
482 volatile u32 EU26; /* SDMA + 0xd8 */
483 volatile u32 EU27; /* SDMA + 0xdc */
484 volatile u32 EU30; /* SDMA + 0xe0 */
485 volatile u32 EU31; /* SDMA + 0xe4 */
486 volatile u32 EU32; /* SDMA + 0xe8 */
487 volatile u32 EU33; /* SDMA + 0xec */
488 volatile u32 EU34; /* SDMA + 0xf0 */
489 volatile u32 EU35; /* SDMA + 0xf4 */
490 volatile u32 EU36; /* SDMA + 0xf8 */
491 volatile u32 EU37; /* SDMA + 0xfc */
492};
493
494/* function prototypes */
495void loadtask(int basetask, int tasks);
496
497#endif /* __ASSEMBLY__ */
498
499#endif /* __ASMPPC_MPC5XXX_H */